Method for reordering concurrent read and write mixing preserving acceleration of ssd and related device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2022-12-20
- Publication Date
- 2026-06-16
AI Technical Summary
对于同一容量的SSD盘，单lun容量成倍增加，lun数会减少，带来的影响是nandflash阵列的并发度降低，SSD的性能降低
[0038] The beneficial effects of this invention compared to existing technologies are as follows: This invention receives erase/write/read requests; formulates a distribution decision based on the type of the erase/write/read request, and distributes the erase/write/read request to a FIFO queue, which includes planeRFIFO and EPFIFO; obtains concurrent transmission requests from the FIFO queue; arbitrates the concurrent transmission requests, and sends the winning request to the corresponding plane of the NAND flash for execution. This invention enables multiple planes to perform reads in parallel while ensuring the order of erase and write operations, thus ensuring performance and data consistency in mixed read/write scenarios and improving SSD read performance and mixed read/write performance.
Smart Images
Figure CN115840536B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data storage technology, and more specifically to a method and related equipment for accelerating out-of-order concurrent reads and erases / writes of SSDs while maintaining order. Background Technology
[0002] The development trend of NAND flash is that the capacity of a single LUN is gradually increasing, from 16GB to 32GB in recent years, and further to 64GB and 128GB in the future. For SSDs of the same capacity, the capacity of a single LUN increases exponentially, while the number of LUNs decreases. This results in a decrease in the concurrency of the NAND flash array and a decrease in the performance of the SSD.
[0003] Existing SSD controllers do not support concurrent read operations between NAND flash planes. They require waiting for the previous read to complete before issuing the next read, preventing concurrent reads between planes and thus hindering the full utilization of NAND flash read performance, impacting the overall SSD read performance. For example... Figure 1 As shown, the consecutive read requests R1-R8 correspond to the four planes of the NAND flash memory. Since concurrent reading of planes is not supported, the commands can only interact with the NAND flash memory one by one. The concurrency of the four planes cannot be utilized, and only the read performance of one plane can be demonstrated. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and related equipment for accelerating out-of-order concurrent read and erase / write hybrid order-preserving operations of SSDs.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] Firstly, SSDs employ a hybrid order-preserving acceleration method that combines out-of-order concurrent reads and erase / write operations, including:
[0007] Receive the erase, write, and read requests sent from the server;
[0008] A decision is made to issue the erase / write / read request based on its type, and the erase / write / read request is issued to the FIFO queue according to the decision. The FIFO queue includes planeRfifo and EPfifo.
[0009] Obtain concurrent send requests from the FIFO queue;
[0010] Arbitrate concurrent send requests and send the winning request to the plane corresponding to the NAND flash for execution.
[0011] The further technical solution is as follows: A decision is made to distribute the erase / write / read request based on its type, and the request is distributed to the FIFO queue according to the decision. The FIFO queue includes planeRFIFO and EPFIFO, comprising:
[0012] If the erase / write / read request is of type write or erase, then check whether all planeRfifos in the FIFO queue are empty;
[0013] If all planeRfifos are empty, write or erase requests are sent to EPfifos.
[0014] The further technical solution is as follows: A decision is made to distribute the erase / write / read request based on its type, and the request is distributed to the FIFO queue according to the decision. The FIFO queue includes planeRFIFO and EPFIFO, and also includes:
[0015] If the erase / write / read request is of type read, then determine whether there is at least one empty planeRfifo in the fifo queue;
[0016] If it exists, the read type request will be sent to planeRfifo.
[0017] Its further technical solution is as follows: arbitrating concurrent sending requests and sending the winning request to the plane corresponding to the NAND flash for execution includes:
[0018] Determine if there is a request in the EPFIFO file;
[0019] If there is a request in the EPFIFO, the request in the EPFIFO will be executed first.
[0020] If there is no requested content in EPfifo, the requested content in multiple planeRfifo will be executed in turn.
[0021] Secondly, the SSD's out-of-order concurrent read and erase / write hybrid order-preserving acceleration device includes a receiving unit, a decision-making unit, a sending unit, and an arbitration unit.
[0022] The receiving unit is used to receive the sent erase / write / read requests;
[0023] The decision-making unit is used to make a distribution decision based on the type of erase / write / read request, and to distribute the erase / write / read request to the FIFO queue according to the made distribution decision. The FIFO queue includes planeRfifo and EPfifo.
[0024] The sending unit is used to obtain concurrent sending requests from the FIFO queue;
[0025] The arbitration unit is used to arbitrate concurrent sending requests and send the winning request to the plane corresponding to the NAND flash for execution.
[0026] The further technical solution is as follows: the decision-making unit includes a first judgment module and a first distribution module;
[0027] The first judgment module is used to determine whether all planeRfifos in the FIFO queue are empty if the sent erase / write / read request is of type write or erase.
[0028] The first sending module is used to send write or erase requests to the EPfifo if all planeRfifos are empty.
[0029] The further technical solution is as follows: the decision-making unit further includes a second judgment module and a second distribution module;
[0030] The second judgment module is used to determine whether there is at least one empty planeRfifo in the fifo queue if the sent erase / write / read request is of the read type;
[0031] The second sending module is used to send read-type requests to planeRfifo if they exist.
[0032] The further technical solution is as follows: the arbitration unit includes a third judgment module, a priority execution module, and a rotation execution module;
[0033] The third judgment module is used to determine whether there is request content in the EPfifo;
[0034] The priority execution module is used to prioritize executing the requested content in the EPfifo if there is requested content in the EPfifo.
[0035] The rotation execution module is used to rotate and execute the request content in multiple planeRfifo if there is no request content in EPfifo.
[0036] Thirdly, a computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor, when executing the computer program, implements the above-described method for accelerating out-of-order concurrent reads and erase / write operations in a hybrid order-preserving manner for SSDs.
[0037] Fourthly, a computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the above-described SSD out-of-order concurrent read and erase-write hybrid order-preserving acceleration method.
[0038] The beneficial effects of this invention compared to existing technologies are as follows: This invention receives erase / write / read requests; formulates a distribution decision based on the type of the erase / write / read request, and distributes the erase / write / read request to a FIFO queue, which includes planeRFIFO and EPFIFO; obtains concurrent transmission requests from the FIFO queue; arbitrates the concurrent transmission requests, and sends the winning request to the corresponding plane of the NAND flash for execution. This invention enables multiple planes to perform reads in parallel while ensuring the order of erase and write operations, thus ensuring performance and data consistency in mixed read / write scenarios and improving SSD read performance and mixed read / write performance.
[0039] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of the present invention more obvious and understandable, preferred embodiments are described in detail below. Attached Figure Description
[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram illustrating the processing procedure for read requests in existing technologies.
[0042] Figure 2 This is a schematic diagram illustrating the process of processing erase / write / read requests in this application;
[0043] Figure 3 A flowchart of a method for accelerating out-of-order concurrent read and erase / write hybrid order-preserving SSDs according to a specific embodiment of the present invention;
[0044] Figure 4 A schematic block diagram of an SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration device provided for a specific embodiment of the present invention;
[0045] Figure 5 This is a schematic block diagram of a computer device provided for a specific embodiment of the present invention. Detailed Implementation
[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0047] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0048] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0049] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0050] This invention provides a method for accelerating out-of-order concurrent reads and erase / write operations in SSDs while maintaining order, such as... Figure 3 As shown, the method includes the following steps: S10-S40.
[0051] S10. Receive the sent erase / write / read request.
[0052] like Figure 2 As shown, continuous erase, write, and read requests in Luninfifo are sequentially issued in luninproc. Each request is marked with a sequence number, and the order of the requests is determined based on the type of the current request and the contents of EPfifo and planeRfifo.
[0053] S20. Make a distribution decision based on the type of erase / write / read request, and distribute the erase / write / read request to the FIFO queue according to the distribution decision. The FIFO queue includes planeRfifo and EPfifo.
[0054] In one embodiment, step S20 specifically includes the following steps: S201-S204.
[0055] S201. If the issued erase / write / read request is of type write or erase, then determine whether all planeRfifo in the fifo queue are empty.
[0056] S202. If all planeRfifos are empty, then write or erase requests are sent to EPfifos.
[0057] S203. If the erase / write / read request is of type read, then determine whether there is at least one empty planeRfifo in the fifo queue.
[0058] S204. If it exists, then send the read type request to planeRfifo.
[0059] like Figure 2 As shown, if the request is to write or erase, the write or erase request must be sent to the EPfifo only if all planeRfifos are empty during the request determination. If the request is to read, the request can be sent directly to the corresponding planeRfifo as long as there is space in the corresponding planeRfifo.
[0060] S30. Obtain concurrent send requests from the FIFO queue.
[0061] like Figure 2 As shown, Planeproc and EPproc obtain requests from their respective FIFOs and send the requests to lunoutproc. This step is executed concurrently.
[0062] S40. Arbitrate concurrent sending requests and send the winning request to the plane corresponding to the NAND flash for execution.
[0063] In one embodiment, step S40 specifically includes the following steps S401-S403.
[0064] S401. Determine if there is any request content in EPfifo.
[0065] S402. If there is a request in the EPfifo, the request in the EPfifo shall be executed first.
[0066] S403. If there is no requested content in EPfifo, the requested content in multiple planeRfifo will be executed in turn.
[0067] like Figure 2As shown, Lunoutproc arbitrates multiple planeproc and EPproc requests and sends the winning request to the plane corresponding to the nandflash for execution. The arbitration scheme is as follows: if there is content in the EPfifo, the request in the EPfifo is executed first; if there is no content in the EPfifo, the requests in multiple planefifos are executed in turn.
[0068] like Figure 2 As shown, this solution allows four planes to read in parallel, achieving four times the performance of existing solutions. It also ensures the order of erasing and writing, guaranteeing performance and data consistency in mixed read / write scenarios, and improving SSD read performance and mixed read / write performance.
[0069] Figure 4 This is a schematic block diagram of an SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration device provided in an embodiment of the present invention; corresponding to the above-described SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration method, the present invention also provides an SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration device 100.
[0070] like Figure 4 As shown, the SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration device 100 includes a receiving unit 110, a decision-making unit 120, a sending unit 130, and an arbitration unit 140.
[0071] The receiving unit 110 is used to receive the sent erase / write / read requests.
[0072] like Figure 2 As shown, continuous erase, write, and read requests in Luninfifo are sequentially issued in luninproc. Each request is marked with a sequence number, and the order of the requests is determined based on the type of the current request and the contents of EPfifo and planeRfifo.
[0073] The decision-making unit 120 is used to make a distribution decision based on the type of erase / write / read request, and to distribute the erase / write / read request to the FIFO queue according to the made distribution decision. The FIFO queue includes planeRFIFO and EPFIFO.
[0074] In one embodiment, the decision-making unit 120 includes a first judgment module, a first distribution module, a second judgment module, and a second distribution module.
[0075] The first judgment module is used to determine whether all planeRfifos in the FIFO queue are empty if the sent erase / write / read request is of type write or erase.
[0076] The first dispatch module is used to dispatch write or erase requests to the EPfifo if all planeRfifos are empty.
[0077] The second judgment module is used to determine whether there is at least one empty planeRfifo in the FIFO queue if the erase / write / read request is of type read.
[0078] The second distribution module is used to distribute read requests to planeRfifo if they exist.
[0079] like Figure 2 As shown, if the request is to write or erase, the write or erase request must be sent to the EPfifo only if all planeRfifos are empty during the request determination. If the request is to read, the request can be sent directly to the corresponding planeRfifo as long as there is space in the corresponding planeRfifo.
[0080] The sending unit 130 is used to obtain concurrent sending requests from the FIFO queue.
[0081] like Figure 2 As shown, Planeproc and EPproc obtain requests from their respective FIFOs and send the requests to lunoutproc. This step is executed concurrently.
[0082] Arbitration unit 140 is used to arbitrate concurrent transmission requests and send the winning request to the plane corresponding to the NAND flash for execution.
[0083] In one embodiment, the arbitration unit 140 includes a third judgment module, a priority execution module, and a rotation execution module.
[0084] The third judgment module is used to determine whether there is requested content in the EPfifo.
[0085] The priority execution module is used to prioritize executing the requested content in the EPFIFO if it contains such content.
[0086] The round-robin execution module is used to execute the request content in multiple planeRfifos in a round-robin fashion if there is no request content in EPfifo.
[0087] like Figure 2As shown, Lunoutproc arbitrates multiple planeproc and EPproc requests and sends the winning request to the plane corresponding to the nandflash for execution. The arbitration scheme is as follows: if there is content in the EPfifo, the request in the EPfifo is executed first; if there is no content in the EPfifo, the requests in multiple planefifos are executed in turn.
[0088] like Figure 2 As shown, this solution allows four planes to read in parallel, achieving four times the performance of existing solutions. It also ensures the order of erasing and writing, guaranteeing performance and data consistency in mixed read / write scenarios, and improving SSD read performance and mixed read / write performance.
[0089] The aforementioned SSD's out-of-order concurrent read and erase-write hybrid order-preserving acceleration device can be implemented as a computer program, which can, for example, Figure 5 It runs on the computer device shown.
[0090] Please see Figure 5 , Figure 5 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 700 can be a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.
[0091] like Figure 5 As shown, the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above-described SSD out-of-order concurrent read and erase-write hybrid order-preserving acceleration method.
[0092] The computer device 700 can be a terminal or a server. The computer device 700 includes a processor 720, a memory, and a network interface 750 connected via a system bus 710, wherein the memory may include a non-volatile storage medium 730 and internal memory 740.
[0093] The non-volatile storage medium 730 can store an operating system 731 and a computer program 732. When the computer program 732 is executed, it enables the processor 720 to execute any SSD's out-of-order concurrent read and erase / write hybrid order-preserving acceleration method.
[0094] The processor 720 provides computing and control capabilities to support the operation of the entire computer device 700.
[0095] The internal memory 740 provides an environment for the execution of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, the processor 720 can execute any SSD out-of-order concurrent read and erase-write hybrid order-preserving acceleration method.
[0096] This network interface 750 is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 700 to which the present application is applied. The specific computer device 700 may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. The processor 720 is used to run program code stored in memory to implement the following steps:
[0097] Methods for accelerating SSD performance through a hybrid order-preserving approach combining out-of-order concurrent reads and erase / write operations include:
[0098] Receive the erase, write, and read requests sent from the server;
[0099] A decision is made to issue the erase / write / read request based on its type, and the erase / write / read request is issued to the FIFO queue according to the decision. The FIFO queue includes planeRfifo and EPfifo.
[0100] Obtain concurrent send requests from the FIFO queue;
[0101] Arbitrate concurrent send requests and send the winning request to the plane corresponding to the NAND flash for execution.
[0102] In one embodiment: the step of formulating a distribution decision based on the type of the erase / write / read request, and distributing the erase / write / read request to the FIFO queue according to the formulated distribution decision, wherein the FIFO queue includes planeRFIFO and EPFIFO, including:
[0103] If the erase / write / read request is of type write or erase, then check whether all planeR fifos in the fifo queue are empty;
[0104] If all planeRfifos are empty, write or erase requests are sent to EPfifos.
[0105] In one embodiment: the step of formulating a distribution decision based on the type of the erase / write / read request, and distributing the erase / write / read request to the FIFO queue according to the formulated distribution decision, wherein the FIFO queue includes planeRFIFO and EPFIFO, and further includes:
[0106] If the erase / write / read request is of type read, then determine whether there is at least one empty planeRfifo in the fifo queue;
[0107] If it exists, the read type request will be sent to planeRfifo.
[0108] In one embodiment: arbitrating concurrent transmission requests and sending the winning request to the plane corresponding to the NAND flash for execution includes:
[0109] Determine if there is a request in the EPFIFO file;
[0110] If there is a request in the EPFIFO, the request in the EPFIFO will be executed first.
[0111] If there is no requested content in EPfifo, the requested content in multiple planeRfifo will be executed in turn.
[0112] It should be understood that in the embodiments of this application, the processor 720 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.
[0113] Those skilled in the art will understand that Figure 5 The structure of the computer device 700 shown does not constitute a limitation on the computer device 700, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0114] In another embodiment of the present invention, a computer-readable storage medium is provided. This computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, wherein when executed by a processor, the computer program implements the out-of-order concurrent read and erase / write hybrid order-preserving acceleration method for SSDs disclosed in this embodiment of the present invention.
[0115] Those skilled in the art will readily understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.
[0116] In the embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Units with the same function may be grouped into one unit. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, or it may be an electrical, mechanical, or other form of connection.
[0117] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.
[0118] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0119] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks.
[0120] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for accelerating out-of-order concurrent reads and erase / write operations in SSDs while maintaining order, characterized in that... include: Receive the erase, write, and read requests sent from the server; A decision is made to issue the erase / write / read request based on its type, and the erase / write / read request is issued to the FIFO queue according to the decision. The FIFO queue includes plane R FIFO and EP FIFO. If the erase / write / read request is of type write or erase, then check whether all plane R FIFOs in the FIFO queue are empty; If all plane R FIFOs are empty, then write or erase requests are sent to the EP FIFO. Obtain concurrent send requests from the FIFO queue; Arbitrate concurrent send requests and send the winning request to the plane corresponding to the NAND flash for execution.
2. The method for accelerating out-of-order concurrent reads and erase / write operations in an SSD according to claim 1, characterized in that, The process involves making a distribution decision based on the type of the erase / write / read request, and then distributing the erase / write / read request to the FIFO queue according to the decision. The FIFO queue includes Plane R FIFO and EP FIFO, and further includes: If the erase / write / read request is of type read, then determine whether there is at least one empty plane Rfifo in the FIFO queue; If it exists, the read type request will be sent to plane R fifo.
3. The method for accelerating out-of-order concurrent reads and erase / write operations in an SSD according to claim 1, characterized in that, The arbitration of concurrent sending requests, and the sending of the winning request to the plane corresponding to the NAND flash for execution, includes: Determine if there is a request in the EP FIFO; If there is a request in the EP FIFO, the request in the EP FIFO will be executed first. If there is no requested content in the EP FIFO, the requested content in multiple plane R FIFOs will be executed in turn.
4. A hybrid order-preserving acceleration device for out-of-order concurrent reads and erase / write operations on an SSD, wherein, during operation, the method for hybrid order-preserving acceleration of out-of-order concurrent reads and erase / write operations on an SSD as described in any one of claims 1-3 is characterized in that, It includes a receiving unit, a decision-making unit, a sending unit, and an arbitration unit; The receiving unit is used to receive the sent erase / write / read requests; The decision-making unit is used to make a distribution decision based on the type of erase / write / read request, and to distribute the erase / write / read request to the FIFO queue according to the made distribution decision. The FIFO queue includes plane R FIFO and EP FIFO. The sending unit is used to obtain concurrent sending requests from the FIFO queue; The arbitration unit is used to arbitrate concurrent sending requests and send the winning request to the plane corresponding to the NAND flash for execution.
5. The SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration device according to claim 4, characterized in that, The decision-making unit includes a first judgment module and a first issuing module; The first judgment module is used to determine whether all plane R FIFOs in the FIFO queue are empty if the sent erase / write / read request is of type write or erase. The first sending module is used to send write or erase requests to the EP FIFO if all plane R FIFOs are empty.
6. The SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration device according to claim 5, characterized in that, The decision-making unit also includes a second judgment module and a second distribution module; The second judgment module is used to determine whether there is at least one empty plane R fifo in the fifo queue if the erase / write / read request is of type read. The second sending module is used to send read-type requests to the plane R fifo if they exist.
7. The SSD out-of-order concurrent read and erase / write hybrid order-preserving acceleration device according to claim 4, characterized in that, The arbitration unit includes a third judgment module, a priority execution module, and a rotation execution module; The third judgment module is used to determine whether there is request content in the EP FIFO; The priority execution module is used to prioritize executing the requested content in the EP FIFO if there is requested content in the EP FIFO. The rotation execution module is used to rotate and execute the request content in multiple plane R FIFOs if there is no request content in EP FIFO.
8. A computer device, characterized in that, The method includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the out-of-order concurrent read and erase-write hybrid order-preserving acceleration method for SSD as described in any one of claims 1 to 3.
9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor, the processor performs the out-of-order concurrent read and erase / write hybrid order-preserving acceleration method for SSD as described in any one of claims 1 to 3.