System and method for reducing interference in radio frequency devices

Abstract

A system and method of reducing interference in a radio frequency device is provided. A transmitter of an electronic device can include one or more intermediate frequency stage circuits. A processing circuit can select one or more intermediate frequency stage circuits of the transmitter that output one or more intermediate frequency signals that cause interference to a signal received by a receiver of the electronic device. The processing circuit can adjust settings of the one or more intermediate frequency stage circuits to reduce the interference to the signal received by the receiver and store the settings. Subsequently, the processing circuit can receive an indication of an operating mode of the receiver and apply the settings to the one or more intermediate frequency stage circuits based on the indication.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 246,732, filed September 21, 2021, entitled “SYSTEMS AND METHODS TOREDUCE INTERFERENCE IN A RADIO FREQUENCY DEVICE”, the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0003] This implementation relates to wireless communication devices, and more specifically to wireless communication devices having multiple transceivers (e.g., multi-radio wireless communication devices).

[0004] Wireless communication devices may include transmitters that transmit radio frequency signals. For this purpose, the transmitter may pass a baseband signal through one or more intermediate frequency (IF) stages to up-convert the baseband signal into radio frequency. However, these one or more IF stages may generate noise that interferes with the receiver of the wireless communication device. Summary of the Invention

[0005] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects not set forth below.

[0006] In one embodiment, the method may include selecting one or more intermediate frequency (IF) stage circuits of a transmitter of an electronic device, the one or more IF stage circuits outputting one or more IF signals that interfere with signals received by a receiver of the electronic device. The method may also include adjusting one or more operating characteristics of the one or more IF stage circuits based on at least one or more settings to reduce interference with signals received by the receiver. The method may further include storing the one or more settings to be applied to the one or more IF stage circuits in response to determining that the receiver is operable.

[0007] In another embodiment, the electronic device may include a transceiver comprising at least one transmitter and one or more receivers, wherein the transmitter may include one or more intermediate frequency (IF) stage circuits. The electronic device may additionally include processing circuitry. The processing circuitry may be configured to receive indications of multiple operating modes for the plurality of receivers. The processing circuitry may be configured to apply settings to the one or more IF stage circuits based on the indications, and to operate the transmitter based on the settings applied to the one or more IF stage circuits.

[0008] In another embodiment, one or more tangible non-transitory computer-readable media store instructions executable by one or more processors of an electronic device, wherein these instructions cause the one or more processors to receive a first set of settings applicable when the receiver of the electronic device is in a first operating mode, for at least a first intermediate frequency (IF) stage circuit and a second IF stage circuit of the transmitter of the electronic device, the first set of settings including causing the first IF stage circuit to have a first gain level and causing a second IF stage circuit of a plurality of frequency stage circuits to have a second gain level. The tangible non-transitory computer-readable medium may further cause the one or more processors to receive a second set of settings applicable when the receiver of the electronic device is in a second operating mode, for the plurality of frequency stage circuits of the transmitter of the electronic device, the second set of settings including a first adjustment to the first gain level of the first IF stage circuit and a second adjustment to the second gain level of the second IF stage circuit, the second adjustment at least partially compensating for the first adjustment. The tangible non-transitory computer-readable medium may further cause the one or more processors to operate the transmitter using the first set of settings based on the receiver of the electronic device being in the first operating mode, and to operate the transmitter using the second set of settings based on the receiver of the electronic device being in the second operating mode.

[0009] Various modifications to the above-described features may exist with respect to various aspects of the invention. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, various features discussed below relating to one or more illustrated embodiments may be incorporated individually or in any combination into any of the above aspects of the invention. The brief summary presented above is intended only to familiarize the reader with specific aspects and context of the embodiments disclosed herein and does not limit the claimed subject matter. Attached Figure Description

[0010] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the accompanying drawings, wherein similar figures refer to similar parts.

[0011] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic devices;

[0013] Figure 3 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of the transmitter of an electronic device;

[0014] Figure 4 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of the receiver of an electronic device;

[0015] Figure 5 It is based on the implementation scheme of this disclosure. Figure 1 Multi-radio systems for electronic devices;

[0016] Figure 6 It is based on the embodiments of this disclosure for determining the application to Figure 5 One or more intermediate frequency stage circuits of the transmitter to mitigate Figure 5 A flowchart of a method for setting one or more interference settings on a receiver;

[0017] Figure 7 This is a flowchart of a method for determining a set of transmitter settings for high-performance operation and a set of transmitter settings for an operable receiver, according to an embodiment of this disclosure.

[0018] Figure 8 Tables showing transmitter settings for high-performance operation and transmitter settings for an operable receiver according to embodiments of the present disclosure are illustrated; and

[0019] Figure 9 It is an implementation scheme according to this disclosure for operation Figure 5 A flowchart of a method for multiple radio systems. Detailed Implementation

[0020] One or more specific implementations will be described below. To provide a brief description of these implementations, not all characteristics of the actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, decisions must be made specific to many implementations to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints that may vary from one implementation to another. Furthermore, it should be understood that such development work can be complex and time-consuming, but will still be routine work of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0021] When describing elements of various embodiments of this disclosure, the articles “an” and “the” are intended to refer to one or more of the elements present. The terms “comprising,” “including,” and “having” are intended to be included and to indicate the presence of additional elements besides those listed. Additionally, it should be understood that reference to “an embodiment” or “an embodiment” of this disclosure is not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. Furthermore, specific features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. The use of the terms “generally,” “approximately,” “about,” “close to,” and / or “substantially” should be understood to mean including close to the target (e.g., design, value, quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.). Furthermore, it should be understood that any exact values, figures, measurements, etc. provided herein may be envisioned as approximations of such exact values, figures, measurements, etc. (e.g., within limits of suitable or conceivable error).

[0022] This disclosure relates to reducing noise output from a transceiver in a wireless communication device to reduce interference between one or more intermediate frequency (IF) stage circuits of the transceiver and one or more receivers in the wireless communication device. The wireless communication device can operate in any suitable radio frequency (RF) range, such as millimeter-wave (mmW) frequency ranges (e.g., 24.25 GHz to 300 GHz). For communication within the mmW frequency range, the wireless communication device may include one or more transceivers having one or more transmitters implemented using one or more stages of upconversion. The transmitter uses upconversion when the output frequency increases relative to the input frequency of the input signal. The input frequency may include a baseband frequency, and the output frequency may include RF. The transmitter can implement upconversion using one or more IF stage circuits, wherein each IF stage circuit may include a mixer, amplifier, and / or filter to convert a corresponding input frequency of a corresponding input signal to a correspondingly higher output frequency.

[0023] However, the one or more intermediate frequency (IF) stage circuits of the transmitter may operate at the same or similar frequencies as one or more receivers in the mobile communication device (e.g., within a threshold frequency range), or cause spurious emissions at the same or similar frequencies as one or more receivers in the mobile communication device. This can cause interference to the one or more receivers and impair their functionality. To prevent such interference, hardware solutions may include inserting additional filters and / or shielding into the mobile communication device to protect the one or more receivers from noise. However, these hardware solutions increase the additional cost and complexity of the mobile communication device.

[0024] The currently disclosed implementations can reduce interference to one or more receivers of a wireless communication device without increasing the hardware cost or complexity of the mobile communication device. In some implementations, reducing the gain value of one or more intermediate frequency (IF) stage circuits can reduce interference to the one or more receivers. Additionally, improving the linearity of one or more IF stage circuits can reduce the spurious noise spectrum at the output of each IF stage circuit, where linearity can refer to the ability of a corresponding amplifier circuit of the respective IF stage circuit to produce an output signal similar to the input signal. Amplifier circuits with a smaller linearity range have a greater likelihood of producing spurious emissions that can affect the one or more receivers. In some cases, these implementations can be implemented simultaneously. The gain value and / or linearity value of each of the one or more IF stage circuits at a given frequency (e.g., 2.4 GHz) can be stored in memory and referenced when the one or more receivers are operational.

[0025] Figure 1 This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. Among other things, the electronic device 10 may include one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry), memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuitry), software elements (including machine-executable instructions), or combinations of hardware and software elements (which may be referred to as logic). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., via or through another component, communication bus, network) to transmit and / or receive data between them. It should be noted that... Figure 1 This is merely one example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0026] For example, electronic device 10 may include any suitable computing device, including desktop computers or laptops (e.g., those available from Apple Inc., Cupertino, California). Pro, MacBook mini or Mac (in the form of) portable electronic devices or handheld electronic devices such as wireless electronic devices or smartphones (e.g., available from Apple Inc. in Cupertino, California). (Model form), tablet computers (for example, those available from Apple in Cupertino, California) (in the form of a model), wearable electronic devices (e.g., Apple products available from Apple Inc. in Cupertino, California) (in the form of) and other similar devices. It should be noted that, Figure 1 The processor 12 and other related items herein may be generally referred to as "data processing circuitry". This data processing circuitry may be embodied wholly or partially in software, hardware, or both. Furthermore, the processor 12 and... Figure 1 Other related items may be a single, independent processing module, or may be incorporated, wholly or partially, into any of the other elements within the electronic device 10. Processor 12 may be implemented using a combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gated logic, discrete hardware components, dedicated hardware finite state machine, or any other suitable entity capable of performing computation or other manipulations of information. Processor 12 may include one or more application processors, one or more baseband processors, or both, and performs the various functions described herein.

[0027] exist Figure 1 In the electronic device 10, a processor 12 may be operatively coupled to a memory 14 and a non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article of writing comprising one or more tangible computer-readable media. The tangible computer-readable media may include the memory 14 and / or the non-volatile storage device 16, individually or jointly, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article of writing for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disk drive, and optical disk. Furthermore, programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by the processor 12 to enable the electronic device 10 to provide various functions.

[0028] In some embodiments, display 18 may facilitate a user's viewing of images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen that facilitates user interaction with the user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0029] The input structure 22 of electronic device 10 allows a user to interact with electronic device 10 (e.g., press a button to increase or decrease the volume level). Like network interface 26, I / O interface 24 enables electronic device 10 to interact with a variety of other electronic devices. In some embodiments, I / O interface 24 may include I / O ports for hardwired connections for charging and / or content manipulation using standard connectors and protocols such as the Lightning connector supplied by Apple Inc. of Cupertino, California, Universal Serial Bus (USB), or other similar connectors and protocols. Network interface 26 may include one or more interfaces, for example, for personal area networks (PANs) such as Ultra Wideband (UWB) or... Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN) such as a protocol using one of the IEEE 802.11x series protocols (e.g., Networks; and / or wide area networks (WANs) such as any standards related to the 3rd Generation Partnership Project (3GPP), including, for example, third-generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), fourth-generation (4G) cellular networks, Long Term Evolution (LTE) networks. Cellular networks, Long Term Evolution License Assisted Access (LTE-LAA) cellular networks, fifth-generation (5G) cellular networks and / or New Radio (NR) cellular networks, satellite networks, etc. Specifically, network interface 26 may include, for example, one or more interfaces for using version 15 cellular communication standards of the 5G specification, including millimeter wave (mm Wave) frequency ranges (e.g., 24.25 GHz - 300 GHz), and / or any other cellular communication standard version (e.g., version 16, version 17, any future version) that defines and / or implements frequency ranges for wireless communication. Network interface 26 of electronic device 10 may allow communication via the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0030] Network interface 26 may also include one or more interfaces for, for example, a broadband fixed wireless access network (e.g., Mobile broadband wireless network (mobile) Asynchronous digital subscriber lines (e.g., ADSL, VDSL) and digital video terrestrial broadcasting Network and its extensions DVB handheld Networks, ultra-wideband (UWB) networks, AC power lines, etc.

[0031] As shown, network interface 26 may include transceiver 30. In some embodiments, all or part of transceiver 30 may be located within processor 12. Transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas, and therefore may include both a transmitter and a receiver. Power supply 29 for electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter. In some embodiments, electronic device 10 may take the form of a computer, portable electronic device, wearable electronic device, or other type of electronic device.

[0032] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic device 10. As shown, processor 12, memory 14, transceiver 30, transmitter 52, receiver 54 and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) may be directly or indirectly communicatively coupled to each other (e.g., through or via another component, communication bus, network) to transmit and / or receive data between each other.

[0033] Electronic device 10 may include transmitter 52 and / or receiver 54, which respectively enable the transmission and reception of data between electronic device 10 and external devices via, for example, a network (e.g., including a base station) or a direct connection. As shown, transmitter 52 and receiver 54 may be combined into transceiver 30. Electronic device 10 may also have one or more antennas 55A to 55N electrically coupled to transceiver 30. Antennas 55A-55N may be configured in omnidirectional or directional configurations, single-beam, dual-beam, or multi-beam arrangements, etc. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in antennas 55A-55N of an antenna group or module may be communicatively coupled to a respective transceiver 30 and each transmits radio frequency signals that can be advantageously and / or destructively combined to form a beam. Applicable to various communication standards, electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas. In some implementations, transmitter 52 and receiver 54 may transmit and receive information via other wired or wired systems or devices.

[0034] As shown in the figure, various components of electronic device 10 can be coupled together via bus system 56. Bus system 56 may include, for example, a data bus, as well as power buses, control signal buses, and status signal buses in addition to the data bus. Components of electronic device 10 can be coupled together or use some other mechanism to accept or provide input to each other.

[0035] As described above, the transceiver 30 of the electronic device 10 may include a transmitter and a receiver coupled to at least one antenna to enable the electronic device 10 to transmit and receive wireless signals. Figure 3 This is a block diagram of a transmitter 52 (e.g., a transmitting circuitry) that may be part of a transceiver 30 according to an embodiment of the present disclosure. As shown, the transmitter 52 may receive outgoing data 60 to be transmitted via one or more antennas 55 in the form of a digital signal. A digital-to-analog converter (DAC) 62 of the transmitter 52 may convert the digital signal into an analog signal, and a modulator 64 may combine the converted analog signal with a carrier signal to amplify the baseband frequency of the converted analog signal to radio frequency. A power amplifier (PA) 67 receives the radio frequency signal from the modulator 64 and may amplify the modulated signal to a suitable level to drive the transmission of the signal via one or more antennas 55. A filter 68 (e.g., filter circuitry and / or software) of the transmitter 52 may then remove unwanted noise from the amplified signal to generate the transmitted data 70 to be transmitted via one or more antennas 55. The filter 68 may include one or more suitable filters, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters, for removing unwanted noise from the amplified signal. Additionally, transmitter 52 may include any suitable additional components not shown, or may exclude some of the components shown, such that transmitter 52 can transmit data 60 via one or more antennas 55. For example, transmitter 52 may include one or more mixers and / or (e.g., digital up-conversion converters that facilitate the conversion of signals having a baseband frequency to signals having an radio frequency). Furthermore, if power amplifier 67 outputs the amplified signal within or substantially within the desired frequency range, then transmitter 52 may not include filter 68 (so that filtering of the amplified signal is unnecessary).

[0036] Figure 4This is a schematic diagram of a receiver 54 (e.g., receiving circuitry) that may be part of transceiver 30 according to an embodiment of this disclosure. As shown, receiver 54 may receive received data 80 from one or more antennas 55 in the form of an analog signal. A low-noise amplifier (LNA) 81 may amplify the received analog signal to a suitable level for processing by receiver 54. A filter 85 (e.g., filter circuitry and / or software) may remove unwanted noise, such as cross-channel interference, from the signal. Filter 85 may also remove additional signals received by one or more antennas 55 at frequencies other than the desired signal. Filter 85 may include one or more of any suitable filters for removing unwanted noise or signals from the received signal, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters. Demodulator 86 may remove the radio frequency envelope from the filtered signal and / or extract the demodulated signal from the filtered signal for processing. Analog-to-digital converter (ADC) 88 may receive the demodulated analog signal and convert it into a digital signal of incoming data 90 for further processing by electronics 10. Additionally, receiver 54 may include any suitable additional components not shown, or may exclude certain components shown, such that receiver 54 can receive received data 80 via one or more antennas 55. For example, receiver 54 may include one or more mixers and / or (e.g., digital downconverters that facilitate the conversion of an input signal with radio frequency to a baseband frequency).

[0037] In view of the above, Figure 5 A multi-radio system 100, comprising a transmitter 102 and a receiver 103, is illustrated according to an embodiment of the present disclosure. For example, the transmitter 102 may be coupled with... Figure 3 The transmitter 52 in the middle has similar components, and the receiver 103 can be connected to... Figure 4 The receiver 54 in the system has similar components. Furthermore, the transmitter 102 and receiver 103 may be located in the same transceiver. In additional or alternative embodiments, the transmitter 102 and receiver 103 may not be located in the same transceiver. In some embodiments, more than one receiver 103 may be present in the multiple radio system 100. The transmitter 102 may include one or more intermediate frequency (IF) stage circuits 104 (shown as 104A-104N, collectively referred to as IF stage circuits 104) (e.g., in modulator 64). Each IF stage circuit 104 converts an input signal having an input frequency to an output signal having a higher output frequency. As shown, the first IF stage circuit 104A may receive a signal having a first frequency 106A and convert the first frequency 106A to a higher output frequency 106B. Each IF stage circuit 104 may include one or more components (e.g., amplifier circuitry) including mixers, amplifiers, and / or filters to upconvert the frequency of the input signal to generate the output signal.

[0038] Furthermore, the first intermediate frequency (IF) stage circuit 104A can send an output signal with a second frequency 106B to the second IF stage circuit 104B. The second IF stage circuit 104B can convert the second frequency 106B to a higher output frequency and send the output signal to the next IF stage circuit. This operation can be repeated with any suitable number of higher output frequencies and IF stage circuits until a final higher output frequency 106N, which is the desired radio frequency and is converted by the final IF stage circuit 104N, is generated.

[0039] The final intermediate frequency stage circuit 104N can send the final output signal with RF 106N to the beamforming and RF output circuit 108. The beamforming and RF output circuit 108 can use the first set of antennas 110 (shown as 110A-110N, collectively referred to as the first set of antennas 110) to form an RF beam using beamforming technology.

[0040] Receiver 103 can receive incoming signals via a second set of antennas 112 (shown as 112A-112N, collectively referred to as the second set of antennas 112). In some embodiments, the incoming signal can be transmitted from an external device. Receiver 103 can receive signals at a specific frequency or frequency range. Receiver 103 may include a bandpass filter 116, a low-noise amplifier 118, and / or other processing circuitry (e.g., a demodulator 86, an ADC 88, a mixer 82, and / or a VCO 84), thus allowing the bandpass filter 116 to filter the received signal, the low-noise amplifier 118 to amplify the received signal, and the demodulator 86 to demodulate the received signal, etc. Receiver 103 can transmit signals to one or more components of electronic device 10, such as processor 12.

[0041] As described above, receiver 103 in the multi-radio system 100 can operate on a designated frequency 106. An intermediate frequency (IF) stage circuit in the intermediate frequency (IF) stage circuit 104 can operate on the same or overlapping frequency as the designated frequency 106 on which receiver 103 operates. This can result in interference 120 between the IF stage circuit 104 and receiver 103. For example, receiver 103 can receive signals at 2.4 GHz. In some embodiments, a first IF stage circuit 104A can output a signal at the same frequency of 2.4 GHz. This can cause the signal output by the first IF stage circuit 104A to interfere with (e.g., introduce noise) the received signal and / or the functionality of receiver 103. Since both the first IF stage circuit 104A and receiver 103 operate at a frequency of 2.4 GHz, this type of interference can be referred to as a “coupled” channel.

[0042] In another example, the first intermediate frequency stage circuit 104A may output a signal with a frequency of 1.9 GHz. In some cases, the output signal may cause spurious emissions at desired frequencies such as 2.4 GHz, thus interfering with the received signal and / or the function of receiver 103. This type of interference may be referred to as "out-of-band" interference. Each type of interference can cause different levels of interference (e.g., noise) in or near the frequency channel used by receiver 103.

[0043] As described above, interference 120 (e.g., noise) introduced by one or more intermediate frequency stage circuits 104 can affect the functionality of receiver 103, such as the sensitivity of receiver 103. That is, interference 120 at or around the frequency at which each receiver 103 operates can affect the strength or quality of the signal received at receiver 103. However, interference 120 introduced by one or more intermediate frequency stage circuits 104 can be mitigated by modifying one or more operating characteristics of each intermediate frequency stage circuit 104.

[0044] In view of the above, Figure 6 This is a flowchart of a method 130 for determining one or more operating characteristics of the intermediate frequency stage circuitry 104 of transmitter 102 to mitigate the effects of interference on receiver 103, according to this embodiment. Method 130 can be performed by any suitable component (e.g., a processor) (such as processor 12 of electronic device 10) that controls the components of the multi-radio system 100. In some embodiments, method 130 can be implemented by using processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14 or storage device 16. Although method 130 is described using steps in a specific order, it should be understood that this disclosure contemplates that the steps described may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0045] At block 132, processor 12 may select or determine one or more intermediate frequency (IF) stage circuits 104 of transmitter 102 of electronic device, which output one or more frequencies 106 that interfere with signals received by receiver 103 of electronic device. Memory 14 and / or storage device 16 may store (e.g., in a table) predetermined frequencies 106 output by IF stage circuits 104, as well as frequencies of spurious emissions caused by IF stage circuits 104. The frequencies 106 output by each IF stage circuit 104 may be compared with frequencies 106 that each receiver 103 in the multiple radio system 100 is configured to receive to determine which signals output by the one or more IF stage circuits 104 of transmitter 102 may cause interference 120.

[0046] At block 134, processor 12 may use one or more settings to adjust one or more operating characteristics of one or more intermediate frequency (IF) stage circuits 104 to reduce interference with signals received by each receiver 103. These one or more settings may include values ​​for modifying one or more operating characteristics, which may include the gain value and / or linearity of each IF stage circuit 104 of transmitter 102. That is, each IF stage circuit 104 can amplify a signal having an input frequency by converting it into an output signal having a higher output frequency by amplifying the signal based on the gain value. The gain value may indicate the increase in amplitude experienced by the signal as it passes through the corresponding IF stage circuit 104 and may be expressed in decibels (dB). Additionally, processor 12 may improve the linearity of one or more components (e.g., amplifier circuits) of each IF stage circuit 104. As described above, linearity may refer to the ability of an amplifier circuit to produce an output signal similar to the input signal. For example, processor 12 may adjust the bias voltage supplied to the amplifier circuit to modify its linearity. It should be noted that the processor 12 may adjust or modify other suitable settings of each intermediate frequency stage circuit 104 to reduce interference with the received signal.

[0047] Noise generated in the received signal can be reduced by decreasing the gain value of the corresponding intermediate frequency (IF) stage circuit 104. Advantageously, the reduced gain value in the first IF stage circuit 104 can be compensated by increasing the gain value in another IF stage circuit 104. For example, when the first IF stage circuit 104A interferes with the corresponding receiver 103, the gain value of the first IF stage circuit 104A can be reduced. To compensate, the gain value of the second IF stage circuit 104B can be increased. It should be noted that the reduced gain value in one or more IF stage circuits 104 can be compensated by modifying the gain value of any one of the IF stage circuits 104.

[0048] Furthermore, the linearity of each intermediate frequency stage circuit 104 can be increased to reduce the spurious noise spectrum at the output of each intermediate frequency stage circuit 104. To increase linearity, the bias voltage supplied to the one or more components (e.g., amplifiers, mixers, and / or filters) of each intermediate frequency stage circuit 104 can be increased.

[0049] To determine the one or more settings, including values ​​for the one or more operating characteristics, to reduce interference, each receiver 103 and transmitter 102 in the multi-radio system 100 may operate simultaneously or synchronously. For example, with respect to multiple receivers 103, for each receiver 103 and / or each combination of receivers 103, a set of settings (e.g., one or more settings) to be applied to the transmitter 102 may be determined by: determining the level of interference experienced by the corresponding receiver 103, and modifying the set of settings (e.g., changing one or more operating characteristics of the transmitter 102) until the signal-to-noise ratio of the received signal is below a threshold. The threshold may be predetermined based on the acceptable amount of noise for each receiver 103 to accurately receive (e.g., with sufficient signal power and / or quality) a signal. When each receiver 103 is operational, the one or more settings may specifically affect the gain value and / or linearity of each intermediate frequency stage circuit 104. It should be noted that when the corresponding receiver 103 is operational, the processor 12 may apply the one or more settings to the transmitter 102. In some implementations, the processor 12 may manually or periodically (e.g., weekly, monthly, bi-monthly, annually, etc.) determine the group of one or more settings to be updated.

[0050] At block 136, processor 12 may store the one or more settings to be applied to one or more intermediate frequency stage circuits 104. Processor 12 may store the one or more settings in any suitable data structure (e.g., memory 14 and / or storage device 16) accessible during operation of the multi-radio system 100. Thus, method 130 enables processor 12 to generate settings to be applied to transmitter 102 to reduce interference to receiver 103.

[0051] When no receiver 103 operates at the frequency output by one or more intermediate frequency circuits 104, or when there are no spurious emissions generated by one or more intermediate frequency circuits 104 of transmitter 102, the one or more intermediate frequency circuits 104 of transmitter 102 can transmit signals using high-performance settings. That is, when transmitter 102 is free to transmit without generating interference 120 to receiver 103, an additional set of settings can be determined in addition to those generated by method 130. These settings may be referred to as "high-performance" settings because transmitter 102 is free to use increased or maximum transmit power, since the transmitted signal may not generate interference 120 to receiver 103.

[0052] In view of the above, Figure 7This is a flowchart of a method 140 for determining one or more settings of transmitter 102 during operation with and without an operable receiver 103, according to a current embodiment. For example, method 140 may be performed during initial testing of electronic device 10 (e.g., at a manufacturing facility, in a test environment, etc.). Any suitable component controlling the parts of the multi-radio system 100 (e.g., a processor) (such as processor 12 of electronic device 10) may perform method 140. In some embodiments, method 140 may be implemented by using processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14 or storage device 16. While method 140 is described using steps in a specific order, it should be understood that this disclosure contemplates that the described steps may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0053] At block 142, processor 12 may initialize the cellular and / or RF functions of the multiple radio system 100. Processor 12 may receive an instruction requesting cellular and / or RF functions from an application running on electronic device 10. At block 144, processor 12 and / or first network layer software 141 may determine one or more settings for high-performance operation of transmitter 102. The first network layer may include one or more components of electronic device 10 capable of transmitting, receiving, and modifying signals (e.g., at least some portions of transceiver 30, transmitter 102, receiver 103, processor 12, etc.). First network layer software 141 may load (e.g., determined by processor 12) settings such as those for high-performance operation of transmitter 102, which correspond to pin layout, voltage, impedance, cable specifications, signal timing, and / or frequency of one or more components of the first network layer. These settings may be stored in memory (e.g., memory 14, storage device 16, etc.) and may be loaded by first network layer software 141 at a later time (e.g., during consumer runtime) to operate transmitter 102 under high performance.

[0054] High-performance operation can refer to the operation of transmitter 102 without generating interference to receiver 103 of the multiple radio system 100. In some embodiments, high-performance operation can be performed when no receiver 103 is operable in the multiple radio system 100. In other embodiments, high-performance operation can be performed when the operation of transmitter 102 does not interfere with operable receiver 103. That is, the operation of transmitter 102 may not interfere with operable receiver 103 when the signal transmitted by transmitter 102 and / or the spurious emissions generated by the transmitter signal have frequencies that are different from and / or do not overlap with the frequencies of operable receiver 103.

[0055] At block 146, processor 12 and / or first network layer software 141 may determine one or more settings of transmitter 102 to reduce interference to operable receiver 103. As described above, for receiver 103, the set of settings for modifying one or more operating characteristics of each intermediate frequency stage circuit 104 of transmitter 102 may be determined by: determining the level of interference experienced by operable receiver 103, and modifying one or more settings until the interference experienced by operable receiver 103 is greater than a signal-to-noise ratio threshold. Thus, method 140 enables processor 12 and / or first network layer software 141 to determine one or more settings for high performance of transmitter 102 and / or operation of receiver 103 utilizing multi-radio system 100.

[0056] As described above, these one or more settings can be stored in any suitable memory 14 or storage device 16 of the electronic device 10. In view of the above, Figure 8 A table showing high-performance operation settings 150 and a table showing multi-receiver operation settings 158 are illustrated. The high-performance operation settings 150 and multi-receiver operation settings 158 may be stored in any suitable storage location within the electronic device 10 (e.g., memory 14, storage device 16). The high-performance operation settings 150 may correspond to settings for transmitter 102 and / or intermediate frequency stage circuitry 104 that result in high-performance operation (e.g., transmission does not interfere with receiver 103 at this time). The table showing high-performance operation settings 150 may include one or more columns, including transmitter power column 152, index column 154, and / or one or more intermediate frequency stage circuitry columns 156 (shown as 156A-156N, collectively referred to as intermediate frequency stage circuitry columns 156).

[0057] Transmitter power column 152 may include each power value provided to transmitter 102. It should be noted that each power value may be set by processor 12 based on the signal transmitted by transmitter 102. Index column 154 may include an index associating transmitter power 152 with settings of intermediate frequency (IF) stage circuitry 104, which may be implemented by the multi-radio system 100. That is, each index value may be associated with a desired transmitter power value listed in transmitter power column 152. One or more IF stage circuit columns 156 may include the one or more settings determined by method 140. That is, each IF stage circuit column 156 may include settings that generate gain values, bias voltages corresponding to desired linearity, and / or any other values ​​associated with noise generation aspects of each IF stage circuitry 104.

[0058] The multi-receiver operation setting 158 may correspond to the settings of the transmitter 102 and / or intermediate frequency (IF) stage circuitry 104 used when one or more receivers 103 are operable. Therefore, the multi-receiver operation setting 158 may be applied when the electronic device 10 operates in a coexistence mode (e.g., when both transmitter 102 and receiver 103 are operational and can “coexist” with each other). Thus, the multi-receiver operation setting 158 may also be referred to as a coexistence setting. The multi-receiver operation setting 158 may include one or more columns, including a transmitter power column 152, an index column 154, and / or one or more IF stage circuitry columns. As described above, the transmitter power column 152 may include power values ​​provided to the transmitter 102. The index column 154 may include an index that associates the transmitter power 152 with settings of the IF stage circuitry 104, which may be implemented by the multi-radio system 100. That is, each index value may be associated with a desired transmitter power value listed in the transmitter power column 152. The IF stage circuitry column 156 may include the one or more settings determined by method 140. In other words, each intermediate frequency stage circuit array 156 may include settings for generating gain values, bias voltages corresponding to desired linearity, and / or any other values ​​associated with noise generation aspects of each intermediate frequency stage circuit 104.

[0059] In view of the above, Figure 9 This is a flowchart of a method 169 for operating a multiple radio system 100 according to a present embodiment. Any suitable component (e.g., a processor) (such as processor 12) that controls the electronic device 10 and / or the multiple radio system 100 can perform method 169. In some embodiments, method 169 can be implemented by using processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14 or storage device 16. Although method 169 is described using steps in a specific order, it should be understood that this disclosure contemplates that the steps described may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0060] In some implementations, the application processor / host 171 may execute a first set of blocks 170 (174, 176, 178, 184) upon initiation of a cellular connection. Specifically, at block 174, the application processor / host 171 (which may be part of processing circuitry 12) may initiate a radio frequency (RF) connection and send a command to the baseband processor 172 (which may also be part of processing circuitry 12) to initiate the RF connection. The RF connection may include, for example, 5G connectivity in the millimeter-wave (mmWave) frequency range (e.g., 24.25 GHz to 300 GHz). The application processor / host 171 may manage software applications executing on the electronic device 10 and provide system resources to the applications. Thus, in some cases, applications may request RF functions of the electronic device 10 (e.g., messaging applications, internet applications, and / or any application that uses RF functions), and the application processor / host 171 may provide these functions through the baseband processor 172. The baseband processor 172 may manage the radio functions of the electronic device 10, including operating the transmitter 102 and receiver 103.

[0061] At block 176, baseband processor 172 may send an instruction to first network layer software 141 to initiate an RF connection. At block 178, first network layer software 141 may load high-performance operation settings 150. That is, first network layer software 141 may retrieve and load high-performance operation settings 150 (e.g., from memory 14, storage device 16, or any suitable storage location). For example, first network layer software 141 may determine a transmitter power value 180 corresponding to high-performance transmission and determine an index value from transmitter power column 152. First network layer software 141 may then transmit transmitter power value 180 to RF software (SW) 182. RF software 182 may configure the operating characteristics of the RF hardware (HW) of electronic device 10 (e.g., transmitter 102, receiver 103, and / or other components of multi-radio system 100). RF software 182 can retrieve an index value 154 associated with a transmitter power value 180 from high-performance operating settings 150, and use index value 154 to retrieve one or more settings 156 of the intermediate frequency stage circuitry 104 of transmitter 102. At block 184, RF software 182 can (e.g., prior to operation of receiver 103) configure each intermediate frequency stage circuitry 104 (e.g., RF hardware) of transmitter 102 in the multi-radio system 100 based on one or more retrieved settings 156 from the intermediate frequency stage circuitry 104 of high-performance operating settings 150. It should be noted that the first network layer software 141 and / or RF software 182 can be executed by processing circuitry 12 (e.g., including application processor 171 and / or baseband processor 172).

[0062] In some embodiments, the baseband processor 172 may determine the operating mode of the receiver 103. That is, the baseband processor 172 may determine whether the receiver 103 is in a first operating mode, wherein the first operating mode is associated with the receiver 103 being operable. In some embodiments, the first operating mode may be associated with the receiver 103 operating at a frequency overlapping with one or more frequencies 106 of the output signal of one or more intermediate frequency stage circuits 104. In additional or alternative embodiments, the first operating mode may be associated with the receiver 103 operating at a frequency overlapping with the frequency of spurious emissions generated by the output signal of one or more intermediate frequency stage circuits 104.

[0063] Furthermore, the baseband processor 172 can also indicate whether the receiver is in a second operating mode, which is associated with the receiver being inoperable. In some embodiments, the second operating mode may be associated with the receiver 103 operating at a frequency that does not overlap with one or more frequencies 106 of the output signals of one or more intermediate frequency stage circuits 104. In additional or alternative embodiments, the second operating mode may be associated with the receiver 103 operating at a frequency that does not overlap with the frequencies of spurious emissions generated by the output signals of one or more intermediate frequency stage circuits 104. The baseband processor 172 may send indications of the operating mode of the receiver 103 to the first network layer software 141 and the RF software 182.

[0064] That is, in some embodiments, the application processor / host 171 may execute a second set of blocks 185 (186, 188, 190, 192, 194, 196) when it determines that the receiver 103 (e.g., a radio different from the radio of transmitter 102) is operable. Thus, the electronic device 10 can operate in a coexistence mode, such that multiple radios of the multi-radio system 100 (e.g., including transmitter 102 and receiver 103) are operational. Therefore, in such embodiments, the application processor / host 171 may proceed from block 182 to block 186, where the baseband processor 172 may determine that the receiver 103 is operable. That is, the application processor / host 171 may determine which receivers 103 to operate based on the established RF connection. In some embodiments, the baseband processor 172 may determine that the receiver 103 is operable based on commands received from the application processor / host 171.

[0065] At block 188, baseband processor 172 can determine whether one or more intermediate frequency (IF) stage circuits 104 generate interference affecting receiver 103. The generated interference affecting receiver 103 can be determined based on the frequency overlap of the transmitter signal and / or spurious emissions generated by transmitting the transmitter signal. In some embodiments, baseband processor 172 can determine whether the generated interference affects receiver 103 based on the frequency schedule of transmitter 102. If baseband processor 172 determines that one or more IF stage circuits 104 generate interference affecting receiver 103, then at block 190, first network layer software 141 can load multi-receiver operation settings 158.

[0066] In other words, the first network layer software 141 can retrieve and load the multi-receiver operation settings 158 (e.g., from memory 14, storage device 16, or any suitable storage location). For example, the first network layer software 141 can determine a transmitter power value 180 corresponding to transmission when one or more receivers 103 are operational, and determine an index value from the transmitter power column 152. The first network layer software 141 can then transmit the transmitter power value 180 to the RF software (SW) 182. The RF software 182 can retrieve an index value 154 associated with the transmitter power value 180 from the multi-receiver operation settings 158, and use the index value 154 to retrieve one or more settings 156 of the intermediate frequency stage circuits 104 of the transmitter 102. At block 192, the RF software 182 can configure each intermediate frequency stage circuit 104 (e.g., RF hardware) in the transmitter 102 of the multi-radio system 100 based on one or more retrieved settings 156 from the intermediate frequency stage circuits 104 of the multi-receiver operation settings 158.

[0067] If the baseband processor 172 determines that one or more intermediate frequency stage circuits 104 do not generate interference affecting the receiver 103, then at block 194, the first network layer software 141 may load high-performance operation settings 150. That is, the first network layer software 141 may retrieve and load high-performance operation settings 150 (e.g., from memory 14, storage device 16, or any suitable storage location). For example, the first network layer software 141 may determine a transmitter power value 180 corresponding to high-performance transmission and determine an index value from the transmitter power column 152. The first network layer software 141 may then transmit the transmitter power value 180 to the RF software (SW) 182. The RF software 182 may retrieve an index value 154 associated with the transmitter power value 180 from the high-performance operation settings 150 and use the index value 154 to retrieve one or more settings 156 of the intermediate frequency stage circuits 104 of the transmitter 102. At box 196, RF software 182 can configure each intermediate frequency stage circuit 104 in the transmitter 102 of the multi-radio system 100 based on one or more retrieved settings 156 from the intermediate frequency stage circuit 104 of the high-performance operation settings 150.

[0068] In some implementations, the application processor / host 171 may execute a third set of blocks 197 (198, 194, 196) when it determines that the receiver 103 (e.g., a radio different from the transmitter 102's radio) is no longer operational. That is, the electronics 10 may exit operation in coexistence mode, leaving the transmitter 102 operational but the receiver 103 inoperable. Therefore, in such implementations, the application processor / host 171 may advance from block 192 to block 198, where the baseband processor 172 may determine that the receiver 103 is inoperable in the multi-radio system 100. In some implementations, at block 198, the baseband processor 172 may determine that the receiver 103 is operational, but the receiver 103's frequency does not overlap with interference caused by the transmitter signal and / or spurious emissions generated by the transmitter signal. The baseband processor 172 may follow a similar decision process when one or more intermediate frequency stage circuits 104 do not generate interference affecting the receiver 103. The first network layer software 141 can load the high-performance operation settings 150. That is, the first network layer software 141 can retrieve and load the high-performance operation settings 150 (e.g., from memory 14, storage device 16, or any suitable storage location). For example, the first network layer software 141 can determine a transmitter power value 180 corresponding to high-performance transmission and determine an index value from the transmitter power column 152. The first network layer software 141 can then transmit the transmitter power value 180 to the RF software (SW) 182. The RF software 182 can retrieve an index value 154 associated with the transmitter power value 180 from the high-performance operation settings 150 and use the index value 154 to retrieve one or more settings 156 of the intermediate frequency stage circuits 104 of the transmitter 102. At block 196, the RF software 182 can configure each intermediate frequency stage circuit 104 of the transmitter 102 in the multiple radio system 100 based on one or more retrieved settings 156 from the intermediate frequency stage circuits 104 of the high-performance operation settings 150. Thus, method 169 enables electronic device 10, processor 12, first network layer software 141 and / or RF software 182 to reduce interference when the signal transmitted by transmitter 102 and / or spurious emissions generated by the transmitter signal have the same and / or overlapping frequencies as the signal received by receiver 103 in the multi-radio system 100.

[0069] The specific embodiments described above have been illustrated by way of example, and it should be understood that various modifications and alternatives are permissible. It should also be understood that the claims are not intended to limit us to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0070] The techniques described herein and protected by the claims are referenced and applied to specific examples of physical and practical nature that significantly improve the technical field and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function]..." or "steps for [performing] [function]...", those elements shall be interpreted in accordance with 35 USC112(f). However, for any claim containing elements designated in any other manner, those elements shall not be interpreted in accordance with 35 USC112(f).

[0071] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. A method for wireless communication, comprising: The processing circuitry of the electronic device determines the interference between a signal received by the receiver and one or more intermediate frequency signals from the transmitter of the electronic device based on the simultaneous operation of the transmitter and receiver of the electronic device; One or more intermediate frequency stage circuits of the transmitter are selected by the processing circuit to output one or more intermediate frequency signals that cause interference to the signal received by the receiver; The processing circuitry adjusts one or more operating characteristics of the one or more intermediate frequency stage circuits based on at least one or more settings to reduce interference to the signal received by the receiver; as well as The processing circuit stores the one or more settings to be applied to the one or more intermediate frequency stage circuits in response to determining that the receiver is operable.

2. The method of claim 1, wherein the one or more intermediate frequency stage circuits comprise one or more filters, one or more amplifiers, one or more mixers, or any combination thereof.

3. The method of claim 2, wherein the one or more intermediate frequency stage circuits include the one or more amplifiers, and the one or more operating characteristics include the gain level, linearity, or both of the one or more amplifiers.

4. The method of claim 1, wherein adjusting the one or more operating characteristics of the one or more intermediate frequency stage circuits by the processing circuit includes decreasing a first gain level of the first intermediate frequency stage circuit and increasing a second gain level of the second intermediate frequency stage circuit.

5. The method of claim 1, wherein the processing circuitry adjusts the one or more operating characteristics to reduce the interference causing the signal-to-noise ratio of the signal received by the receiver to be below a threshold.

6. The method of claim 1, further comprising determining the intermediate frequency of each intermediate frequency signal by the processing circuitry before selecting the one or more intermediate frequency stage circuits.

7. An electronic device, comprising: A transceiver, comprising a transmitter and a plurality of receivers, the transmitter comprising one or more intermediate frequency stage circuits; and Processing circuitry, coupled to the transceiver, is configured to perform the following operations: Interference between the signal received by the receiver and one or more intermediate frequency signals from the transmitter of the electronic device is determined based on the simultaneous operation of the transmitter and one of the receivers among the plurality of receivers. At least one intermediate frequency (IF) stage circuit of the transmitter is selected to output one or more IF signals that cause interference to the signals received by the receivers among the plurality of receivers. The operating characteristics of one or more intermediate frequency stage circuits are adjusted based on at least one or more settings to reduce interference with the signal received by the receiver. In response to determining that the receiver is operable, the one or more settings to be applied to the at least one intermediate frequency stage circuit are stored.

8. The electronic device of claim 7, wherein the processing circuitry is configured to receive the desired transmit power of the transmitter based on the operating mode of each of the plurality of receivers.

9. The electronic device of claim 8, wherein the processing circuitry is configured to receive an index value based on the desired transmit power of the transmitter.

10. The electronic device of claim 9, wherein the processing circuit is configured to adjust one or more operating characteristics of the at least one intermediate frequency stage circuit based on the index value.

11. The electronic device of claim 7, wherein the one or more intermediate frequency stage circuits comprise one or more filters, one or more amplifiers, one or more mixers, or any combination thereof.

12. The electronic device of claim 11, wherein the one or more intermediate frequency stage circuits include the one or more amplifiers, and the one or more operating characteristics include the gain level, linearity, or both of the one or more amplifiers.

13. The electronic device of claim 7, wherein adjusting the one or more operating characteristics of the at least one intermediate frequency stage circuit by the processing circuit includes decreasing a first gain level of the first intermediate frequency stage circuit and increasing a second gain level of the second intermediate frequency stage circuit.

14. The electronic device of claim 13, wherein the increase in the second gain level of the second intermediate frequency stage circuit at least partially compensates for the decrease in the first gain level of the first intermediate frequency stage circuit.

15. The electronic device of claim 7, wherein adjusting the one or more operating characteristics to reduce the interference causes the signal-to-noise ratio of the signal received by the receiver to be below a threshold.

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