Signal generation circuit, chip and signal generation method

Abstract

The application discloses a signal generation circuit, a chip and a signal generation method. The circuit comprises: a voltage division unit for dividing a power supply voltage to generate a first comparison signal; a selection unit for outputting second comparison signals of different sizes; and a comparator unit for outputting a representation signal representing whether a target signal is established based on comparison between the target signal or the second comparison signal and the first comparison signal. According to the signal generation circuit, the chip and the signal generation method, the comparator unit compares the target signal or the second comparison signal generated under the control of the first comparison signal with the first comparison signal varying with the power supply voltage, and outputs the representation signal representing that the target signal is established when the power supply voltage rises to a stable state, so that the representation signal can be accurately generated in the process of rising of the power supply voltage, and the problem that the representation signal is randomly generated in the process of rising of the power supply voltage due to the change of the flip threshold of the POR circuit is solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a signal generation circuit, chip, and signal generation method. Background Technology

[0002] In analog chip design, a reference voltage generation circuit, Bandgap, is often required to provide a reference voltage for internal modules (typically UVLO and OTP). However, a BGOK signal indicating successful reference voltage establishment is also needed to control the startup timing of each module using the reference voltage, preventing modules from starting up before the reference voltage is established or before it is stable, which would disrupt the overall system timing of the chip.

[0003] The usual method for generating the BGOK indicator signal is to use a POR (Power-On Reset) circuit to detect the operating power supply voltage VDD of the Bandgap reference voltage generation circuit. When VDD > the upper threshold of the POR flip, the BGOK indicator signal is high, indicating that the reference voltage has been established. When VDD < the lower threshold of the POR flip, the BGOK indicator signal is low, indicating that the reference voltage has not yet been established.

[0004] Using a POR (Power-On Reversal) circuit for detection, the POR switching threshold often varies significantly with process technology and temperature. Based on different switching thresholds, the characterization signal BGOK will be established at either high or low power supply voltage VDD during power-on, introducing considerable uncertainty. If the system can tolerate a relatively large range of power supply voltage VDD when the characterization signal BGOK is established, then implementing the characterization signal BGOK using POR is simple and inexpensive. However, in some applications, a more precise characterization signal BGOK is required, meaning the characterization signal BGOK must switch precisely when the power supply voltage VDD changes to a desired value. In such cases, the POR implementation method is definitely insufficient.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a signal generation circuit that can generate a highly accurate characterization signal BGOK in response to changes in power supply voltage.

[0007] To achieve the above objectives, embodiments of the present invention provide a signal generation circuit, including: a voltage divider unit, a selection unit, and a comparator unit.

[0008] The voltage divider unit is connected to the power supply voltage and the ground voltage, and is used to divide the power supply voltage to generate a first comparison signal; the selection unit is connected to the power supply voltage and the ground voltage, and is used to output second comparison signals of different magnitudes based on the control of the first comparison signal; the comparator unit has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of the comparator unit is used to receive the second comparison signal, the second input terminal of the comparator unit is used to receive the target signal, the third input terminal of the comparator unit is used to receive the first comparison signal, and the output terminal of the comparator unit outputs a characterization signal to characterize whether the target signal is established based on the comparison result between the selected second comparison signal or the target signal and the first comparison signal.

[0009] In one or more embodiments of the present invention, the voltage divider unit includes a first resistor unit and a second resistor unit, a first terminal of the first resistor unit is connected to a power supply voltage, a second terminal of the first resistor unit is connected to the first terminal of the second resistor unit to output a first comparison signal, and a second terminal of the second resistor unit is connected to ground voltage.

[0010] In one or more embodiments of the present invention, the selection unit includes a pull-up unit and a pull-down unit, the pull-up unit and the pull-down unit are connected to output a second comparison signal, the pull-up unit pulls up the second comparison signal under the control of the first comparison signal, and the pull-down unit turns on the pull-down of the second comparison signal under the control of the first comparison signal.

[0011] In one or more embodiments of the present invention, the pull-up unit includes a resistor.

[0012] In one or more embodiments of the present invention, the pull-down unit includes a first MOS transistor, the gate of the first MOS transistor is used to receive a first comparison signal, the drain of the first MOS transistor is connected to the pull-up unit, and the source of the first MOS transistor is connected to ground voltage.

[0013] In one or more embodiments of the present invention, the pull-down unit further includes a second MOS transistor or a diode, wherein the gate and drain of the second MOS transistor are connected and simultaneously connected to the pull-up unit, the source of the second MOS transistor is connected to the drain of the first MOS transistor, the anode of the diode is connected to the pull-up unit, and the cathode of the diode is connected to the drain of the first MOS transistor.

[0014] In one or more embodiments of the present invention, the comparator unit includes a first current mirror unit, a second current mirror unit, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, and a flip-delay unit;

[0015] The gate of the third MOS transistor is used to receive the second comparison signal, the gate of the fourth MOS transistor is used to receive the target signal, and the gate of the fifth MOS transistor is used to receive the first comparison signal. The drains of the third and fourth MOS transistors are connected and simultaneously connected to the first current mirror unit. The drain of the fifth MOS transistor is connected to the first current mirror unit. The sources of the third, fourth, and fifth MOS transistors are connected to the second current mirror unit. The source of the sixth MOS transistor is connected to the power supply voltage. The gate of the sixth MOS transistor is connected to the drain of the fifth MOS transistor. The drain of the sixth MOS transistor is connected to the second current mirror unit and the toggle delay unit. The toggle delay unit is used to toggle and delay the signal output by the comparator unit.

[0016] In one or more embodiments of the present invention, the flip delay unit includes a first inverter, a second inverter, and a delay unit. The input terminal of the first inverter is connected to the drain of a sixth MOS transistor. The input terminal of the delay unit is connected to the output terminal of the first inverter. The output terminal of the delay unit is connected to the input terminal of the second inverter. The output terminal of the second inverter is used to output a characterization signal.

[0017] The present invention also discloses a chip including the signal generation circuit described above. The chip further includes a bandgap reference circuit and / or an undervoltage lockout circuit. The second input terminal of the comparator unit is used to receive a reference voltage signal generated by the bandgap reference circuit and / or an undervoltage lockout signal from the undervoltage lockout circuit.

[0018] The present invention also discloses a signal generation method, comprising:

[0019] Acquire the first comparison signal that varies with the power supply voltage;

[0020] The selection unit acquires second comparison signals of different magnitudes based on the control of the first comparison signal;

[0021] The comparator unit selects either the second comparison signal or the target signal based on the magnitudes of the second comparison signal and the target signal to compare with the first comparison signal, and outputs a characterization signal to characterize whether the target signal has been established.

[0022] Compared with existing technologies, the signal generation circuit, chip, and signal generation method according to embodiments of the present invention compare a target signal or a second comparison signal generated under the control of a first comparison signal with a first comparison signal that varies with the power supply voltage through a comparator unit. When the power supply voltage rises to a point where the target signal has stabilized, a characterization signal indicating that the target signal has stabilized is output. This allows for precise generation of the characterization signal as the power supply voltage rises, solving the problem of random generation of the characterization signal due to changes in the switching threshold of the POR circuit during power supply voltage increases. This ensures the timing of subsequent system operation. Furthermore, precise generation of the characterization signal allows the chip to start operating at lower power supply voltages, broadening the chip's application range. Simultaneously, this circuit can also be applied to UVLO (Undervoltage Lockout) circuits. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of a signal generation circuit according to an embodiment of the present invention.

[0024] Figure 2 This is a flowchart of a signal generation method according to an embodiment of the present invention. Detailed Implementation

[0025] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0026] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0027] like Figure 1 As shown, a signal generation circuit includes: a voltage divider unit 10, a selection unit 20, and a comparator unit 30.

[0028] The voltage divider unit 10 is connected to the power supply voltage VDD and the ground voltage. The voltage divider unit 10 is used to divide the power supply voltage VDD to generate the first comparison signal VDIV.

[0029] Selection unit 20 is connected to power supply voltage VDD and ground voltage. Selection unit 20 is used to control the output of a second comparison signal VM of different magnitudes based on the first comparison signal VDIV.

[0030] Comparator unit 30 has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of comparator unit 30 is used to receive a second comparison signal VM, the second input terminal is used to receive a target signal VREF, and the third input terminal is used to receive a first comparison signal VDIV. The output terminal of comparator unit 30 outputs a characterization signal BGOK, which characterizes whether the target signal VREF is established, based on the comparison result between the selected second comparison signal VM or the target signal VREF and the first comparison signal VDIV. In this embodiment, the target signal VREF is provided by a bandgap reference circuit, i.e., comparator unit 30 outputs a characterization signal BGOK, which characterizes whether the reference voltage of the bandgap reference circuit Bandgap is established. In other embodiments, the target signal VREF can be a reference voltage provided by an undervoltage lockout circuit, i.e., comparator unit 30 outputs a characterization signal BGOK, which characterizes whether the undervoltage lockout reference voltage signal of the undervoltage lockout circuit is established.

[0031] like Figure 1 As shown, the voltage divider unit 10 includes a first resistor unit and a second resistor unit. The first end of the first resistor unit is connected to the power supply voltage VDD, and the second end of the first resistor unit is connected to the first end of the second resistor unit to output a first comparison signal VDIV. The second end of the second resistor unit is connected to the ground voltage.

[0032] Both the first and second resistor units consist of one or more resistors connected in series and / or in parallel. In this embodiment, the first resistor unit consists of a first resistor R0, with its first terminal connected to the power supply voltage VDD and its second terminal connected to the second resistor unit to obtain the first comparison signal VDIV. The second resistor unit consists of a second resistor R1 and a third resistor R2 connected in series. The first terminal of the second resistor R1 is connected to the first terminal of the first resistor R0 in the first resistor unit, and the second terminal of the first resistor R0 is connected to the first terminal of the third resistor R2. The second terminal of the third resistor R2 is connected to ground. The number of first resistors R0, second resistors R1, and third resistors R2 is not specifically limited and can be increased or decreased as needed. The first comparison signal VDIV is formed by dividing the power supply voltage VDD using the first resistors R0, second resistors R1, and third resistors R2. The magnitude of the first comparison signal VDIV can be flexibly adjusted by adjusting the resistance values ​​of the first resistors R0, second resistors R1, and third resistors R2.

[0033] like Figure 1As shown, the selection unit 20 includes a pull-up unit and a pull-down unit. The pull-up unit and the pull-down unit are connected to output a second comparison signal VM. The pull-up unit pulls up the second comparison signal VM under the control of the first comparison signal VDIV, and the pull-down unit enables the pull-down of the second comparison signal VM under the control of the first comparison signal VDIV.

[0034] In this embodiment, the pull-up unit includes a fourth resistor R3. The first terminal of the fourth resistor R3 is connected to the power supply voltage VDD, and the second terminal of the fourth resistor R3 is connected to the pull-down unit to output the second comparison signal VM. The pull-down unit includes a first MOSFET MN1 and a second MOSFET MN0. The gate and drain of the second MOSFET MN0 are connected and simultaneously connected to the second terminal of the fourth resistor R3. The gate of the first MOSFET is used to receive the first comparison signal VDIV. The drain of the first MOSFET MN1 is connected to the source of the second MOSFET MN0, and the source of the first MOSFET is connected to ground.

[0035] In other embodiments, a diode can be used to replace the second MOSFET MN0, with the anode of the diode connected to the pull-up unit and the cathode of the diode connected to the drain of the first MOSFET MN1. In other embodiments, either the diode or the second MOSFET MN0 can be removed.

[0036] In this embodiment, both the first MOSFET MN1 and the second MOSFET MN0 are N-channel MOSFETs. In other embodiments, both the first MOSFET MN1 and the second MOSFET MN0 are P-channel MOSFETs. In this case, due to the change in the type of the first MOSFET MN1 and the second MOSFET MN0, the positions of the pull-up and pull-down units need to be swapped.

[0037] like Figure 1 As shown, the comparator unit 30 includes a first current mirror unit, a second current mirror unit, a third MOSFET MN3, a fourth MOSFET MN4, a fifth MOSFET MN5, a sixth MOSFET MP0, and a flip-out delay unit.

[0038] The gate of the third MOSFET MN3 is used to receive the second comparison signal VM, the gate of the fourth MOSFET MN4 is used to receive the target signal VREF, and the gate of the fifth MOSFET MN5 is used to receive the first comparison signal VDIV. The drains of the third MOSFET MN3 and the fourth MOSFET MN4 are connected and simultaneously connected to the first current mirror unit, and the drain of the fifth MOSFET MN5 is connected to the first current mirror unit. The sources of the third MOSFET MN3, the fourth MOSFET MN4, and the fifth MOSFET MN5 are connected to the second current mirror unit. The source of the sixth MOSFET MP0 is connected to the power supply voltage VDD, the gate of the sixth MOSFET MP0 is connected to the drain of the fifth MOSFET MN5, and the drain of the sixth MOSFET MP0 is connected to the second current mirror unit and the toggle delay unit. The toggle delay unit is used to toggle and delay the signal output by the comparator unit 30.

[0039] The first current mirror unit includes a seventh MOSFET MP1 and an eighth MOSFET MP2. The gates of the seventh MOSFET MP1 and the eighth MOSFET MP2 are connected, and the gate and drain of the seventh MOSFET MP1 are connected. The sources of the seventh MOSFET MP1 and the eighth MOSFET MP2 are connected and connected to the power supply voltage VDD. The drain of the seventh MOSFET MP1 is connected to the drains of the third MOSFET MN3 and the fourth MOSFET MN4, and the drain of the eighth MOSFET MP2 is connected to the drain of the fifth MOSFET MN5 and the gate of the sixth MOSFET MP0.

[0040] The second current mirror unit includes a ninth MOSFET MN2 and a tenth MOSFET MN6. The drain of the ninth MOSFET MN2 is connected to the source of the third MOSFET MN3, the fourth MOSFET MN4, and the fifth MOSFET MN5, and the source of the ninth MOSFET MN2 is connected to ground. The drain of the tenth MOSFET MN6 is connected to the drain of the sixth MOSFET MP0 and the flip-delay unit, and the source of the tenth MOSFET MN6 is connected to ground. The gates of the ninth MOSFET MN2 and the tenth MOSFET MN6 are connected and used to receive the control voltage VB to generate a bias current on the ninth MOSFET MN2 and the tenth MOSFET MN6 to provide to the comparator unit 30.

[0041] The flip-delay unit includes a first inverter INV1, a second inverter INV2, and a delay unit Delay. The input terminal of the first inverter INV1 is connected to the drain of the sixth MOSFET MP0 and the drain of the tenth MOSFET MN6. The input terminal of the delay unit Delay is connected to the output terminal of the first inverter INV1, and the output terminal of the delay unit Delay is connected to the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 is used to output the characterization signal BGOK.

[0042] In this embodiment, the first comparison signal VDIV determines the switching voltage of the comparator unit 30. When the power supply voltage VDD is slowly powered on, the characterization signal BGOK is initially low and the first MOS transistor MN1 is in the off state. The second comparison signal VM is pulled up to near the power supply voltage VDD by the fourth resistor R3. At this time, because the second comparison signal VM is greater than the first comparison signal VDIV, the characterization signal BGOK output by the comparator unit 30 is low.

[0043] As the power supply voltage VDD continues to rise, and the target signal VREF begins to build up and rise, when the gradually increasing first comparison signal VDIV (that is, the voltage division of the power supply voltage VDD) exceeds the threshold voltage of the first MOSFET MN1, the first MOSFET MN1 is turned on. At this time, the second comparison signal VM is pulled down to be less than the target signal VREF. At this time, the target signal VREF is greater than the first comparison signal VDIV, and the characterization signal BGOK output by the comparator unit 30 is still a low level signal.

[0044] As the power supply voltage VDD continues to rise, the target signal VREF has stabilized. When the first comparison signal VDIV rises to be equal to the target signal VREF, the output of comparator unit 30 flips, and the characterization signal BGOK flips to a high level, indicating that the target signal VREF has been established.

[0045] As can be seen, during the slow power-up process of the power supply voltage VDD, the target signal VREF is established when the power supply voltage VDD is low, and the characterization signal BGOK flips to a high level. In the prior art, the power supply voltage VDD must rise to a certain value to determine that the reference bandgap voltage (i.e., the target signal VREF) has been established. Compared with the prior art, this solution can establish the reference bandgap voltage when the power supply voltage VDD is even lower, so that the chip or each module can start working at a lower power supply voltage VDD, thus widening the operating voltage range of the chip or each module.

[0046] When the power supply voltage VDD is rapidly powered on, the delay unit Delay is set to delay the characterization signal BGOK for a certain period of time before it flips to a high level. This ensures that the target signal VREF has been established when the characterization signal BGOK flips, thus improving the output stability of the signal generation circuit.

[0047] The signal generation circuit of the present invention can also be used as an undervoltage lockout circuit. By setting the resistance value of the voltage divider unit 10 to match the undervoltage action value, the undervoltage protection function can be realized.

[0048] The present invention also discloses a chip including the signal generation circuit described above. The chip further includes a bandgap reference circuit and / or an undervoltage lockout circuit. The second input terminal of the comparator unit 30 is used to receive the reference voltage signal generated by the bandgap reference circuit and / or the undervoltage lockout signal from the undervoltage lockout circuit.

[0049] like Figure 2 As shown, based on the signal generation circuit described above, this embodiment also discloses a signal generation method, including:

[0050] The voltage divider unit 10 acquires the first comparison signal VDIV, which varies with the power supply voltage VDD.

[0051] The selection unit 20 acquires second comparison signals VM of different sizes based on the control of the first comparison signal VDIV;

[0052] The comparator unit 30 selects either the second comparison signal VM or the target signal VREF based on the magnitudes of the second comparison signal VM and the target signal VREF, compares them with the first comparison signal VDIV, and outputs a characterization signal to characterize whether the target signal VREF is established.

[0053] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A signal generating circuit, characterized by comprising: include: The voltage divider unit, connected to the power supply voltage and the ground voltage, is used to divide the power supply voltage to generate the first comparison signal; The selection unit, connected to the power supply voltage and the ground voltage, is used to control the output of second comparison signals of different magnitudes based on the first comparison signal; as well as A comparator unit has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of the comparator unit is used to receive a second comparison signal, the second input terminal of the comparator unit is used to receive a target signal, the third input terminal of the comparator unit is used to receive a first comparison signal, and the output terminal of the comparator unit outputs a characterization signal to characterize whether the target signal is established based on the comparison result between the selected second comparison signal or the target signal and the first comparison signal.

2. The signal generating circuit of claim 1, wherein, The voltage divider unit includes a first resistor unit and a second resistor unit. The first end of the first resistor unit is connected to the power supply voltage, and the second end of the first resistor unit is connected to the first end of the second resistor unit to output a first comparison signal. The second end of the second resistor unit is connected to the ground voltage.

3. The signal generating circuit of claim 1, wherein, The selection unit includes a pull-up unit and a pull-down unit, which are connected to output a second comparison signal. The pull-up unit pulls up the second comparison signal under the control of the first comparison signal, and the pull-down unit pulls down the second comparison signal under the control of the first comparison signal.

4. The signal generating circuit of claim 3, wherein, The pull-up unit includes a resistor.

5. The signal generation circuit as described in claim 3, characterized in that, The pull-down unit includes a first MOS transistor, the gate of which is used to receive a first comparison signal, the drain of which is connected to the pull-up unit, and the source of which is connected to ground voltage.

6. The signal generation circuit as described in claim 5, characterized in that, The pull-down unit further includes a second MOS transistor or a diode. The gate and drain of the second MOS transistor are connected and simultaneously connected to the pull-up unit. The source of the second MOS transistor is connected to the drain of the first MOS transistor. The anode of the diode is connected to the pull-up unit, and the cathode of the diode is connected to the drain of the first MOS transistor.

7. The signal generation circuit as described in claim 1, characterized in that, The comparator unit includes a first current mirror unit, a second current mirror unit, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, and a flip-delay unit; The gate of the third MOS transistor is used to receive the second comparison signal, the gate of the fourth MOS transistor is used to receive the target signal, and the gate of the fifth MOS transistor is used to receive the first comparison signal. The drains of the third and fourth MOS transistors are connected and simultaneously connected to the first current mirror unit. The drain of the fifth MOS transistor is connected to the first current mirror unit. The sources of the third, fourth, and fifth MOS transistors are connected to the second current mirror unit. The source of the sixth MOS transistor is connected to the power supply voltage. The gate of the sixth MOS transistor is connected to the drain of the fifth MOS transistor. The drain of the sixth MOS transistor is connected to the second current mirror unit and the toggle delay unit. The toggle delay unit is used to toggle and delay the signal output by the comparator unit.

8. The signal generation circuit as described in claim 7, characterized in that, The flip-delay unit includes a first inverter, a second inverter, and a delay unit. The input terminal of the first inverter is connected to the drain of the sixth MOS transistor. The input terminal of the delay unit is connected to the output terminal of the first inverter. The output terminal of the delay unit is connected to the input terminal of the second inverter. The output terminal of the second inverter is used to output a characterization signal.

9. A chip, characterized in that, The chip includes the signal generation circuit as described in any one of claims 1 to 8, and further includes a bandgap reference circuit and / or an undervoltage lockout circuit, wherein the second input terminal of the comparator unit is used to receive a reference voltage signal generated by the bandgap reference circuit and / or an undervoltage lockout signal from the undervoltage lockout circuit.

10. A signal generation method, characterized in that, include: Acquire the first comparison signal that varies with the power supply voltage; The selection unit acquires second comparison signals of different magnitudes based on the control of the first comparison signal; The comparator unit selects either the second comparison signal or the target signal based on the magnitudes of the second comparison signal and the target signal to compare with the first comparison signal, and outputs a characterization signal to characterize whether the target signal has been established.

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