SSD read delay optimization method and device, computer device, and storage medium
By introducing a tracking table of optimal read voltage for physical blocks/pages inside the SSD, the read process is optimized, resolving read errors caused by dense distribution of read reference voltages, and improving the performance consistency and response latency of the SSD.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2022-12-27
- Publication Date
- 2026-06-16
AI Technical Summary
In existing technologies, with the evolution of NAND technology, the read reference voltage distribution of SSDs is dense, which increases the probability of read errors. The Read Retry method is time-consuming and cannot meet the response latency requirements of enterprise applications.
An optimal read voltage tracking table for physical blocks/pages is introduced inside the SSD. By scanning and counting the number of error bits in the background, the optimal read reference voltage is recorded and the table is updated to optimize the read process.
It improves the performance consistency of SSDs, ensures command response latency, and meets the response latency requirements of enterprise applications.
Smart Images
Figure CN115862714B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SSD read latency technology, and in particular to SSD read latency optimization methods, apparatus, computer equipment, and storage media. Background Technology
[0002] With the evolution of NAND technology, it has progressed from the early 1bit / cell (SLC) to 2bit / cell (MLC), 3bit / cell (TLC), and 4bit / cell (QLC), with the data storage capacity becoming larger and larger. However, due to the increase in the number of bits in each cell, the voltage distribution becomes more dense.
[0003] NAND data representation is achieved through voltage comparison. As voltage distribution becomes increasingly dense, voltage offsets / aliasing can easily occur in adjacent areas, causing the conventional read reference voltage to fail to read the correct data. To address this, manufacturers provide a Read Retry method, which attempts to read the correct data by offsetting the read reference voltage. This process requires fine-tuning the reference voltage left and right, and using decoding and verification methods to determine data correctness. This process requires repeated attempts and takes a considerable amount of time to correct the data. When a host initiates a data read, there are generally response latency requirements. For example, enterprise-level applications typically require 99.9% of read command response latency to be within a specific threshold (e.g., 1ms). Frequent triggering of Read Retry will result in extremely high command latency, failing to meet product requirements. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide SSD read latency optimization methods, devices, computer equipment, and storage media.
[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0006] Firstly, this embodiment provides an SSD read latency optimization method, including the following steps:
[0007] Initialize the optimal reading voltage meter and the most recent scan timestamp table, and write them to the NAND flash memory;
[0008] Upon power-up, the corresponding optimal reading voltage meter and the most recent scan timestamp table are loaded into memory;
[0009] Determine if the SSD meets the background voltage scan conditions;
[0010] If the background voltage scan conditions are met, data scan is performed on the physical blocks that meet the conditions, and the voltage value that can be read back correctly and has the fewest erroneous bits is written into the best read voltage table. At the same time, the most recent scan timestamp table is updated.
[0011] Retrieve commands issued by the host;
[0012] Determine if the command is a read command;
[0013] If the command is a read command, then the optimal read voltage is found based on the physical page address in the accessed physical block;
[0014] Perform NAND reads based on the optimal read voltage and return the correct data to the host.
[0015] The further technical solution is as follows: The process of scanning physical blocks that meet the conditions and writing the voltage value that can be correctly read back and has the fewest erroneous bits into the optimal read voltage table, while simultaneously updating the most recent scan timestamp table, includes the following steps:
[0016] Arrange all physical blocks containing user data in order of their write time.
[0017] Based on the write timestamp and the current system timestamp, physical blocks that have a difference greater than a first threshold are selected and referred to as the first physical block set.
[0018] Based on the recent scan timestamp table, physical blocks whose recent scan timestamp and current system timestamp differ from the recent scan timestamp by a second threshold are selected from the first physical block set and are called the second physical block set.
[0019] Obtain a physical block from the second physical block set, denoted as the selected physical block;
[0020] According to the read voltage configuration table, obtain the next available read reference voltage, configure the NAND to use the corresponding read reference voltage, and select a physical page from the selected physical blocks, denoted as the selected physical page;
[0021] Read the NAND flash memory, count the number of erroneous bits, and record the value in memory.
[0022] Determine if there are other read reference voltage settings in the NAND flash memory;
[0023] If there are no other read reference voltage settings in the NAND, compare all the record value combinations of the physical page, select the one with the smallest number of error bits, and obtain the corresponding reference voltage value, which is recorded as the best reference voltage value.
[0024] Update the optimal reading voltage meter, changing the optimal reading voltage of the selected physical page to the optimal reference voltage value;
[0025] Determine if there are other physical pages within the selected physical block;
[0026] If there are no other physical pages within the selected physical block, then update the scan timestamp of the selected physical block in the most recent scan timestamp table to the current system timestamp.
[0027] The further technical solution is as follows: after the step of updating the scan timestamp of the physical block selected in the most recently scanned timestamp table to the current system timestamp, it also includes:
[0028] Determine if there are any remaining unscanned physical blocks in the second physical block set;
[0029] If there are no remaining unscanned physical blocks in the second physical block set, then the current background data reading voltage scan is completed.
[0030] The further technical solution is as follows: after the step of determining whether the command is a read command, it also includes:
[0031] Get other commands issued by the host;
[0032] Determine if NAND flash memory has been erased;
[0033] If NAND flash memory is erased, the optimal read voltage of all physical pages in the optimal read voltage table will be cleared to zero.
[0034] Clear the timestamp corresponding to the physical block in the most recently scanned timestamp table to zero.
[0035] Secondly, this embodiment provides an SSD read latency optimization device, including: an initialization write unit, a loading unit, a first judgment unit, a scan write update unit, a first acquisition unit, a second judgment unit, a search unit, and a read return unit;
[0036] The initialization write unit is used to initialize the optimal read voltage meter and the most recent scan timestamp table, and write them into the NAND flash memory.
[0037] The loading unit is used to load the corresponding optimal reading voltage meter and the most recent scan timestamp table into memory upon power-up;
[0038] The first judgment unit is used to determine whether the SSD meets the background voltage scan conditions;
[0039] The scan write update unit is used to scan the physical blocks that meet the background voltage scan conditions if the background voltage scan conditions are met, and write the voltage value that can be read back correctly and has the fewest erroneous bits into the best read voltage table, while updating the most recent scan timestamp table.
[0040] The first acquisition unit is used to acquire commands issued by the host;
[0041] The second judgment unit is used to determine whether the command is a read command;
[0042] The lookup unit is used to find the optimal read voltage based on the physical page address in the accessed physical block if the command is a read command.
[0043] The read return unit is used to perform NAND reads based on the optimal read voltage and return the correct data to the host.
[0044] The further technical solution is as follows: the scanning, writing, and updating unit includes: a writing module, a first filtering module, a second filtering module, an acquisition module, an acquisition configuration selection module, a reading statistical record module, a first judgment module, a comparison selection acquisition module, a first update module, a second judgment module, and a second update module;
[0045] The write module is used to arrange all physical blocks containing user data in order of write time.
[0046] The first filtering module is used to filter physical blocks that meet the condition that the difference between the write timestamp and the current system timestamp is greater than a first threshold, which is called the first physical block set;
[0047] The second filtering module is used to filter physical blocks from the first physical block set whose difference between the most recent scan timestamp and the current system timestamp is greater than a second threshold, based on the most recent scan timestamp table. This is called the second physical block set.
[0048] The acquisition module is used to acquire a physical block from the second physical block set, denoted as the selected physical block;
[0049] The configuration selection module is used to obtain the next available read reference voltage according to the read voltage configuration table, configure the NAND to use the corresponding read reference voltage, and select a physical page from the selected physical blocks, denoted as the selected physical page;
[0050] The read statistics recording module is used to read NAND, count the number of error bits, and record them in memory, i.e., record the value;
[0051] The first judgment module is used to determine whether there are other read reference voltage settings in the NAND;
[0052] The comparison and selection acquisition module is used to compare and select all combinations of recorded values in the physical page if there are no other read reference voltage settings in the NAND, select the one with the smallest number of error bits, and obtain the corresponding reference voltage value, which is recorded as the best reference voltage value.
[0053] The first update module is used to update the optimal reading voltage meter, updating the optimal reading voltage of the selected physical page to the optimal reference voltage value;
[0054] The second judgment module is used to determine whether there are other physical pages within the selected physical block;
[0055] The second update module is used to update the scan timestamp of the selected physical block in the most recently scanned timestamp table to the current system timestamp if there are no other physical pages within the selected physical block.
[0056] The further technical solution is as follows: the scanning, writing, and updating unit further includes: a third judgment module and a completion module;
[0057] The third judgment module is used to determine whether there are any remaining unscanned physical blocks in the second physical block set;
[0058] The completion module is used to complete the current background data reading voltage scan if there are no remaining unscanned physical blocks in the second physical block set.
[0059] The further technical solution is as follows: the device further includes: a second acquisition unit, a third judgment unit, a first clearing unit, and a second clearing unit;
[0060] The second acquisition unit is used to acquire other commands issued by the host;
[0061] The third judgment unit is used to determine whether the NAND flash memory has been erased;
[0062] The first clearing unit is used to clear the optimal read voltage of all physical pages in the optimal read voltage table if there is an erase in the NAND flash memory.
[0063] The second clearing unit is used to clear the timestamp corresponding to the physical block in the most recently scanned timestamp table.
[0064] Thirdly, this embodiment provides a computer device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the SSD read latency optimization method as described above.
[0065] Fourthly, this embodiment provides a storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, can implement the SSD read latency optimization method described above.
[0066] The beneficial effects of this invention compared to existing technologies are: it introduces a tracking table for the optimal read voltage of physical blocks / pages, scans data in the background inside the SSD, reads data using various read reference voltages and counts the number of error bits, and records the optimal read reference voltage in the optimal read reference voltage table so that when the host accesses the data later, it can use the optimal read voltage to read physical pages as soon as possible, which greatly improves performance consistency and ensures command response latency.
[0067] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0068] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0069] Figure 1 A flowchart illustrating the SSD read latency optimization method provided in this embodiment of the invention;
[0070] Figure 2 A schematic diagram of the optimal reading voltmeter provided for an embodiment of the present invention;
[0071] Figure 3 A schematic diagram of the most recent scan timestamp table provided in an embodiment of the present invention;
[0072] Figure 4 This is a schematic diagram of a sub-process of the SSD read latency optimization method provided in an embodiment of the present invention;
[0073] Figure 5 This is a schematic block diagram of an SSD read latency optimization device provided in an embodiment of the present invention;
[0074] Figure 6 This is a schematic block diagram of an SSD read latency optimization device provided in an embodiment of the present invention;
[0075] Figure 7 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation
[0076] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0077] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0078] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0079] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0080] A typical NAND flash memory consists of the following: DIE, a cell that can be operated independently and concurrently; Block, a cell that can be erased independently, where the entire block must be erased before the next write operation after data is written to each physical location; and Page, a read / write cell, where Pages within the same physical block must be programmed sequentially: 0->1->2->3…
[0081] Please see Figure 1 The specific embodiment shown in this invention discloses an SSD read latency optimization method, comprising the following steps:
[0082] S1, initialize the optimal reading voltage meter and the most recent scan timestamp table, and write them to the NAND;
[0083] Please see Figure 2 As shown, the optimal reading voltmeter includes:
[0084] CH is the internal physical channel number of the SSD. Different CHs have independent buses and can execute in full concurrency.
[0085] CE, the internal physical chip select number of the SSD, the bus is shared in a time-sharing manner between different CEs, and typically one DIE is connected under each CE;
[0086] Block, corresponding to the physical block number within the DIE;
[0087] Page, corresponding to the physical page number within a Block;
[0088] BestReadVref: The optimal read voltage for the corresponding physical page (with the fewest error bits).
[0089] Please see Figure 3 As shown, the most recent scan timestamp table includes:
[0090] CH is the internal physical channel number of the SSD. Different CHs have independent buses and can execute in full concurrency.
[0091] CE, the internal physical chip select number of the SSD, the bus is shared in a time-sharing manner between different CEs, and typically one DIE is connected under each CE;
[0092] Block, corresponding to the physical block number within the DIE;
[0093] LatestScanTimestamp is the timestamp of the most recent voltage scan of this physical block.
[0094] Specifically, initialization means clearing both BestReadVref and LatestScanTimestamp to zero. BestReadVref being 0 indicates that the default read reference voltage (without offset) is used, while LatestScanTimestamp being 0 indicates that a read voltage scan has not been performed.
[0095] S2, upon power-on, load the corresponding optimal reading voltage meter and the most recent scan timestamp table into memory;
[0096] S3, determine whether the SSD meets the background voltage scan conditions; if the background voltage scan conditions are not met, proceed to step S5.
[0097] Specifically, the SSD is run first, and then it is determined whether the SSD meets the background voltage scan conditions. The background voltage scan conditions can be customized. One implementation method is to trigger the background voltage scan periodically (by minute / hour / day, etc.); another method is to trigger it when the host is idle and there are no commands accessing it.
[0098] S4. If the background voltage scan conditions are met, perform data scan on the physical blocks that meet the conditions, and write the voltage value that can be read back correctly and has the fewest erroneous bits into the best read voltage table, while updating the most recent scan timestamp table.
[0099] Specifically, a qualifying physical block refers to a physical block that stores valid user data, excluding blank blocks, bad blocks, system data blocks, etc.
[0100] In one embodiment, please refer to Figure 4 As shown, the process of scanning physical blocks that meet the conditions and writing the voltage value that can be read back correctly and has the fewest erroneous bits into the optimal read voltage table, while updating the most recent scan timestamp table, includes the following steps:
[0101] S4a, arranges all physical blocks containing user data in order of write time;
[0102] S4b: Based on the write timestamp and the current system timestamp, select physical blocks whose difference is greater than the first threshold, and call them the first physical block set;
[0103] Specifically, the first threshold (Data_Hold_TH) can be defined by the user, such as 100.
[0104] S4c, based on the recent scan timestamp table, select physical blocks from the first physical block set whose difference between the recent scan timestamp and the current system timestamp is greater than the second threshold, which are called the second physical block set;
[0105] Specifically, the second threshold (Data_Scan_TH) can be defined by the user, such as 50.
[0106] S4d, retrieves a physical block from the second physical block set, denoted as the selected physical block;
[0107] Specifically, a physical block is randomly selected from the second set of physical blocks.
[0108] S4e obtains the next available read reference voltage according to the read voltage configuration table, configures the NAND to use the corresponding read reference voltage, and selects a physical page from the selected physical blocks, denoted as the selected physical page;
[0109] Specifically, the read voltage configuration table is generally provided by the NAND manufacturer. The corresponding read reference voltage is denoted as Vref_i.
[0110] S4f reads the NAND flash memory, counts the number of error bits, and records the value in memory.
[0111] Specifically, the record value is (Vref_i, error_bit_num_i).
[0112] S4g: Determine if there are other read reference voltage settings in the NAND flash memory; if there are other read reference voltage settings in the NAND flash memory, return to execute step S4e.
[0113] S4h, if there are no other read reference voltage settings in the NAND, compare all the record value combinations of the physical page, select the one with the smallest number of error bits, and obtain the corresponding reference voltage value, which is recorded as the best reference voltage value;
[0114] Specifically, the recorded value combination is (Vref, error_bit_num), the number of error bits is (error_bit_num), and the optimal reference voltage value is Vref_Best.
[0115] S4i, Update the best read voltage meter, update the best read voltage of the selected physical page to the best reference voltage value;
[0116] S4j: Determine if there are other physical pages within the selected physical block; if there are other physical pages within the selected physical block, return to execute step S4e.
[0117] If there are no other physical pages within the selected physical block, then the scan timestamp of the selected physical block in the most recent scan timestamp table is updated to the current system timestamp.
[0118] In one embodiment, after the step of updating the scan timestamp of the physical block selected in the most recently scanned timestamp table to the current system timestamp, the method further includes:
[0119] S4l, determine whether there are any remaining unscanned physical blocks in the second physical block set;
[0120] S4m, if there are no remaining unscanned physical blocks in the second physical block set, then complete the current background data reading voltage scan;
[0121] S4n: If there are remaining unscanned physical blocks in the second physical block set, then obtain the next physical block to be scanned in the second physical block set and return to execute step S4e.
[0122] S5, retrieves commands issued by the host;
[0123] S6, determine whether the command is a read command;
[0124] S7, if the command is a read command, then find the optimal read voltage based on the physical page address in the accessed physical block;
[0125] Specifically, the physical page address in the physical block is the corresponding CH / CE / Block / Page.
[0126] S8 performs NAND reading based on the optimal read voltage and returns the correct data to the host.
[0127] In one embodiment, after step S8, the process further includes: returning to execute step S3.
[0128] In one embodiment, after the step of determining whether the command is a read command, the method further includes:
[0129] S9, retrieve other commands issued by the host;
[0130] Specifically, other commands refer to regular commands other than the read command.
[0131] S10, determine if the NAND flash memory has been erased; if the NAND flash memory has not been erased, return to step S3.
[0132] S11, If NAND has been erased, then clear the optimal read voltage of all physical pages in the optimal read voltage table to zero;
[0133] Specifically, all physical pages refer to all pages under CH / CE / Block.
[0134] S12, clear the timestamp corresponding to the physical block in the most recently scanned timestamp table to zero.
[0135] In one embodiment, after step S12, the process further includes: returning to execute step S3.
[0136] Furthermore, the optimal read voltage table and the latest scan timestamp table in memory can be periodically saved to NAND, or saved to NAND when the host sends a power-down command, so that the information can be inherited after power failure / power-on.
[0137] This invention introduces a tracking table for the optimal read voltage of physical blocks / pages. Data is scanned in the background inside the SSD, and reads are performed using various read reference voltages. The number of error bits is counted, and the optimal read reference voltage is recorded in the optimal read reference voltage table. This allows the host to use the optimal read voltage to read physical pages as soon as possible when accessing them later, which greatly improves performance consistency and ensures command response latency.
[0138] Please see Figure 5 As shown, the present invention also discloses an SSD read latency optimization device, including: an initialization writing unit 10, a loading unit 20, a first judgment unit 30, a scan write update unit 40, a first acquisition unit 50, a second judgment unit 60, a search unit 70, and a read return unit 80.
[0139] The initialization writing unit 10 is used to initialize the optimal read voltage meter and the most recent scan timestamp table, and write them into the NAND flash memory.
[0140] The loading unit 20 is used to load the corresponding optimal reading voltage meter and the most recent scan timestamp table into memory upon power-up;
[0141] The first judgment unit 30 is used to determine whether the SSD meets the background voltage scan conditions;
[0142] The scan write update unit 40 is used to scan the physical blocks that meet the background voltage scan conditions if the background voltage scan conditions are met, and write the voltage value that can be read back correctly and has the fewest erroneous bit data into the best read voltage table, while updating the most recent scan timestamp table.
[0143] The first acquisition unit 50 is used to acquire commands issued by the host;
[0144] The second judgment unit 60 is used to determine whether the command is a read command;
[0145] The lookup unit 70 is used to find the optimal read voltage based on the physical page address in the accessed physical block if the command is a read command.
[0146] The read return unit 80 is used to perform NAND reads based on the optimal read voltage and return the correct data to the host.
[0147] In one embodiment, please refer to Figure 6 As shown, the scan, write, and update unit 40 includes: a write module 40a, a first filtering module 40b, a second filtering module 40c, an acquisition module 40d, an acquisition configuration selection module 40e, a read statistics record module 40f, a first judgment module 40g, a comparison selection acquisition module 40h, a first update module 40i, a second judgment module 40j, and a second update module 40k.
[0148] The writing module 40a is used to arrange all physical blocks containing user data in order of writing time.
[0149] The first filtering module 40b is used to filter physical blocks that meet the condition that the difference between the write timestamp and the current system timestamp is greater than a first threshold, which is called the first physical block set;
[0150] The second filtering module 40c is used to filter physical blocks from the first physical block set whose difference between the most recent scan timestamp and the current system timestamp is greater than a second threshold, based on the most recent scan timestamp table. This is called the second physical block set.
[0151] The acquisition module 40d is used to acquire a physical block from the second physical block set, denoted as the selected physical block;
[0152] The configuration selection module 40e is used to obtain the next available read reference voltage according to the read voltage configuration table, configure the NAND to use the corresponding read reference voltage, and select a physical page from the selected physical block, denoted as the selected physical page;
[0153] The read statistics recording module 40f is used to read NAND, count the number of error bits, and record them in memory, i.e., record the value;
[0154] The first judgment module 40g is used to determine whether there are other read reference voltage settings in the NAND;
[0155] The comparison selection acquisition module 40h is used to compare and select all the record value combinations of the physical page if there are no other read reference voltage settings in the NAND, select the one with the smallest number of error bits, and obtain the corresponding reference voltage value, which is recorded as the best reference voltage value.
[0156] The first update module 40i is used to update the optimal reading voltage meter, and update the optimal reading voltage of the selected physical page to the optimal reference voltage value;
[0157] The second judgment module 40j is used to determine whether there are other physical pages within the selected physical block;
[0158] The second update module 40k is used to update the scan timestamp of the selected physical block in the most recent scan timestamp table to the current system timestamp if there are no other physical pages in the selected physical block.
[0159] In one embodiment, please refer to Figure 6 As shown, the scan-write-update unit 40 further includes: a third judgment module 401 and a completion module 40m;
[0160] The third judgment module 40l is used to determine whether there are any remaining unscanned physical blocks in the second physical block set;
[0161] The completion module 40m is used to complete the current background data reading voltage scan if there are no remaining unscanned physical blocks in the second physical block set.
[0162] In one embodiment, please refer to Figure 6 As shown, the scan write update unit 40 further includes: an acquisition return module 40n, used to acquire the next physical block to be scanned in the second physical block set, and return to execute the acquisition of the next available read reference voltage according to the read voltage configuration table, configure the NAND to use the corresponding read reference voltage, and select a physical page from the selected physical blocks, denoted as the selected physical page.
[0163] In one embodiment, please refer to Figure 5 As shown, the device further includes: a second acquisition unit 90, a third judgment unit 100, a first clearing unit 110, and a second clearing unit 120;
[0164] The second acquisition unit 90 is used to acquire other commands issued by the host;
[0165] The third judgment unit 100 is used to determine whether the NAND has been erased;
[0166] The first clearing unit 110 is used to clear the optimal read voltage of all physical pages in the optimal read voltage table if there is an erase in the NAND.
[0167] The second clearing unit 120 is used to clear the timestamp corresponding to the physical block in the most recently scanned timestamp table.
[0168] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned SSD read latency optimization device and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.
[0169] The aforementioned SSD read latency optimization device can be implemented as a computer program, which can, for example... Figure 7 It runs on the computer device shown.
[0170] Please see Figure 7 , Figure 7 This is a schematic block diagram of a computer device 500 provided in an embodiment of this application; the computer device 500 can be a terminal or a server, wherein the terminal can be an electronic device with communication functions such as a smartphone, tablet computer, laptop computer, desktop computer, personal digital assistant, and wearable device. The server can be a standalone server or a server cluster composed of multiple servers.
[0171] See Figure 7 The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.
[0172] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform an SSD read latency optimization method.
[0173] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.
[0174] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute an SSD read latency optimization method.
[0175] This network interface 505 is used for network communication with other devices. Those skilled in the art will understand that... Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0176] The processor 502 is used to run a computer program 5032 stored in the memory to perform the following steps:
[0177] Initialize the optimal read voltage table and the most recent scan timestamp table, and write them to the NAND flash memory; load the corresponding optimal read voltage table and most recent scan timestamp table into memory upon power-up; determine if the SSD meets the background voltage scan conditions; if it does, scan the physical blocks that meet the conditions, and write the voltage value that can be read back correctly and has the fewest error bits into the optimal read voltage table, while updating the most recent scan timestamp table; obtain the command issued by the host; determine if the command is a read command; if it is a read command, find the optimal read voltage based on the physical page address in the accessed physical block; perform NAND reading based on the optimal read voltage, and return the correct data to the host.
[0178] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.
[0179] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.
[0180] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions that, when executed by a processor, can implement the above-described SSD read latency optimization method. The storage medium stores a computer program, which includes program instructions that, when executed by a processor, can implement the above-described method. The program instructions include the following steps:
[0181] Initialize the optimal read voltage table and the most recent scan timestamp table, and write them to the NAND flash memory; load the corresponding optimal read voltage table and most recent scan timestamp table into memory upon power-up; determine if the SSD meets the background voltage scan conditions; if it does, scan the physical blocks that meet the conditions, and write the voltage value that can be read back correctly and has the fewest error bits into the optimal read voltage table, while updating the most recent scan timestamp table; obtain the command issued by the host; determine if the command is a read command; if it is a read command, find the optimal read voltage based on the physical page address in the accessed physical block; perform NAND reading based on the optimal read voltage, and return the correct data to the host.
[0182] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.
[0183] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0184] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.
[0185] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0186] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.
[0187] The above embodiments are preferred implementations of the present invention. In addition, the present invention can be implemented in other ways. Any obvious substitutions without departing from the concept of the present technical solution are within the protection scope of the present invention.
Claims
1. An SSD read latency optimization method, characterized in that, Includes the following steps: Initialize the optimal reading voltage meter and the most recent scan timestamp table, and write them to the NAND flash memory; Upon power-up, the corresponding optimal reading voltage meter and the most recent scan timestamp table are loaded into memory; Determine if the SSD meets the background voltage scan conditions; If the background voltage scan conditions are met, data scan is performed on the physical blocks that meet the conditions, and the voltage value that can be read back correctly and has the fewest erroneous bits is written into the best read voltage table. At the same time, the most recent scan timestamp table is updated. Retrieve commands issued by the host; Determine if the command is a read command; If the command is a read command, then the optimal read voltage is found based on the physical page address in the accessed physical block; Perform NAND reads based on the optimal read voltage and return the correct data to the host; The process of scanning physical blocks that meet the criteria and writing the voltage values that can be read back correctly with the fewest erroneous bits into the optimal read voltage table, while simultaneously updating the most recent scan timestamp table, includes the following steps: Arrange all physical blocks containing user data in order of their write time. Based on the write timestamp and the current system timestamp, physical blocks that have a difference greater than a first threshold are selected and referred to as the first physical block set. Based on the recent scan timestamp table, physical blocks whose recent scan timestamp and current system timestamp differ from the recent scan timestamp by a second threshold are selected from the first physical block set and are called the second physical block set. Obtain a physical block from the second physical block set, denoted as the selected physical block; According to the read voltage configuration table, obtain the next available read reference voltage, configure the NAND to use the corresponding read reference voltage, and select a physical page from the selected physical blocks, denoted as the selected physical page; Read the NAND flash memory, count the number of erroneous bits, and record the value in memory. Determine if there are other read reference voltage settings in the NAND flash memory; If there are no other read reference voltage settings in the NAND, compare all the record value combinations of the physical page, select the one with the smallest number of error bits, and obtain the corresponding reference voltage value, which is recorded as the best reference voltage value. Update the optimal reading voltage meter, changing the optimal reading voltage of the selected physical page to the optimal reference voltage value; Determine if there are other physical pages within the selected physical block; If there are no other physical pages within the selected physical block, then update the scan timestamp of the selected physical block in the most recent scan timestamp table to the current system timestamp.
2. The SSD read latency optimization method according to claim 1, characterized in that, After the step of updating the most recently scanned timestamp table and selecting the scan timestamp of the physical block as the current system timestamp, the method further includes: Determine if there are any remaining unscanned physical blocks in the second physical block set; If there are no remaining unscanned physical blocks in the second physical block set, then the current background data reading voltage scan is completed.
3. The SSD read latency optimization method according to claim 1, characterized in that, After determining whether the command is a read command, the method further includes: Get other commands issued by the host; Determine if NAND flash memory has been erased; If NAND flash memory is erased, the optimal read voltage of all physical pages in the optimal read voltage table will be cleared to zero. Clear the timestamp corresponding to the physical block in the most recently scanned timestamp table to zero.
4. An SSD read latency optimization device, characterized in that, include: The system includes an initialization write unit, a loading unit, a first judgment unit, a scan write update unit, a first acquisition unit, a second judgment unit, a search unit, and a read return unit. The initialization write unit is used to initialize the optimal read voltage meter and the most recent scan timestamp table, and write them into the NAND flash memory. The loading unit is used to load the corresponding optimal reading voltage meter and the most recent scan timestamp table into memory upon power-up; The first judgment unit is used to determine whether the SSD meets the background voltage scan conditions; The scan write update unit is used to scan the physical blocks that meet the background voltage scan conditions if the background voltage scan conditions are met, and write the voltage value that can be read back correctly and has the fewest erroneous bits into the best read voltage table, while updating the most recent scan timestamp table. The first acquisition unit is used to acquire commands issued by the host; The second judgment unit is used to determine whether the command is a read command; The lookup unit is used to find the optimal read voltage based on the physical page address in the accessed physical block if the command is a read command. The read return unit is used to perform NAND reads based on the optimal read voltage and return the correct data to the host. The scan, write, and update unit includes: a write module, a first filtering module, a second filtering module, an acquisition module, an acquisition configuration selection module, a read statistics record module, a first judgment module, a comparison selection acquisition module, a first update module, a second judgment module, and a second update module; The write module is used to arrange all physical blocks containing user data in order of write time. The first filtering module is used to filter physical blocks that meet the condition that the difference between the write timestamp and the current system timestamp is greater than a first threshold, which is called the first physical block set; The second filtering module is used to filter physical blocks from the first physical block set whose difference between the most recent scan timestamp and the current system timestamp is greater than a second threshold, based on the most recent scan timestamp table. This is called the second physical block set. The acquisition module is used to acquire a physical block from the second physical block set, denoted as the selected physical block; The configuration selection module is used to obtain the next available read reference voltage according to the read voltage configuration table, configure the NAND to use the corresponding read reference voltage, and select a physical page from the selected physical blocks, denoted as the selected physical page; The read statistics recording module is used to read NAND, count the number of error bits, and record them in memory, i.e., record the value; The first judgment module is used to determine whether there are other read reference voltage settings in the NAND; The comparison and selection acquisition module is used to compare and select all combinations of recorded values in the physical page if there are no other read reference voltage settings in the NAND, select the one with the smallest number of error bits, and obtain the corresponding reference voltage value, which is recorded as the best reference voltage value. The first update module is used to update the optimal reading voltage meter, updating the optimal reading voltage of the selected physical page to the optimal reference voltage value; The second judgment module is used to determine whether there are other physical pages within the selected physical block; The second update module is used to update the scan timestamp of the selected physical block in the most recently scanned timestamp table to the current system timestamp if there are no other physical pages within the selected physical block.
5. The SSD read latency optimization device according to claim 4, characterized in that, The scan-write-update unit further includes: a third judgment module and a completion module; The third judgment module is used to determine whether there are any remaining unscanned physical blocks in the second physical block set; The completion module is used to complete the current background data reading voltage scan if there are no remaining unscanned physical blocks in the second physical block set.
6. The SSD read latency optimization device according to claim 4, characterized in that, The device further includes: a second acquisition unit, a third judgment unit, a first clearing unit, and a second clearing unit; The second acquisition unit is used to acquire other commands issued by the host; The third judgment unit is used to determine whether the NAND flash memory has been erased; The first clearing unit is used to clear the optimal read voltage of all physical pages in the optimal read voltage table if there is an erase in the NAND flash memory. The second clearing unit is used to clear the timestamp corresponding to the physical block in the most recently scanned timestamp table.
7. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the SSD read latency optimization method as described in any one of claims 1-3.
8. A storage medium, characterized in that, The storage medium stores a computer program, which includes program instructions that, when executed by a processor, can implement the SSD read latency optimization method as described in any one of claims 1-3.