Semiconductor structure and method of fabricating the same
By growing an ultrathin epitaxial layer structure on a sapphire substrate and utilizing dislocation turning and annihilation techniques, the warping problem of GaN epitaxial layers was solved, achieving high-quality GaN epitaxial layer growth and improving chip process yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG INST OF SEMICON IND TECH
- Filing Date
- 2022-11-30
- Publication Date
- 2026-07-03
AI Technical Summary
There is a significant problem of epitaxial layer warping when growing GaN on sapphire substrates, especially on large-size substrates, which affects the yield of subsequent chip manufacturing processes.
An ultrathin epitaxial layer structure is adopted, including a sapphire substrate, an AlN buffer layer, a seed layer, a merging layer, a SiN insertion layer, and a fusion layer. By controlling the thickness and reflectivity of each layer, the rapid turning and annihilation of dislocations are achieved, and a high-quality GaN epitaxial layer is grown.
It effectively alleviates epitaxial layer warpage, improves the crystal quality of the epitaxial layer, reduces dislocation density, and improves chip process yield.
Smart Images
Figure CN115863145B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for fabricating the same. Background Technology
[0002] GaN, as a core material for third-generation wide-bandgap semiconductors, has demonstrated excellent performance and broad application prospects in applications such as light-emitting diodes (LEDs) and power electronic devices (HEMTs). However, due to the high cost and difficulty in fabricating large sizes of homogeneous GaN substrates, GaN devices currently employ heterogeneous substrates, such as sapphire, silicon, and silicon carbide.
[0003] However, considering the current performance and production cost of GaN materials, sapphire substrates offer superior material quality compared to silicon substrates and are significantly cheaper than silicon carbide substrates. Therefore, sapphire substrates are currently the preferred substrate for GaN materials due to their cost-effectiveness. However, due to the large lattice mismatch between sapphire substrates and GaN, a two-step method is currently used to grow GaN of a certain thickness to improve the epitaxial layer quality, first achieving full three-dimensional growth and then two-dimensional growth. However, due to the large thermal mismatch between sapphire and GaN, the lack of effective methods to improve epitaxial layer warpage during GaN epitaxy on large-size (4 inches or larger) sapphire substrates leads to significant wafer warpage after the epitaxial process, increasing the difficulty of subsequent chip manufacturing processes and affecting chip yield.
[0004] In summary, existing technologies for growing GaN epitaxial layers on sapphire substrates suffer from significant epitaxial layer warping. Summary of the Invention
[0005] The purpose of this application is to provide a semiconductor structure and its fabrication method to solve the problem of significant epitaxial layer warping in the prior art when growing GaN epitaxy on a sapphire substrate.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:
[0007] On one hand, embodiments of this application provide a semiconductor structure, the semiconductor structure comprising:
[0008] Sapphire substrate;
[0009] An AlN buffer layer located on one side of the sapphire substrate;
[0010] A seed layer located on the side of the AlN buffer layer away from the sapphire substrate; wherein the seed layer includes a plurality of spaced-apart base islands;
[0011] A merged layer located on the side of the seed crystal layer away from the sapphire substrate;
[0012] A discontinuous SiN insertion layer located on the side of the merged layer away from the sapphire substrate;
[0013] A merging layer located on the side of the merging layer and the insertion layer away from the sapphire substrate; wherein the seed layer, the merging layer and the merging layer are all made of GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the merging layer, the insertion layer and the merging layer is less than 1 μm.
[0014] Optionally, the reflectivity of the AlN buffer layer is greater than that of the seed crystal layer, and the reflectivity of the seed crystal layer, the merging layer, and the converging layer increases sequentially.
[0015] Optionally, the reflectivity of the AlN buffer layer is 0.1 to 0.13, the reflectivity of the seed crystal layer is less than 0.05, the reflectivity of the merged layer is 0.16 to 0.2, and the reflectivity of the fused layer is 0.19 to 0.23.
[0016] Optionally, the thickness of the AlN buffer layer is 20-50 nm, the average thickness of the seed layer is less than 80 nm, the thickness of the merging layer is less than or equal to 150 nm, the thickness of the insertion layer is 0.5-3 nm, and the thickness of the merging layer is less than or equal to 800 nm.
[0017] Optionally, the ratio of the area of the merged layer not covered by the insert layer to the surface area of the merged layer is 10% to 40%.
[0018] On the other hand, embodiments of this application also provide a method for fabricating a semiconductor structure, used to fabricate the aforementioned semiconductor structure, the method comprising:
[0019] Provide a sapphire substrate;
[0020] An AlN buffer layer is sputtered onto one side of the sapphire substrate;
[0021] A seed layer is grown on the side of the AlN buffer layer away from the sapphire substrate; wherein the seed layer includes a plurality of spaced-apart base islands;
[0022] A merging layer is grown on the side of the seed layer away from the sapphire substrate;
[0023] A discontinuous SiN insertion layer is grown in situ on the side of the merged layer away from the sapphire substrate;
[0024] A fusion layer is grown on the side of the sapphire substrate away from the merging layer and the insertion layer; wherein the seed layer, the fusion layer and the fusion layer are all made of GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the fusion layer, the fusion layer and the fusion layer is less than 1 μm.
[0025] Optionally, the step of sputtering an AlN buffer layer on one side of the sapphire substrate includes:
[0026] An AlN buffer layer with a sputtered reflectivity of 0.085 to 0.115 is deposited on one side of the sapphire substrate;
[0027] Following the step of sputtering an AlN buffer layer on one side of the sapphire substrate, the method further includes:
[0028] The sapphire substrate and the AlN buffer layer are annealed, and the reflectivity of the AlN buffer layer is increased by 10% to 20% after annealing.
[0029] Optionally, the step of growing a seed layer based on the side of the AlN buffer layer away from the sapphire substrate includes:
[0030] Seed crystal layers are grown under conditions of 900-1000℃, 450mbar-750mbar, and a V / III element ratio of 800-2000.
[0031] Optionally, the step of growing a merged layer based on the side of the seed layer away from the sapphire substrate includes:
[0032] Merged layers were grown under conditions of 1000-1100℃, 100mbar-200mbar, and a V / III element ratio of 1500-4000.
[0033] Optionally, the step of growing an insertion layer based on the side of the merged layer away from the sapphire substrate includes:
[0034] Using SiH4 and ammonia as reaction raw materials, the material is grown for 30S-70S at a temperature of 1000-1100℃ and a pressure of 100mbar-200mbar to form an insertion layer.
[0035] Compared with the prior art, this application has the following effects:
[0036] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a sapphire substrate, an AlN buffer layer located on one side of the sapphire substrate, a seed layer located on the side of the AlN buffer layer away from the sapphire substrate, wherein the seed layer includes a plurality of spaced-apart base islands, a merging layer located on the side of the seed layer away from the sapphire substrate, a discontinuous SiN insertion layer located on the side of the merging layer away from the sapphire substrate, and a fusion layer located on the side of the merging layer and the insertion layer away from the sapphire substrate. The seed layer, the merging layer, and the fusion layer are all made of GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the merging layer, the insertion layer, and the fusion layer is less than 1 μm. On the one hand, because the thickness of the other layers besides the sapphire substrate in the semiconductor structure provided in this application is less than 1 μm, an ultrathin epitaxial film is formed on the sapphire substrate, thus effectively alleviating the warping of the epitaxial layer. On the other hand, in the semiconductor structure of this application, by setting a structure including a seed layer, a merging layer, an insertion layer and a closing layer of the base island, a rapid turning of dislocations can be achieved, which is conducive to the annihilation of dislocations. Therefore, the epitaxial crystal quality of the entire semiconductor structure is high.
[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 An exemplary flowchart illustrating a semiconductor structure fabrication method provided in an embodiment of this application.
[0040] Figure 2 Provided for the embodiments of this application Figure 1 A schematic cross-sectional view of S104.
[0041] Figure 3 Provided for the embodiments of this application Figure 1 A schematic cross-sectional view of S106.
[0042] Figure 4 Provided for the embodiments of this application Figure 1 A schematic cross-sectional view of S108.
[0043] Figure 5 This is a schematic diagram of reflectivity provided in an embodiment of this application.
[0044] Figure 6 Provided for the embodiments of this application Figure 1 A schematic cross-sectional view of S110.
[0045] Figure 7 Provided for the embodiments of this application Figure 1 A schematic cross-sectional view of S112. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0047] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0048] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0049] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0050] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0051] As described in the background section, heterogeneous substrates are generally used when growing GaN materials in the prior art. Among them, sapphire substrates are commonly used heterogeneous substrates. However, the thermal mismatch between sapphire and GaN materials is large, which can lead to significant wafer warping after epitaxy when GaN is epitaxially grown on large-size sapphire substrates.
[0052] In view of this, this application provides a semiconductor structure fabrication method that solves the problem of significant wafer warpage after epitaxial processing by fabricating an ultrathin epitaxial layer.
[0053] The semiconductor structure fabrication method provided in this application is illustrated below:
[0054] As an optional implementation, please refer to Figure 1 The method includes:
[0055] S102 provides a sapphire substrate;
[0056] S104, based on AlN buffer layer sputtered on sapphire substrate;
[0057] S106, a seed layer is grown on the side of the AlN buffer layer away from the sapphire substrate; wherein, the seed layer includes a plurality of spaced-apart base islands;
[0058] S108, a merged layer is grown on the side of the seed layer away from the sapphire substrate;
[0059] S110, based on the in-situ growth of a discontinuous SiN insertion layer on the side of the merged layer away from the sapphire substrate;
[0060] S112, a merging layer is grown on the side of the sapphire substrate away from the merging layer and the insertion layer; wherein the materials used to fabricate the seed layer, the merging layer and the merging layer are all GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the merging layer, the merging layer and the merging layer is less than 1 μm.
[0061] In this application, when growing the epitaxial layer (which includes an AlN buffer layer, a seed layer, a merging layer, a convergence layer, and a converging layer), an ultrathin GaN epitaxial film with a total thickness of no more than 1 μm is used, and the epitaxial film is less prone to warping, thus achieving the goal of improving epitaxial layer warping. Simultaneously, the epitaxial layer structure described above enables rapid dislocation turning, which is beneficial for dislocation annihilation, thereby improving the growth quality of the epitaxial layer.
[0062] In one implementation, in order to grow an ultrathin GaN epitaxial film with a thickness of no more than 1 μm, the flat sapphire substrate provided in this application has an initial reflectivity of 0.074 to 0.078.
[0063] The reflectivity provided in this application refers to the reflectivity of the material surface to 633nm light. For example, the initial reflectivity of a sapphire substrate represents the reflectivity of the sapphire substrate surface to 633nm light; the reflectivity of an AlN buffer layer represents the reflectivity of the AlN buffer layer surface to 633nm light. Furthermore, reflectivity is used to characterize the surface morphology of a material, and the reflectivity is not the same for different materials; for the same material, a higher reflectivity indicates a smoother surface.
[0064] By acquiring the reflectivity of each material surface, the growth process of the epitaxial layer can be monitored, thereby ensuring that the epitaxial layer grows according to the specified parameters and guaranteeing the growth quality of the epitaxial layer.
[0065] When growing an AlN buffer layer on a sapphire substrate, it can be grown by sputtering on a flat sapphire substrate using a PVD device. The structure after growing the AlN buffer layer is as follows: Figure 2 As shown. It should be noted that in order to grow a high-quality GaN epitaxial layer, base islands need to be grown on the seed layer so that dislocations are not only along the vertical direction. This facilitates the bending of penetrating dislocations in the seed layer, thus providing a basis for the subsequent annihilation of dislocations.
[0066] Building upon this, AlN can be chosen as the material for the AlN buffer layer to grow a seed layer comprising multiple spaced-apart base islands. The seed layer fully utilizes the surface roughness of the AlN buffer layer after annealing for a certain period at a specific thickness. GaN is then grown on top of this seed layer. Since the GaN lattice is larger than AlN, GaN is subjected to compressive stress. This mismatch stress drives GaN to form island-like morphologies. Simultaneously, the presence of compressive stress also drives the bending of the GaN seed layer through dislocations, thus providing a foundation for subsequent dislocation annihilation.
[0067] Meanwhile, the thickness of the AlN buffer layer needs to be strictly controlled during growth. If an excessively thick AlN buffer layer is used, the surface flatness of the deposited AlN buffer layer will be very high (generally with a reflectivity exceeding 0.13). Growing a GaN seed layer on top of this will make it difficult to form a small seed layer, instead resulting in a continuous large seed film. This means the base island morphology of the seed layer is difficult to achieve, and the seed film layer has little or no lateral growth, making it difficult to achieve bending of subsequent penetrating dislocations and hindering high-quality epitaxial growth. Conversely, if a thinner AlN buffer layer is used, the GaN seed layer on the AlN buffer layer will form very tall three-dimensional base islands. The long merging time makes effective merging difficult within a total thickness of 1µm. Furthermore, the introduction of intercalation layers on the three-dimensional base islands further increases the difficulty of subsequent merging, leading to more merging defects. Therefore, if the AlN buffer layer is too thin, it will be impossible to grow epitaxial films with a thickness less than 1µm, and there will be large merging defects, reducing the quality of epitaxial layer growth. The applicant's research found that epitaxial layer growth is more effective when the AlN buffer layer thickness is 20–50 nm. Therefore, the AlN buffer layer provided in this application has a thickness of 20–50 nm. Furthermore, the reflectivity of the AlN buffer layer grown by sputtering is 0.085–0.115.
[0068] It should be noted that the existing patent with application number CN202111261789.2 also mentions sputtering an AlN layer on a sapphire substrate, but its thickness is 8-17 nm, and it limits the formation of holes exposing the sapphire substrate after annealing. In this application, the AlN buffer layer cannot be so thin, because such a thin AlN base island exposed on the sapphire would result in extremely strong three-dimensionality, which would greatly affect the bonding time.
[0069] After growing the AlN buffer layer, subsequent epitaxial layer structures can be grown. One way to achieve this is to place the substrate after growing the AlN buffer layer into the reaction chamber of the MOCVD equipment and use the MOCVD process to grow the subsequent epitaxial layers, that is, to use the MOCVD process to grow seed layers, merging layers, insertion layers and fusion layers.
[0070] In this process, after the substrate with the grown AlN buffer layer is placed in the reaction chamber, it can be annealed at a certain temperature for a certain period of time, for example, 60s-480s. This increases the reflectivity of the AlN buffer layer by 10%-20%, and the surface atoms of the AlN buffer layer undergo reorganization. Using the growth conditions of the seed layer, a seed layer morphology for discrete base islands can be achieved on the reorganized AlN buffer layer surface atoms, which is beneficial for dislocation turning at the heteroepitaxial interface and can significantly reduce dislocations in subsequent epitaxial layers. In one implementation, the reflectivity of the annealed AlN buffer layer is 0.1-0.13. Within this reflectivity range, the surface roughness of the AlN buffer layer is more conducive to the formation of base islands in the seed layer.
[0071] In one implementation, after the annealing process, the reaction chamber environment can be raised to the temperature, pressure, and V / III element ratio conditions required for GaN seed layer growth using a TMG organic source. The V / III element ratio refers to the ratio of the molar number of group V source to the molar number of group III source. Generally, ammonia is used as the group V source, and trimethylgallium (TMGa) is used as the group III source. Optionally, the seed layer can be grown at a temperature of 900-1000℃, a pressure of 450-750 mbar, and a group V / III element ratio of 800-2000. The grown seed layer is as follows: Figure 3 As shown.
[0072] By configuring the AlN buffer layer and the aforementioned growth environment, discontinuous base islands can be grown relatively quickly on the AlN buffer. Specifically, the average thickness of the seed layer is less than 80 nm, and the reflectivity of the seed layer is less than 0.05. Figure 3 The base islands in the seed layer may be partially or completely discontinuous, and the base islands mentioned in this application refer to the structure of each protrusion therein. Understandably, due to the presence of discontinuous base islands, the surface of the seed layer is not smooth, and therefore its reflectivity is much lower than that of the AlN buffer layer.
[0073] The base islands in the seed layer facilitate the bending of dislocations, which in turn facilitates the annihilation of dislocations. However, the surface of the epitaxial layer after growth needs to be relatively flat. Therefore, this application achieves the gradual merging of the base islands by setting the reflectivity of the seed layer, the merging layer and the merging layer to increase sequentially in the subsequent epitaxial layer structure, thereby growing an epitaxial layer with high flatness.
[0074] The seed layer, merging layer, and converging layer constitute the main structure of the epitaxial layer, all made of GaN. During the growth of the GaN merging layer, based on the goal of growing an ultrathin GaN epitaxial layer, it is essential to achieve a certain level of flatness through GaN epitaxial merging as quickly as possible. Research has found that using continuously varying low-pressure, high 5 / 3 ratio, and high-temperature conditions can achieve surface flatness in the shortest time, resulting in a reflectivity of 0.16–0.2 for the merging layer. For example, the merging layer can be grown at temperatures of 1000–1100℃, pressures of 100–200 mbar, and V / III element ratios of 1500–4000. The grown merging layer is shown below. Figure 4 As shown. It should be noted that, please refer to [link / reference needed]. Figure 5 Since the reflectivity of the merged layer is oscillating, the reflectivity range of the merged layer described in this application represents the median range of the oscillating reflection curve. It should also be noted that, because the thickness of the GaN merged layer affects the overall thickness of the epitaxial film, the thickness of the GaN merged layer provided in this application does not exceed 150 nm.
[0075] Within the aforementioned reflectivity and thickness ranges, the merged layer allows dislocations to bend most effectively, facilitating dislocation annihilation. Simultaneously, the corresponding SiN insertion layer provides better dislocation blocking, reducing dislocations along the growth direction and enabling more dislocations to bend effectively, thus achieving high-quality epitaxial growth at the target thickness.
[0076] It should be noted that if the merging layer is too thick, it will be difficult to achieve high-quality flatness in the subsequent merging layer within a total thickness of 1µm. If the reflectivity of the merging layer is too high, it will also result in a high degree of two-dimensionality, meaning that the dislocations at the turning point of the seed layer cannot be effectively annihilated, and more mismatch dislocations will be generated due to the merging of the base islands. Moreover, the high surface reflectivity will also affect the morphology of the subsequent SiN insertion layer. An overly rough merging layer will lead to uneven distribution of the SiN insertion layer, resulting in a poorer dislocation blocking effect and hindering the flattening of the discrete islands in the subsequent merging layer. At the same time, excessively inconsistent orientation of the discrete islands will also generate more mismatch dislocations during merging, which is not conducive to the growth of high-quality epitaxy.
[0077] Next, please refer to Figure 6In situ growth of insertion layers on GaN merging layers was carried out using MOCVD technology. The material of the insertion layers was SiN. The insertion layers are mainly used to form a partially discontinuous thin film on the GaN surface with a certain roughness. The film thickness is 0.5-3 nm. The study found that the surface of the SiN insertion layer is more stable after annealing. Since the surface atomic migration time is insufficient during the growth of the SiN layer, annealing for a certain time (annealing time 30-80s) was used to make the surface discontinuity rate stable. The discontinuity rate refers to the ratio of the area of GaN not covered to the total area, that is, the ratio of the area of the insertion layer not covered to the surface area of the merging layer.
[0078] Studies have found that a discontinuity rate in the SiN insertion layer ranging from 10% to 40% best matches the aforementioned surface flatness, thus optimizing the growth of subsequent GaN fusion layers. Too small a discontinuity rate indicates insufficient exposed GaN (i.e., exposed fusion layer), resulting in large distances between GaN islands during the initial fusion stage, requiring an extremely long time to fuse into a planar film, significantly impacting the realization of ultrathin GaN films. Conversely, too large a discontinuity rate indicates excessive exposed GaN, leading to numerous dislocations extending upwards. Furthermore, the fusion between GaN islands in the fusion layer also generates additional dislocations, potentially causing further dislocation increases and even worse film quality.
[0079] In one implementation, SiH4 and ammonia are used as reaction raw materials, and the mixture is grown for 30S-70S at a temperature of 1000-1100℃ and a pressure of 100mbar-200mbar to form an insertion layer.
[0080] Please refer to the following: Figure 7 A GaN rapid merging layer is grown on the annealed SiN insertion layer. This merging layer forms a relatively flat plane on the surface of the epitaxial layer. Due to the presence of the SiN insertion layer, a certain spacing is required in the initial growth of the GaN merging layer to achieve good dislocation blocking. The merging layer needs to achieve rapid lateral merging and a flat surface during epitaxial growth within a short time. Therefore, the epitaxial growth conditions are set as follows: reaction chamber temperature range of 1000-1100℃, reaction chamber pressure range of 100mbar-200mbar, and group V / III element ratio of 1500-4000. Furthermore, since the thickness of the GaN merging layer determines the overall film thickness, in this application, to meet the requirements of an ultrathin GaN epitaxial layer, the thickness of the GaN merging layer does not exceed 800nm.
[0081] In summary, the above-described process enables the growth of ultrathin GaN epitaxial layers on sapphire substrates, preventing epitaxial layer warping. Furthermore, the reflectivity of each layer during growth allows for monitoring of the epitaxial layer growth process, ensuring high-quality growth. Additionally, the design of rapid fusion using a specially thick sputtered AlN buffer layer and GaN with a certain surface roughness before SiN insertion enables rapid dislocation turning, which facilitates dislocation annihilation and improves the epitaxial layer growth quality.
[0082] Based on the above implementation, this application embodiment also provides a semiconductor structure, which includes a sapphire substrate, an AlN buffer layer on one side of the sapphire substrate, a seed layer on the side of the AlN buffer layer away from the sapphire substrate, wherein the seed layer includes a plurality of spaced-apart base islands, a merging layer on the side of the seed layer away from the sapphire substrate, a discontinuous SiN insertion layer on the side of the merging layer away from the sapphire substrate, and a merging layer on the side of the merging layer and the insertion layer away from the sapphire substrate; wherein the seed layer, the merging layer and the merging layer are all made of GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the merging layer, the insertion layer and the merging layer is less than 1 μm.
[0083] Among them, the reflectivity of the AlN buffer layer is greater than that of the seed crystal layer, and the reflectivity of the seed crystal layer, the merging layer, and the agglomeration layer increases sequentially. In one implementation, the reflectivity of the AlN buffer layer is 0.1 to 0.13, the reflectivity of the seed crystal layer is less than 0.05, the reflectivity of the merging layer is 0.16 to 0.2, and the reflectivity of the agglomeration layer is 0.19 to 0.23.
[0084] Optionally, the material used to fabricate the AlN buffer layer is AlN, the material used to fabricate the insertion layer is SiN, and the material used to fabricate the seed layer, merging layer, and bonding layer is GaN.
[0085] Furthermore, the thickness of the AlN buffer layer is 20–50 nm, the average thickness of the seed layer is less than 80 nm, the thickness of the merging layer is less than or equal to 150 nm, the thickness of the insertion layer is 0.5–3 nm, and the thickness of the merging layer is less than or equal to 800 nm.
[0086] In addition, the ratio of the area of the merged layer that is not covered by the insertion layer to the surface area of the merged layer is 10% to 40%.
[0087] In summary, this application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a sapphire substrate, an AlN buffer layer located on one side of the sapphire substrate, a seed layer located on the side of the AlN buffer layer away from the sapphire substrate, wherein the seed layer includes multiple spaced-apart base islands, a merging layer located on the side of the seed layer away from the sapphire substrate, a discontinuous SiN insertion layer located on the side of the merging layer away from the sapphire substrate, and a fusion layer located on the side of the merging layer and the insertion layer away from the sapphire substrate. The seed layer, the merging layer, and the fusion layer are all made of GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the merging layer, the insertion layer, and the fusion layer is less than 1 μm. On the one hand, because the thickness of the other layers besides the sapphire substrate in the semiconductor structure provided by this application is less than 1 μm, an ultrathin epitaxial film is formed on the sapphire substrate, thus effectively mitigating epitaxial layer warpage. On the other hand, in the semiconductor structure of this application, by setting a structure including a seed layer, a merging layer, an insertion layer and a closing layer of the base island, a rapid turning of dislocations can be achieved, which is conducive to the annihilation of dislocations. Therefore, the epitaxial crystal quality of the entire semiconductor structure is high.
[0088] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
[0089] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A semiconductor structure, characterized by, The semiconductor structure includes: Sapphire substrate; An AlN buffer layer located on one side of the sapphire substrate; A seed layer located on the side of the AlN buffer layer away from the sapphire substrate; wherein the seed layer includes a plurality of spaced-apart base islands; A merged layer located on the side of the seed crystal layer away from the sapphire substrate; A discontinuous SiN insertion layer located on the side of the merged layer away from the sapphire substrate; A merging layer located on the side of the merging layer and the insertion layer away from the sapphire substrate; wherein the seed layer, the merging layer and the merging layer are all made of GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the merging layer, the insertion layer and the merging layer is less than 1 μm.
2. The semiconductor structure of claim 1, wherein, The reflectivity of the AlN buffer layer is greater than that of the seed crystal layer, and the reflectivity of the seed crystal layer, the merging layer, and the converging layer increases sequentially.
3. The semiconductor structure of claim 2, wherein, The reflectivity of the AlN buffer layer is 0.1 to 0.13, the reflectivity of the seed crystal layer is less than 0.05, the reflectivity of the merged layer is 0.16 to 0.2, and the reflectivity of the combined layer is 0.19 to 0.
23.
4. The semiconductor structure of claim 1, wherein, The thickness of the AlN buffer layer is 20-50 nm, the average thickness of the seed layer is less than 80 nm, the thickness of the merging layer is less than or equal to 150 nm, the thickness of the insertion layer is 0.5-3 nm, and the thickness of the merging layer is less than or equal to 800 nm.
5. The semiconductor structure of claim 1, wherein, The ratio of the area of the merged layer not covered by the insert layer to the surface area of the merged layer is 10% to 40%.
6. A method of fabricating a semiconductor structure, the method comprising: The method for fabricating a semiconductor structure as described in any one of claims 1 to 5 includes: Provide a sapphire substrate; An AlN buffer layer is sputtered onto one side of the sapphire substrate; A seed layer is grown on the side of the AlN buffer layer away from the sapphire substrate; wherein the seed layer includes a plurality of spaced-apart base islands; A merging layer is grown on the side of the seed layer away from the sapphire substrate; A discontinuous SiN insertion layer is grown in situ on the side of the merged layer away from the sapphire substrate; A fusion layer is grown on the side of the sapphire substrate away from the merging layer and the insertion layer; wherein the seed layer, the fusion layer and the fusion layer are all made of GaN, and the sum of the thicknesses of the AlN buffer layer, the seed layer, the fusion layer, the fusion layer and the fusion layer is less than 1 μm.
7. The method of claim 6, wherein The step of sputtering an AlN buffer layer on one side of the sapphire substrate includes: An AlN buffer layer with a sputtered reflectivity of 0.085 to 0.115 is deposited on one side of the sapphire substrate; Following the step of sputtering an AlN buffer layer on one side of the sapphire substrate, the method further includes: The sapphire substrate and the AlN buffer layer are annealed, and the reflectivity of the AlN buffer layer is increased by 10% to 20% after annealing.
8. The method of claim 7, wherein The step of growing a seed layer on the side of the AlN buffer layer away from the sapphire substrate includes: Seed crystal layers are grown under conditions of 900-1000℃, 450mbar-750mbar, and a V / III element ratio of 800-2000.
9. The semiconductor structure fabrication method as described in claim 7, characterized in that, The step of growing a merged layer based on the side of the seed layer away from the sapphire substrate includes: Merged layers were grown under conditions of 1000-1100℃, 100mbar-200mbar, and a V / III element ratio of 1500-4000.
10. The method of claim 7, wherein The step of growing an insertion layer based on the side of the merged layer away from the sapphire substrate includes: Using SiH4 and ammonia as reaction raw materials, the material is grown for 30S-70S at a temperature of 1000-1100℃ and a pressure of 100mbar-200mbar to form an insertion layer.