A method for producing doped single crystal silicon, doped single crystal silicon, a method for producing a silicon slice

Abstract

This invention provides a method for preparing doped monocrystalline silicon, and a method for preparing doped monocrystalline silicon wafers. The preparation method includes the following steps: providing a crucible, the crucible including a bottom and a wall; the crucible including a first accommodating cavity and a second accommodating cavity; the first accommodating cavity being formed by the bottom and wall of the crucible; the second accommodating cavity being a groove structure formed by the bottom of the crucible recessed away from the opening of the crucible, the second accommodating cavity being interconnected with the first accommodating cavity; the opening area of ​​the second accommodating cavity being smaller than the bottom area of ​​the first accommodating cavity; placing a portion of the doping material in the second accommodating cavity, and placing silicon material and the remaining doping material in the first accommodating cavity to form a material system; sequentially performing melting and pulling processes on the material system to obtain doped monocrystalline silicon. This method for preparing doped monocrystalline silicon can produce silicon rods with low segregation and high yield.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a method for preparing doped monocrystalline silicon, a method for preparing doped monocrystalline silicon wafers. Background Technology

[0002] Back-contact (BC) cells offer significant advantages such as no grid line obstruction on the front side and high light absorption efficiency, making them the mainstream high-efficiency cell technology for mass production of photovoltaic modules. They place stringent requirements on the substrate monocrystalline silicon, demanding not only high carrier mobility, uniform resistivity, and high minority carrier lifetime to accommodate key processes like high-precision partitioned diffusion and low-temperature metallization on the back side, but also compatibility with large-size silicon wafers and existing CZ Czochralski furnace mass production platforms. Furthermore, they must possess long-term outdoor stability to avoid power degradation caused by defects such as boron-oxygen complexes, thus meeting lifespan requirements.

[0003] Currently, BC battery substrates mainly use element-doped single-crystal silicon, which has obvious limitations in large-scale mass production. During crystal growth and subsequent high-temperature preparation, the doping elements are prone to redistribution, resulting in uneven element distribution within the silicon crystal. This leads to severe crystal rod segregation and low yield of silicon rods, making it difficult to meet the high-precision doping process requirements of BC batteries.

[0004] Therefore, the industry urgently needs to develop a preparation method that can effectively suppress the uneven distribution of elements within silicon crystals during the preparation process, in order to improve the problems of severe crystal segregation and low silicon rod yield. Summary of the Invention

[0005] This invention provides a method for preparing doped monocrystalline silicon, a method for preparing doped monocrystalline silicon and silicon wafers. The method for preparing doped monocrystalline silicon can produce silicon rods with low segregation and high yield.

[0006] This invention provides a method for preparing doped single-crystal silicon, comprising the following steps:

[0007] A crucible is provided, the crucible including a crucible bottom and a crucible wall;

[0008] The crucible includes a first receiving cavity and a second receiving cavity;

[0009] The first accommodating cavity is formed by the bottom of the crucible and the crucible wall;

[0010] The second accommodating cavity is a groove structure formed by the bottom of the crucible being recessed in a direction away from the opening of the crucible, and the second accommodating cavity is in communication with the first accommodating cavity;

[0011] The opening area of ​​the second accommodating cavity is smaller than the bottom area of ​​the first accommodating cavity;

[0012] A portion of the doped material is placed in the second accommodating cavity, and the silicon material and the remaining doped material are placed in the first accommodating cavity to form a material system;

[0013] The raw material system is subjected to melting and pulling processes in sequence to obtain the doped single crystal silicon.

[0014] In some embodiments of the present invention, the concentration of the dopant element in the doped raw material in the raw material system is 1×10⁻⁶. 15 ~5×10 16 atoms / cm 3 ;

[0015] And / or, the drawing process is performed at a pressure of 0.07 MPa to 0.1 MPa and at a temperature of 1435°C to 1440°C;

[0016] And / or, the temperature gradient of the raw material liquid surface towards the opening of the crucible during the drawing process is 9℃ / mm ~ 11℃ / mm.

[0017] In some embodiments of the present invention, the height of the second accommodating cavity accounts for 10% to 80% of the thickness of the bottom of the crucible;

[0018] And / or, the opening area of ​​the second accommodating cavity accounts for 5% to 30% of the bottom area of ​​the first accommodating cavity.

[0019] In some embodiments of the present invention, the mass ratio of the partially doped material to the remaining doped material is (1:9):(9:1).

[0020] And / or, the doping element in the doped material includes one or more elements with an atomic mass greater than that of silicon; preferably, the doping element includes one or more of antimony, arsenic, and gallium.

[0021] In some embodiments of the present invention, the crucible is a 32-inch crucible, and the diameter of the second accommodating cavity is 80mm~150mm, and the depth is 40mm~100mm;

[0022] The crucible is a 36-inch crucible, and the diameter of the second accommodating cavity is 80mm~150mm, and the depth is 40mm~100mm.

[0023] In some embodiments of the present invention, the drawing pressure in the 32-inch crucible is 0.07 MPa to 0.09 MPa;

[0024] And / or, in the 36-inch crucible, the pressure of the drawing process is 0.08 MPa ~ 0.1 MPa;

[0025] And / or, in the 32-inch crucible, the melting treatment temperature is 1435℃~1440℃, the treatment time is 45min~50min, and the inert gas flow rate is 50 L / min~60 L / min;

[0026] And / or, in the 36-inch crucible, the melting treatment temperature is 1435℃~1440℃, the treatment time is 55min~65min, and the inert gas flow rate is 50 L / min~60 L / min;

[0027] And / or, the ratio of the height of the raw material system to the height of the crucible wall is ≤70%.

[0028] In some embodiments of the present invention, the melting process further includes dividing the remaining doped material into N portions and adding them into the crucible, where N ≥ 2;

[0029] And / or, the melting process further includes a stirring process, wherein the stirring speed is 0.5~10 r / min;

[0030] And / or, the drawing process further includes sequentially subjecting the drawn product to annealing, cooling, cutting, and polishing.

[0031] This invention also provides a doped single-crystal silicon, which is prepared by the doped single-crystal silicon preparation method described above.

[0032] The present invention also provides a method for preparing a silicon wafer, including processing the doped single-crystal silicon obtained by the doped single-crystal silicon preparation method described above, or processing the doped single-crystal silicon as described above.

[0033] In some embodiments of the present invention, the processing includes sequential laser diffusion treatment, passivation treatment, and back-side sintering treatment;

[0034] The laser diffusion process is carried out at a temperature of 850℃ to 900℃ for 15 min to 20 min.

[0035] And / or, the thickness of the alumina layer formed by the passivation treatment is 10nm~100nm, the thickness of the silicon nitride layer is 80nm~85nm, and the thickness of the silicon oxide layer is 10nm~100nm;

[0036] And / or, the temperature of the back sintering treatment is 750℃~800℃.

[0037] The present invention provides a method for preparing doped single-crystal silicon, a method for preparing doped single-crystal silicon and silicon wafers. By setting a groove at the bottom of the crucible, the uniformity of the distribution of doped elements in the silicon melt can be effectively improved, resulting in more uniform doped elements in the prepared silicon rod, and thus a lower degree of segregation and a higher yield. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0039] Figure 1 This is a schematic diagram of the crucible structure provided in an embodiment of the present invention.

[0040] Explanation of reference numerals in the attached figures

[0041] 1: Crucible wall; 2: Crucible bottom; 3: First accommodating cavity; 4: Second accommodating cavity.

[0042] The accompanying drawings have illustrated specific embodiments of the invention, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0044] Currently, conventional methods for preparing doped single-crystal silicon suffer from the problem of low uniformity of dopant element distribution in the silicon melt, resulting in severe segregation and low yield of the prepared silicon rods.

[0045] Existing preparation technologies still have many obvious drawbacks: co-doping technology is prone to lattice distortion and high impurity residue, resulting in a significant reduction in cell yield; relying solely on thermal gradient optimization is difficult to control resistivity uniformity, and the resistivity deviation at the beginning and end of the crystal rod is too large, which cannot meet the consistency requirements of BC cells; using a dedicated doping device requires a high cost of modification to the existing 1600-type Czochralski furnace, which is complex to maintain and is not suitable for mass production; while the traditional CZ Czochralski method is prone to problems such as melt bottom agglomeration and crystal rod segregation due to the large difference in density between the doping element (e.g., antimony) and silicon, resulting in low crystal rod yield and a lack of mature processes adapted to 210mm large-size silicon wafers and BC cells, making it difficult to achieve large-scale mass production applications.

[0046] Therefore, there is an urgent need to improve existing methods for preparing doped single-crystal silicon.

[0047] Based on this, embodiments of the present invention provide a method for preparing doped single-crystal silicon, comprising the following steps:

[0048] A crucible is provided, comprising a crucible bottom and crucible walls;

[0049] The crucible includes a first receiving cavity and a second receiving cavity;

[0050] The first accommodating cavity is formed by the bottom of the crucible and the crucible wall;

[0051] The second accommodating cavity is a groove structure formed by the bottom of the crucible being recessed in the direction away from the opening of the crucible, and the second accommodating cavity is connected to the first accommodating cavity.

[0052] The opening area of ​​the second accommodating cavity is smaller than the bottom area of ​​the first accommodating cavity;

[0053] Part of the doped material is placed in the second cavity, and the silicon material and the remaining doped material are placed in the first cavity to form a material system;

[0054] The raw material system is subjected to melting and pulling processes in sequence to obtain doped single-crystal silicon.

[0055] The present invention provides an embodiment of a method for preparing doped single-crystal silicon, which can produce doped single-crystal silicon rods with low segregation and high yield.

[0056] In detail, the reason why the method for preparing doped single-crystal silicon in this embodiment of the invention can improve the severe segregation and low yield of silicon rods is that: the groove structure can form a relatively stable local melt region, weaken the concentration fluctuation caused by strong global convection during the preparation of doped single-crystal silicon, and allow the dopant element to diffuse slowly and steadily; at the same time, the partitioned placement of dopant raw materials can realize the dynamic release of dopant elements. In the early stage, the dopant in the first accommodating cavity provides the basic concentration, and in the later stage, the dopant raw material in the groove (second accommodating cavity) slowly replenishes the dopant element, compensating for the solute segregation effect during crystal growth and suppressing the axial segregation of the crystal rod; in addition, the groove structure optimizes the bottom melt flow field and reduces the radial concentration gradient, thereby making the axial and radial distribution of dopant elements in the silicon crystal rod more uniform, significantly improving the problem of severe segregation and low yield of silicon rods.

[0057] Some embodiments of the present invention, such as Figure 1As shown, the crucible includes a crucible bottom 2 and a crucible wall 1; the crucible includes a first receiving cavity 3 and a second receiving cavity 4; the first receiving cavity 3 is formed by the crucible bottom 2 and the crucible wall 1 (specifically, the first receiving cavity is formed by the plane where the crucible bottom is located and the crucible wall); the second receiving cavity 3 is a groove structure formed by the crucible bottom 2 being recessed in the direction away from the opening of the crucible, and the second receiving cavity 4 is interconnected with the first receiving cavity 3; the opening area of ​​the second receiving cavity 4 is smaller than the bottom area of ​​the first receiving cavity 3.

[0058] In some embodiments of the present invention, the raw material system is further pretreated before melting, including a crushing process and a drying process performed sequentially. In one specific embodiment, the silicon raw material can be crushed into particles with a particle size range of 20 mm to 50 mm, and the doped raw material can be crushed into particles with a particle size range of 3 mm to 5 mm. In one specific embodiment, the raw material system can be dried so that the moisture content of the raw material system after drying is ≤0.001%.

[0059] The embodiments of the present invention do not impose special limitations on the shape of the groove structure. The groove structure can be, for example, circular, square, or elliptical, but is not limited to these.

[0060] In this embodiment of the invention, the pulling process includes steps such as crystal pulling, shoulder formation, equal diameter pulling, and tail pulling. The process parameters of each step can be adjusted according to the requirements for the crystal rod.

[0061] In some embodiments of the present invention, the concentration of the dopant element in the doped raw material in the raw material system is 1×10⁻⁶. 15 ~5×10 16 atoms / cm 3 This can further optimize doping uniformity, better suppress crystal rod segregation, and improve the resistivity consistency and yield of silicon rods. For example, the concentration of the dopant in the raw material system is, for instance, 1×10⁻⁶. 15 atoms / cm 3 5×10 15 atoms / cm 3 1×10 16 atoms / cm 3 2×10 16 atoms / cm 3 3×10 16 atoms / cm 3 5×10 16 atoms / cm 3 Or a range consisting of any two of them.

[0062] In some embodiments, the pulling process is carried out at a pressure of 0.07 MPa to 0.1 MPa and a temperature of 1435°C to 1440°C, which can further improve the stability of the silicon melt, better suppress dopant agglomeration and crystal segregation, and ensure the continuity and consistency of the silicon rod growth process. For example, the pulling process pressure is, for example, a range of 0.07 MPa, 0.08 MPa, 0.09 MPa, 0.095 MPa, 0.1 MPa, or any two thereof; and the processing temperature is, for example, a range of 1435°C, 1436°C, 1438°C, 1439°C, 1440°C, or any two thereof.

[0063] In some embodiments, the temperature gradient of the raw material liquid surface towards the crucible opening during the pulling process is 9°C / mm to 11°C / mm. This can further optimize the temperature distribution of the silicon melt, better suppress melt convection intensity, further reduce local concentration unevenness of dopants caused by temperature differences, and further improve the segregation problem and yield of silicon rods. For example, the temperature gradient of the raw material liquid surface towards the crucible opening during the pulling process is, for example, a range of 9°C / mm, 9.5°C / mm, 10°C / mm, 10.5°C / mm, 11°C / mm, or any combination thereof.

[0064] In some embodiments, the height of the second accommodating cavity accounts for 10% to 80% of the thickness of the crucible bottom, which can further form a stable local melt region, better control the release rate of dopant elements, further reduce dopant element agglomeration and concentration fluctuations, and further improve the segregation problem and yield of silicon rods. For example, the proportion of the height of the second accommodating cavity to the thickness of the crucible bottom is, for example, 10%, 20%, 40%, 60%, 80%, or any combination thereof.

[0065] In some embodiments of the present invention, the loading amount (raw material system) of the 32-inch crucible is controlled to be 80kg~100kg, and that of the 36-inch crucible is 120kg~150kg.

[0066] In some embodiments, the opening area of ​​the second accommodating cavity accounts for 5% to 30% of the bottom area of ​​the second accommodating cavity, which can further form a stable local melt region, better control the diffusion rate of dopant elements, further reduce dopant element agglomeration and concentration fluctuations, and further improve the segregation problem and yield of silicon rods. For example, the proportion of the opening area of ​​the second accommodating cavity to the bottom area of ​​the second accommodating cavity is, for example, 5%, 10%, 15%, 20%, 30%, or any combination thereof.

[0067] In some embodiments of the present invention, the mass ratio of the partially doped material to the remaining doped material is 1:9 to 9:1, which can further achieve dynamic and stable release of dopant elements, better compensate for the solute segregation effect during crystal growth, further reduce the axial and radial concentration unevenness of the silicon rod, and further improve the segregation problem and yield of the silicon rod. For example, the mass ratio of the partially doped material to the remaining doped material is, for example, 1:9, 3:7, 5:5, 7:3, 9:1, or any combination thereof.

[0068] In some embodiments, the doping elements in the doping material include one or more elements with an atomic mass greater than that of silicon. This further ensures good matching with the silicon lattice, better controls the resistivity and conductivity of single-crystal silicon, further improves doping uniformity and minority carrier lifetime, and further meets the high precision requirements of BC solar cells for substrate materials. Preferably, the doping elements include one or more of antimony, arsenic, and gallium, which provides even better results.

[0069] In some embodiments of the present invention, the crucible is a 32-inch crucible, and the diameter of the second accommodating cavity is 80mm~150mm and the depth is 40mm~100mm. This can further form a stable local melt region, better control the diffusion and release rate of dopant elements, further reduce dopant element agglomeration and concentration fluctuations, further improve the segregation problem and yield of silicon rods, and at the same time, it can better adapt to the existing production line system without the need for major modifications to existing mass production equipment, further reducing mass production adaptation costs.

[0070] In some embodiments, the crucible is a 36-inch crucible, and the diameter of the second accommodating cavity is 80mm~150mm and the depth is 40mm~100mm. This can further stabilize the flow state of the local melt, better control the dissolution and release rate of the doped raw materials, and is more conducive to reducing the concentration fluctuation inside the melt and improving the uniformity of the axial and radial resistivity of the crystal rod. At the same time, it can also be further adapted to existing mass production equipment and production line systems, better reduce equipment modification investment, and is more conducive to achieving efficient and large-scale production.

[0071] In some embodiments, the pulling pressure in the 32-inch crucible is 0.07 MPa to 0.09 MPa, which further stabilizes the melt growth environment, better suppresses melt convection, and is more conducive to ensuring uniform distribution of doped elements, improving silicon rod segregation problems, and increasing yield. For example, the pulling pressure is, for example, a range of 0.07 MPa, 0.075 MPa, 0.08 MPa, 0.085 MPa, 0.09 MPa, or any combination thereof.

[0072] In some embodiments, the pulling pressure in the 36-inch crucible is 0.08 MPa to 0.1 MPa, which can further stabilize the melt growth environment within the 36-inch crucible, better suppress violent melt convection, and better ensure the uniform distribution of dopant elements in the melt, effectively improving silicon rod segregation problems and enhancing the growth quality and yield of single-crystal silicon rods. For example, the pulling pressure is, for instance, 0.08 MPa, 0.085 MPa, 0.09 MPa, 0.095 MPa, 0.1 MPa, or any combination thereof.

[0073] In this embodiment of the invention, the 32-inch crucible maintains a drawing pressure of 0.07MPa to 0.09MPa, and 6L to 8L of inert gas can be added to the 32-inch crucible every 30 minutes; the 36-inch crucible maintains a drawing pressure of 0.08MPa to 0.1MPa, and 7L to 8L of inert gas can be added to the 36-inch crucible every 30 minutes.

[0074] In some embodiments, in a 32-inch crucible, the melting treatment temperature is 1435°C to 1440°C, the treatment time is 45 min to 50 min, and the inert gas flow rate is 50 L / min to 60 L / min. This further ensures that the raw material is fully melted and the melt state is stable, better reducing internal thermal disturbance and impurity volatilization, and is more conducive to improving the uniformity and stability of the subsequent drawing process. For example, the melting treatment temperature is, for example, 1435°C, 1436°C, 1438°C, 1439°C, or 1440°C; the treatment time is, for example, 45 min, 46 min, 47 min, 48 min, 49 min, or 50 min; and the inert gas flow rate is, for example, 50 L / min, 52 L / min, 55 L / min, 58 L / min, or 60 L / min, or any combination thereof.

[0075] In some embodiments, the melting treatment in the 36-inch crucible is carried out at a temperature of 1435°C to 1440°C for 55 min to 65 min, with an inert gas flow rate of 50 L / min to 60 L / min. This further ensures complete and uniform melting of the raw material within the large-size crucible, better eliminating internal temperature gradients and thermal convection within the melt, and improving melt uniformity and subsequent drawing quality. For example, the melting treatment temperature may be 1435°C, 1436°C, 1438°C, 1439°C, or 1440°C; the treatment time may be 55 min, 58 min, 60 min, 62 min, or 65 min; and the inert gas flow rate may be 50 L / min, 52 L / min, 55 L / min, 58 L / min, or 60 L / min, or any combination thereof.

[0076] In some embodiments, the ratio of the raw material liquid level height to the crucible wall height is ≤70%, which further reduces the risk of melt fluctuations during growth, better stabilizes the solid-liquid interface morphology, and is more conducive to improving the overall uniformity and growth stability of the silicon rod. For example, the ratio of the raw material liquid level height to the crucible wall height is, for example, 60%, 62%, 65%, 68%, 70%, or any combination thereof.

[0077] In some embodiments of the present invention, the melting process further includes adding the remaining dopant material into the crucible in N portions, where N ≥ 2. This further enables dynamic and stable replenishment of the dopant elements, better compensates for the solute segregation effect during crystal growth, and helps avoid problems such as excessively high local concentration and uneven doping caused by a single addition, thereby further improving silicon rod segregation and increasing yield. For example, N can be 2, 3, 4, 5, 6, or any integer greater than or equal to 2. The mass of each of the N additions can be the same or different, and can be selected according to the actual situation.

[0078] In some embodiments, the melt treatment further includes a stirring process at a speed of 0.5 r / min to 10 r / min, which further promotes the homogenization of temperature and composition within the melt, better reduces local concentration segregation, and is more conducive to improving the resistivity uniformity of the entire silicon rod. For example, the stirring speed is, for instance, a range of 0.5 r / min, 1 r / min, 2 r / min, 3 r / min, 5 r / min, 6 r / min, 7 r / min, 8 r / min, 9 r / min, 10 r / min, or any combination thereof.

[0079] In some embodiments, the product after the pulling process is further subjected to annealing, cooling, cutting, and polishing processes in sequence to further eliminate internal stress and defects in the crystal, improve the flatness of the silicon rod's appearance and the uniformity of its internal structure, and improve the yield of the silicon rod.

[0080] In some embodiments, the annealing process may include the following steps: After the crystal is pulled (i.e., after the pulling process), the pulled product is moved into the holding zone of the furnace and a segmented annealing process adapted to a 1600-type furnace is adopted to further eliminate the internal stress of the crystal, better improve the crystal lattice integrity, and better ensure the stability of subsequent processing; specifically, the temperature is reduced to 820℃~860℃ at a rate of 2.5℃ / min~3℃ / min. For the pulled product corresponding to the 32-inch crucible, the holding time is 70min~80min, and for the pulled product corresponding to the 36-inch crucible, the holding time is 80min~90min. Through this segmented annealing operation, the stress generated inside the crystal can be effectively eliminated, and defects such as cracking and bending can be better avoided in subsequent processing.

[0081] In some embodiments, the cooling process may include the following steps: after annealing, the temperature is reduced to below 300°C at a rate of 1.5°C / min to 2°C / min, and cooling argon gas is introduced into the furnace. The cooling argon gas flow rate is 70L / min to 80L / min for a 32-inch crucible and 80L / min to 90L / min for a 36-inch crucible. After cooling, the temperature is allowed to cool naturally to room temperature. The furnace can only be opened if the temperature difference between the furnace and room temperature is ≤20°C. After cooling, doped single-crystal silicon is obtained. This cooling process can further avoid secondary stress caused by rapid cooling of the crystal, better ensure the appearance and internal quality of the single-crystal silicon rod, and facilitate the smooth progress of subsequent post-processing.

[0082] In some embodiments, the cutting process includes: using an MB360 multi-wire dicing machine to cut the doped single-crystal silicon obtained after cooling into silicon wafers with a thickness of 220μm to 250μm, which better aligns with mass production trends and is more conducive to large-scale application.

[0083] In some embodiments, the polishing process includes: processing the cut silicon wafer sequentially through a grinding machine and a polishing machine, wherein the grinding machine has an accuracy controlled within ±2μm, removing the defect layer within a 5μm range on the surface of the silicon wafer through grinding, and then polishing the silicon wafer to achieve a surface roughness Ra≤0.2nm; and passing mass production testing.

[0084] In some embodiments of the present invention, the silicon wafers obtained after the above-mentioned annealing, cooling, cutting and polishing processes have an XRD characterization lattice integrity retention rate of ≥98.5%, a resistivity distribution deviation of ≤±6.5% across the wafer, and a minority carrier lifetime of ≥230μs, which further ensures the high quality of the battery substrate, better meets the requirements for use in BC batteries, and is more conducive to improving the photoelectric conversion efficiency of battery devices.

[0085] This invention also provides a doped single-crystal silicon, prepared by the above-described method for preparing doped single-crystal silicon. The doped single-crystal silicon of this invention has advantages corresponding to the above-described method for preparing doped single-crystal silicon, which will not be elaborated upon here.

[0086] This invention also provides a method for preparing a silicon wafer, comprising processing the doped single-crystal silicon obtained by the above-described method for preparing doped single-crystal silicon, or processing the doped single-crystal silicon described above. The silicon wafer preparation method of this invention has advantages corresponding to the above-described method for preparing doped single-crystal silicon, which will not be elaborated upon here.

[0087] In some embodiments of the present invention, the processing includes sequential laser diffusion processing, passivation processing, and back-side sintering processing, which can produce silicon wafers with good light conversion efficiency.

[0088] In some embodiments, the laser diffusion treatment is carried out at a temperature of 850°C to 900°C and for a time of 15 min to 20 min, which further improves the diffusion uniformity of the dopant elements, better controls the doping depth and sheet resistance distribution, and is more conducive to improving the electrical performance and stability of the device. For example, the laser diffusion treatment temperature is, for example, 850°C, 860°C, 870°C, 880°C, or 900°C, and the treatment time is, for example, 15 min, 16 min, 17 min, 18 min, or 20 min, or any combination thereof.

[0089] In some embodiments, the thickness of the alumina layer formed by the passivation treatment is 10 nm to 100 nm, the thickness of the silicon nitride layer is 80 nm to 85 nm, and the thickness of the silicon oxide layer is 10 nm to 100 nm, further improving the surface passivation and interface adaptation effect, better reducing carrier recombination loss, and more conducive to improving minority carrier lifetime and photoelectric conversion efficiency. For example, the thickness of the alumina layer is, for example, 10 nm, 30 nm, 50 nm, 80 nm, or 100 nm; the thickness of the silicon nitride layer is, for example, 80 nm, 81 nm, 82 nm, 83 nm, or 85 nm; and the thickness of the silicon oxide layer is, for example, 10 nm, 30 nm, 50 nm, 80 nm, or 100 nm, or any combination thereof.

[0090] In some embodiments, the back-side sintering temperature is 750°C to 800°C, which further improves the ohmic contact performance between the metal and the silicon substrate, better reduces contact resistance, and is more conducive to improving the fill factor and photoelectric conversion efficiency of the battery. For example, the back-side sintering temperature is, for example, a range of 750°C, 760°C, 770°C, 780°C, 800°C, or any combination thereof.

[0091] The technical solution of the present invention will be further described below with reference to specific embodiments.

[0092] Example 1

[0093] Doped single-crystal silicon in this embodiment of the invention is prepared by the following method:

[0094] 1) Raw material pretreatment: High-purity N-type polycrystalline silicon (i.e., silicon raw material, purity 99.999999%, grade: SMM-N08) and antimony dopant (i.e., dopant raw material, purity 99.999%, in the form of antimony-silicon alloy ingots with a particle size range of 3mm-5mm, antimony content 5wt%) are selected for mass production. The polycrystalline silicon is crushed into particles with a particle size range of 20mm-50mm, and sieved to remove powder with a particle size <20mm (to avoid splashing during melting). The antimony-silicon alloy ingot does not require additional crushing and is dried in a vacuum drying oven (model: DZF-6050, mass production general-purpose model) at 130℃ for 2.5 hours to remove surface adsorbed water (moisture content ≤0.001% after drying). The concentration of the dopant element (antimony) in the raw material system is 2×10⁻⁶. 16 atoms / cm 3 .

[0095] 2) Crucible Loading and Vacuum Melting: A mass-produced 32-inch electric arc furnace quartz crucible (compatible with a 1600-type Czochralski furnace, with an inner layer of 5mm imported transparent quartz sand and an outer layer of bubble composite material) is used. The crucible has a pre-designed circular groove at the bottom (32-inch crucible groove dimensions are φ100mm×60mm). The pre-treated polycrystalline silicon and 50% antimony-silicon alloy ingot are loaded into the main body of the crucible (first receiving cavity). The remaining 50% alloy ingot is laid flat in the groove (second receiving cavity, the height of which is 30% of the crucible bottom thickness, and the opening area of ​​which is 15% of the bottom area of ​​the first receiving cavity). The total weight of the 32-inch crucible (total mass of the raw material system) is 90kg, and the loading height does not exceed 70% of the total crucible height (to avoid melting splashes). The crucible is then placed in the JS-1600 Czochralski furnace, positioned on the furnace support, and aligned with the center of the heating components. After closing the furnace, a vacuum of 3×10⁻⁶ is created using a Roots vacuum pump. -3 Pa, introduce industrial-grade argon gas (purity 99.999%), with an argon flow rate of 55 L / min corresponding to a 32-inch crucible, heat to 1440℃ and melt for 50 min (real-time monitoring by platinum-rhodium thermocouples in the furnace, temperature control accuracy of 1600 furnace ±0.5℃), stir the melt once every 10 min during this period (i.e., stirring treatment, stirring speed 5 r / min, duration 30 s) to ensure that the raw material system is completely melted and mixed evenly, and the standard for acceptance is that there are no obvious particulate impurities on the surface of the melt.

[0096] 3) Temperature Field Regulation and Crystal Seeding: Adjust the power through a 1600-type furnace thermal field controller (dual-zone heating regulation) to stabilize the melt surface temperature gradient at 10 °C / mm (the distance between temperature measurement points is 50 mm, and the temperature difference is controlled within 3 °C). Set the crucible rotation speed to 10 r / min. Select a mass-production standard <100> crystal orientation silicon seed crystal (resistivity 120 Ω·cm, length 200 mm, diameter 8 mm), and slowly lower it to the melt surface through the seed crystal lifting mechanism. Keep the contact temperature at 1415 °C and hold for 8 min (to eliminate the surface stress of the seed crystal). Then, start crystal seeding at a pulling speed of 0.22 mm / min and a seed crystal rotation speed of 19 r / min to form a seed crystal neck with a diameter of 4 mm (qualified if there are no cracks visible to the naked eye, and continue with the subsequent operations). The pressure during the above process is maintained at 0.08 MPa.

[0097] 4) Shoulder Release, Equal-Diameter Growth, and Tail-End Pulling: After crystal seeding is completed, gradually reduce the pulling speed to 0.08 mm / min at a rate of 0.02 mm / min, and at the same time increase the heating power by 2% (corresponding to a temperature increase of 3 °C). Operate at a shoulder release angle of 40°, and observe the crystal diameter through the visual monitoring system. Pull a 210 mm specification crystal rod using a 32-inch crucible. After shoulder release, the pulling speed suitable for a 32-inch crucible is 0.3 mm / min, and the crucible rotation speed is 14 r / min. Keep the melt temperature fluctuation ≤ ±0.5 °C and perform equal-diameter growth. Use an ST-2000 type four-probe tester to sample and detect the resistivity every 30 min, and control the test error within ±2%. The length of the crystal rod is 2.2 m. After the length meets the standard, increase the pulling speed to 0.6 mm / min, and at the same time reduce the heating power by 5%. Slowly perform the tail-end pulling, and the tail-end diameter ≥ 50 mm to reduce raw material waste. It is qualified if there are no obvious cracks. The pressure during the above process is maintained at 0.08 MPa.

[0098] 5) Annealing Treatment and Cooling Treatment: After crystal pulling is completed, move the crystal into the heat preservation area of the furnace. Adopt a process of segmented annealing treatment adapted to the 1600-type furnace. Specifically, cool down to 840 °C at a rate of 3 °C / min and hold for 75 min; then cool down to below 300 °C at a rate of 2 °C / min, introduce cooling argon gas (75 L / min), and naturally cool to room temperature (the furnace can be opened only when the temperature difference between the furnace and room temperature ≤ 20 °C) to obtain antimony-doped single crystal silicon (qualified if there are no bending, cracks, and the surface is smooth, and continue with the subsequent operations).

[0099] 6) Post-treatment: Use an MB360 type multi-wire cutting machine to cut the single crystal silicon rod into silicon wafers with a thickness of 250 μm, and process them through a grinding machine (precision ±2 μm) and a polishing machine to remove the defect layer within 5 μm. After polishing, the surface roughness Ra ≤ 0.2 nm.

[0100] Example 2

[0101] The difference between this embodiment and Embodiment 1 is that in step 1) of this embodiment, the concentration of the dopant element (antimony) in the raw material system is 1×10⁻⁶. 15 atoms / cm 3 In step 2), the height of the second accommodating cavity is 10% of the thickness of the bottom of the crucible, and the opening area of ​​the second accommodating cavity is 5% of the bottom area of ​​the first accommodating cavity; the mass ratio of the partially doped material to the remaining doped material is (1:9), and the pressure of the pulling process is 0.07MPa.

[0102] Example 3

[0103] The difference between this embodiment and Embodiment 1 is that in step 1) of this embodiment, the concentration of the dopant element (antimony) in the raw material system is 5 × 10⁻⁶. 16 atoms / cm 3 In step 2), the height of the second accommodating cavity is 80% of the thickness of the bottom of the crucible, and the opening area of ​​the second accommodating cavity is 30% of the bottom area of ​​the second accommodating cavity; the mass ratio of the partially doped material to the remaining doped material is (9:1), and the pressure of the pulling process is 0.09 MPa.

[0104] Example 4

[0105] The difference between this embodiment and embodiment 1 is that in step 1) and step 2) of this embodiment, the height of the second accommodating cavity accounts for 5% of the thickness of the bottom of the crucible, and the opening area of ​​the second accommodating cavity accounts for 3% of the bottom area of ​​the first accommodating cavity.

[0106] Example 5

[0107] The difference between this embodiment and embodiment 1 is that in step 1) and step 2) of this embodiment, the height of the second accommodating cavity accounts for 85% of the thickness of the bottom of the crucible, and the opening area of ​​the second accommodating cavity accounts for 35% of the bottom area of ​​the first accommodating cavity.

[0108] Comparative Example 1

[0109] The difference between this comparative example and Example 1 is that the crucible in this comparative example is a common 32-inch electric arc method quartz crucible, which does not have a groove on the bottom.

[0110] Test case

[0111] The silicon wafers obtained in the above embodiments and comparative examples were processed as follows:

[0112] 1) Substrate cleaning: Using the BC cell mass production standard cleaning line, the antimony-doped silicon wafers (the silicon wafers obtained by polishing in the above examples and comparative examples) are sequentially placed in an alkaline cleaning tank and an acidic cleaning tank for ultrasonic cleaning; among them, the cleaning solution composition in the alkaline cleaning tank is 2wt% potassium hydroxide + 5wt% isopropyl alcohol, the cleaning temperature is controlled at 60°C, the cleaning solution composition in the acidic cleaning tank is 10wt% hydrofluoric acid + 30wt% nitric acid, the cleaning temperature is controlled at 25°C, the ultrasonic cleaning time for both times is 15 min, and the ultrasonic power is 800 W; after cleaning, taking the continuous and unbroken water film on the silicon wafer surface as the qualified standard, the qualified silicon wafers are placed in a hot air drying oven for drying and standby, the temperature of the hot air drying oven is set at 120°C, and the wind speed is set at 5 m / s.

[0113] 2) Backside diffusion: Using a DL-4000 type laser doping machine, P-type diffusion regions and N-type diffusion regions are prepared in a partitioned manner on the backside of the silicon wafer after the above substrate cleaning, ensuring that the diffusion boundaries are clear and there is no overflow; among them, the P-type diffusion source is borane with a concentration of 5%, the carrier gas is nitrogen, the N-type diffusion source is phosphine with a concentration of 3%, the carrier gas is nitrogen, the diffusion temperature is controlled at 890°C, and the holding time is controlled at 20 min; in this test example, the detection standard is that the sheet resistance of the P region is 120 Ω / □, the sheet resistance of the N region is 100 Ω / □, and the resistance deviation is controlled at ±5%.

[0114] 3) Passivation and metallization: Using a PECVD device to deposit a passivation layer on the surface of the silicon wafer after the above backside diffusion; among them, the passivation layer deposited on the front side of the silicon wafer is 50 nm thick alumina + 85 nm thick silicon nitride, the passivation layer deposited on the back side of the silicon wafer is 60 nm thick silicon oxide, and it is qualified if there is no passivation layer peeling after tape testing; using an SP-900 type screen printing machine, silver electrodes and aluminum electrodes are respectively printed in the PN junction region on the back side of the silicon wafer, where the silver electrode line width is 50 μm and the aluminum electrode thickness is 20 μm, ensuring that the electrodes are precisely fitted to the PN region; the printed silicon wafers are placed in a rapid sintering furnace for sintering to form a good ohmic contact, the sintering temperature is controlled at 790°C, and the sintering time is controlled at 13 min, and finally the BC cell products are obtained; using an IV tester to detect the BC cell products, the detection standard is that the conversion efficiency ≥ 27.5%, and the conversion efficiency of the BC cell products prepared in this test example reaches 27.8%, meeting the qualified standard (20 silicon wafers are tested for each example and comparative example, and the qualification rate is calculated to evaluate the yield of the doping single-crystalline silicon preparation methods in the examples and comparative examples). The test results are shown in Table 1.

[0115] Segregation degree testing method: A four-probe resistivity meter was used to measure the resistivity at 20 points at equal intervals along the axial direction (equal diameter section) of the single-crystal silicon rod. Simultaneously, secondary ion mass spectrometry (SIMS) was used to measure the antimony concentration distribution along the rod's axial direction. The segregation degree was calculated using the formula "Segregation degree = (Maximum resistivity - Minimum resistivity) / Average resistivity × 100%", or the doping uniformity was characterized using the formula "Antimony element concentration coefficient of variation (CV) = Standard deviation / Average value × 100%". A smaller CV indicates better doping uniformity and lower segregation degree. The test results are shown in Table 1.

[0116]

[0117] As shown in Table 1, compared with the comparative example, the present invention effectively improves the yield of silicon rods and reduces the degree of segregation by setting grooves at the bottom of the crucible and dividing the raw materials into sections for the preparation of doped single crystal silicon.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of producing a doped monocrystalline silicon, characterized by, Includes the following steps: A crucible is provided, the crucible including a crucible bottom and a crucible wall; The crucible includes a first receiving cavity and a second receiving cavity; The first accommodating cavity is formed by the bottom of the crucible and the crucible wall; The second accommodating cavity is a groove structure formed by the bottom of the crucible being recessed in a direction away from the opening of the crucible, and the second accommodating cavity is in communication with the first accommodating cavity; The opening area of ​​the second accommodating cavity is smaller than the bottom area of ​​the first accommodating cavity; A portion of the doped material is placed in the second accommodating cavity, and the silicon material and the remaining doped material are placed in the first accommodating cavity to form a material system; The raw material system is subjected to melting and pulling processes in sequence to obtain the doped single crystal silicon.

2. The method of producing a doped monocrystalline silicon according to claim 1, wherein The concentration of the doping element in the doping raw material in the raw material system is 1 x 10 15 atoms / cm 3 ; and the concentration of the doping element in the raw material system is 5 x 10 16 atoms / cm 3 . And / or, the drawing process is performed at a pressure of 0.07 MPa to 0.1 MPa and at a temperature of 1435°C to 1440°C; And / or, the temperature gradient of the raw material liquid surface towards the opening of the crucible during the drawing process is 9℃ / mm~11℃ / mm.

3. The method for preparing doped single-crystal silicon according to claim 1 or 2, characterized in that, The height of the second accommodating cavity accounts for 10% to 80% of the thickness of the bottom of the crucible; And / or, the opening area of ​​the second accommodating cavity accounts for 5% to 30% of the bottom area of ​​the first accommodating cavity.

4. The method for preparing doped single-crystal silicon according to any one of claims 1-3, characterized in that, The mass ratio of the partially doped material to the remaining doped material is (1:9):(9:1). And / or, the doping element in the doped material includes one or more elements with an atomic mass greater than that of silicon; preferably, the doping element includes one or more of antimony, arsenic, and gallium.

5. The method for preparing doped single-crystal silicon according to any one of claims 1-4, characterized in that, The crucible is a 32-inch crucible, and the diameter of the second accommodating cavity is 80mm~150mm, and the depth is 40mm~100mm; The crucible is a 36-inch crucible, and the diameter of the second accommodating cavity is 80mm~150mm, and the depth is 40mm~100mm.

6. The method for preparing doped single-crystal silicon according to claim 5, characterized in that, In the 32-inch crucible, the pressure during the drawing process is 0.07 MPa ~ 0.09 MPa; And / or, in the 36-inch crucible, the pressure of the drawing process is 0.08 MPa ~ 0.1 MPa; And / or, in the 32-inch crucible, the melting treatment temperature is 1435℃~1440℃, the treatment time is 45min~50min, and the inert gas flow rate is 50 L / min~60 L / min; And / or, in the 36-inch crucible, the melting treatment temperature is 1435℃~1440℃, the treatment time is 55min~65min, and the inert gas flow rate is 50 L / min~60 L / min; And / or, the ratio of the height of the raw material system to the height of the crucible wall is ≤70%.

7. The method for preparing doped single-crystal silicon according to claim 5 or 6, characterized in that, The melting process further includes dividing the remaining doped material into N portions and adding them into the crucible, where N≥2; And / or, the melting process further includes a stirring process, wherein the stirring speed is 0.5~10 r / min; And / or, the drawing process further includes sequentially subjecting the drawn product to annealing, cooling, cutting, and polishing.

8. A doped single-crystal silicon, characterized in that, It is prepared by the method for preparing doped single-crystal silicon according to any one of claims 1-7.

9. A method for preparing a silicon wafer, characterized in that, This includes processing the doped single-crystal silicon obtained by the method for preparing doped single-crystal silicon according to any one of claims 1-8, or processing the doped single-crystal silicon according to claim 8.

10. The method for preparing a silicon wafer according to claim 9, characterized in that, The processing includes laser diffusion treatment, passivation treatment, and back sintering treatment performed sequentially. The laser diffusion process is carried out at a temperature of 850℃ to 900℃ for 15 min to 20 min. And / or, the thickness of the alumina layer formed by the passivation treatment is 10nm~100nm, the thickness of the silicon nitride layer is 80nm~85nm, and the thickness of the silicon oxide layer is 10nm~100nm; And / or, the temperature of the back sintering treatment is 750℃~800℃.

Images