Interleaving control channel element to resource element group mapping

Abstract

This invention relates to "interleaving control channel element to resource element group mapping". A system and method for deinterleaving data from multiple resource element groups (REGs) and constructing one or more CCEs based on a control channel element (CCE) to REG mapping includes performing operations including: obtaining a CCE to REG mapping, the CCE to REG mapping including a mapping parameter value for each of one or more mapping parameters; obtaining interleaved data transmission specifying a control resource set (CORESET); selecting a first CCE from a set of CCEs for assembly; for the first CCE: assigning the REG bundle of the interleaved data transmission to the first CCE based on an index value of the REG bundle and based on the mapping parameter value; extracting the REG bundle having the index value into a memory; and combining the extracted REG bundle with any existing extracted REG bundles to generate an assembled CCE in the memory.

Description

[0001] Priority requirements

[0002] This application claims priority to U.S. Patent Application Serial No. 63 / 248,292, filed September 24, 2021, pursuant to 35 U.S. SC §119(e), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates in whole to wireless communications. Background Technology

[0004] For fifth-generation (5G) New Radio (NR) networks, resource allocation is performed using control resource sets (CORESETs). Generally, in Long Term Evolution (LTE) networks, control channels are allocated across the entire system bandwidth. This makes inter-cell interference difficult to control. To address this issue, in 5G NR systems, the Physical Downlink Control Channel (PDCCH) is transmitted within a specially designed CORESET. A CORESET is similar to an LTE control area, but is encapsulated by a set of resource blocks (RBs) and orthogonal frequency division multiplexing (OFDM) symbols. Frequency allocations within a CORESET configuration can be continuous or discontinuous. In the time domain, a CORESET configuration spans one to three consecutive OFDM symbols. REs within a CORESET are organized into REGs (RE groups). Each REG consists of 12 REs from one OFDM symbol within one RB. Summary of the Invention

[0005] This application describes a data processing system and process for mapping control channel elements (CCEs) to resource element groups (REGs). Generally, fifth-generation (5G) New Radio (NR) telecommunications networks support distributed and local resource allocation of DCIs in CORESET.

[0006] The parameters of CORESET are defined as follows: A Resource Element (RE) is the smallest unit of a resource grid and consists of one OFDM symbol comprising one subcarrier. A Resource Element Group (REG) comprises one Resource Block (RB), such that one OFDM symbol has 12 REs. A REG bundle comprises multiple REGs. Here, the REG size is specified by the parameter "L". A CCE comprises multiple REGs. The aggregation level indicates the number of CCEs allocated to the PDCCH. This number can be 1, 2, 4, 8, or 16. Generally, the time-domain and frequency-domain parameters of CORESET are defined in 3GPP TS 38.211. Radio Resource Control (RRC) signaling messages include the following fields: N RB CORESET N is the number of redox receptors (RBs) in the frequency domain within the CORESET. Symb CORESETN is the number of symbols in the time domain of the CORESET. Symb CORESET It can be 1, 2, or 3. N REG CORESET L is the number of REGs in the CORESET. L is the REG bundle size. Generally, the PDCCH channel is limited to one CORESET and transmitted using its own DMRS (Demodulation Reference Signal). User Equipment (UE) specific beamforming can be performed on the control channel. The PDCCH channel is carried by 1, 2, 4, 8, or 16 CCEs to carry various DCI payload sizes or decoding rates. Each CCE includes 6 REGs. The CCE-to-REG mapping of the CORESET can be interleaved (to support frequency diversity) or non-interleaved (for local beamforming). For interleaved CCE-to-REG mapping, the CCE is decomposed into dispersed REG bundles in the frequency domain. A REG bundle is a set of indivisible resources consisting of adjacent REGs. The REG bundle spans all OFDM symbols of a given CORESET. Interleaved CCE-to-REG mapping achieves both time-domain processing gain and frequency-domain diversity.

[0007] The system and process described in this document achieve one or more of the following advantages, as well as others. As previously described, a data processing system (e.g., one or more parts of one or more of the UE or base station) is configured to perform REG deinterleaving functions in the NR PDCCH. The REG bundles constituting the CCE are obtained using a block interleaver to extend different REG bundles by frequency, thereby achieving frequency diversity. The data processing system described herein is configured to be more flexible than existing hardware (HW) instructions. For example, the DECIMATE function is not flexible enough to handle different interleaving configurations, thus requiring the extraction of different REG block sizes and different distances between the extracted blocks to aggregate and construct the CCE. The process described herein uses basic, readily available instructions to perform deinterleaving in firmware or hardware without special HW instructions. The process includes deinterleaving of REGs in both the time and frequency domains. The process includes deinterleaving at symbol boundaries rather than CORESET duration boundaries. The data processing system is configured to initiate deinterleaving earlier in the timeline than could be performed using functions such as DECIMATE or similar functions. The data processing system is configured to deinterleave one symbol at a time, thereby improving the processing timeline by requiring fewer iterations across different frequency bands. The data processing system is configured to aggregate deinterleaved REGs during memory writes to meet the 4-byte limit. Extraction does not require REG alignment. Because extraction can scale to multiple REGs configured per CORESET, extraction time can be reduced significantly compared to extractions that require REG alignment and do not scale to multiple REGs per CORESET. The extraction size is limited to the size of the REG block, which is equal to the number of PDCCH bits per RB x * L divided by the duration.

[0008] The disclosed technology is implemented through one or more specific embodiments, which are subsequently described in the Embodiments section.

[0009] Details of one or more specific embodiments are set forth in the following figures and detailed descriptions. The techniques described herein can be implemented by one or more wireless communication systems, components of wireless communication systems (e.g., sites, access points, user equipment, base stations, etc.) or other systems, devices, methods, or non-transitory computer-readable media. Other features and advantages will become apparent from the detailed descriptions, the figures, and the claims. Attached Figure Description

[0010] Figure 1 Exemplary wireless communication systems according to various specific implementations herein are shown.

[0011] Figure 2 Examples of computing devices according to various specific implementations are shown.

[0012] Figure 3 Exemplary processes for mapping interleaved control channel elements to resource element groups according to some specific implementations of this disclosure are shown.

[0013] Figure 4 Exemplary processes for mapping interleaved control channel elements to resource element groups according to some specific implementations of this disclosure are shown.

[0014] Figure 5A An exemplary representation of generating a CCE from an interleaved REG is shown.

[0015] Figure 5B An exemplary representation of generating a CCE from an interleaved REG is shown.

[0016] Figure 5C The mapping table generated from these parameter values ​​is shown.

[0017] Figure 6 Exemplary processes for mapping interleaved control channel elements to resource element groups according to some specific implementations of this disclosure are shown.

[0018] Similar reference symbols in the various figures indicate similar elements. Detailed Implementation

[0019] Figure 1 An example of a wireless communication system 100 is illustrated. For convenience and not limitation, the exemplary system 100 is described in the context of Long Term Evolution (LTE) and Fifth Generation (5G) New Radio (NR) communication standards, as defined by the 3rd Generation Partnership Project (3GPP) technical specifications. More specifically, the wireless communication system 100 is described in the context of a non-standalone (NSA) network combining both LTE and NR, such as an E-UTRA (Evolved Universal Terrestrial Radio Access)-NR Dual Connectivity (EN-DC) network and a NE-DC network. However, the wireless communication system 100 could also be a standalone (SA) network combining only NR. Furthermore, other types of communication standards are also possible, including future 3GPP systems (e.g., sixth generation (6G)) systems, IEEE 802.16 protocols (e.g., WMAN, WiMAX, etc.), etc.

[0020] like Figure 1As shown, system 100 includes UE 101a and UE 101b (collectively referred to as "UE 101"). In this example, UE 101 is shown as a smartphone (e.g., a handheld touchscreen mobile computing device that can connect to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as consumer electronics devices, mobile phones, smartphones, feature phones, tablets, wearable computing devices, personal digital assistants (PDAs), pagers, wireless handheld devices, desktop computers, laptops, in-vehicle infotainment (IVI), in-vehicle entertainment (ICE) devices, instrument cluster (IC), head-up display (HUD) devices, onboard diagnostic (OBD) devices, dashtop mobile equipment (DME), mobile data terminal (MDT), electronic engine management system (EEMS), electronic / engine electronic control unit (ECU), electronic / engine electronic control module (ECM), embedded systems, microcontrollers, control modules, engine management system (EMS), connected or "smart" appliances, MTC devices, M2M, IoT devices, etc.

[0021] UE 101 can be configured to connect to RAN 110, for example, communicatively coupled. In a specific implementation, RAN 110 can be an NG RAN or 5G RAN, E-UTRAN, or a legacy RAN such as UTRAN or GERAN. As used herein, the term "NG RAN," etc., can refer to RAN 110 operating in NR or 5G system 100, while the term "E-UTRAN," etc., can refer to RAN 110 operating in LTE or 4G or 5G system 100. Multiple UEs 101 utilize connections (or channels) 103 and 104 respectively, each connection including a physical communication interface or layer (discussed in further detail below).

[0022] In this example, connections 103 and 104 are shown as air interfaces for communication coupling and can be consistent with cellular communication protocols such as GSM, CDMA, PTT, POC, UMTS, 3GPP LTE, LTE-A (LTE-Advanced Long Term Evolution), LTE-U (LTE-U), 5G, NR, NR-U (NR-U), and / or any other communication protocols discussed herein. In a specific implementation, UE 101 can directly exchange communication data via ProSe interface 105. ProSe interface 105 may also be referred to as SL interface 105 and may include one or more logical channels, including but not limited to PSCCH, PSSCH, PSDCH, and PSBCH.

[0023] The diagram shows UE 101b configured to access AP 106 (also referred to as "WLAN node 106", "WLAN 106", "WLAN terminal 106", "WT 106", etc.) via connection 107. Connection 107 may include a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, where AP 106 will include Wireless Fibre. Router. In this example, AP106 is shown connected to the Internet but not to the core network of the wireless system (described in further detail below). In various specific implementations, UE 101b, RAN 110, and AP 106 can be configured to utilize LWA operation and / or LWIP operation. LWA operation may involve RAN nodes 111a-b configuring UE 101b, which is in the RRC_CONNECTED state, to utilize the radio resources of LTE and WLAN. LWIP operation may involve UE 101b using WLAN radio resources (e.g., connection 107) via an IPsec protocol tunnel to authenticate and encrypt packets (e.g., IP packets) transmitted through connection 107. IPsec tunneling may include encapsulating the entire original IP packet and adding a new packet header to protect the original header of the IP packet.

[0024] RAN 110 includes one or more AN nodes or RAN nodes 111a and 111b (collectively referred to as "RAN node 111") that enable connections between 103 and 104. As used herein, the terms "access node," "access point," etc., can describe equipment that provides radio baseband functionality for data and / or voice connections between the network and one or more users. These access nodes can be referred to as BS, gNB, RAN node, eNB, NodeB, RSU, TRxP, or TRP, etc., and can include ground stations (e.g., terrestrial access points) or satellite stations that provide coverage within a geographic area (e.g., a cell). As used herein, the terms "NG RAN node," etc., can refer to RAN node 111 (e.g., gNB) operating in NR or 5G system 100, while the terms "E-UT RAN node," etc., can refer to RAN node 111 (e.g., gNB) operating in LTE or 4G or 5G system 100. Depending on the specific implementation, RAN node 111 may be implemented as one or more of dedicated physical devices such as macro cell base stations and / or low-power (LP) base stations for providing smaller coverage areas, smaller user capacity, or higher bandwidth compared to macro cells.

[0025] In some implementations, all or part of RAN node 111 may be implemented as one or more software entities running on a server computer as part of a virtual network, which may be referred to as CRAN and / or Virtual Baseband Unit Pool (vBBUP). In these implementations, CRAN or vBBUP may implement RAN function partitioning, such as PDCP partitioning, where the RRC and PDCP layers are operated by CRAN / vBBUP, while other L2 protocol entities are operated by individual RAN nodes 111; MAC / PHY partitioning, where the RRC, PDCP, RLC, and MAC layers are operated by CRAN / vBBUP, and the PHY layer is operated by individual RAN nodes 111; or "lower PHY" partitioning, where the upper portion of the RRC, PDCP, RLC, MAC, and PHY layers is operated by CRAN / vBBUP, and the lower portion of the PHY layer is operated by individual RAN nodes 111.

[0026] Any node in RAN 111 can serve as the endpoint of the air interface protocol and can be the first point of contact for UE 101. In some implementations, any node in RAN 111 can perform various logical functions of RAN 110, including but not limited to the functions of the Radio Network Controller (RNC), such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0027] In a specific implementation, UE 101 may be configured to communicate with each other or with any of the RAN nodes 111 on a multi-carrier communication channel using OFDM communication signals according to various communication technologies, such as, but not limited to, OFDMA communication technology (e.g., for downlink communication) or SC-FDMA communication technology (e.g., for uplink and ProSe or sidelink communication), although the scope of the specific implementation is not limited in this respect. The OFDM signal may include multiple orthogonal subcarriers.

[0028] In some implementations, the downlink resource grid can be used for downlink transmissions from any node in RAN 111 to UE101, while uplink transmissions can utilize similar techniques. The grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which represents the physical resources in the downlink within each time slot. This time-frequency plane representation is common practice for OFDM systems, making radio resource allocation intuitive. Each column and row of the resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to a time slot in a radio frame. The smallest time-frequency unit in the resource grid is represented as a resource element. Each resource grid comprises multiple resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block comprises a set of resource elements; in the frequency domain, this can represent the minimum amount of resources currently available for allocation. Such resource blocks are used to transmit several different physical downlink channels.

[0029] Depending on the specific implementation, UE 101 and RAN node 111 transmit data (e.g., transmit and receive data) through licensed media (also referred to as “licensed spectrum” and / or “licensed band”) and unlicensed shared media (also referred to as “unlicensed spectrum” and / or “unlicensed band”). Licensed spectrum may include channels operating in the frequency range of approximately 400 MHz to approximately 3.8 GHz, while unlicensed spectrum may include a 5 GHz band. NR in the unlicensed spectrum may be referred to as NR-U, and LTE in the unlicensed spectrum may be referred to as LTE-U, Licensed Assisted Access (LAA), or MulteFire.

[0030] To operate in unlicensed spectrum, UE 101 and RAN node 111 may use LAA, eLAA, and / or feLAA mechanisms. In these specific implementations, UE 101 and RAN node 111 may perform one or more known medium sensing and / or carrier sensing operations to determine whether one or more channels in the unlicensed spectrum are unavailable or otherwise occupied before transmission in the unlicensed spectrum. Medium / carrier sensing operations may be performed according to a Listen-After-Talk (LBT) protocol.

[0031] LBT is a mechanism that equipment (e.g., UE 101, RAN node 111, etc.) uses to sense a medium (e.g., a channel or carrier frequency) and transmit when the medium is sensed to be idle (or when a specific channel in the medium is sensed to be unoccupied). The medium sensing operation may include CCA, which utilizes at least ED to determine the presence of other signals on the channel in order to determine whether the channel is occupied or idle. This LBT mechanism allows cellular / LAA networks to coexist with existing systems in unlicensed spectrum and with other LAA networks. ED may include sensing RF energy in the intended transmission band over a period of time and comparing the sensed RF energy with a predefined or configured threshold.

[0032] The PDSCH carries user data and higher-layer signaling to multiple UEs 101. Among other information, the PDCCH carries information about the transmission format and resource allocation related to the PDSCH channel. It can also inform multiple UEs 101 about the transmission format, resource allocation, and HARQ information related to the uplink shared channel. Typically, downlink scheduling (allocating control and shared channel resource blocks to UEs 101b within the cell) can be performed at any of the RAN nodes 111 based on channel quality information fed back from any of the UEs 101. Downlink resource allocation information can be transmitted on the PDCCH used for (e.g., allocated to) each UE in the UEs 101.

[0033] PDCCH uses CCEs to transmit control information. Before being mapped to resource elements, the complex-valued symbols of the PDCCH can first be organized into quadruplets, which can then be arranged using a sub-block interleaver for rate matching. One or more of these CCEs can be used to transmit each PDCCH, where each CCE can correspond to nine sets, called REGs, each with four physical resource elements. Four Quadrature Phase Shift Keying (QPSK) symbols can be mapped to each REG. Depending on the DCI size and channel conditions, one or more CCEs can be used to transmit the PDCCH. Four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, L = 1, 2, 4, or 8) can exist.

[0034] Some implementations may apply the concept of resource allocation to control channel information; the concept of resource allocation is an extension of the above-mentioned concept. For example, some implementations may utilize EPDCCH, which uses PDSCH resources for control information transmission. One or more ECCEs may be used to transmit EPDCCH. Similarly, each ECCE may correspond to a set of nine, each consisting of four physical resource elements, called EREG. In some cases, an ECCE may have a different number of EREGs.

[0035] RAN nodes 111 can be configured to communicate with each other via interface 112. In a specific implementation where system 100 is an LTE system, interface 112 can be an X2 interface 112. The X2 interface can be defined between two or more RAN nodes 111 connected to EPC 120 (e.g., two or more gNBs, etc.), and / or between two gNBs connected to EPC 120. In some implementations, the X2 interface may include an X2 user plane interface (X2-U) and an X2 control plane interface (X2-C). X2-U can provide flow control mechanisms for user data packets transmitted through the X2 interface and can be used to transmit information about the delivery of user data between gNBs.

[0036] In a specific implementation where system 100 is a 5G or NR system, interface 112 may be an Xn interface 112. The Xn interface is defined between two or more RAN nodes 111 (e.g., two or more gNBs) connected to 5GC 120, between a RAN node 111 (e.g., a gNB) connected to 5GC 120 and an eNB, and / or between two gNBs connected to 5GC 120. In some implementations, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. Xn-U provides non-guaranteed delivery of user plane PDUs and supports / provides data forwarding and flow control functions. Xn-C provides management and error handling functions for managing the functionality of the Xn-C interface; mobility support for UE 101 in connected modes (e.g., CM-CONNECTED) includes functions for managing UE mobility in connected modes between one or more RAN nodes 111. This mobility support may include context transfer from the old (source) serving RAN node 111 to the new (destination) serving RAN node 111; and control of the user plane tunnel between the old (source) serving RAN node 111 and the new (destination) serving RAN node 111. The Xn-U protocol stack may include a transport network layer built on top of the Internet Protocol (IP) transport layer, and a GTP-U layer on top of the UDP and / or IP layers for carrying user plane PDUs. The Xn-C protocol stack may include an application layer signaling protocol (referred to as the Xn Application Protocol (Xn-AP)) and a transport network layer built on top of SCTP. SCTP may be on top of the IP layer and provides guaranteed delivery of application layer messages. In the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In other specific implementations, the Xn-U protocol stack and / or the Xn-C protocol stack may be the same as or similar to the user plane and / or control plane protocol stacks shown and described herein.

[0037] RAN 110 is shown communicatively coupled to the core network, which in this embodiment is communicatively coupled to the core network (CN) 120. CN 120 may include multiple network elements 122 configured to provide various data and telecommunications services to customers / subscribers (e.g., users of multiple UEs 101) connected to CN 120 via RAN 110. Components of CN 120 may be implemented in a physical node or separate physical nodes, including components for reading and executing instructions from machine-readable or computer-readable media (e.g., non-transitory machine-readable storage media). In some embodiments, NFV may be used to virtualize any or all of the aforementioned network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). A logical instance of CN 120 may be referred to as a network slice, and a logical instance of a portion of CN 120 may be referred to as a network subslice. NFV architectures and infrastructure may be used to virtualize one or more network functions onto physical resources comprising a combination of industry-standard server hardware, storage hardware, or switches (optionally implemented by proprietary hardware). In other words, an NFV system can be used to perform a virtual or reconfigurable concrete implementation of one or more EPC components / functions.

[0038] Generally, application server 130 can be a component that provides IP bearer resources for use with the core network (e.g., UMTS PS domain, LTE PS data service, etc.). Application server 130 can also be configured to support one or more communication services for UE 101 via EPC 120 (e.g., VoIP sessions, PTT sessions, group communication sessions, social networking services, etc.).

[0039] In a specific implementation, CN 120 can be a 5GC (referred to as "5GC 120", etc.), and RAN 110 can be connected to CN 120 via NG interface 113. In a specific implementation, NG interface 113 can be divided into two parts: NG user plane (NG-U) interface 114, which carries traffic data between RAN node 111 and UPF; and S1 control plane (NG-C) interface 115, which is the signaling interface between RAN node 111 and AMF.

[0040] In specific implementations, CN 120 can be a 5G CN (referred to as "5GC 120", etc.), while in other implementations, CN120 can be an EPC. When CN 120 is an EPC (referred to as "EPC 120", etc.), RAN 110 can connect to CN 120 via S1 interface 113. In specific implementations, S1 interface 113 can be divided into two parts: S1 user plane (S1-U) interface 114, which carries traffic data between RAN node 111 and S-GW; and S1-MME interface 115, which is the signaling interface between RAN node 111 and MME.

[0041] Figure 2 Examples of platform 200 (or “device 200”) according to various specific implementations are illustrated. In specific implementations, computer platform 200 may be adapted to function as UE 101, application server, and / or any other element / device discussed herein. Platform 200 may include any combination of the components shown in the examples. Components of platform 200 may be implemented as integrated circuits (ICs), portions of ICs, discrete electronic devices, or other modules, logic components, hardware, software, firmware, or combinations thereof adapted in computer platform 200, or may be implemented as components otherwise incorporated within the framework of a larger system. Figure 2 The block diagram is intended to show a high-level view of the components of the computer platform 200. However, some of the components shown may be omitted, additional components may be present, and different arrangements of the components shown may occur in other specific embodiments.

[0042] Application circuit 205 includes circuitry such as, but not limited to, one or more processors (or processor cores), cache memory, and one or more of the following: LDO, interrupt controller, serial interface (such as SPI), I2C or general programmable serial interface module, RTC, timer-counter (including interval timer and watchdog timer), general-purpose I / O, memory card controller (such as SD MMC or similar controller), USB interface, MIPI interface, and JTAG test access port.

[0043] The processor of the application circuit may include, for example, one or more processor cores, one or more application processors, one or more GPUs, one or more RISC processors, one or more ARM processors, one or more CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, multi-threaded processors, ultra-low voltage processors, embedded processors, some other known processing elements, or any suitable combination thereof. In some specific implementations, the application circuit may include or may be a dedicated processor / controller for operation according to the various specific implementations herein.

[0044] As an example, the processor of application circuit 205 may include an Apple A-series processor. The processor of application circuit 205 may also be one or more of the following: based on... Architecture Core TM processors, such as Quark TM Atom TM i3, i5, i7 or MCU-level processors, or available from Santa Clara, California. company( Another processor of this type from [Company Name], Santa Clara, CA; and Advanced Micro Devices (AMD). Processor or Accelerated Processing Unit (APU); from Snapdragon by Technologies, Inc. TM Processor, Texas Instruments Open Multimedia ApplicationsPlatform(OMAP) TM Processors; MIPS-based designs from MIPS Technologies, Inc., such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings, Ltd., such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; etc. In some specific implementations, application circuitry 205 may be part of a system-on-a-chip (SoC), where application circuitry 205 and other components are formed as a single integrated circuit.

[0045] Additionally or alternatively, application circuitry 205 may include circuitry such as, but not limited to, one or more field-programmable devices (FPDs) such as FPGAs; programmable logic devices (PLDs) such as complex PLDs (CPLDs), high-capacity PLDs (HCPLDs); ASICs such as structured ASICs; programmable SoCs (PSoCs); and so on.

[0046] The baseband circuit 210 may be implemented, for example, as a soldered substrate, which includes one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits.

[0047] RFEM 215 may include a millimeter-wave (mmWave) RFEM and one or more sub-millimeter-wave radio frequency integrated circuits (RFICs). In some embodiments, the one or more sub-millimeter-wave RFICs may be physically separated from the millimeter-wave RFEM. The RFIC may include connectors to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In another embodiment, the radio functions of both millimeter-wave and sub-millimeter-wave technologies may be implemented in the same physical RFEM 215 that combines both the millimeter-wave antenna and the sub-millimeter-wave technology.

[0048] Memory circuitry 220 may include any number and type of memory devices for providing a fixed amount of system memory. For example, memory circuitry 220 may include one or more of the following: volatile memory including random access memory (RAM), dynamic RAM (DRAM) and / or synchronous dynamic RAM (SDRAM), non-volatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as flash memory), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc.

[0049] The removable memory circuitry 223 may include devices, circuitry, enclosures / housings, ports, or sockets for coupling portable data storage devices to platform 200. These portable data storage devices can be used for mass storage and may include, for example, flash memory cards (e.g., Secure Digital (SD) cards, MicroSD cards, xD picture cards, etc.), as well as USB flash drives, optical discs, external HDDs, etc.

[0050] Platform 200 may also include interface circuitry (not shown) for connecting external devices to platform 200. External devices connected to platform 200 via this interface circuitry include sensor circuitry 221 and electromechanical components (EMC) 222, as well as a removable memory device coupled to removable memory circuitry 223.

[0051] Sensor circuit 221 includes devices, modules, or subsystems designed to detect events or changes in their environment and to transmit information about the detected events (sensor data) to other devices, modules, subsystems, etc. Examples of such sensors include, in particular: inertial measurement units (IMUs) including accelerometers, gyroscopes, and / or magnetometers; microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS) including triaxial accelerometers, triaxial gyroscopes, and / or magnetometers; level sensors; flow sensors; temperature sensors (e.g., thermistors); pressure sensors; barometric pressure sensors; gravimeters; altimeters; image capture devices (e.g., cameras or lensless aperture sensors); light detection and ranging (LiDAR) sensors; proximity sensors (e.g., infrared radiation detectors, etc.), depth sensors, ambient light sensors, ultrasonic transceivers; microphones or other similar audio capture devices; etc.

[0052] EMC 222 includes devices, modules, or subsystems intended to enable platform 200 to change its state, position, and / or orientation, or to move or control mechanisms or (sub)systems. Additionally, EMC 222 can be configured to generate messages / signaling and send messages / signaling to other components of platform 200 to indicate the current state of EMC 222.

[0053] In some implementations, this interface circuitry can connect platform 200 to positioning circuitry 245. Positioning circuitry 245 includes circuitry for receiving and decoding signals transmitted / broadcast by a GNSS positioning network. Examples of navigation satellite constellations (or GNSS) may include the US GPS, Russia's GLONASS, the EU's Galileo system, China's BeiDou Navigation Satellite System, regional navigation systems, or GNSS augmentation systems (e.g., NAVIC, Japan's QZSS, France's DORIS, etc.).

[0054] In some implementations, the interface circuitry can connect platform 200 to near-field communication (NFC) circuitry 240. NFC circuitry 240 is configured to provide contactless short-range communication based on radio frequency identification (RFID) standards, wherein a magnetic field sensor is used to enable communication between NFC circuitry 240 and NFC-enabled devices (e.g., “NFC contacts”) external to platform 200.

[0055] The drive circuitry 246 may include software and hardware elements for controlling specific devices embedded in, attached to, or otherwise communicatively coupled to the platform 200. The drive circuitry 246 may include various drivers that allow other components of the platform 200 to interact with or control various input / output (I / O) devices that may exist within or be connected to the platform.

[0056] The power management integrated circuit (PMIC) 225 (also referred to as "power management circuit 225") manages the power supplied to various components of the platform 200. Specifically, relative to the baseband circuit 210, the PMIC 225 controls power selection, voltage scaling, battery charging, or DC-DC conversion. The PMIC 225 is typically included when the platform 200 can be powered by the battery 230.

[0057] In some implementations, the PMIC 225 can be controlled or otherwise integrated into various power-saving mechanisms of the platform 200. For example, if the platform 200 is in the RRC_Connected state, where it remains connected to the RAN node as it anticipates receiving traffic soon, it can enter a state known as Discontinuous Receive (DRX) after a period of inactivity. During this state, the platform 200 can power down for short intervals to conserve power. If there is no data traffic activity for an extended period, the platform 200 can transition to the RRC_Idle state, in which the device is disconnected from the network and does not perform operations such as channel quality feedback or handover. The platform 200 enters a very low-power state and performs paging, during which the device periodically wakes up again to listen to the network and then power down again. The platform 200 may not receive data in this state; to receive data, the platform must transition back to the RRC_Connected state. Additional power-saving modes can allow the device to be unable to use the network for longer than the paging interval (ranging from a few seconds to several hours). During this period, the device is completely unable to connect to the network and can be completely powered off. Any data sent during this time will result in significant latency, which is assumed to be acceptable.

[0058] Battery 230 can power platform 200, but in some examples, platform 200 may be mounted in a fixed location and may have a power source coupled to the grid. Battery 230 may be a lithium-ion battery, a metal-air battery such as a zinc-air battery, an aluminum-air battery, a lithium-air battery, etc. In some specific implementations, such as in V2X applications, battery 230 may be a typical lead-acid automotive battery.

[0059] A power block coupled to the power grid or other power source can be coupled to the BMS to charge battery 230. In some examples, the power block can be replaced by a wireless power receiver to wirelessly acquire power, for example, via a loop antenna in computer platform 200.

[0060] User interface circuitry 250 includes various input / output (I / O) devices present in or connected to platform 200, and includes one or more user interfaces designed to enable user interaction with platform 200 and / or peripheral interface designed to enable interaction with peripheral components of platform 200.

[0061] Figure 3 Exemplary procedures 300 for interleaving control channel element-to-resource element group mappings according to some specific implementations of this disclosure are illustrated. Generally, a UE can be configured to deinterleave REG bundles to construct a CCE. A base station (e.g., a next-generation node or gNB) is configured to interleave REG bundles using a CCE-to-REG mapping.

[0062] The procedure 300 for configuring the NR PDCCH stream and CORESET is defined by several parameters. These parameters set the search space (SS) and are used to determine how to configure the CCE-to-REG mapping. Generally, the RRC signaling message parameters that define the CORESET include the following parameters. The parameter controlResourceSetId corresponds to the Layer 1 parameter CORESET-ID. A value of CORESET ID equal to 0 identifies a common CORESET configured in the Master Information Block (MIB) and in ServingCellConfigCommon. Non-zero values, such as those up to values ​​smaller than the maximum number of control resources, each identify a CORESET configured by dedicated signaling. The controlResourceSetId parameter is unique within the Bandwidth Part (BWP) of the serving cell. The parameter frequencyDomainResources represents frequency domain resources. This parameter defines the resource blocks assigned to the UE within the BWP. The frequency resource parameter corresponds to the Layer 1 parameter CORESET-freq-dom. In the value of the frequency resource parameter, each bit corresponds to a group of 6 RBs.

[0063] The packet begins with Physical Resource Block (PRB) 0, which is entirely contained within the bandwidth portion of the configured CORESET. The most significant bit in the Frequency Resource parameter corresponds to the lowest frequency group, which is entirely contained within the bandwidth portion of the configured CORESET. If applicable, each subsequent less significant bit corresponds to the next lowest frequency group entirely contained within the bandwidth portion of the configured CORESET. Generally, bits corresponding to groups not entirely contained within the bandwidth portion of the configured CORESET are set to zero. The duration parameter corresponds to the Level 1 parameter CORESET-time-duration. The duration parameter defines a consecutive time period across multiple symbols of the CORESET. The precoderGranularity parameter specifies the precoder granularity defined in the frequency domain. The tci-StatesPDCCH parameter indexes the configured Transport Configuration Indicator (TCI) status that provides quasi-co-location configuration data for PDCCH. The tci-PresentInDCI parameter indicates whether the TCI field is present or absent in the DL-related DCI. The pdcch-DMRS-ScramblingID parameter indicates the PDCCH DMRS scrambling initialization parameter. If no value is specified, the UE applies the value of the physical cell ID configured for the serving cell.

[0064] Several parameters are positively correlated with CCE-to-REG mapping. The `cce-reg-MappingType` parameter provides the selection of the CCE-to-REG mapping method. The `reg-BundleSize` parameter indicates the number of REGs within a REG bundle, or the number of adjacent REG blocks included together. The `REG bundle size` parameter indicates the size of the REG bundle used for mapping. The `interleaveSize` parameter indicates the size of each interleaving portion of the mapping. The `shiftIndex` parameter represents the CORESET shift index. If no value is provided for this parameter, the UE applies the value of the physical cell ID configured for the serving cell.

[0065] For the NR PDCCH stream and CORESET configuration, the aggregation-level DCI comprises consecutively numbered CCEs. CCEs are mapped onto multiple REGs within the CORESET. The data processing system is configured to implement distributed resource allocation for the DCIs within the CORESET. This is accomplished by configuring interleaved CCE-to-REG mappings for each CORESET. For interleaved CCE-to-REG mappings, the REG bundles of the CCEs constituting the PDCCH are distributed in the frequency domain as REG bundles. As previously described, a REG bundle is a set of indivisible resources consisting of adjacent REGs. The REG bundles span all OFDM symbols of a given CORESET. Therefore, interleaved CCE-to-REG mappings enable both time-domain processing gain and frequency-domain diversity. Adjacent CCEs of the PDCCH are decomposed into dispersed REG bundles in the frequency domain. Generally, once the REGs corresponding to the PDCCH are determined, the modulation symbols of the PDCCH are mapped, first in the frequency domain and then in the time domain, to the REs of the determined REGs (e.g., in ascending order of RE index and symbol index, respectively).

[0066] Generally, the interleaving mapping is calculated at each symbol. After the demapping process, the de-interleaved CCE-to-REG mapping is applied to the log-likelihood ratio (LLR) of a given candidate for a given aggregation level. Generally, for a good channel, the LLR value is saturated, thus clearly indicating 0 or 1. The UE applies interleaving to the LLR generated by demapping. The UE iterates through the symbols and CORESET. The UE can demapping and de-interleaving one symbol at a time, rather than waiting for all symbols of the CORESET to arrive. The UE is configured to calculate and retrieve parameters required for the de-interleaving process, such as calculating the REG block size.

[0067] To compute the interleaving map, the values ​​of the mapping parameters are set and combined in the interleaving function. For example, a data processing system uses N RB CORESET The parameter calculates the number of resource blocks in the CORESET, which is the number of RBs in the frequency domain within the CORESET, as previously described. Specifically, this value is the number of count set bits * the number of frequency domain resources * 6. N Symb CORESET N is the number of symbols in the time domain of the CORESET. Symb CORESET It can be 1, 2, or 3. N REG CORESET It is the number of REGs in the CORESET, which is equal to N. RB CORESET *N Symb CORESETL is the REG bundle size. R is the interleaver size. C represents the interval between RBs in the memory of the interleaving unit, and is the ratio of the REG bundle size to the interleaver size in the CORESET, such that C = N. REG CORESET / (LR). Therefore, the interleaving map is set by the following equation, where each REG RB is selected according to C and R. The interleaving deindexer instructs how the interleaved REGs are ordered such that they are read in that order. The UE is configured to read the REG block size and thus be able to process one symbol at a time. More specifically, the REG block size can be different in different cases. By reading the REG block size and extracting the REG blocks individually, each symbol is extracted individually and can be aggregated into a CCE, as described herein. The computed interleaving map (which selects multiple PRBs for each CCE) is applied to the log-likelihood ratio data storage area (e.g., an LLR buffer), as discussed in... Figures 5A to 6 The process described above involves applying interleaving to LLRs that are read from the LLR buffer and written back to the LLR buffer after deinterleaving.

[0068] Figure 4 An exemplary process 400 for mapping control channel elements to resource element groups is illustrated. This mapping is performed according to some specific embodiments of this disclosure. A base station (e.g., a node such as a next-generation node gNB) is configured to generate interleaved transmissions. A UE (e.g., using a baseband processor or other part of the baseband processor) is configured to perform process 400 to deinterleave REGs and construct CCEs according to the CCE-REG mapping. CCEs are constructed from bundles comprising 1, 2, 3, or 6 REGs per bundle. The bits per RB are based on the REG size (e.g., L). The duration is 1, 2, or 3. Process 400 is repeated for all CORESETs across all bandwidth portions to construct all CCEs.

[0069] The UE is configured to load (402) a CORESET from the LLR data storage area. The CORESET is received from the base station in an interleaved format according to the CCE-to-REG mapping specified by the base station (e.g., in the RRC configuration message). The UE is configured to select (404) a CCE for deinterleaving processing. The selected CCE can be any CCE. The UE selects a CCE by choosing a specific index value of a REG in the CORESET and then assigning the REG to a first CCE based on the REG's position in the CORESET. The index value corresponds to the frequency band occupied by the REG. For example, REG 0 is at PRB frequency f0. For a 2-symbol OFDM CORESET, REG 0 and REG 1 correspond to f0, and so on. Because the REG size, REG bundle size, number of REGs in the CORESET, and interleaver size are determined by the UE in procedure 400, the UE's data processing system is configured to map each REG to a corresponding REG bundle that includes that REG.

[0070] The UE's data processing system determines (406) whether there are additional CCEs for processing. If the number of CCEs constructed matches the total number in the CORSET, the process ends (408). If there are additional CCEs to be constructed, the process continues.

[0071] The UE’s data processing system receives (410) CCE to REG mapping parameter values, including REG size, REG bundle size, number of REGs in CORESET and interleaver size, as previously described.

[0072] The UE's data processing system is configured to extract the value of the (412) RB size from the received mapped data. The REG size is the block size, which is limited to the number of PDCCH bits per RB * L per duration.

[0073] The UE's data processing system determines (414) whether the current bundle index of the RB being extracted is less than the total number of REG bundles per CCE. If the REG bundle index is less than the total number of REG bundles in the CCE, the UE's data processing system is configured to perform a (416) VRSHIFT function on the REG bundle with the current index value to align the extracted data so that the extracted data can be aggregated (e.g., via an XOR function). The UE's data processing system is configured to perform a (418) XOR function on the extracted REG bundle and any other extracted REG bundle at the current CCE index to aggregate each extracted REG block in the extracted REG block into a single register.

[0074] Generally, a register shift function (VRSHIFT) and a combination function (XOR) are performed to align the extracted data from a REG bundle into a single data vector (e.g., from multiple registers). The VRSHIFT function allows REG blocks in a vector storage device to be aligned so that they can be concatenated via the XOR function. Specifically, each fetch (e.g., vector fetch (VEXT)) is performed to extract vector values, and the results are stored in a vector register file (VRF). Each fetch is performed based on the REG block size. In other words, the VEXT function is applied for the length of the REG block size to extract a specific REG block into each VRF. As mentioned earlier, the REG block size can vary in different cases. Each row includes multiple registers, and each register holds 32 bits (4 bytes). To aggregate the extracted REG blocks and make them lie in a row and adjacent to each other, the VRSHIFT and XOR functions are applied in summary as shown in Table 1. Intermediate results are omitted for clarity.

[0075] Table 1: VRSHIFT and VXOR in the deinterleaved flow

[0076] memory Register 0 Register 1 Register 2 Vector Register File (VRF) 0 <![CDATA[F0]]> VRF 1 (VRSHIFT) alignment <![CDATA[F1]]> VRF 2 (VRSHIFT) alignment <![CDATA[F2]]> VRF 3(XOR)*2 aggregation <![CDATA[F0]]> <![CDATA[F1]]> <![CDATA[F2]]>

[0077] The data processing system is configured to increment (420) to the next bundle index and repeatedly extract the VEXT function, the alignment VRSHIFT function, and the aggregation XOR function until the entire CCE is constructed. Once a CCE is constructed from all REG bundles of that CCE, the data processing system determines (422) whether the extracted CCE is 4-byte aligned in memory. When the number of bytes in a CCE is a multiple of 4, the CCE is 4-byte aligned in memory, such that the CCE occupies a vector storage area (VSW) that stores multiples of 4 bytes, while REGs are 18 bytes. If the CCE is 4-byte aligned, the data processing system loads (424) the constructed CCE into the LLR storage area without extracting another CCE from the interleaved data. If another CCE exists in the CORESET, the data processing system then increments the CCE index (428) to repeat the process of constructing another CCE. If the data of the extracted CCE is not 4-byte aligned, the data processing system is configured to construct another CCE and append it to the first CCE. The second CCE is constructed using steps 406, 408, 410, 412, 414, 416, 418, and 420. When constructing the second CCE, the data of both the first and second CCEs is aligned to the bytes of a 4-byte block in memory. Generally, each CCE has 18 LLRs. Because each LLR is 6 bits, the REG block is not aligned to every byte. Here, 4-byte alignment means that the CCE data is aligned to a 4-byte block in memory (e.g., double-word alignment). If the CCE is not byte-aligned, a second CCE is appended to achieve alignment with the 4-byte memory block. Process 400 is typically repeated for all CORSETs across all bandwidth portions.

[0078] Figure 4 The mapping process 400 is flexible, enabling the UE to hardware-accelerate the deinterleaving process. In one example, the interleaving mapping calculation is performed in the firmware, as the mapping can be done according to the UE's semi-static (re)configuration. The UE's processor (e.g., the baseband processor) is configured to access LLR data stored in Level 1 memory using a Vector Load (VLW) function that follows the mapping pattern. Specifically, the VLW loads data from L1 memory to the VRF, and the VSW stores data from the VRF to L1 memory.

[0079] The processor uses a vector-inherent mode to indirectly access LLR data. In vector mode, the processor performs memory copy and arrangement commands on the extracted LLR data and then returns the LLR data to L1 memory. Because using vector mode to extract LLR data consumes excessive processing cycles (e.g., including significant processing bandwidth overhead), the LLR is provided from the base station along with the interleaving map. The UE then generates the deinterleaved LLR during procedure 400.

[0080] Deinterleaving is challenging for memory writes because consecutive RBs in memory are separated into C RBs in the deinterleaved data. To write data, an entire memory region can be loaded into memory, followed by the generation of deinterleaved outputs. To enable memory reuse, the processor generates deinterleaved outputs in blocks, and thus the deinterleaving process can operate incrementally. In some implementations, dedicated processing units are hardware adapted to perform the deinterleaving process as described above.

[0081] Figures 5A to 5C An exemplary representation of generating a CCE from an interleaved REG is shown. Figure 5A An example of each RB 502 interleaved to generate four CCEs (CCE0, CCE1, CCE2, and CCE3) is shown. For this example, the deinterleaving parameters are as follows. N CORSET RB =12. N CORESET sym =2. N CORESET REG =24. Shift size n_shift is 0. REG bundle size L is 2. Interleaver size R is 3. Spacing C between RBs in the memory of the interleaving unit is 4. Figure 5C A mapping table 530 generated from these parameter values ​​is shown.

[0082] exist Figure 5A In this context, each index (e.g., f0, f1, f2...) represents a REG bundle (e.g., for a PRB). Specifically, f0 represents REG indices 0 and 1, and is extracted from PRB index 18. f1 represents REG indices 2 and 3, and is extracted from PRB index 19. f2 represents REG indices 4 and 5, and is extracted from PRB index 20. f3 represents REG indices 6 and 7, and is extracted from PRB index 21. Figure 5B It shows f4–f 11 The PRB index for each of them. The UE's processor is configured to deinterleave one dimension (e.g., one symbol at a time).

[0083] like Figure 5BAs shown, to construct CCE0 (shown as 506a), the UE is configured to extract REGs 0, 8, and 16 for symbol 0 and REGs 1, 9, and 17 for symbol 1. To construct CCE1 (shown as 506b), the UE is configured to extract REGs 2, 10, and 18 for symbol 0 and REGs 3, 11, and 19 for symbol 1. To construct CCE2 (shown as 506c), the UE is configured to extract REGs 4, 12, and 20 for symbol 0 and REGs 5, 13, and 21 for symbol 1. To construct CCE3 (shown as 506d), the UE is configured to extract REGs 6, 14, and 22 for symbol 0 and REGs 7, 15, and 23 for symbol 1. In this case, neither one REG nor one CCE can be stored at a time because neither REGs nor CCEs are 4-byte aligned, as previously described. As previously described, the second deinterleaving result is extracted to be loaded into the destination register for 4-byte alignment.

[0084] Figure 6 An exemplary process 600 for mapping interleaved control channel elements to resource element groups according to some specific embodiments of this disclosure is illustrated. In some specific embodiments, the UE may include Figures 1 to 2 UE 101a to UE 101b. In some specific implementations, the base station includes, as per [the relevant information] Figures 1 to 5C The nodes 111a-b or network 120 are mentioned. Process 600 can be performed by the UE. Process 600 includes: obtaining (602) a CCE-to-REG mapping, which includes a mapping parameter value for each of one or more mapping parameters. Process 600 includes: obtaining (604) interleaved data transmission received from a base station, which specifies the UE's control resource set (CORESET). Process 600 includes: selecting (606) a first CCE from a set of CCEs for assembly. Process 600 includes: for the first CCE, assigning (608) the REG bundles of the interleaved data transmission to the first CCE based on the index value of the REG bundles in the CORESET and based on the mapping parameter values. Process 600 includes: for the first CCE, extracting (610) the REG bundles with the index values ​​into memory. Process 600 includes: for the first CCE, combining (612) the extracted REG bundles with any existing extracted REG bundles of the first CCE to generate the assembled first CCE in memory. Process 600 includes loading (614) the assembled CCE into the log-likelihood ratio (LLR) data storage area.

[0085] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0086] Specific implementations of the subject matter and functional operations described in this specification may be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed herein and their equivalents), or in a combination of one or more of these. Software implementations of the subject matter may be implemented as one or more computer programs. Each computer program may include one or more modules of computer program instructions encoded on a tangible, non-transitory, computer-readable computer storage medium for execution by a data processing apparatus or for controlling the operation of the data processing apparatus. Alternatively or additionally, the program instructions may be encoded in / on an artificially generated propagated signal. In one example, the signal may be a machine-generated electrical signal, optical signal, or electromagnetic signal generated to encode information for transmission to a suitable receiver device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of computer storage media.

[0087] The terms “data processing apparatus,” “computer,” and “computing device” (or their equivalents as understood by one of ordinary skill in the art) refer to data processing hardware. For example, a data processing apparatus may encompass various means, devices, and machines for processing data, including programmable processors, computers, or multiple processors or computers. The apparatus may also include special-purpose logic circuitry, including, for example, a central processing unit (CPU), a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). In some embodiments, the data processing apparatus or special-purpose logic circuitry (or a combination thereof) may be hardware-based or software-based (or a combination of hardware-based and software-based). The apparatus may optionally include code that creates an execution environment for computer programs, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of execution environments. This disclosure contemplates the use of data processing apparatuses with or without conventional operating systems (e.g., LINUX, UNIX, WINDOWS, MAC OS, ANDROID, or IOS).

[0088] A computer program, also referred to or described as a program, software, software application, module, software module, script, or code, can be written in any form of programming language. Programming languages ​​may include, for example, compiled languages, interpreted languages, declarative languages, or procedural languages. A program can be deployed in any form, including as a standalone program, module, component, subroutine, or unit for use in a computing environment. A computer program may, but does not necessarily, correspond to a file in a file system. A program may be stored as part of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple harmonized files storing one or more modules, subroutines, or code portions. A computer program may be deployed to execute on a single computer or on multiple computers located at, for example, a single site or distributed across multiple sites interconnected by a communication network. While portions of a program shown in various figures may be depicted as separate modules implementing various features and functions through various objects, methods, or processes, a program may alternatively include multiple submodules, third-party services, components, and libraries. Conversely, the features and functions of various components may be combined into a single component as appropriate. Thresholds determined for computation may be determined statically, dynamically, or simultaneously statically and dynamically.

[0089] While this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims, but rather as descriptions of features that may be specific to particular implementations. Some features described in the context of different implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, while the features previously described may be described as functioning in certain combinations, and even initially claimed in this manner, one or more features in a claimed combination may be removed from that combination in certain circumstances, and the claimed combination may involve sub-combinations or variations thereof.

[0090] Specific embodiments of the subject matter have been described. Other embodiments, modifications, and arrangements of the described embodiments are within the scope of the following claims, and will be apparent to those skilled in the art. Although the operations are shown in a specific order in the drawings or claims, this should not be construed as requiring such operations to be performed in the specific order or successive order shown, or requiring the performance of all the operations shown (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed as appropriate.

[0091] Furthermore, the division or integration of various system modules and components in the previously described specific implementations should not be construed as requiring such division or integration in all specific implementations, and it should be understood that the program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0092] Therefore, the exemplary embodiments described above do not limit or restrict this disclosure. Other changes, substitutions, and modifications are also possible without departing from the spirit and scope of this disclosure.

[0093] Example

[0094] Further exemplary implementations are provided in the following sections.

[0095] Example 1 includes a user equipment (UE) for deinterleaving data from multiple resource element groups (REGs) and constructing one or more CCEs based on a control channel element (CCE) to REG mapping. The UE includes: one or more processors; and a memory storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations including: obtaining a CCE to REG mapping, the CCE to REG mapping including a mapping parameter value for each of one or more mapping parameters; obtaining interleaved data transmission received from a base station, the data transmission specifying the UE's control resource set (CORESET); selecting a first CCE from a set of CCEs for assembly; for the first CCE: assigning the REG bundle of the interleaved data transmission to the first CCE based on an index value of a REG bundle in the CORESET and based on the mapping parameter value; extracting the REG bundle having the index value into the memory; combining the extracted REG bundle with any existing extracted REG bundles of the first CCE to generate an assembled first CCE in the memory; and loading the assembled first CCE into a data storage area.

[0096] Example 2 includes a UE according to Example 1 or some other embodiment herein, wherein extracting the REG bundle includes: determining the REG block size of the data of the REG bundle; and applying Vector Extraction (VEXT) based on the REG block size to extract the REG bundle.

[0097] Example 3 includes a UE according to Examples 1 to 2 or some other embodiment herein, wherein extracting the REG bundle into the memory includes: aligning each extracted REG bundle in a corresponding row of the memory; and aggregating the aligned REG bundles in the memory to generate an assembled CCE.

[0098] Example 4 includes a UE according to Examples 1 to 3 or some other embodiment herein, wherein combining the extracted REG bundles with any existing extracted REG bundles of the first CCE to generate the assembled first CCE in the memory includes: determining that one or more REG bundles are loaded into a corresponding portion of the memory; and performing an XOR function on the one or more REG bundles at the corresponding portion of the memory and the extracted REG bundles in the memory to co-locate the REG bundles in a single vector file in the memory.

[0099] Example 5 includes the UE according to Examples 1 to 4 or some other embodiment herein, the operations further including: determining whether the assembled first CCE is four-byte aligned in a register such that the assembled first CCE occupies one or more registers of the memory but not any portion of the registers of the memory; loading the assembled first CCE into the data storage area in response to determining that the assembled first CCE is four-byte aligned; incrementing the CCE index to specify a second CCE in response to determining that the assembled first CCE is not four-byte aligned; assembling the second CCE; and appending the assembled second CCE to the assembled first CCE.

[0100] Example 6 includes a UE according to Examples 1 to 5 or some other embodiment herein, the operations of which further include: determining that the index value of the REG bundle in the CORESET is less than the total number of REG bundles per CCE; and incrementing to a second REG bundle having a second index value in order to extract the second REG bundle having the second index value into the memory, wherein the assembled first CCE includes the REG bundle and the second REG bundle.

[0101] Example 7 includes a UE according to Examples 1 to 6 or some other example herein, wherein the index value of the REG corresponds to the frequency band occupied by the REG.

[0102] Example 8 includes a UE according to Examples 1 to 7 or some other example herein, and these operations further include: receiving the CCE to REG mapping from the base station in a Radio Resource Configuration (RRC) message.

[0103] Example 9 includes a UE according to Examples 1 to 8 or some other embodiment herein, wherein the mapping parameters of the CCE to REG mapping include at least one of REG size, REG bundle size, number of REGs in the CORESET, and interleaver size.

[0104] Example 10 includes a UE according to Examples 1 to 9 or some other embodiment herein, wherein the data storage area includes a log-likelihood ratio (LLR) data storage area.

[0105] Example 11 includes the UE according to Examples 1 to 10 or some other embodiment herein, wherein the memory is a Level 1 (L1) register.

[0106] Example 12 includes a UE according to Examples 1 to 11 or some other embodiment herein, wherein the REG bundle size is selected from 1, 2, 3 or 6 REGs per REG bundle.

[0107] Example 13 includes a baseband processor for deinterleaving data from multiple resource element groups (REGs) and constructing one or more CCEs based on a control channel element (CCE) to REG mapping. The UE includes: a processor; and a memory storing instructions that, when executed by the processor, cause the processor to perform operations including: obtaining a CCE to REG mapping, the CCE to REG mapping including a mapping parameter value for each of one or more mapping parameters; obtaining interleaved data transmission received from a base station, the data transmission specifying the UE's control resource set (CORESET); selecting a first CCE from a set of CCEs for assembly; for the first CCE: assigning the REG bundle of the interleaved data transmission to the first CCE based on an index value of a REG bundle in the CORESET and based on the mapping parameter value; extracting the REG bundle having the index value into the memory; combining the extracted REG bundle with any existing extracted REG bundles of the first CCE to generate an assembled first CCE in the memory; and loading the assembled first CCE into a data storage area.

[0108] Example 14 includes a baseband processor according to Example 13 or some other embodiment herein, wherein extracting the REG bundle includes: determining the REG block size of the data of the REG bundle; and applying Vector Extraction (VEXT) based on the REG block size to extract the REG bundle.

[0109] Example 15 includes a baseband processor according to Examples 13 to 14 or some other embodiment herein, wherein extracting the REG bundle into the memory includes: aligning each extracted REG bundle in a corresponding row of the memory; and aggregating the aligned REG bundles in the memory to generate an assembled CCE.

[0110] Example 16 includes a baseband processor according to Examples 13 to 15 or some other embodiment herein, wherein combining the extracted REG bundles with any existing extracted REG bundles of the first CCE to generate the assembled first CCE in the memory includes: determining that one or more REG bundles are loaded into a corresponding portion of the memory; and performing an XOR function on the one or more REG bundles at the corresponding portion of the memory and the extracted REG bundles in the memory to co-locate the REG bundles in a single vector file in the memory.

[0111] Example 17 includes a baseband processor according to Examples 13 to 16 or some other embodiment herein, the operations further comprising: determining whether the assembled first CCE is four-byte aligned in a register such that the assembled first CCE occupies one or more registers of the memory but not any portion of the registers of the memory; loading the assembled first CCE into the data storage area in response to determining that the assembled first CCE is four-byte aligned; incrementing the CCE index to specify a second CCE in response to determining that the assembled first CCE is not four-byte aligned; assembling the second CCE; and appending the assembled second CCE to the assembled first CCE.

[0112] Example 18 includes a baseband processor according to Examples 13 to 17 or some other embodiment herein, the operations of which further include: determining that the index value of the REG bundle in the CORESET is less than the total number of REG bundles per CCE; and incrementing to a second REG bundle having a second index value to extract the second REG bundle having the second index value into the memory, wherein the assembled first CCE includes the REG bundle and the second REG bundle.

[0113] Example 19 includes a baseband processor according to Examples 13 to 18 or some other embodiment herein, wherein the index value of the REG corresponds to the frequency band occupied by the REG.

[0114] Example 20 includes a baseband processor according to Examples 13 to 19 or some other embodiment herein, which further includes receiving the CCE-to-REG mapping from the base station in a Radio Resource Configuration (RRC) message.

[0115] Example 21 may include a signal, or a portion thereof, described or associated with any of Examples 1 to 52.

[0116] Example 22 may include datagrams, information, elements, packets, frames, segments, PDUs or messages, or portions or components thereof, as described or otherwise in this disclosure, according to any of Examples 1 to 52.

[0117] Example 23 may include a signal encoded with data, or a portion or component thereof, as described or associated with any of Examples 1 to 22, or otherwise described in this disclosure.

[0118] Example 24 may include a signal, or a portion or component thereof, encoded as a datagram, IE, packet, frame, segment, PDU, or message, as described or associated with any of Examples 1 to 23, or otherwise described in this disclosure.

[0119] Example 25 may include an electromagnetic signal carrying computer-readable instructions, wherein execution of these computer-readable instructions by one or more processors will cause the one or more processors to perform a method, technique, or process, or a portion thereof, as described or associated with any of Examples 1 to 24.

[0120] Example 26 may include a computer program comprising instructions, wherein execution of the program by a processing element will cause the processing element to perform a method, technique, or process, or a portion thereof, as described or associated with any of Examples 1 to 25.

[0121] Example 27 may include signals in a wireless network as shown and described herein.

[0122] Example 28 may include methods for communicating in a wireless network as shown and described herein.

[0123] Example 29 may include a system for providing wireless communication as shown and described herein.

[0124] Example 30 may include a device for providing wireless communication as shown and described herein.

Claims

1. An apparatus for wireless communication, the apparatus comprising one or more processors, the one or more processors being configured to: Obtain the control channel element (CCE) to resource element group (REG) mapping, wherein the CCE to REG mapping includes the mapping parameter value of each of one or more mapping parameters; Obtain interleaved data transmission received from a base station, the data transmission specifying the control resource set CORESET of the device, the CORESET including one or more orthogonal frequency division multiplexing (OFDM) symbols; Detect the symbol boundaries of the OFDM symbols of the one or more OFDM symbols; Based on the detection of the symbol boundary, the first CCE in a set of CCEs is selected for assembly; For the first CCE: The REG bundles of the interleaved data transmission are assigned to the first CCE based on the index value of the REG bundles in the CORESET and based on the mapping parameter value. Extract the REG bundle with the index value into memory; as well as The extracted REG bundles are combined with any existing extracted REG bundles of the first CCE to generate the assembled first CCE in the memory; as well as The first assembled CCE is loaded into the data storage area.

2. The apparatus of claim 1, wherein extracting the REG bundle comprises: Determine the REG block size of the data in the REG bundle; as well as Based on the REG block size, a vector extraction VEXT is applied to extract the REG bundle.

3. The apparatus of claim 2, wherein extracting the REG bundle into the memory comprises: Align each extracted REG bundle in the corresponding row of the memory; as well as The aligned REG bundles in the memory are aggregated to generate the first assembled CCE.

4. The apparatus of claim 1, wherein combining the extracted REG bundle with any existing extracted REG bundle of the first CCE to generate the assembled first CCE in the memory comprises: Determine that one or more REG bundles are loaded into the corresponding portions of the memory; as well as An XOR function is performed on the one or more REG bundles at the corresponding portions of the memory and the extracted REG bundles in the memory to co-locate the REG bundles in a single vector file in the memory.

5. The apparatus of claim 1, wherein the one or more processors are further configured to: Determine whether the assembled first CCE is four-byte aligned in the register, such that the assembled first CCE occupies one or more registers of the memory without occupying any part of the registers of the memory; In response to determining that the assembled first CCE is four-byte aligned, the assembled first CCE is loaded into the data storage area; In response to determining that the first CCE being assembled is not four-byte aligned, the CCE index is incremented to specify a second CCE in order to assemble the second CCE; Assemble the second CCE; and The assembled second CCE is attached to the assembled first CCE.

6. The apparatus of claim 1, wherein the one or more processors are further configured to: Determine that the index value of the REG bundle in the CORESET is less than the total number of REG bundles per CCE; and Increment to a second REG bundle with a second index value to extract the second REG bundle with the second index value into the memory. The first CCE assembled therein includes the REG bundle and the second REG bundle.

7. The apparatus of claim 1, wherein the index value of the REG corresponds to the frequency band occupied by the REG.

8. The apparatus of claim 1, wherein the one or more processors are further configured to: receive the CCE-to-REG mapping from the base station in a Radio Resource Configuration (RRC) message.

9. The apparatus of claim 1, wherein the mapping parameters of the CCE-to-REG mapping include at least one of REG size, REG bundle size, the number of REGs in the CORESET, and interleaver size.

10. The apparatus of claim 1, wherein the data storage area comprises a log-likelihood ratio (LLR) data storage area.

11. The apparatus of claim 1, wherein the memory is a first-level L1 register.

12. The apparatus of claim 1, wherein the REG bundle size is any one of 1, 2, 3 or 6 REGs per REG bundle.

13. A baseband processor configured to perform operations including the following: Obtain the control channel element (CCE) to resource element group (REG) mapping, wherein the CCE to REG mapping includes the mapping parameter value of each of one or more mapping parameters; Obtain interleaved data transmission received from the base station, the data transmission specifying a control resource set CORESET, the CORESET including one or more orthogonal frequency division multiplexing (OFDM) symbols; Detect the symbol boundaries of the OFDM symbols of the one or more OFDM symbols; Based on the detection of the symbol boundary, the first CCE in a set of CCEs is selected for assembly; For the first CCE: The REG bundles of the interleaved data transmission are assigned to the first CCE based on the index value of the REG bundles in the CORESET and based on the mapping parameter value. Extract the REG bundle with the index value into memory; as well as The extracted REG bundles are combined with any existing extracted REG bundles of the first CCE to generate the assembled first CCE in the memory; as well as The first assembled CCE is loaded into the data storage area.

14. The baseband processor of claim 13, wherein extracting the REG bundle comprises: Determine the REG block size of the data in the REG bundle; as well as Based on the REG block size, a vector extraction VEXT is applied to extract the REG bundle.

15. The baseband processor of claim 14, wherein extracting the REG beam into the memory comprises: Align each extracted REG bundle in the corresponding row of the memory; as well as The aligned REG bundles in the memory are aggregated to generate the first assembled CCE.

16. The baseband processor of claim 13, wherein combining the extracted REG bundle with any existing extracted REG bundle of the first CCE to generate the assembled first CCE in the memory comprises: Determine that one or more REG bundles are loaded into the corresponding portions of the memory; as well as An XOR function is performed on the one or more REG bundles at the corresponding portions of the memory and the extracted REG bundles in the memory to co-locate the REG bundles in a single vector file in the memory.

17. The baseband processor according to claim 13, further comprising: Determine whether the assembled first CCE is four-byte aligned in the register, such that the assembled first CCE occupies one or more registers of the memory without occupying any part of the registers of the memory; In response to determining that the assembled first CCE is four-byte aligned, the assembled first CCE is loaded into the data storage area; In response to determining that the first CCE being assembled is not four-byte aligned, the CCE index is incremented to specify a second CCE in order to assemble the second CCE; Assemble the second CCE; and The assembled second CCE is attached to the assembled first CCE.

18. The baseband processor according to claim 13, further comprising: The index value of the REG bundle in the CORESET is determined to be less than the total number of REG bundles per CCE; as well as Increment to a second REG bundle with a second index value to extract the second REG bundle with the second index value into the memory. The first CCE assembled therein includes the REG bundle and the second REG bundle.

19. The baseband processor of claim 13, wherein the index value of the REG corresponds to the frequency band occupied by the REG.

20. The baseband processor according to claim 13, further comprising: The CCE-to-REG mapping is received from the base station in the Radio Resource Configuration (RRC) message.

21. A method for wireless communication, the method comprising: Obtain the control channel element (CCE) to resource element group (REG) mapping, wherein the CCE to REG mapping includes the mapping parameter value of each of one or more mapping parameters; Obtain interleaved data transmission received from the base station, the data transmission specifying the control resource set CORESET of the device, the CORESET including one or more orthogonal frequency division multiplexing (OFDM) symbols; Detect the symbol boundaries of the OFDM symbols of the one or more OFDM symbols; Based on the detection of the symbol boundary, the first CCE in a set of CCEs is selected for assembly; For the first CCE: The REG bundles of the interleaved data transmission are assigned to the first CCE based on the index value of the REG bundles in the CORESET and based on the mapping parameter value. Extract the REG bundle with the index value into memory; as well as The extracted REG bundles are combined with any previously extracted REG bundles of the first CCE to generate the assembled first CCE in the memory; as well as The first assembled CCE is loaded into the data storage area.

22. The method of claim 21, wherein extracting the REG bundle comprises: Determine the REG block size of the data in the REG bundle; as well as Based on the REG block size, a vector extraction VEXT is applied to extract the REG bundle.

23. The method of claim 22, wherein extracting the REG bundle into the memory comprises: Align each extracted REG bundle in the corresponding row of the memory; as well as The aligned REG bundles in the memory are aggregated to generate the first assembled CCE.

24. The method of claim 21, wherein combining the extracted REG bundle with any existing extracted REG bundle of the first CCE to generate the assembled first CCE in the memory comprises: Determine that one or more REG bundles are loaded into the corresponding portions of the memory; as well as An XOR function is performed on the one or more REG bundles at the corresponding portions of the memory and the extracted REG bundles in the memory to co-locate the REG bundles in a single vector file in the memory.

25. The method of claim 21, further comprising: Determine whether the assembled first CCE is four-byte aligned in the register, such that the assembled first CCE occupies one or more registers of the memory without occupying any part of the registers of the memory; In response to determining that the assembled first CCE is four-byte aligned, the assembled first CCE is loaded into the data storage area; In response to determining that the first CCE being assembled is not four-byte aligned, the CCE index is incremented to specify a second CCE in order to assemble the second CCE; Assemble the second CCE; and The assembled second CCE is attached to the assembled first CCE.

26. The method of claim 21, further comprising: The index value of the REG bundle in the CORESET is determined to be less than the total number of REG bundles per CCE; as well as Increment to a second REG bundle with a second index value to extract the second REG bundle with the second index value into the memory. The first CCE assembled therein includes the REG bundle and the second REG bundle.

27. The method of claim 21, wherein the index value of the REG corresponds to the frequency band occupied by the REG.

28. The method of claim 21, further comprising: The CCE-to-REG mapping is received from the base station in the Radio Resource Configuration (RRC) message.

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