A video resolution format independent digital video switching system

Abstract

The application discloses a kind of video resolution format independent digital video switching system, including video decoding module, video detection and re-encoding module, video switching module, video decoding reconstruction module, each input video has a video decoding module, video decoding module is decoded into video data, synchronization signal and video clock after input video signal is decoded, and is input to video detection and re-encoding module and re-encoding, video switching module is each video stream output by video detection and re-encoding module is written in FIFO and is carried out line buffer, then according to the read video stream output to video decoding reconstruction module for decoding from the corresponding buffer area according to strobe command, to re-decode video data, synchronization signal reconstruction video timing.The application carries out line buffer video switching after video re-encoding, can effectively reduce the video content noise caused by video switching, and the video switching with smaller delay is realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of digital video processing, and relates to a video processing device of an aerospace vehicle, in particular to a digital video switching system independent of video resolution format, which realizes digital video switching by uniformly re-encoding after self-detecting video resolution format and then decoding and reconstructing timing format. BACKGROUND

[0002] Digital video switching technology is one of the keys for a video processing device to realize video distribution. The video of an aerospace vehicle is derived from various functional onboard devices, and has the characteristics of multiple videos and multiple video formats. Traditional video distribution is mainly realized by a dedicated video switching chip. The dedicated video switching chip realizes an analog switch, and a host computer controls the control switch of the dedicated video switching chip through I2C or a local bus to realize video switching, which requires that the video electrical characteristics input to the dedicated video switching chip are exactly the same, i.e., the dedicated video switching chip can only switch videos that are all PAL videos or all XGA videos. With the development of onboard devices of an aerospace vehicle, the video content and the video transmission mode have greatly developed, and the video format of onboard devices is diversified, i.e., the video transmission mode involved in video switching includes PAL, XGA, DVI and ARINC818 videos, which leads to the fact that the dedicated video switching chip cannot meet the video switching of multiple types.

[0003] Under the above application background, a video switching scheme based on a programmable logic device becomes the mainstream for a video processing device to realize video distribution. According to the video transmitted by an onboard transmission mode, the video is switched through a decoding chip or directly connected to a programmable logic device. In the video switching scheme based on a programmable logic device, the programmable logic video switching mode is mainly divided into two types: 1. directly switching the video signal (including video clock, video data and synchronization), which is more common for the application of a generally low video clock, and for a higher video clock, the advantage is small switching delay, but it is easy to cause noise in the video data; 2. storing the video through a DDR3 for video frame buffering, and then switching after reconstructing the video timing, which has the advantages of stable video output and the ability to reconstruct the timing according to the characteristics and needs, but the method needs an additional DDR3 chip, and due to the upper limit of the bandwidth of the video buffering DDR3, there is an upper limit of the video channel number, and after the video buffering, the video transmission will bring a large transmission delay. If the video frame rate is 60 Hz, the switching delay of the method is usually 1 frame video time, which is 16.6 ms. SUMMARY

[0004] The application aims to provide a digital video switching system independent of video resolution format, which uses encoding line buffer mode to switch video, can avoid video noise caused by switching clock, only buffers video lines, and can realize video switching in a short time and reduce video switching delay.

[0005] The application aims to provide a digital video switching system independent of video resolution format, which uses encoding line buffer mode to switch video, can avoid video noise caused by switching clock, only buffers video lines, and can realize video switching in a short time and reduce video switching delay.

[0006] The application aims to provide a digital video switching system independent of video resolution format, which uses encoding line buffer mode to switch video, can avoid video noise caused by switching clock, only buffers video lines, and can realize video switching in a short time and reduce video switching delay.

[0007] Each input video has a video decoding module, which decodes the input video signal into video data, video line synchronization, video field synchronization and video clock, and inputs them to the video detection and re-encoding module.

[0008] The video detection and re-encoding module detects the video resolution of the video data, line synchronization and field synchronization decoded by each video decoding module, embeds the line synchronization and field synchronization into the video data, and re-encodes the video data.

[0009] The video switching module writes each video stream output by the video detection and re-encoding module into the corresponding buffer area FIFO for line buffering, and reads the buffered video stream from the corresponding buffer area according to the gating command and outputs it to the video decoding and reconstruction module. When the re-encoded video data stream is written into the corresponding FIFO, the write clock of the FIFO is the video clock, the read clock of the FIFO is the internal production clock of the FPGA, the FIFO reads out the video stream with 1 row of full mark, and the length of 1 row is obtained by resolution detection.

[0010] The video decoding and reconstruction module decodes the video stream obtained by switching according to the encoding rule of the video detection and re-encoding module to re-decode the video data, video line synchronization, video field synchronization and reconstruct the video timing.

[0011] Preferably, the video decoding module is realized by programmable logic device or standard video decoding chip, and the video detection and re-encoding module, the video switching module and the video decoding and reconstruction module are realized by programmable logic device.

[0012] Preferably, the video detection and re-encoding module re-encodes the video according to the following encoding rule:

[0013] Video sync reference codes are inserted at the beginning and end of the effective video data, each reference code including a 4-byte sequence, the first 3 bytes being a preamble, and the fourth byte containing a field sync, line sync, and the original effective data is padded with 0s to make the data bit width 32 bits.

[0014] Preferably, the gating command is determined by a conventional RS232 gating code, the gating code being 1 byte, the high 4 bits representing the input channel, and the low 4 bits representing the output channel.

[0015] Preferably, in the video switching module, if the FIFO is about to be full, the invalid video data is discarded, otherwise the invalid video data is filled in.

[0016] The present application has the following advantages:

[0017] The video switching after video re-encoding and line buffering can effectively reduce the video content noise caused by video switching, and realize video switching with less delay. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The figure is a structural schematic diagram of the digital video switching system independent of video resolution format.

[0019] Figure 2 The figure is an implementation schematic diagram of the video decoding module. DETAILED DESCRIPTION

[0020] The present application will be further described in detail below in combination with the drawings and embodiments.

[0021] Referring to Figure 1 The figure is a structural schematic diagram of the digital video switching system independent of video resolution format, mainly including a video decoding module, a video detection and re-encoding module, a video switching module, and a video decoding reconstruction module. The present embodiment takes the switching of 1 VGA video with resolution of 1024x768, 1 DVI video with resolution of 1600x1200, 1 LVDS video with resolution of 1280x1024, and 1 ARINC818 video with resolution of 1920x1080 to RS232 transmission as an example for illustration.

[0022] Each input video has a video decoding module, which decodes the input video signal into video data, video line sync, video field sync, and video clock, and then inputs them to the video detection and re-encoding module. If the input video is interlaced video, the video decoding module will also decode the odd-even field flag signal.

[0023] The video decoding module can be implemented by a programmable logic device (such as an FPGA), or a standard video decoding chip can be used to decode the video signal and convert it into a parallel video signal that can be processed by the programmable logic device and input into the FPGA. As shown in FIG. 8, in this example, the VGA video is decoded by a 7501 standard video decoding chip into VGA video data I_VGA_RGB[23:0], VGA video horizontal synchronization I_VGA_HS, VGA video vertical synchronization I_VGA_VS, and a VGA video clock I_VGA_PCLK signal, which are input into the programmable logic device FPGA for subsequent processing. The DVI video, LVDS video, and ARINC818 video signals are decoded by the DVI video decoding function, LVDS video decoding function, and ARINC818 video decoding function of the programmable logic device into corresponding video data, horizontal and vertical synchronization signals, and clock signals. Figure 2

[0024] The video detection and re-encoding module detects the video resolution of the video data, horizontal synchronization, and vertical synchronization decoded by each video decoding module, where the video resolution refers to the number of valid video data and invalid video data in one horizontal synchronization period, and the number of valid lines and invalid lines in one vertical synchronization period, and embeds the horizontal synchronization, vertical synchronization, and odd-even field flag signal into the video data and re-encodes the video data.

[0025] In this embodiment, the video is re-encoded according to the following encoding rules:

[0026] A video synchronization reference code is inserted at the beginning and end of the valid video data, and each reference code includes a 4-byte sequence in the format of 0xFFFFFFFF 0x00000000 0x00000000 0xXX000000 (the values are represented in hexadecimal, the first three bytes are a preamble, and the fourth byte contains the synchronization state). The high bits of the original valid data are padded with 0s to make the data bit width 32 bits.

[0027]

[0028] In the table, F is the odd-even field flag signal, F is 0 if the input video is a progressive video and the video decoding module does not perform decoding; V represents the VS signal; H represents the HS signal; P0, P1, P2, and P3 are reserved words.

[0029] This encoding method can be compatible with the video interfaces of some existing video encoding and decoding chips, and secondary encoding is not required.

[0030] ​The video switching module writes each video stream outputted by the video detection and re-encoding module into a corresponding cache area FIFO for line caching, and then reads the cached video stream from the corresponding cache area according to a strobe command and outputs the video stream to the video decoding and reconstruction module. When the re-encoded video data stream is written into the corresponding FIFO, the write clock of the FIFO is the video clock. The output clock of the FIFO is the internal production clock of the FPGA, and the frequency is 150 MHz. The FIFO can read out the video stream marked as one full line, and the length of one line is obtained by resolution detection. The strobe command is determined by the agreed RS232 strobe code. For this example, the strobe code is one byte, the high 4 bits represent the input channel, and the low 4 bits represent the output channel. If the strobe code is 0x22 (hexadecimal representation), the second input video is switched to the second output channel, that is, the second output channel reads from the second video line cache FIFO. If the average data bandwidth of reading the FIFO data across the clock domain is greater than the average data bandwidth of writing the FIFO, the FIFO will be full. At this time, the video write judgment FIFO is full or not. If the FIFO is full, the invalid video data is discarded, otherwise the invalid video data is filled.

[0031] The video decoding and reconstruction module decodes the switched video stream according to the encoding rule of the video detection and re-encoding module to re-decode the video data, video line synchronization and video field synchronization to reconstruct the video timing and realize video distribution. In this example, the video clock after switching is 150 MHz. The clock line of the BUFGCTRL or MMCM of the FPGA can also be used to output the same clock as the original video pixel according to the needs.

[0032] It can be understood that, for those skilled in the art, equivalent replacements or changes can be made according to the technical solutions and inventive concepts of the present application, and all such changes or replacements shall fall within the protection scope of the appended claims of the present application.

Claims

1. A video resolution format independent digital video switching system, comprising a video decoding module, a video detection and re-encoding module, a video switching module, a video decoding reconstruction module, characterized in that: each input video has a video decoding module, which decodes the input video signal into video data, video line synchronization, video field synchronization and video clock, and inputs them to the video detection and re-encoding module; the video detection and re-encoding module detects the video resolution of the video data, line synchronization and field synchronization decoded by each video decoding module, and embeds the line synchronization and field synchronization into the video data, and re-encodes the video data; wherein the video detection and re-encoding module re-encodes the video according to the following encoding rules: a video synchronization reference code is inserted at the beginning and the end of the effective video data, each reference code includes a 4-byte sequence, the first three bytes are a preamble, and the fourth byte contains field synchronization and line synchronization, and 0 is added to the high bit of the original effective data to make the data bit width 32 bits; the video switching module writes each video stream output by the video detection and re-encoding module into a corresponding FIFO for line buffering, and reads the buffered video stream from the corresponding FIFO according to a gating command and outputs it to the video decoding reconstruction module; wherein when the re-encoded video data stream is written into the corresponding FIFO, the write clock of the FIFO is the video clock, the read clock of the FIFO is the internal production clock of the FPGA, the FIFO reads a video stream with 1 row of data, and the length of 1 row is obtained by resolution detection; the video decoding reconstruction module decodes the video stream obtained by switching according to the encoding rules of the video detection and re-encoding module to reconstruct the video data, video line synchronization, video field synchronization and video timing. The video decoding module is implemented by a programmable logic device or a standard video decoding chip, and the video detection and re-encoding module, the video switching module and the video decoding reconstruction module are implemented by a programmable logic device. The gating command is determined by a conventional RS232 gating code, which is 1 byte, the high 4 bits represent the input channel, and the low 4 bits represent the output channel. In the video switching module, if the FIFO is about to be full, the invalid video data is discarded, otherwise the invalid video data is filled in. ​ ​ 2. A digital video switching system independent of video resolution format according to claim 1, characterized in that ​ 3. A digital video switching system independent of video resolution format according to claim 1, wherein ​ 4. A digital video switching system independent of video resolution format according to claim 1, wherein ​

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