Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate, a method for manufacturing the same, and a display device. The display substrate includes a drive circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the drive circuit layer away from the substrate. The drive circuit layer includes multiple circuit units, and the light-emitting structure layer includes multiple light-emitting devices. At least one circuit unit includes a first power line, an initial signal line, and a pixel drive circuit. The initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersecting the second direction. The orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] On the one hand, the present disclosure provides a display substrate, including a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer including a plurality of circuit units, and the light-emitting structure layer including a plurality of light-emitting devices; at least one circuit unit includes a first power line, an initial signal line and a pixel driving circuit, the initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersecting the second direction; the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

[0005] In an exemplary embodiment, the second initial signal line in at least one circuit unit includes an extending portion and a connecting portion connected to each other, the extending portion extending along the second direction, the connecting portion extending along the first direction, and the connecting portion connected to the first initial signal line through a via.

[0006] In an exemplary embodiment, an orthographic projection of the extending portion on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate, and an orthographic projection of the connecting portion on the substrate at least partially overlaps with an orthographic projection of the first initial signal line on the substrate.

[0007] In an exemplary embodiment, at least one circuit unit includes a second connection electrode, the connection portion is connected to the second connection electrode through a via hole, and the second connection electrode is connected to the first initial signal line through a via hole.

[0008] In an exemplary embodiment, the second connection electrode is connected to the first region of the active layer of the first transistor and the first region of the active layer of the seventh transistor in the pixel driving circuit through a via hole.

[0009] In an exemplary embodiment, the driving circuit layer includes a plurality of unit rows and a plurality of unit columns, the unit rows include a plurality of circuit units arranged along the first direction, and the unit columns include a plurality of circuit units arranged along the second direction; in at least one unit column, the second initial signal lines in adjacent circuit units are connected to each other, or the second initial signal lines in adjacent circuit units are arranged at intervals.

[0010] In an exemplary embodiment, the plurality of circuit units include a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light; the plurality of unit columns include a first unit column and a second unit column, the first circuit units and the second circuit units in the first unit column are alternately arranged along the second direction, and the third circuit units and the fourth circuit units in the second unit column are alternately arranged along the second direction; and at least part of the second initial signal line is arranged in the first unit column.

[0011] In an exemplary embodiment, the light-emitting device includes an anode and a pixel definition layer; the anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device; the pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode, a third pixel opening exposing the third anode, and a fourth pixel opening exposing the fourth anode; a first center line of the first pixel opening projected on the substrate at least partially overlaps with a second center line of the second initial signal line projected on the substrate.

[0012] In an exemplary embodiment, the driving circuit layer further includes a data signal line, and a third center line of an orthographic projection of the second pixel opening on the substrate at least partially overlaps with a fourth center line of an orthographic projection of the data signal line on the substrate.

[0013] In an exemplary embodiment, the light-emitting device includes an anode and a pixel definition layer; the anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device; the pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode, a third pixel opening exposing the third anode, and a fourth pixel opening exposing the fourth anode; the driving circuit layer also includes a data signal line; the second center line of the extension portion of the second initial signal line projected on the substrate and the fourth center line of the data signal line projected on the substrate are located on both sides of the first center line of the first pixel opening projected on the substrate.

[0014] In an exemplary embodiment, a second center line of the extension portion of the second initial signal line projected on the substrate and a fourth center line of the data signal line projected on the substrate are symmetrically arranged with respect to a first center line of the first pixel opening projected on the substrate.

[0015] In an exemplary embodiment, a second center line of an orthographic projection of the extension of the second initial signal line on the substrate and a fourth center line of an orthographic projection of the data signal line on the substrate are located on both sides of a third center line of an orthographic projection of the second pixel opening on the substrate.

[0016] In an exemplary embodiment, a second center line of the extension portion of the second initial signal line projected on the substrate and a fourth center line of the data signal line projected on the substrate are symmetrically arranged with respect to a third center line of the second pixel opening projected on the substrate.

[0017] In an exemplary embodiment, the plurality of circuit units include a first circuit unit connected to a red light-emitting device emitting red light, a second circuit unit connected to a blue light-emitting device emitting blue light, a third circuit unit connected to a first green light-emitting device emitting green light, and a fourth circuit unit connected to a second green light-emitting device emitting green light. The plurality of unit columns include a first unit column and a second unit column, the first and second circuit units in the first unit column being alternately arranged along the second direction, and the third and fourth circuit units in the second unit column being alternately arranged along the second direction. At least a portion of the second initial signal line is disposed in the second unit column.

[0018] In an exemplary embodiment, the light-emitting device includes an anode and a pixel definition layer; the anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device; the pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode, a third pixel opening exposing the third anode, and a fourth pixel opening exposing the fourth anode; a fifth center line of the third pixel opening projected on the substrate at least partially overlaps with a seventh center line of the connecting portion of the second initial signal line projected on the substrate.

[0019] In an exemplary embodiment, a sixth center line of an orthographic projection of the fourth pixel opening on the substrate at least partially overlaps with a seventh center line of an orthographic projection of the connecting portion of the second initial signal line on the substrate.

[0020] In an exemplary embodiment, the plurality of circuit units include a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light; the plurality of unit columns include a first unit column and a second unit column, the first circuit units and the second circuit units in the first unit column are alternately arranged along the second direction, and the third circuit units and the fourth circuit units in the second unit column are alternately arranged along the second direction; and the second initial signal line is arranged in the first unit column and the second unit column.

[0021] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on a base; the semiconductor layer includes an active layer of multiple transistors in the pixel driving circuit, the first conductive layer includes a scanning signal line and gate electrodes of multiple transistors, the second conductive layer includes the first initial signal line, the third conductive layer includes a first power line, and the fourth conductive layer includes a data signal line and the second initial signal line.

[0022] In an exemplary embodiment, the third conductive layer further includes a second connection electrode, the second connection electrode is connected to the first initial signal line through a via hole, and the second initial signal line is connected to the second connection electrode through a via hole.

[0023] In an exemplary embodiment, the second conductive layer further includes a shielding electrode, and the first power line is connected to the shielding electrode through a via.

[0024] In an exemplary embodiment, an orthographic projection of at least a portion of the shielding electrode on the substrate is located between an orthographic projection of the data signal line on the substrate and an orthographic projection of the second electrode of the first transistor in the pixel driving circuit on the substrate.

[0025] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0026] In another aspect, the present disclosure further provides a method for preparing a display substrate. The display substrate includes a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer including a plurality of circuit units, and the light-emitting structure layer including a plurality of light-emitting devices; at least one circuit unit includes a first power line, an initial signal line, and a pixel driving circuit, the initial signal line including a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersecting the second direction; the preparation method includes:

[0027] forming a first initial signal line extending along the first direction on the substrate;

[0028] A second initial signal line extending along the second direction is formed, and an orthographic projection of the second initial signal line on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0031] Figure 1 is a structural schematic diagram of a display device;

[0032] Figure 2a and Figure 2b A schematic diagram of the planar structure of a display substrate;

[0033] Figure 3 A schematic diagram of the cross-sectional structure of a display substrate;

[0034] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0035] Figure 5 This is a working timing diagram of a pixel driving circuit;

[0036] Figure 6aThis is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Figure 6b A schematic diagram of an initial signal line in a display substrate according to an exemplary embodiment of the present disclosure;

[0038] Figure 7 This is a schematic diagram showing a substrate after a semiconductor layer pattern is formed in the present disclosure;

[0039] Figure 8a This is a schematic diagram showing a substrate after forming a first conductive layer pattern according to the present disclosure;

[0040] Figure 8b for Figure 8a A plan view of the first conductive layer;

[0041] Figure 9a This is a schematic diagram showing a substrate after forming a second conductive layer pattern according to the present disclosure;

[0042] Figure 9b for Figure 9a A plan view of the second conductive layer;

[0043] Figure 10a This is a schematic diagram showing a substrate after a fourth insulating layer pattern is formed in the present disclosure;

[0044] Figure 10b for Figure 10a A plan view of multiple vias in FIG.

[0045] Figure 11a This is a schematic diagram showing a substrate after a third conductive layer pattern is formed in the present disclosure;

[0046] Figure 11b for Figure 11a A plan view of the third conductive layer;

[0047] Figure 12a This is a schematic diagram showing a substrate after forming a first flat layer pattern according to the present disclosure;

[0048] Figure 12b for Figure 12a A plan view of multiple vias in FIG.

[0049] Figure 13a This is a schematic diagram showing a substrate after a fourth conductive layer pattern is formed on the substrate according to the present disclosure;

[0050] Figure 13b for Figure 13a A plan view of the fourth conductive layer;

[0051] Figure 14a This is a schematic diagram showing a substrate after forming a second flat layer pattern according to the present disclosure;

[0052] Figure 14b for Figure 14a A plan view of multiple vias in FIG.

[0053] Figure 15a This is a schematic diagram showing a substrate after an anode pattern is formed in the present disclosure;

[0054] Figure 15b for Figure 15a Schematic diagram of the middle anode;

[0055] Figure 16a This is a schematic diagram of a display substrate according to the present disclosure after a pixel definition layer pattern is formed;

[0056] Figure 16b for Figure 16a A schematic diagram of the pixel definition layer in the figure;

[0057] Figure 17a This is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure;

[0058] Figure 17b for Figure 17a A plan view of the fourth conductive layer;

[0059] Figure 18a Schematic diagram of the structure of another driving circuit layer according to an exemplary embodiment of the present disclosure;

[0060] Figure 18b for Figure 18a A plan view of the fourth conductive layer;

[0061] Figure 19a Schematic diagram of the structure of another driving circuit layer according to an exemplary embodiment of the present disclosure;

[0062] Figure 19b for Figure 19a A plan view of the fourth conductive layer;

[0063] Figure 20a Schematic diagram of the structure of another driving circuit layer according to an exemplary embodiment of the present disclosure;

[0064] Figure 20b for Figure 20a A plan view of the fourth conductive layer;

[0065] Figure 21a This is a schematic diagram of another exemplary embodiment of the present disclosure after forming an anode pattern;

[0066] Figure 21b for Figure 21a Schematic diagram of the middle anode;

[0067] Figure 22aThis is a schematic diagram of another exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;

[0068] Figure 22b for Figure 22a A schematic diagram of the pixel definition layer in Figure 2.

[0069] Description of the accompanying drawings:

[0070] 11—first active layer; 12—second active layer; 13—third active layer;

[0071] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0072] 17—seventh active layer; 21—first scanning signal line; 22—second scanning signal line;

[0073] 23—light-emitting control line; 24—first electrode plate; 31—first initial signal line;

[0074] 32—second electrode plate; 33—shielding electrode; 34—opening;

[0075] 35—plate connection line; 41—first power line; 42—data connection electrode;

[0076] 43—first connecting electrode; 44—second connecting electrode; 45—third connecting electrode;

[0077] 51—data signal line; 52—second initial signal line; 53—anode connection electrode;

[0078] 71—anode; 72—pixel definition layer; 73—pixel opening;

[0079] 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer;

[0080] 104—encapsulation layer; 301—anode; 302—pixel definition layer;

[0081] 303—organic light-emitting layer; 304—cathode; 401—first encapsulation layer;

[0082] 402—second encapsulation layer; 403—third encapsulation layer. DETAILED DESCRIPTION

[0083] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0084] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0085] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0086] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0087] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0088] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0089] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0090] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0091] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0092] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0093] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0094] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0095] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, a display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0096] Figure 2a and Figure 2bThis is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and two third and fourth subpixels P3 and P4 that emit a third color light. Each of the four subpixels may include a circuit unit and a light-emitting device. The circuit unit may include scan signal lines, data signal lines, and light-emitting signal lines, and a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal lines under the control of the scan signal lines and the light-emitting signal lines, and output a corresponding current to the light-emitting device. The light-emitting device in each subpixel is respectively connected to the pixel driving circuit of the subpixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0097] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal. In an exemplary embodiment, four sub-pixels may be arranged in a square to form a GGRB pixel arrangement, such as Figure 2a In another exemplary embodiment, the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement, as shown in FIG. Figure 2b In other exemplary embodiments, the four sub-pixels may be arranged in parallel horizontally or vertically. In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0098] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as pixel rows, and a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as pixel columns. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0099] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of the display substrate. Figure 3As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base, and an encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 away from the base. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0100] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. Figure 3 In the figure, only one driving transistor 210 and one storage capacitor 211 are used as examples for illustration. The light-emitting structure layer 103 of each sub-pixel may include multiple film layers constituting a light-emitting device. The multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0101] In an exemplary embodiment, the organic light-emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer and the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer and the electron transport layer of all sub-pixels may be a common layer connected together, and the hole blocking layer of all sub-pixels may be a common layer connected together. The emitting layers and electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0102] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 Figure 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 4 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light-emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0103] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0104] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0105] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0106] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0107] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0108] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0109] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0110] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting device to initialize the charge accumulated in the first electrode of the light-emitting device or release the charge accumulated in the first electrode of the light-emitting device.

[0111] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first pole (anode), an organic light-emitting layer and a second pole (cathode), or can be a QLED, including a stacked first pole (anode), a quantum dot light-emitting layer and a second pole (cathode).

[0112] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row. This can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0113] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0114] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0115] Figure 5 This is a working timing diagram of a pixel driving circuit. Figure 4 The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. Figure 4 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.

[0116] In an exemplary embodiment, taking OLED as an example, the operation process of the pixel driving circuit may include:

[0117] The first phase A1, known as the reset phase, is characterized by a low-level signal on the second scan signal line S2, and a high-level signal on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on the first transistor T1, and the signal on the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0118] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line S1 is a low-level signal, the signals on the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initialization signal line INIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing the initialization and ensuring that the OLED does not emit light. The signal of the second scanning signal line S2 is a high-level signal, turning off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0119] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting signal line E is a low-level signal, while the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0120] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0121] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0122] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0123] Figure 6a FIG1 is a schematic diagram of a structure of a driving circuit layer of an exemplary embodiment of the present disclosure, illustrating a planar structure of eight circuit units (two unit rows and four unit columns). Figure 6a As shown, in a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, wherein the plurality of circuit units sequentially arranged along a first direction X are referred to as unit rows, and the plurality of circuit units sequentially arranged along a second direction Y are referred to as unit columns. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X intersects the second direction Y.

[0124] In an exemplary embodiment, at least one circuit unit may include a first power line, an initial signal line, and a pixel driving circuit connected to the first power line and the initial signal line, wherein the pixel driving circuit may include a plurality of transistors and a storage capacitor. In an exemplary embodiment, the first power line may be configured as a signal line receiving a power signal, and the initial signal line may be configured to initialize (reset) the storage capacitor.

[0125] In an exemplary embodiment, the initial signal line of at least one circuit unit may include a first initial signal line 31 having a main portion extending along a first direction X and a second initial signal line 52 having a main portion extending along a second direction Y, wherein the first initial signal line 31 and the second initial signal line 52 are connected by a via. In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, wherein the main portion is a line, line segment, or strip-shaped body, and the main portion extends along direction B, and the length of the main portion extending along direction B is greater than the length of the secondary portion extending along other directions.

[0126] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 52 may include an extending portion 521 and a connecting portion 522 connected to each other, wherein the main portion of the extending portion 521 extends along the second direction Y, and the main portion of the connecting portion 522 extends along the first direction X. In an exemplary embodiment, an end of the connecting portion 522 away from the extending portion 521 may be connected to the first initial signal line 31 through a via.

[0127] In an exemplary embodiment, an orthographic projection of at least a portion of the connecting portion 522 on the substrate is located within a range of an orthographic projection of the first initial signal line 31 on the substrate.

[0128] In an exemplary embodiment, an orthographic projection of at least a portion of the extending portion 521 on the substrate is located within a range of an orthographic projection of the first power line 41 on the substrate.

[0129] Figure 6b FIG. 1 is a schematic diagram of an initial signal line in a driving circuit layer according to an exemplary embodiment of the present disclosure. Figure 6b As shown, the driving circuit layer may include a plurality of unit rows and a plurality of unit columns. The first initial signal line 31 may be disposed in each unit row, and the second initial signal line 52 may be disposed in alternate unit columns. That is, at least one unit column is disposed between two adjacent second initial signal lines 52 in the first direction X. In an exemplary embodiment, the direction of the unit rows may be the first direction X, and the direction of the unit columns may be the second direction Y.

[0130] In an exemplary embodiment, a plurality of sub-pixels in a display substrate may include a red sub-pixel R emitting red light, a blue sub-pixel B emitting blue light, a first green sub-pixel G1 emitting green light, and a second green sub-pixel G2 emitting green light. The red sub-pixel R may include a red light-emitting device emitting red light and a first circuit unit Q1 connected to the red light-emitting device. The blue sub-pixel B may include a blue light-emitting device emitting blue light and a second circuit unit Q2 connected to the blue light-emitting device. The first green sub-pixel G1 may include a first green light-emitting device emitting green light and a third circuit unit Q3 connected to the first green light-emitting device. The second green sub-pixel G2 may include a second green light-emitting device emitting green light and a fourth circuit unit Q4 connected to the second green light-emitting device. The first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3, and the fourth circuit unit Q4 constitute a circuit unit group. The four circuit units in at least one circuit unit group may be arranged in a square pattern, i.e., the four circuit units are arranged in two unit rows and two unit columns. The term "sub-pixel" in this disclosure refers to a region divided by a light-emitting device, and the term "circuit unit" in this disclosure refers to a region divided by a pixel driving circuit. In exemplary embodiments, the positions of the sub-pixels and the circuit units may correspond, or the positions of the sub-pixels and the circuit units may not correspond.

[0131] In an exemplary embodiment, the plurality of unit columns may include a first unit column and a second unit column, the first unit column being a column formed by a plurality of first circuit cells Q1 and second circuit cells Q2, and the second unit column being a column formed by a plurality of third circuit cells Q3 and fourth circuit cells Q4. The first circuit cells Q1 and the second circuit cells Q2 in the first unit column are alternately arranged along the second direction Y, and the third circuit cells Q3 and the fourth circuit cells Q4 in the second unit column are alternately arranged along the second direction Y.

[0132] In an exemplary embodiment, the second initial signal line 52 may be provided in the first unit column. For example, the Nth unit column and the N+2th unit column are the first unit column, and the N+1th unit column and the N+3th unit column are the second unit column. Then, the second initial signal line 52 may be provided in the Nth unit column, the N+2th unit column, the N+4th unit column, and so on. The second initial signal line 52 is repeated every other second unit column.

[0133] In another exemplary embodiment, the second initial signal line 52 may be provided in the second unit column. For example, the Nth unit column and the N+2th unit column are first unit columns, and the N+1th unit column and the N+3th unit column are second unit columns. Then, the second initial signal line 52 may be provided in the N+1th unit column, the N+3th unit column, the N+5th unit column, and so on. The second initial signal line 52 is repeated every other first unit column.

[0134] In yet another exemplary embodiment, the second preliminary signal line 52 may be provided in the first cell column and the second cell column.

[0135] In an exemplary embodiment, the Nth unit column and the N+2th unit column may be the first unit column, and the N+1th unit column and the N+3th unit column may be the second unit column. In the Nth unit column, the circuit cells in the Mth row are the first circuit cells, and the circuit cells in the M+1th row are the second circuit cells, so that the first circuit cells and the second circuit cells in the Nth unit column are alternately arranged along the second direction Y. In the N+2th unit column, the circuit cells in the Mth row are the second circuit cells, and the circuit cells in the M+1th row are the first circuit cells, so that the second circuit cells and the first circuit cells in the N+2th unit column are alternately arranged along the second direction Y.

[0136] In an exemplary embodiment, since the M-th row, N-th column circuit unit and the M+1-th row, N+2-th column circuit unit are both first circuit units, the shape of the second initial signal line in the M-th row, N-th column circuit unit may be the same as the shape of the second initial signal line in the M+1-th row, N+2-th column circuit unit. Since the M+1-th row, N-th column circuit unit and the M-th row, N+2-th column circuit unit are both second circuit units, the shape of the second initial signal line in the M+1-th row, N-th column circuit unit may be the same as the shape of the second initial signal line in the M-th row, N+2-th column circuit unit.

[0137] In an exemplary embodiment, in the M-th row, N-th column circuit unit and the M+1-th row, N+2-th column circuit unit, the extension portion 521 may include a first initial portion, a second initial portion, and a third initial portion connected in sequence. The first initial portion and the third initial portion may be parallel to the second direction Y. The second initial portion may have a first angle with the second direction Y. The first angle may be greater than 0° and less than 90°. In an exemplary embodiment, the ends of the first initial portion and / or the third initial portion may be connected to the connection portion 522.

[0138] In an exemplary embodiment, in the circuit unit in the Mth row and N+2th column and the circuit unit in the M+1th row and Nth column, the extension portion 521 may include a fourth initial portion, a fifth initial portion, a sixth initial portion, a seventh initial portion, and an eighth initial portion connected in sequence. The fourth initial portion, the sixth initial portion, and the eighth initial portion may be parallel to the second direction Y. The fifth initial portion may have a first angle with the second direction Y. The seventh initial portion may have a second angle with the second direction Y. The first angle may be greater than 0° and less than 90°, and the second angle may be greater than 0° and less than 90°. In an exemplary embodiment, the extension direction of the fifth initial portion and the extension direction of the seventh initial portion may be mirror-symmetrical with respect to the first direction X.

[0139] In some possible exemplary embodiments, the second initial signal line 52 may be arranged in an alternate first unit column or second unit column, that is, between two second initial signal lines 52 adjacent in the first direction X, there are three unit columns between them. For example, the second initial signal line 52 may be arranged in the Nth unit column, the N+4th unit column, the N+8th unit column, ..., and the second initial signal line 52 is repeated every other first unit column and every two second unit columns. Alternatively, the second initial signal line 52 may be arranged in the N+1th unit column, the N+5th unit column, the N+9th unit column, ..., and the second initial signal line 52 is repeated every two first unit columns and every second unit column. In an exemplary embodiment, there is no special requirement for the number of unit columns between adjacent second initial signal lines 52, and it can be set as needed, and the present disclosure is not limited thereto.

[0140] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the base; the semiconductor layer may include an active layer of a plurality of transistors, the first conductive layer may include a scanning signal line and gate electrodes of a plurality of transistors, the second conductive layer may include the first initial signal line 31, the third conductive layer may include a first power line and first and second electrodes of a plurality of transistors, and the fourth conductive layer may include a data signal line and a second initial signal line 52.

[0141] In an exemplary embodiment, the third conductive layer may further include a second connection electrode 44. The second connection electrode 44 located in the third conductive layer may be connected to the first initial signal line 31 located in the second conductive layer through a via, and the second initial signal line 52 located in the fourth conductive layer may be connected to the second connection electrode 44 located in the third conductive layer through a via. In this disclosure, the second connection electrode may be referred to as an initial connection electrode.

[0142] In an exemplary embodiment, the second connection electrode 44 may be connected to the first region of the active layer of the first transistor and the first region of the active layer of the seventh transistor in the pixel driving circuit through a via hole.

[0143] In an exemplary embodiment, the second conductive layer may further include a shielding electrode, and the first power line is connected to the shielding electrode through a via. An orthographic projection of at least a portion of the shielding electrode on the substrate is located between an orthographic projection of the data signal line on the substrate and an orthographic projection of the second electrode of the first transistor in the pixel driving circuit on the substrate.

[0144] In an exemplary embodiment, the driving circuit layer may further include a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23 and a storage capacitor, the storage capacitor may include a first electrode plate and a second electrode plate, the plurality of transistors may include a first transistor to a seventh transistor, and the third transistor is a driving transistor.

[0145] In an exemplary embodiment, the first conductive layer may include a first scan signal line 21, a second scan signal line 22, a light emitting control line 23, a first plate of a storage capacitor and gate electrodes of multiple transistors, the second conductive layer may include a first initial signal line 31, a second plate of a storage capacitor, a shielding electrode and a plate connecting line, the third conductive layer may include a first power line 41, a data connection electrode, a first connection electrode, a second connection electrode 44, a third connection electrode and a fourth connection electrode, and the fourth conductive layer may include a data signal line 51, a second initial signal line 52 and an anode connecting electrode.

[0146] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, the first insulating layer being disposed between the substrate and the semiconductor layer, the second insulating layer being disposed between the semiconductor layer and the first conductive layer, the third insulating layer being disposed between the first conductive layer and the second conductive layer, the fourth insulating layer being disposed between the second conductive layer and the third conductive layer, and the fifth insulating layer being disposed between the third conductive layer and the fourth conductive layer.

[0147] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0148] In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the preparation process of the driving circuit layer may include the following operations.

[0149] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as Figure 7 shown.

[0150] In an exemplary embodiment, the semiconductor layer of each circuit unit may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 are interconnected as an integrated structure, and the sixth active layer 16 of the circuit unit in the Mth row and the seventh active layer 17 of the circuit unit in the M+1th row in each unit column are interconnected, that is, the semiconductor layers of adjacent circuit units in each unit column are interconnected as an integrated structure.

[0151] In an exemplary embodiment, the first active layer 11, the second active layer 12, the fourth active layer 14 and the seventh active layer 17 in the M-th row circuit unit are located on the side of the third active layer 13 of the circuit unit away from the M+1-th row circuit unit, the first active layer 11 and the seventh active layer 17 are located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13, and the fifth active layer 15 and the sixth active layer 16 in the M-th row circuit unit are located on the side of the third active layer 13 close to the M+1-th row circuit unit.

[0152] In an exemplary embodiment, the shape of the first active layer 11 may be an "n" shape, the shape of the second active layer 12 may be a "7" shape, the shape of the third active layer 13 may be a "J" shape, the shape of the fourth active layer 14 may be a "1" shape, and the shapes of the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be an "L" shape.

[0153] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 11-1 of the first active layer 11 also serves as the first region 17-1 of the seventh active layer 17, the second region 11-2 of the first active layer 11 also serves as the first region 12-1 of the second active layer 12, the first region 13-1 of the third active layer 13 also serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, the second region 13-2 of the third active layer 13 also serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, and the second region 16-2 of the sixth active layer 16 also serves as the second region 17-2 of the seventh active layer 17. In an exemplary embodiment, the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are provided separately.

[0154] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, wherein the first conductive layer pattern includes at least: a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23, and a first electrode 24, as shown in FIG. Figure 8a and Figure 8b As shown, Figure 8b for Figure 8a In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0155] Combine Figures 7 to 8bAs shown, the first scan signal line 21, the second scan signal line 22, and the light emitting control line 23 can extend in the first direction X. The first scan signal line 21 and the second scan signal line 22 in the M-th row of circuit units are located on a side of the first electrode plate 24 of the circuit unit away from the M+1-th row of circuit units, the second scan signal line 22 is located on a side of the first scan signal line 21 of the circuit unit away from the first electrode plate 24, and the light emitting control line 23 can be located on a side of the first electrode plate 24 of the circuit unit close to the M+1-th row of circuit units.

[0156] In an exemplary embodiment, the first electrode plate 24 may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 24 on the substrate overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 24 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0157] In an exemplary embodiment, the region where the first scan signal line 21 overlaps with the second active layer 12 serves as the gate electrode of the second transistor T2. The first scan signal line 21 is provided with a gate block 21-1 that protrudes toward the second scan signal line 22. The orthographic projection of the gate block 21-1 on the substrate overlaps with the orthographic projection of the second active layer 12 on the substrate, forming a dual-gate structure for the second transistor T2. The region where the first scan signal line 21 overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4. The region where the second scan signal line 22 overlaps with the first active layer 11 serves as the gate electrode of the first transistor T1 of the dual-gate structure. The region where the second scan signal line 22 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7. The region where the light emission control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5. The region where the light emission control line 23 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6.

[0158] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are both conductorized.

[0159] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, wherein the second conductive layer pattern includes at least: a first initial signal line 31, a second electrode 32, a shielding electrode 33, and an electrode connecting line 35, such as Figure 9a and Figure 9b As stated, Figure 9b for Figure 9a In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0160] Combine Figures 7 to 9b As shown, the first initial signal line 31 can extend in the first direction X as a main part. The first initial signal line 31 in the Mth row circuit unit is located on the side of the second scanning signal line 22 of this circuit unit away from the M+1th row circuit unit. The second electrode 32 serves as another electrode plate of the storage capacitor and is located between the first scanning signal line 21 and the light-emitting control line 23 of this circuit unit. The shielding electrode 33 is located between the second scanning signal line 22 and the first scanning signal line 21 (excluding the main part of the gate block 21-1) of this circuit unit. The shielding electrode 33 is configured to shield the influence of data voltage jumps on key nodes, thereby preventing data voltage jumps from affecting the potential of key nodes of the pixel driving circuit and improving the display effect.

[0161] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 32 on the substrate overlaps with the orthographic projection of the first electrode plate 24 on the substrate. The first electrode plate 24 and the second electrode plate 32 constitute a storage capacitor of the pixel driving circuit. An opening 34 is provided on the second electrode plate 32, and the opening 34 can be located in the middle of the second electrode plate 32. The opening 34 can be rectangular, so that the second electrode plate 32 forms a ring structure. The opening 34 exposes the third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate. In an exemplary embodiment, the opening 34 is configured to accommodate a first via hole formed subsequently. The first via hole is located in the opening 34 and exposes the first electrode plate 24, so that the second electrode of the first transistor T1 formed subsequently is connected to the first electrode plate 24.

[0162] In an exemplary embodiment, a plate connection line 35 is disposed between the second plates 32 of adjacent circuit units in the first direction X or in the direction opposite to the first direction X. The first end of the plate connection line 35 is connected to the second plate 32 of the circuit unit in question, and the second end of the plate connection line 35 extends along the first direction X or in the direction opposite to the first direction X and is connected to the second plate 32 of the adjacent circuit unit. In other words, the plate connection line 35 is configured to interconnect the second plates of adjacent circuit units in a unit row. In an exemplary embodiment, the plate connection line 35 can be used to form an interconnected integrated structure of the second plates of multiple circuit units in a unit row. The integrated second plates can be reused as power signal lines, ensuring that the multiple second plates in a unit row have the same potential, which helps improve panel uniformity, avoid display defects on the display substrate, and ensure the display quality of the display substrate.

[0163] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with a plurality of vias, and the plurality of vias include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9, as shown in FIG. Figure 10a and Figure 10b As shown, Figure 10b for Figure 10a A plan view of multiple vias in a circuit.

[0164] Combine Figures 7 to 10b As shown, the first via hole V1 is located within the opening 34 of the second electrode plate 32. The orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the opening 34 on the substrate. The fourth insulating layer and the third insulating layer within the first via hole V1 are etched away, exposing the surface of the first electrode plate 24. The first via hole V1 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first electrode plate 24 through the via hole.

[0165] In an exemplary embodiment, the second via V2 is located within the range of the orthographic projection of the second electrode plate 32 on the substrate. The orthographic projection of the second via V2 on the substrate is also located within the range of the orthographic projection of the second electrode plate 32 on the substrate. The fourth insulating layer within the second via V2 is etched away, exposing the surface of the second electrode plate 32. The second via V2 is configured to connect a subsequently formed first power line to the second electrode plate 32 through the via. In an exemplary embodiment, multiple second vias V2 serving as power vias may be included, and the multiple second vias V2 may be arranged sequentially along the second direction Y to increase the reliability of the connection between the first power line and the second electrode plate 32.

[0166] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is within the range of the orthographic projection of the fifth active layer on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to connect a subsequently formed first power line to the fifth active layer through the via.

[0167] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the sixth active layer on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer). The fourth via V4 is configured to connect the second electrode of a subsequently formed sixth transistor T6 to the sixth active layer through the via, and to connect the second electrode of a subsequently formed seventh transistor T7 to the seventh active layer through the via.

[0168] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is within the orthographic projection of the fourth active layer on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the fourth active layer. The fifth via V5 is configured to connect a subsequently formed data signal line to the fourth active layer through this via. The fifth via V5 is referred to as a data write hole.

[0169] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is within the range of the orthographic projection of the second active layer on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the first region of the second active layer (also the second region of the first active layer). The sixth via V6 is configured to connect the second electrode of a subsequently formed first transistor T1 to the first active layer through the via, and to connect the first electrode of a subsequently formed second transistor T2 to the second active layer through the via.

[0170] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the seventh active layer on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer (also the first region of the first active layer). The seventh via V7 is configured to connect the first electrode of a subsequently formed seventh transistor T7 to the seventh active layer through the via, and to connect the first electrode of a subsequently formed first transistor T1 to the first active layer through the via.

[0171] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the shielding electrode 33 on the substrate. The fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the shielding electrode 33. The eighth via V8 is configured to connect a subsequently formed first power line to the shielding electrode 33 through the via.

[0172] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fourth insulating layer within the ninth via V9 is etched away, exposing the surface of the first initial signal line 31. The ninth via V9 is configured to connect the first electrode of the subsequently formed seventh transistor T7 (which is also the first electrode of the first transistor T1) to the first initial signal line 31 through the via.

[0173] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, wherein the third conductive layer includes at least: a first power line 41, a data connection electrode 42, a first connection electrode 43, a second connection electrode 44, and a third connection electrode 45, as shown in FIG. Figure 11a and Figure 11b As shown, Figure 11b for Figure 11a In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0174] Combine Figures 7 to 11b As shown, the main portion of the first power line 41 extends along the second direction Y. The first power line 41 is connected to the second electrode plate 32 through the second via V2, to the fifth active layer through the third via V3, and to the shielding electrode 33 through the eighth via V8. This allows the shielding electrode 33 and the second electrode plate 32 to have the same potential as the first power line 41. Because the shielding electrode 33 is connected to the first power line 41, and the orthographic projection of at least a portion of the shielding electrode 33 (such as the protruding portion on the right side of the shielding electrode 33) on the substrate is located between the orthographic projection of the first connection electrode 43 (serving as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, i.e., the second node N2) on the substrate and the orthographic projection of the subsequently formed data signal line on the substrate, the impact of data voltage jumps on key nodes in the pixel driving circuit can be effectively shielded, preventing the data voltage jumps from affecting the potentials of the key nodes of the pixel driving circuit, thereby improving the display effect.

[0175] In an exemplary embodiment, the orthographic projection of at least a portion of the shielding electrode 33 on the substrate may at least partially overlap with the orthographic projection of a subsequently formed data signal line on the substrate. In an exemplary embodiment, the shielding electrodes 33 in adjacent circuit units in the first direction X may be interconnected to reduce resistance.

[0176] In an exemplary embodiment, the data link electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5 , and the data link electrode 42 is configured to be connected to a subsequently formed data signal line.

[0177] In an exemplary embodiment, the first connection electrode 43 extends along the second direction Y. Its first end is connected to the second region of the first active layer (also the first region of the second active layer) through a sixth via V6, and its second end is connected to the first electrode plate 24 through a first via V1. This allows the first electrode plate 24, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 to have the same potential. In an exemplary embodiment, the first connection electrode 43 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0178] In an exemplary embodiment, the first end of the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via V9, and the second end thereof is connected to the first region of the seventh active layer (also the first region of the first active layer) through the seventh via V7, so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the first initial signal line 31. In an exemplary embodiment, the second connection electrode 44 can serve as the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1, and the second connection electrode is configured to connect to the second initial signal line formed subsequently. The present disclosure can reduce the number of vias and the number of transfer electrodes and save wiring space by providing the second connection electrode to simultaneously connect the seventh active layer, the first initial signal line, and the second initial signal line.

[0179] In an exemplary embodiment, the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via V4, so that the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 have the same potential. In an exemplary embodiment, the third connection electrode 45 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the third connection electrode 45 is configured to be connected to an anode connection electrode formed subsequently.

[0180] In an exemplary embodiment, the first power line 41 of at least one circuit unit may be a zigzag line with unequal widths. Along the second direction Y, the first power line 41 of each circuit unit may include a first power section d1, a second power section d2, a third power section d3, a fourth power section d4, and a fifth power section d5, which are sequentially connected. The first power section d1, the third power section d3, and the fifth power section d5 may be parallel to the second direction Y. The second power section d2 may be bent toward the first direction X, and the fourth power section d4 may be bent in the opposite direction of the first direction X. The angle between the second power section d2 and the first power section d1 may be greater than 0° and less than 90°, and the angle between the fourth power section d4 and the third power section d3 may be greater than 0° and less than 90°. The fifth power section d5 is provided with a connection section d6 extending in the opposite direction of the first direction X. The connection section d6 is configured to connect to the fifth active layer through a third via. The zigzag arrangement of the first power line 41 not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between the first power line and the data signal line.

[0181] In an exemplary embodiment, the shapes of the first power lines of the various circuit units may be the same or different. In an exemplary embodiment, the shape of the first power line in the M-th row, N-th column circuit unit may be the same as the shape of the first power line in the M+1-th row, N+2-th column circuit unit, the shape of the first power line in the M+1-th row, N-th column circuit unit may be the same as the shape of the first power line in the M-th row, N+2-th column circuit unit, the shape of the first power line in the M-th row, N+1-th column circuit unit may be the same as the shape of the first power line in the M+1-th row, N+3-th column circuit unit, and the shape of the first power line in the M+1-th row, N+1-th column circuit unit may be the same as the shape of the first power line in the M-th row, N+3-th column circuit unit.

[0182] In an exemplary embodiment, the shape of the second connection electrodes in each circuit unit in the Nth column may be the same as the shape of the second connection electrodes in each circuit unit in the N+2th column, and the shape of the second connection electrodes in each circuit unit in the N+1th column may be the same as the shape of the second connection electrodes in each circuit unit in the N+3th column. The second connection electrodes in the circuit units in the N+1th and N+3th columns may be strips extending along the second direction Y, and the second connection electrodes are configured to be connected to the first initial signal line and the first region of the seventh active layer through the ninth and seventh vias, respectively. The shape of the second connection electrode 44 in the Nth column and the N+2th column circuit unit may include a first portion 44-1 and a second portion 44-2 connected to each other, the first portion 44-1 is a strip shape extending along the second direction Y, the second portion 44-2 may be rectangular, and the second portion 44-2 is arranged on the side opposite to the first direction X of the first portion 44-1, the first portion 44-1 is configured to be connected to the first initial signal line and the first region of the seventh active layer through the ninth via hole and the seventh via hole respectively, and the second portion 44-2 is configured to be connected to the second initial signal line formed subsequently through the subsequently formed via hole, thereby realizing the connection between the first initial signal line and the second initial signal line.

[0183] In an exemplary embodiment, the shapes of the third connection electrodes of the respective circuit units may be the same or different. In an exemplary embodiment, the shape of the third connection electrode in the M-th row, N-th column circuit unit may be the same as the shape of the third connection electrode in the M+1-th row, N+2-th column circuit unit, the shape of the third connection electrode in the M+1-th row, N-th column circuit unit may be the same as the shape of the third connection electrode in the M-th row, N+2-th column circuit unit, the shape of the third connection electrode in the M-th row, N+1-th column circuit unit may be the same as the shape of the third connection electrode in the M+1-th row, N+3-th column circuit unit, and the shape of the third connection electrode in the M+1-th row, N+1-th column circuit unit may be the same as the shape of the third connection electrode in the M+1-th row, N+3-th column circuit unit.

[0184] In an exemplary embodiment, the shapes of the data link electrodes and the first link electrodes of the respective circuit units may be the same, or may be different.

[0185] (6) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein the first planar layer is provided with an eleventh via hole V11, a twelfth via hole V12, and a thirteenth via hole V13, as shown in FIG. Figure 12a and Figure 12b As shown, Figure 12b for Figure 12a A plan view of multiple vias in a circuit.

[0186] Combine Figures 7 to 12b As shown, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the data connection electrode 42 on the substrate, the first flat layer in the eleventh via hole V11 is removed, exposing the surface of the data connection electrode 42, and the eleventh via hole V11 is configured to connect a subsequently formed data signal line to the data connection electrode 42 through the via hole.

[0187] In an exemplary embodiment, the eleventh via hole V11 may be in a strip shape, and the extension length of the eleventh via hole V11 in the second direction Y is greater than the extension length in the first direction X. By providing the eleventh via hole V11 in a strip shape extending along the second direction Y, the present disclosure can reduce the width of the eleventh via hole V11 in the first direction X, thereby reducing the tilt of the subsequently formed anode.

[0188] The orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second connecting electrode 44 on the substrate. The first flat layer in the twelfth via hole V12 is removed to expose the surface of the second connecting electrode 44. The twelfth via hole V12 is configured to connect the subsequently formed second initial signal line to the second connecting electrode 44 through the via hole.

[0189] The orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the third connecting electrode 45 on the substrate. The first flat layer in the thirteenth via hole V13 is removed to expose the surface of the third connecting electrode 45. The thirteenth via hole V13 is configured to connect the subsequently formed anode connecting electrode to the third connecting electrode 45 through the via hole.

[0190] In an exemplary embodiment, all circuit units are provided with the eleventh via V11 and the thirteenth via V13, each circuit unit in the Nth column and the N+2th column is provided with the twelfth via V12, and each circuit unit in the N+1th column and the N+3th column is not provided with the twelfth via V12.

[0191] In an exemplary embodiment, the positions of the eleventh via hole V11 and the thirteenth via hole V13 in each circuit unit may be the same, or may be different.

[0192] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, wherein the fourth conductive layer includes at least: a data signal line 51, a second initial signal line 52, and an anode connection electrode 53, such as Figure 13a and Figure 13b As shown, Figure 13b for Figure 13a Schematic plan view of the fourth conductive layer in FIG.

[0193] Combine Figures 7 to 13b As shown, a data signal line 51 is provided in each cell column. The data signal line 51 can extend along the second direction Y and is connected to the data connection electrode 42 through the eleventh via hole V11. Since the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5, the data signal line 51 is connected to the first region of the fourth active layer through the data connection electrode 42, thereby writing the data signal to the fourth transistor T4.

[0194] In an exemplary embodiment, the second initial signal line 52 is arranged in the Nth unit column and the N+2th unit column, and the second initial signal line 52 of each circuit unit in the unit column is connected to each other. The main portion of the second initial signal line 52 extends along the second direction Y, and the second initial signal line 52 is connected to the second connection electrode 44 through the twelfth via V12. Since the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via V9, the second initial signal line 52 is connected to the first initial signal line 31 through the second connection electrode 44, so that the first initial signal line 31 and the second initial signal line 52 have the same potential. The present disclosure forms a mesh structure of the initial signal lines by providing the first initial signal line 31 whose main portion extends along the first direction X and the second initial signal line 52 extending along the second direction Y. This not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0195] In an exemplary embodiment, the anode connection electrode 53 is provided in at least a portion of the circuit unit. The anode connection electrode 53 is connected to the third connection electrode 45 through the thirteenth via hole V13. Since the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, the anode connection electrode 53 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the third connection electrode 45.

[0196] In an exemplary embodiment, the second initial signal line 52 in a circuit unit may include an extension portion 521 and a connection portion 522. The extension portion 521 may be a folded line extending along the second direction Y, and the connection portion 522 may be a straight line extending along the first direction X. In an exemplary embodiment, the end of the connection portion 522 away from the extension portion 521 may be connected to the second connection electrode 44 through a twelfth via V12.

[0197] In an exemplary embodiment, the orthographic projection of at least part of the extension portion 521 on the substrate is located within the range of the orthographic projection of the first power line 41 on the substrate. This not only allows the first power line 41 to effectively shield the influence of the second initial signal line 52 on the key nodes in the pixel driving circuit, thereby preventing the initial signal from affecting the potential of the key nodes of the pixel driving circuit, but also allows full utilization of the layout space, thereby avoiding the influence of the second initial signal line on the light transmittance, and improving the display effect.

[0198] In an exemplary embodiment, the orthographic projection of at least part of the connecting portion 522 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can fully utilize the layout space, avoid affecting the light transmittance due to the setting of the second initial signal line, and improve the display effect.

[0199] In an exemplary embodiment, the shape of the second initial signal line 52 in the M-th row and N-th column circuit unit can be the same as the shape of the second initial signal line 52 in the M+1-th row and N+2-th column circuit unit, and the shape of the second initial signal line 52 in the M+1-th row and N-th column circuit unit can be the same as the shape of the second initial signal line 52 in the M-th row and N+2-th column circuit unit.

[0200] In an exemplary embodiment, in the M-th row and N-th column circuit unit and the M+1-th row and N+2-th column circuit unit, the extension portion 521 may include a first initial portion c1, a second initial portion c2, and a third initial portion c3 sequentially connected along the second direction Y, the first initial portion c1 and the third initial portion c3 may be parallel to the second direction Y, the second initial portion c2 may be deflected in the opposite direction of the first direction X, and the second initial portion c2 has a first angle θ1 with the second direction Y, and the first angle θ1 may be greater than 0° and less than 90°.

[0201] In an exemplary embodiment, in the M-th row and N+2-th column circuit unit and the M+1-th row and N-th column circuit unit, the extension portion 521 may include a fourth initial portion c4, a fifth initial portion c5, a sixth initial portion c6, a seventh initial portion c7 and an eighth initial portion c8 connected in sequence along the second direction Y, the fourth initial portion c4, the sixth initial portion c6 and the eighth initial portion c8 may be parallel to the second direction Y, the fifth initial portion c5 may have a first angle θ1 with the second direction Y, the seventh initial portion c7 may have a second angle θ2 with the second direction Y, the first angle θ1 may be greater than 0° and less than 90°, and the second angle θ2 may be greater than 0° and less than 90°.

[0202] In an exemplary embodiment, an extending direction of the fifth initial portion c5 and an extending direction of the seventh initial portion c7 may be mirror-symmetrical with respect to the first direction X.

[0203] In an exemplary embodiment, at least part of the circuit units are provided with data signal lines 51 and anode connection electrodes 53, each circuit unit in the Nth column and the N+2th column is provided with a second initial signal line 52, and each circuit unit in the N+1th column and the N+3th column is not provided with a second initial signal line 52.

[0204] In an exemplary embodiment, the shape of the anode connecting electrode in the M-th row, N-th column circuit unit may be the same as the shape of the anode connecting electrode in the M+1-th row, N+2-th column circuit unit, and the shape of the anode connecting electrode may be rectangular. The shape of the anode connecting electrode in the M+1-th row, N-th column circuit unit may be the same as the shape of the anode connecting electrode in the M-th row, N+2-th column circuit unit, and the shape of the anode connecting electrode may be dumbbell-shaped. The shape of the anode connecting electrode in the M-th row, N+1-th column circuit unit may be the same as the shape of the anode connecting electrode in the M+1-th row, N+3-th column circuit unit, and the shape of the anode connecting electrode may be rectangular. The shape of the anode connecting electrode in the M+1-th row, N+1-th column circuit unit may be the same as the shape of the anode connecting electrode in the M-th row, N+3-th column circuit unit, and the shape of the anode connecting electrode may be rectangular.

[0205] (8) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, and providing a fourteenth via hole V14 on the second planar layer, such as Figure 14a and Figure 14b As shown, Figure 14b for Figure 14a A plan view of multiple vias in a circuit.

[0206] Combine Figures 7 to 14b As shown, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the anode connecting electrode 53 on the substrate, the second flat layer in the fourteenth via hole V14 is removed, exposing the surface of the anode connecting electrode 53, and the fourteenth via hole V14 is configured to connect the subsequently formed anode to the anode connecting electrode 53 through the via hole.

[0207] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a light-emitting control line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer stacked in sequence on the substrate.

[0208] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0209] (9) Forming an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form an anode pattern disposed on the second flat layer, wherein the anode forms a GGRB pixel arrangement, such as Figure 15a and Figure 15b As shown, Figure 15b for Figure 15a Schematic plan view of the middle anode.

[0210] Combine Figures 7 to 15b As shown, the anode pattern may include a first anode 71A of a red light-emitting device, a second anode 71B of a blue light-emitting device, a third anode 71C of a first green light-emitting device, and a fourth anode 71D of a second green light-emitting device. The area where the first anode 71A is located can form a red sub-pixel R that emits red light, the area where the second anode 71B is located can form a blue sub-pixel B that emits blue light, the area where the third anode 71C is located can form a first green sub-pixel G1 that emits green light, and the area where the fourth anode 71D is located can form a second green sub-pixel G2 that emits green light. The red sub-pixel R and the blue sub-pixel B are arranged in sequence along the second direction Y, the first green sub-pixel G1 and the second green sub-pixel G2 are arranged in sequence along the second direction Y, and the first green sub-pixel G1 and the second green sub-pixel G2 are respectively arranged on one side of the red sub-pixel R and the blue sub-pixel B in the first direction X. The red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1 and the second green sub-pixel G2 constitute a pixel unit.

[0211] In an exemplary embodiment, in a pixel unit, the first anode 71A is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M-th row and N-th column circuit unit, the second anode 71B is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M+1-th row and N-th column circuit unit, the third anode 71C is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M-th row and N+1 column circuit unit, and the fourth anode 71D is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M+1-th row and N+1 column circuit unit. In another pixel unit, the first anode 71A is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M+1th row and N+2th column circuit unit, the second anode 71B is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M-th row and N+2th column circuit unit, the third anode 71C is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M+1th row and N+3th column circuit unit, and the fourth anode 71D is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M-th row and N+3th column circuit unit.

[0212] In an exemplary embodiment, since the anode connection electrode 53 in at least one circuit unit is connected to the third connection electrode 45 through the thirteenth via hole V13, and the third connection electrode 45 is connected to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the fourth via hole V4, the third connection electrode 45 serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and thus the anode can be connected to the sixth transistor T6 and the seventh transistor T7 through the anode connection electrode 53 and the third connection electrode 45. The four anodes in at least one pixel unit are respectively connected to the pixel driving circuits of the four circuit units in a circuit unit group, thereby realizing that the pixel driving circuit can drive the light-emitting device to emit light.

[0213] In an exemplary embodiment, the positional relationship between the four sub-pixels of a pixel unit and the four circuit units in a circuit unit group can be the same or different. In an exemplary embodiment of the present disclosure, the main portion of the first anode 71A is located on the side of the corresponding connected circuit unit in the opposite direction of the first direction X, and the orthographic projection of the first anode 71A on the substrate can at least partially overlap with the orthographic projection of the extended portion of the second initial signal line on the substrate. The main portion of the second anode 71B is located on the side of the first direction X of the corresponding connected circuit unit, and the orthographic projection of the second anode 71B on the substrate can at least partially overlap with the orthographic projection of the data signal line on the substrate. The main portion of the third anode 71C is located on the side of the second direction Y of the corresponding connected circuit unit, and the main portion of the fourth anode 71D is located in the next row of circuit units of the corresponding connected circuit unit.

[0214] In one possible exemplary embodiment, the main portion of the first anode 71A may be located on one side of the corresponding connected circuit unit in the first direction X, and the orthographic projection of the first anode 71A on the substrate may at least partially overlap with the orthographic projection of the data signal line on the substrate. The main portion of the second anode 71B may be located on one side of the corresponding connected circuit unit in the opposite direction of the first direction X, and the orthographic projection of the second anode 71B on the substrate may at least partially overlap with the orthographic projection of the extended portion of the second initial signal line on the substrate.

[0215] In an exemplary embodiment, the shape and position of the first anode 71A in different pixel units may be the same or different. The shape and position of the second anode 71B in different pixel units may be the same or different. The shape and position of the third anode 71C in different pixel units may be the same or different. The shape and position of the fourth anode 71D in different pixel units may be the same or different. In the exemplary embodiments of the present disclosure, the two first anodes 71A respectively connected to the pixel driving circuits in the M-th row and N-th column circuit unit and the M+1-th row and N+2-th column circuit unit are the same in shape and position, the two second anodes 71B respectively connected to the pixel driving circuits in the M+1-th row and N-th column circuit unit and the M-th row and N+2-th column circuit unit are the same in shape and position, the two third anodes 71C respectively connected to the pixel driving circuits in the M-th row and N+1-th column circuit unit and the M+1-th row and N+3-th column circuit unit are the same in shape and position, and the two fourth anodes 71D respectively connected to the pixel driving circuits in the M+1-th row and N+1-th column circuit unit and the M-th row and N+3-th column circuit unit are the same in shape and position.

[0216] In an exemplary embodiment, the anode shapes and areas of the four sub-pixels in a pixel unit can be the same or different. In an exemplary embodiment of the present disclosure, the shapes and areas of the first anode 71A, the second anode 71B, the third anode 71C, and the fourth anode 71D in a pixel unit are all different.

[0217] In an exemplary embodiment, the first anode 71A in the red subpixel may include a first anode main portion, which may be shaped like a hexagon. In an exemplary embodiment, the first anode 71A may further include a first protrusion 71-1 and a second protrusion 71-2, both of which are connected to the first anode main portion. The first protrusion 71-1 may be a rectangle protruding toward the gate electrode of the third transistor T3 in the connected pixel driving circuit, and the second protrusion 71-2 may be a rectangle protruding toward the gate electrode of the sixth transistor T6 in the connected pixel driving circuit. The first protrusion 71-1 and the second protrusion 71-2 are configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, reducing the difference in parasitic capacitance of the N3 nodes in adjacent circuit units, thereby reducing brightness differences and improving display effects.

[0218] In an exemplary embodiment, the second anode 71B in the blue subpixel may include a second anode main portion, which may be shaped like a hexagon. In an exemplary embodiment, the second anode 71B may further include a third protrusion 71-3, a fourth protrusion 71-4, and a fifth protrusion 71-5. The third protrusion 71-3, the fourth protrusion 71-4, and the fifth protrusion 71-5 are all connected to the second anode main portion. The third protrusion 71-3 may be a rectangle protruding toward the first power line of the connected pixel driving circuit, the fourth protrusion 71-4 may be a rectangle protruding away from the first power line of the connected pixel driving circuit, and the fifth protrusion 71-5 may be a polygon protruding toward the sixth transistor T6 of the connected pixel driving circuit. The third protrusion 71-3, the fourth protrusion 71-4, and the fifth protrusion 71-5 are configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, reduce the difference in parasitic capacitance of the N3 nodes between adjacent circuit units, thereby reducing brightness differences and improving display effects.

[0219] In an exemplary embodiment, the third anode 71C may include a third anode main portion, which may be shaped like a pentagon. In an exemplary embodiment, the third anode 71C may further include a sixth protrusion 71-6, which is connected to the third anode main portion. The sixth protrusion 71-6 may be a rectangle protruding toward the sixth transistor T6 in the connected pixel driving circuit. The sixth protrusion 71-6 is configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, reducing the difference in parasitic capacitance of the N3 nodes in adjacent circuit units, thereby reducing brightness differences, particularly reducing the brightness difference between the current sub-pixel and the second green sub-pixel, and improving the display effect.

[0220] In an exemplary embodiment, the fourth anode 71D may include a fourth anode main portion, which may be shaped like a pentagon. In an exemplary embodiment, the fourth anode 71D may further include a seventh protrusion 71-7, which is connected to the fourth anode main portion. The seventh protrusion 71-7 may be in the shape of a bar protruding toward the gate electrode of the third transistor T3 in the connected pixel driving circuit. The seventh protrusion 71-7 is configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, reducing the difference in parasitic capacitance of the N3 nodes in adjacent circuit units, thereby reducing brightness differences, particularly reducing the brightness difference between the current sub-pixel and the first green sub-pixel, and improving the display effect.

[0221] (10) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film through a patterning process to form a pixel definition layer 72 pattern, such as Figure 16a and Figure 16b As shown, Figure 16b for Figure 16a A schematic diagram of the pixel definition layer in Figure 2.

[0222] Combine Figures 7 to 16b As shown, the pattern of the pixel definition layer 72 may include a first pixel opening 73A exposing the first anode 71A, a second pixel opening 73B exposing the second anode 71B, a third pixel opening 73C exposing the third anode 71C, and a fourth pixel opening 73D exposing the fourth anode 71D.

[0223] In an exemplary embodiment, the orthographic projection of the first pixel opening 73A on the substrate has a first center line Z1, and the orthographic projection of the extended portion of the second initial signal line 52 on the substrate has a second center line. The first center line Z1 is a line extending along the second direction Y and bisecting the orthographic projection of the first pixel opening 73A on the substrate in the first direction X. The second center line is a line extending along the second direction Y and bisecting the orthographic projection of the extended portion of the second initial signal line on the substrate in the first direction X. In an exemplary embodiment, the second center line is a line extending along the second direction Y and bisecting the orthographic projection of the first initial portion c1 of the extended portion on the substrate in the first direction X. In an exemplary embodiment, the first center line and the second center line at least partially overlap. By setting the first center line of the first pixel opening 73A and the second center line of the extended portion of the second initial signal line to at least partially overlap, the present disclosure can maintain bilateral symmetry of the second initial signal line in the first pixel opening 73A, ensure the flatness of the first anode, and avoid large visual angle deviation.

[0224] In an exemplary embodiment, the orthographic projection of the second pixel opening 73B on the substrate has a third centerline Z3, and the orthographic projection of the data signal line 51 on the substrate has a fourth centerline. The third centerline Z3 is a line extending along the second direction Y and bisecting the orthographic projection of the second pixel opening 73B on the substrate in the first direction X. The fourth centerline is a line extending along the second direction Y and bisecting the orthographic projection of the data signal line on the substrate in the first direction X. In an exemplary embodiment, the third centerline and the fourth centerline at least partially overlap. By setting the third centerline of the second pixel opening 73B and the fourth centerline of the data signal line to at least partially overlap, the present disclosure can maintain bilateral symmetry of the data signal line within the second pixel opening 73B, ensure the flatness of the second anode, and avoid significant color shift in the viewing angle.

[0225] As used herein, "bisecting A" may mean that the centerline is such that the distances between the two sides of A's orthographic projection on the substrate and the centerline are substantially equal. This substantially equal distance between the two sides and the centerline may vary within an allowable range due to process or tolerance. For example, the ratio of the minimum distance between the two edges of A's orthographic projection on the substrate and the centerline may be approximately 0.8 to 1.2. As used herein, "A and B overlap" does not require that A and B completely overlap; variations within an allowable range due to process or tolerance may exist.

[0226] In exemplary embodiments, other methods can be used to ensure the flatness of the anode. For example, increasing the thickness of the second flattening layer can be used. In another example, the signal line can be widened to substantially conform to the shape of the anode. In another example, the signal line can be divided into two sections, with the two sections symmetrically located on either side of the center line and placed under the anode on both sides. In another example, the signal line can be divided into two sections located on either side of the center line, with each section placed under the left and right sides of the anode, etc., and this disclosure is not limited hereto.

[0227] In an exemplary embodiment, the subsequent preparation process may include: forming an organic light-emitting layer using an evaporation or inkjet printing process, connecting the organic light-emitting layer to an anode through a pixel opening, forming a cathode on the organic light-emitting layer, and connecting the cathode to the organic light-emitting layer; forming an encapsulation layer, which may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of an organic material. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0228] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0229] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate. The second insulating layer and the third insulating layer are called gate insulating (GI) layers, and the fourth insulating layer is called an interlayer insulating (ILD) layer. The active layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology. The first flat layer and the second flat layer can be made of organic materials, such as resins. The fifth conductive layer can be a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure, such as ITO / Ag / ITO. The pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate. The cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0230] From the structure and preparation process of the display substrate described above, it can be seen that the display substrate provided by the present disclosure, by setting a first initial signal line extending in a first direction of the main part and a second initial signal line extending in a second direction of the main part, the first initial signal line and the second initial signal line are connected by vias, so that the initial signal line forms a mesh structure, which not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality. The present disclosure sets the first initial signal line and the second initial signal line in different conductive layers, and the extension of the second initial signal line at least partially overlaps with the first power line, and the connection part of the second initial signal line at least partially overlaps with the first initial signal line. This not only allows the first power line to effectively shield the influence of the second initial signal line on the key nodes in the pixel driving circuit, avoiding the initial signal affecting the potential of the key nodes of the pixel driving circuit, but also can make full use of the layout space and avoid affecting the light transmittance due to the setting of the second initial signal line. The present disclosure sets the second initial signal line in the first unit column, which can avoid the brightness difference between the two green sub-pixels in the same pixel unit and improve the display quality. By arranging the first center line of the first pixel opening to at least partially overlap the second center line of the extension of the second initial signal line, the present disclosure maintains bilateral symmetry of the second initial signal line within the first pixel opening, thereby ensuring the flatness of the first anode, avoiding large viewing angle color shift, and improving display quality. The disclosed manufacturing process is well compatible with existing manufacturing processes, is simple to implement, and has high production efficiency, low production cost, and a high yield rate.

[0231] Figure 17a FIG. 1 is a structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure. Figure 17b for Figure 17a FIG2 is a plan view of the fourth conductive layer in FIG2 , illustrating the planar structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the structure of the data signal lines 51 and the anode connection electrode 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the drive circuit layer of this exemplary embodiment is substantially similar to that of the aforementioned embodiment, with the difference being that the second initial signal lines 52 in the fourth conductive layer are disposed in some circuit units in a unit column, and two adjacent second initial signal lines 52 in a unit column can be isolated from each other.

[0232] like Figure 17a and Figure 17bAs shown, in an exemplary embodiment, the main portions of the second initial signal line 52 are respectively disposed in the M-th row, N-th column circuit unit and the M+1-th row, N+2-th column circuit unit. The second initial signal line 52 is not only connected to the second connection electrode 44 of the current circuit unit through the twelfth via hole V12 of the current circuit unit, but is also connected to the second connection electrode 44 of the circuit unit in the next row through the twelfth via hole V12 of the circuit unit in the next row. For example, for the M-th row, N-th column circuit unit, the second initial signal line 52 is connected to the second connection electrode 44 of the M-th row, N-th column circuit unit through the twelfth via hole V12 of the M-th row, N-th column circuit unit, and is connected to the second connection electrode 44 of the M+1-th row, N-th column circuit unit through the twelfth via hole V12 of the M+1-th row, N-th column circuit unit. For the M+1th row and Nth column circuit unit, the second initial signal line 52 is connected to the second connection electrode 44 of the M+1th row and Nth column circuit unit through the twelfth via V12 of the M+1th row and Nth column circuit unit, and is connected to the second connection electrode 44 of the M+2th row and Nth column circuit unit through the twelfth via V12 of the M+2th row and Nth column circuit unit.

[0233] In an exemplary embodiment, at least one second initial signal line 52 may include an extension portion 521, a first connection portion 523, and a second connection portion 524. The extension portion 521 may be a fold line extending along the second direction Y, and the first connection portion 523 and the second connection portion 524 may be straight lines extending along the first direction X. The first connection portion 523 may be provided in the current circuit unit, and the second connection portion 524 may be provided in the next row of circuit units. In an exemplary embodiment, the end of the first connection portion 523 away from the extension portion 521 may be connected to the second connection electrode 44 of the current circuit unit through the twelfth via V12 of the current circuit unit, and the end of the second connection portion 524 away from the extension portion 521 may be connected to the second connection electrode 44 of the next row of circuit units through the twelfth via V12 of the next row of circuit units. In this way, one second initial signal line 52 may be connected to the first initial signal lines of two unit rows, so that the first initial signal lines and the second initial signal lines form a mesh structure.

[0234] In an exemplary embodiment, the orthographic projection of the extension portion 521 on the substrate is at least partially located within the range of the orthographic projection of the first power line 41 on the substrate, and the orthographic projections of the first connection portion 523 and the second connection portion 524 on the substrate are at least partially located within the range of the orthographic projection of the first initial signal line 31 on the substrate. This can fully utilize the layout space, avoid affecting the light transmittance due to the setting of the second initial signal line, and improve the display effect.

[0235] In this exemplary embodiment, the subsequent process of forming the light-emitting structure layer is substantially similar to that of the aforementioned embodiment. After forming the anode pattern, the orthographic projection of the first anode on the substrate can at least partially overlap with the orthographic projection of the extended portion of the second initial signal line on the substrate, and the first centerline of the first pixel opening can at least partially overlap with the second centerline of the extended portion of the second initial signal line. This ensures the flatness of the first anode and prevents significant viewing angle color shift.

[0236] Figure 18a FIG. 1 is a structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure. Figure 18b for Figure 18a FIG2 is a plan view of the fourth conductive layer in FIG2 , illustrating the planar structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the structure of the data signal lines 51 and the anode connection electrode 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the drive circuit layer of this exemplary embodiment is substantially similar to that of the aforementioned embodiment, with the difference being that the second initial signal lines 52 in the fourth conductive layer are disposed in some circuit units in a unit column, and two adjacent second initial signal lines 52 in a unit column can be isolated from each other.

[0237] like Figure 18a and Figure 18b As shown, in an exemplary embodiment, the main parts of the second initial signal line 52 are respectively arranged in the M+1th row and Nth column circuit unit and the Mth row and N+2th column circuit unit, and the second initial signal line 52 is not only connected to the second connection electrode 44 of the current circuit unit through the twelfth via V12 of the current circuit unit, but also connected to the second connection electrode 44 of the next row of circuit units through the twelfth via V12 of the next row of circuit units.

[0238] In an exemplary embodiment, the main structure of at least one second initial signal line 52 may include an extension portion 521, a first connection portion 523, and a second connection portion 524. The extension portion 521, the first connection portion 523, and the second connection portion 524 may be connected to the first connection portion 523. Figure 17b The structure described above is similar. A single second initial signal line 52 can be connected to the first initial signal lines of two unit rows, forming a mesh structure of the first and second initial signal lines. The orthographic projection of the extension portion 521 on the substrate is at least partially within the orthographic projection of the first power line 41 on the substrate. The orthographic projections of the first connecting portion 523 and the second connecting portion 524 on the substrate are at least partially within the orthographic projection of the first initial signal line 31 on the substrate. This fully utilizes the layout space, avoids the impact of the second initial signal line on light transmittance, and improves the display effect.

[0239] In this exemplary embodiment, the subsequent process for forming the light-emitting structure layer is substantially similar to that of the aforementioned embodiment. After forming the anode pattern, the orthographic projections of the first and second anodes on the substrate can have no overlap with the orthographic projection of the second initial signal line on the substrate. The extended portion of the second initial signal line does not pass through any pixel openings, further ensuring the flatness of the first and second anodes and preventing significant color shift in the viewing angle.

[0240] Figure 19a FIG. 1 is a structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure. Figure 19b for Figure 19a A schematic plan view of the fourth conductive layer in FIG. 1 illustrates the planar structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the structures of the data signal lines 51 and the anode connection electrodes 53 in the semiconductor layer, first conductive layer, second conductive layer, third conductive layer, and fourth conductive layer in the driving circuit layer of this exemplary embodiment are substantially similar to those in the aforementioned embodiment, with the difference being that the second initial signal lines 52 in the fourth conductive layer are disposed in the (N+1)th and (N+3)th unit columns, and the second initial signal lines 52 of each circuit unit in the unit column are interconnected.

[0241] like Figure 19a and Figure 19b As shown, in an exemplary embodiment, the second connection electrodes 44 in the N+1th and N+3th column circuit cells include a first portion and a second portion connected to each other. The main portion of the second initial signal line 52 extends along the second direction Y. The second initial signal line 52 is connected to the second portion of the second connection electrode 44 through the twelfth via V12 in each circuit cell, so that the first initial signal line and the second initial signal line form a mesh structure.

[0242] In an exemplary embodiment, the shape of the second initial signal line 52 in the M-th row and N+1-th column circuit unit can be the same as the shape of the second initial signal line 52 in the M+1-th row and N+3-th column circuit unit, and the shape of the second initial signal line 52 in the M+1-th row and N+1-th column circuit unit can be the same as the shape of the second initial signal line 52 in the M-th row and N+3-th column circuit unit.

[0243] In an exemplary embodiment, the second initial signal line 52 in one circuit unit may include an extension portion 525 and a connection portion 526. The extension portion 525 may be a folded line extending along the second direction Y, and the connection portion 526 may be a straight line extending along the first direction X. In an exemplary embodiment, the end of the connection portion 526 away from the extension portion 525 may be connected to the second connection electrode 44 through a twelfth via V12.

[0244] In an exemplary embodiment, the orthographic projection of the extension portion 525 on the substrate is at least partially located within the range of the orthographic projection of the first power line 41 on the substrate. This not only allows the first power line 41 to effectively shield the influence of the second initial signal line 52 on the key nodes in the pixel driving circuit, thereby preventing the initial signal from affecting the potential of the key nodes of the pixel driving circuit, but also allows full utilization of the layout space, thereby avoiding the influence of the second initial signal line on the light transmittance, and improving the display effect.

[0245] In an exemplary embodiment, the orthographic projection of the connecting portion 526 on the substrate is at least partially located within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can fully utilize the layout space, avoid affecting the light transmittance due to the setting of the second initial signal line, and improve the display effect.

[0246] In an exemplary embodiment, there is no special requirement for the number of unit columns between adjacent second initial signal lines 52 , and the number can be set as needed, which is not limited in the present disclosure.

[0247] In this exemplary embodiment, the subsequent process of forming the light-emitting structure layer is substantially similar to that of the aforementioned embodiment. After the anode pattern is formed, the orthographic projections of the third and fourth anodes on the substrate can at least partially overlap with the orthographic projection of the connecting portion of the second initial signal line on the substrate, while the orthographic projections of the first and second anodes on the substrate do not overlap with the orthographic projection of the second initial signal line on the substrate, and the orthographic projections of the first and second pixel openings on the substrate do not overlap with the orthographic projection of the second initial signal line on the substrate. That is, the second initial signal line does not pass through the first and second pixel openings. Therefore, the flatness of the first and second anodes can be ensured, and large viewing angle angular deviation can be avoided.

[0248] In this exemplary embodiment, since the second initial signal line passes through the first green pixel opening and / or the second green pixel opening, the area where the first green pixel opening and / or the second green pixel opening is located can adopt measures such as thickening the flattening layer to improve the flatness of the third anode and / or the fourth anode.

[0249] In an exemplary embodiment, the second initial signal line 52 can be arranged in some circuit units in the N+1th unit column and the N+3th unit column, and two adjacent second initial signal lines 52 in a unit column can be isolated from each other. For example, the main portion of the second initial signal line 52 can be respectively arranged in the Mth row, N+1th column circuit unit and the M+1th row, N+3th column circuit unit, so that the orthographic projection of the subsequently formed third anode on the substrate at least partially overlaps with the orthographic projection of the extension of the second initial signal line on the substrate, and the orthographic projection of the fourth anode on the substrate has no overlapping area with the orthographic projection of the extension of the second initial signal line on the substrate. For another example, the main portion of the second initial signal line 52 can be respectively arranged in the M+1th row, N+1th column circuit unit and the Mth row, N+3th column circuit unit, so that the orthographic projection of the subsequently formed fourth anode on the substrate at least partially overlaps with the orthographic projection of the extension of the second initial signal line on the substrate, and the orthographic projection of the third anode on the substrate has no overlapping area with the orthographic projection of the extension of the second initial signal line on the substrate. The present disclosure is not limited here.

[0250] Figure 20a FIG. 1 is a structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure. Figure 20b for Figure 20a FIG2 is a plan view of the fourth conductive layer in FIG2 , illustrating the planar structure of eight circuit units (two unit rows and four unit columns). In the exemplary embodiment, the structures of the data signal lines 51 and the anode connection electrodes 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the driving circuit layer of this exemplary embodiment are substantially similar to those in the aforementioned embodiment, with the difference being that the second initial signal lines 52 in the fourth conductive layer are respectively arranged in the Nth unit column, the N+1th unit column, the N+2th unit column, and the N+3th unit column, and the second initial signal lines 52 of each circuit unit in at least one unit column are interconnected.

[0251] like Figure 20a and Figure 20b As shown, in an exemplary embodiment, the second connection electrode 44 in at least one column of circuit units includes a first portion and a second portion that are interconnected. The main portion of the second initial signal line 52 extends along the second direction Y. The second initial signal line 52 is connected to the second portion of the second connection electrode 44 through the twelfth via V12 in each circuit unit, forming a mesh structure between the first and second initial signal lines. This minimizes the resistance of the initial signal lines, reduces the initial voltage drop, and effectively improves the uniformity of the initial voltage across the display substrate, effectively improving display uniformity and enhancing display quality.

[0252] In an exemplary embodiment, the second initial signal line 52 of one circuit unit in the Nth unit column and the N+2th unit column may include an extension portion 521 and a connection portion 522. The extension portion 521 may be a folded line with a main portion extending along the second direction Y, and the connection portion 522 may be a straight line with a main portion extending along the first direction X. In an exemplary embodiment, the end of the connection portion 522 away from the extension portion 521 may be connected to the second connection electrode 44 through a twelfth via V12.

[0253] In an exemplary embodiment, the second initial signal line 52 of one circuit unit in the (N+1)th and (N+3)th unit columns may include an extension portion 525 and a connection portion 526. The extension portion 525 may be a folded line with a main portion extending along the second direction Y, and the connection portion 526 may be a straight line with a main portion extending along the first direction X. In an exemplary embodiment, the end of the connection portion 526 away from the extension portion 525 may be connected to the second connection electrode 44 through a twelfth via V12.

[0254] In an exemplary embodiment, the orthographic projections of the extension portion 521 and the extension portion 525 on the substrate are at least partially located within the range of the orthographic projection of the first power line 41 on the substrate. This not only allows the first power line 41 to effectively shield the influence of the second initial signal line 52 on the key nodes in the pixel driving circuit, thereby preventing the initial signal from affecting the potential of the key nodes of the pixel driving circuit, but also allows full utilization of the layout space, avoiding the influence of light transmittance due to the setting of the second initial signal line, and improving the display effect.

[0255] In an exemplary embodiment, the orthographic projections of the connecting portion 522 and the connecting portion 526 on the substrate are at least partially located within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can fully utilize the layout space, avoid affecting the light transmittance due to the setting of the second initial signal line, and improve the display effect.

[0256] In this exemplary embodiment, the subsequent process of forming the light-emitting structure layer is substantially similar to that of the aforementioned embodiment. After forming the anode pattern, the orthographic projections of the first anode, the second anode, the third anode, and the fourth anode on the substrate can at least partially overlap with the orthographic projection of the second initial signal line on the substrate, the first center line of the first pixel opening at least partially overlaps with the second center line of the extension of the second initial signal line, and the third center line of the second pixel opening at least partially overlaps with the fourth center line of the data signal line, which helps to eliminate the differences in flatness between the individual anodes and avoid large visual angle skew. Since the second initial signal line will pass through the first green pixel opening and / or the second green pixel opening, the area where the first green pixel opening and / or the second green pixel opening is located can be improved by increasing the thickness of the planarization layer or other means to improve the flatness of the third anode and / or the fourth anode.

[0257] In an exemplary embodiment, the second initial signal line 52 may be provided in some circuit cells in the Nth unit column, the N+1th unit column, the N+2th unit column, and the N+3th unit column, and two adjacent second initial signal lines 52 in a unit column may be isolated from each other. For example, in the Nth unit column and the N+2th unit column, the second initial signal lines 52 of adjacent circuit cells may be interconnected, while in the N+1th unit column and the N+3th unit column, the second initial signal line 52 may be provided only in the Mth row, N+1th column circuit cell and the M+1th row, N+3th column circuit cell, or the second initial signal line 52 may be provided only in the Mth row, N+3th column circuit cell and the M+1th row, N+1th column circuit cell. For another example, in the N+1th unit column and the N+3th unit column, the second initial signal lines 52 of adjacent circuit units may be interconnected, while in the Nth unit column and the N+2th unit column, the second initial signal line 52 may be set only in the Mth row and Nth column circuit unit and the M+1th row and N+2th column circuit unit, or the second initial signal line 52 may be set only in the Mth row and N+2th column circuit unit and the M+1th row and Nth column circuit unit. For another example, the second initial signal line 52 can be set only in the M-th row and N-th column circuit unit and the M+1-th row and N+2-th column circuit unit, or the second initial signal line 52 can be set only in the M-th row and N+2-th column circuit unit and the M+1-th row and N-th column circuit unit, the second initial signal line 52 can be set only in the M-th row and N+1-th column circuit unit and the M+1-th row and N+3-th column circuit unit, or the second initial signal line 52 can be set only in the M-th row and N+3-th column circuit unit and the M+1-th row and N+1-th column circuit unit, and the present disclosure does not limit this.

[0258] Figure 21a This is another schematic diagram of an exemplary embodiment of the present disclosure after forming an anode pattern. Figure 21b for Figure 21a A schematic plan view of the anode in the middle illustrates the planar structure of eight circuit units (two unit rows and four unit columns). In the exemplary embodiment, the structure of the driving circuit layer of this exemplary embodiment is substantially similar to that of the aforementioned embodiment. The second initial signal line 52 in the fourth conductive layer is disposed in the Nth unit column, the N+1th unit column, the N+2th unit column, and the N+3th unit column. The second initial signal line 52 of each circuit unit in the unit column is interconnected. The difference is that the anodes of the light-emitting structure layer are arranged in a diamond shape to form an RGBG pixel arrangement.

[0259] like Figure 21a and Figure 21bAs shown, the anode pattern may include a first anode 71A of a red light-emitting device, a second anode 71B of a blue light-emitting device, a third anode 71C of a first green light-emitting device, and a fourth anode 71D of a second green light-emitting device. The area where the first anode 71A is located can form a red sub-pixel R that emits red light, the area where the second anode 71B is located can form a blue sub-pixel B that emits blue light, the area where the third anode 71C is located can form a first green sub-pixel G1 that emits green light, and the area where the fourth anode 71D is located can form a second green sub-pixel G2 that emits green light. The red sub-pixel R and the blue sub-pixel B are arranged in sequence along the second direction Y, the first green sub-pixel G1 and the second green sub-pixel G2 are arranged in sequence along the first direction X, the first green sub-pixel G1 is arranged on the opposite side of the red sub-pixel R and the blue sub-pixel B in the first direction X, and the second green sub-pixel G2 is arranged on one side of the red sub-pixel R and the blue sub-pixel B in the first direction X. The red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1, and the second green sub-pixel G2 constitute a pixel unit.

[0260] In an exemplary embodiment, in a pixel unit, the first anode 71A is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M-th row and N-th column circuit unit, the second anode 71B is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M+1-th row and N-th column circuit unit, the third anode 71C is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M-th row and N+1-th column circuit unit, and the fourth anode 71D is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M-th row and N-1-th column circuit unit. In another pixel unit, the first anode 71A is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the M+1th row and N+2th column circuit unit, the second anode 71B is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the Mth row and N+2th column circuit unit, the third anode 71C is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the Mth row and N+1th column circuit unit, and the fourth anode 71D is connected to the anode connecting electrode 53 in the circuit unit through the fourteenth via V14 in the Mth row and N+3th column circuit unit.

[0261] In an exemplary embodiment, the orthographic projections of the first anode 71A and the second anode 71B on the substrate may at least partially overlap with the orthographic projection of the extended portion of the second initial signal line on the substrate, and the orthographic projections of the third anode 71C and the second green anode 71D on the substrate may at least partially overlap with the orthographic projection of the connecting portion of the second initial signal line on the substrate.

[0262] In an exemplary embodiment, the shape and position of the anodes in different pixel units may be the same or different, and the shape and area of ​​the anodes of the four sub-pixels in one pixel unit may be the same or different, which is not limited in the present disclosure.

[0263] Figure 22a This is another schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition layer pattern. Figure 22b for Figure 22a A schematic plan view of the pixel definition layer in FIG. 1 illustrates the planar structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the structure of the drive circuit layer and anode is substantially similar to that of the previous embodiment, except that the openings of the pixel definition layer 72 in the light-emitting structure layer are arranged in a diamond shape.

[0264] like Figure 22a and Figure 22b As shown, the pattern of the pixel definition layer 72 may include a first pixel opening 73A exposing the first anode 71A, a second pixel opening 73B exposing the second anode 71B, a third pixel opening 73C exposing the third anode 71C, and a fourth pixel opening 73D exposing the fourth anode 71D.

[0265] In an exemplary embodiment, the orthographic projection of the first pixel opening 73A on the substrate has a first center line Z1, the orthographic projection of the extended portion of the second initial signal line 52 on the substrate has a second center line, the orthographic projection of the second pixel opening 73B on the substrate has a third center line Z3, and the orthographic projection of the data signal line 51 on the substrate has a fourth center line. The first center line Z1 is a line extending along the second direction Y and bisecting the orthographic projection of the first pixel opening 73A on the substrate in the first direction X. The second center line is a line extending along the second direction Y and bisecting the orthographic projection of the extended portion of the second initial signal line on the substrate in the first direction X. The third center line Z3 is a line extending along the second direction Y and bisecting the orthographic projection of the second pixel opening 73B on the substrate in the first direction X. The fourth center line is a line extending along the second direction Y and bisecting the orthographic projection of the data signal line on the substrate in the first direction X.

[0266] As used herein, "bisecting A" means that the centerline makes the areas of the two sides of A's orthographic projection onto the substrate substantially equal. This substantially equal area may have variations within an acceptable range due to process or tolerances. For example, the ratio of the two areas may be between approximately 0.8 and 1.2. As used herein, "A and B overlap" does not require that A and B completely overlap; variations within an acceptable range due to process or tolerances may exist.

[0267] In an exemplary embodiment, the first centerline Z1 may at least partially overlap the third centerline Z3, the second centerline and the fourth centerline may be located on both sides of the first centerline Z1, and the second centerline and the fourth centerline may be located on both sides of the third centerline.

[0268] In an exemplary embodiment, the second center line of the second initial signal line and the fourth center line of the data signal line can be symmetrically arranged relative to the first center line Z1 of the first pixel opening, and the second center line of the second initial signal line and the fourth center line of the data signal line can be symmetrically arranged relative to the third center line Z3 of the second pixel opening. By arranging the extended portion of the second initial signal line and the data signal line on either side of the first center line of the first pixel opening 73A or the third center line of the second pixel opening 73B, respectively, the present disclosure ensures the flatness of the first anode and the second anode, thereby preventing significant color shift in the viewing angle.

[0269] The term "center line A and center line B are symmetrically arranged relative to center line C" in the present disclosure means that the ratio of the distance between center line A and center line C to the distance between center line B and center line C is approximately 0.8 to 1.2.

[0270] In an exemplary embodiment, the position of the anode in the circuit unit can be adjusted so that the second center line of the second initial signal line overlaps with the first center line of the first pixel opening and the third center line of the second pixel opening, or the fourth center line of the data signal line overlaps with the first center line of the first pixel opening and the third center line of the second pixel opening. The present disclosure does not limit this.

[0271] In an exemplary embodiment, the orthographic projection of the third pixel opening 73C on the substrate has a fifth center line Z5, the orthographic projection of the fourth pixel opening 73D on the substrate has a sixth center line Z6, and the orthographic projection of the connecting portion of the second initial signal line 52 on the substrate has a seventh center line. The fifth center line Z5 is a line extending along the first direction X and bisecting the orthographic projection of the third pixel opening 73C on the substrate in the second direction Y. The sixth center line Z6 is a line extending along the first direction X and bisecting the orthographic projection of the fourth pixel opening 73D on the substrate in the second direction Y. The seventh center line is a line extending along the first direction X and bisecting the orthographic projection of the connecting portion of the second initial signal line 52 on the substrate in the second direction Y.

[0272] In an exemplary embodiment, the fifth center line Z5 may at least partially overlap with the seventh center line, and the sixth center line Z6 may at least partially overlap with the seventh center line. The present disclosure ensures the flatness of the third and fourth anodes and avoids significant color shift in viewing angle by ensuring that the fifth center line of the third pixel opening 73C at least partially overlaps with the seventh center line of the connection portion of the second initial signal line, and that the sixth center line of the fourth pixel opening 73D at least partially overlaps with the seventh center line of the connection portion of the second initial signal line.

[0273] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the first initial signal line can be set in the first conductive layer (GATE 1). For another example, the second initial signal line can be set in the third conductive layer (SD1), and the first power line can be set in the fourth conductive layer (SD2), which is not limited in the present disclosure. The display substrate of the present disclosure can be applied to other display devices having a pixel driving circuit, which is not limited in the present disclosure.

[0274] The present disclosure also provides a method for preparing a display substrate, for producing the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer including a plurality of circuit units, and the light-emitting structure layer including a plurality of light-emitting devices; at least one circuit unit includes a first power line, an initial signal line, and a pixel driving circuit, the initial signal line including a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersecting the second direction; the preparation method includes:

[0275] forming a first initial signal line extending along the first direction on the substrate;

[0276] A second initial signal line extending along the second direction is formed, and an orthographic projection of the second initial signal line on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate.

[0277] The display substrate manufactured by the method for manufacturing the display substrate provided in the present disclosure has similar implementation principles and implementation effects, which will not be described in detail here.

[0278] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0279] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a drive circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the drive circuit layer away from the base, the drive circuit layer including a plurality of circuit units, and the light-emitting structure layer including a plurality of light-emitting devices; at least one circuit unit including a first power line, an initial signal line, and a pixel drive circuit, the initial signal line including a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersecting the second direction; An orthographic projection of the second initial signal line on the substrate at least partially overlaps with an orthographic projection of the first power line extending along the second direction on the substrate; The second initial signal line in at least one circuit unit includes an extending portion and a connecting portion connected to each other, the extending portion extends along the second direction, the connecting portion extends along the first direction, and the connecting portion is connected to the first initial signal line through a via; The orthographic projection of the extending portion on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and the orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate.

2. The display substrate according to claim 1, wherein At least one circuit unit includes a second connection electrode, the connection portion is connected to the second connection electrode through a via hole, and the second connection electrode is connected to the first initial signal line through a via hole.

3. The display substrate according to claim 2, wherein: The second connection electrode is connected to the first area of ​​the active layer of the first transistor and the first area of ​​the active layer of the seventh transistor in the pixel driving circuit through a via hole.

4. The display substrate according to claim 1, wherein The driving circuit layer includes multiple unit rows and multiple unit columns, the unit rows include multiple circuit units arranged along the first direction, and the unit columns include multiple circuit units arranged along the second direction; in at least one unit column, the second initial signal lines in adjacent circuit units are connected to each other, or the second initial signal lines in adjacent circuit units are arranged at intervals.

5. The display substrate according to claim 4, wherein: The multiple circuit units include a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light; the multiple unit columns include a first unit column and a second unit column, the first circuit units and the second circuit units in the first unit column are alternately arranged along the second direction, and the third circuit units and the fourth circuit units in the second unit column are alternately arranged along the second direction; at least part of the second initial signal line is arranged in the first unit column. The display substrate according to claim 5 , wherein: The light-emitting device includes an anode and a pixel definition layer; the anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device; The pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode, a third pixel opening exposing the third anode, and a fourth pixel opening exposing the fourth anode; A first center line of an orthographic projection of the first pixel opening on the substrate at least partially overlaps with a second center line of an orthographic projection of the second initial signal line on the substrate.

7. The display substrate according to claim 6, wherein: The driving circuit layer further includes a data signal line, and a third center line of an orthographic projection of the second pixel opening on the substrate at least partially overlaps with a fourth center line of an orthographic projection of the data signal line on the substrate.

8. The display substrate according to claim 5, wherein: The light-emitting device includes an anode and a pixel definition layer; the anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device; The pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode, a third pixel opening exposing the third anode, and a fourth pixel opening exposing the fourth anode; the driving circuit layer further includes a data signal line; A second center line of the extension of the second initial signal line projected on the substrate and a fourth center line of the data signal line projected on the substrate are located on both sides of a first center line of the first pixel opening projected on the substrate.

9. The display substrate according to claim 8, wherein: The second center line of the extension portion of the second initial signal line projected on the substrate and the fourth center line of the data signal line projected on the substrate are symmetrically arranged relative to the first center line of the first pixel opening projected on the substrate.

10. The display substrate according to claim 8, wherein A second center line of the extension of the second initial signal line projected on the substrate and a fourth center line of the data signal line projected on the substrate are located on both sides of a third center line of the second pixel opening projected on the substrate.

11. The display substrate according to claim 10, wherein: The second center line of the extension portion of the second initial signal line projected on the substrate and the fourth center line of the data signal line projected on the substrate are symmetrically arranged with respect to the third center line of the second pixel opening projected on the substrate.

12. The display substrate according to claim 4, wherein: The multiple circuit units include a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light; the multiple unit columns include a first unit column and a second unit column, the first circuit units and the second circuit units in the first unit column are alternately arranged along the second direction, and the third circuit units and the fourth circuit units in the second unit column are alternately arranged along the second direction; at least part of the second initial signal line is arranged in the second unit column.

13. The display substrate according to claim 12, wherein: The light-emitting device includes an anode and a pixel definition layer; the anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device; The pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode, a third pixel opening exposing the third anode, and a fourth pixel opening exposing the fourth anode; A fifth center line of an orthographic projection of the third pixel opening on the substrate at least partially overlaps with a seventh center line of an orthographic projection of the connecting portion of the second initial signal line on the substrate.

14. The display substrate according to claim 13, wherein: A sixth center line of an orthographic projection of the fourth pixel opening on the substrate at least partially overlaps with a seventh center line of an orthographic projection of the connecting portion of the second initial signal line on the substrate.

15. The display substrate according to claim 4, wherein The multiple circuit units include a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light; the multiple unit columns include a first unit column and a second unit column, the first circuit units and the second circuit units in the first unit column are alternately arranged along the second direction, and the third circuit units and the fourth circuit units in the second unit column are alternately arranged along the second direction; the second initial signal line is arranged in the first unit column and the second unit column.

16. The display substrate according to any one of claims 1 to 15, wherein: In a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the base; the semiconductor layer includes an active layer of multiple transistors in the pixel driving circuit, the first conductive layer includes a scanning signal line and gate electrodes of multiple transistors, the second conductive layer includes the first initial signal line, the third conductive layer includes a first power line, and the fourth conductive layer includes a data signal line and the second initial signal line.

17. The display substrate according to claim 16, wherein: The third conductive layer further includes a second connecting electrode, the second connecting electrode is connected to the first initial signal line through a via hole, and the second initial signal line is connected to the second connecting electrode through a via hole.

18. The display substrate according to claim 16, wherein: The second conductive layer further includes a shielding electrode, and the first power line is connected to the shielding electrode through a via hole.

19. The display substrate according to claim 18, wherein: The orthographic projection of at least a portion of the shielding electrode on the substrate is located between the orthographic projection of the data signal line on the substrate and the orthographic projection of the second electrode of the first transistor in the pixel driving circuit on the substrate.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

21. A method for manufacturing a display substrate, the display substrate comprising a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer comprising a plurality of circuit units, and the light-emitting structure layer comprising a plurality of light-emitting devices; at least one circuit unit comprising a first power line, an initial signal line, and a pixel driving circuit, the initial signal line comprising a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersecting the second direction; the manufacturing method comprising: forming a first initial signal line extending along the first direction on the substrate; forming a second initial signal line extending along the second direction, wherein an orthographic projection of the second initial signal line on the substrate at least partially overlaps with an orthographic projection of the first power line extending along the second direction on the substrate; The second initial signal line in at least one circuit unit includes an extending portion and a connecting portion connected to each other, the extending portion extends along the second direction, the connecting portion extends along the first direction, and the connecting portion is connected to the first initial signal line through a via; The orthographic projection of the extending portion on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and the orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate.

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