Display panel and display device

Abstract

The embodiment of the present invention discloses a display panel and a display device, comprising: a plurality of pixel units, a plurality of scan lines, a plurality of data lines, a multiplexer and h control signal lines. In the same data writing phase of the display panel, in the first phase, in the enable segment of the jth control signal, a data signal is written to the data line. In the second phase, the first scan enable voltage edge of the i-th scan signal is located after the first control enable voltage edge of the j-th control signal, and the data signal on the data line is written to the pixel unit; the second scan enable voltage edge of the i-th scan signal in the m-th data writing phase is located before the second control enable voltage edge of the n-th control signal in the m+1-th data writing phase, |n‑j|<h, 1≤n≤h, m, n are positive integers. The solution provided by the present invention solves the problem of black lines or bright lines appearing at the junction of black and white images of the display device, and improves the display quality of the display device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of display technology, people's requirements for the quality of display panels are getting higher and higher. Figure 1 is a schematic diagram of a display screen of an existing display panel, such as Figure 1 As shown, the image displayed by the display panel includes both white and black images. When the white image switches to the black image, a black line usually appears between the two black images. Figure 1 The area around the dotted circle in the upper middle, and when the black screen switches to the white screen, a bright line usually appears between the two black screens. Figure 1 This results in a poor display effect of the display panel, thereby reducing the display quality of the display device. Summary of the invention

[0003] The present invention provides a display panel and a display device to solve the problem of black lines or bright lines appearing at the junction of black and white images of the display device, thereby improving the display quality of the display device.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] A plurality of pixel units;

[0006] A plurality of scan lines, including an i-th scan line, wherein the i-th scan line is configured to transmit an i-th scan signal to the pixel units arranged in a row along a first direction; the i-th scan signal includes a first scan enable voltage edge and a second scan enable voltage edge that appear in sequence, and a period between the first scan enable voltage edge and the second scan enable voltage edge is an enable segment of the i-th scan signal; i is a positive integer;

[0007] a plurality of data lines configured to transmit data signals to the pixel units arranged in a column along a second direction, including a first data line and a second data line, the first data line being electrically connected to the pixel units in odd rows in a column of the pixel units, the second data line being electrically connected to the pixel units in even rows in a column of the pixel units, the first direction intersecting the second direction;

[0008] A multiplexer, comprising a plurality of selector output terminals and a plurality of selector control terminals, wherein the selector output terminals are electrically connected to the data lines;

[0009] h control signal lines, the control signal lines are electrically connected to the selector control end, including a j-th control signal line, the j-th control signal line is configured to transmit a j-th control signal; the j-th control signal includes a first control enable voltage edge and a second control enable voltage edge that appear in sequence, and a period between the first control enable voltage edge and the second control enable voltage edge is an enable period of the j-th control signal; 1≤j≤h, j and h are positive integers;

[0010] The driving timing of the display panel includes a data writing phase, and the data writing phase includes a first phase and a second phase;

[0011] In the same data writing phase, in the first phase, in the enable segment of the j-th control signal, the data signal is written to the data line, and in the second phase, the first scan enable voltage edge of the i-th scan signal is located after the first control enable voltage edge of the j-th control signal, and the data signal on the data line is written to the pixel unit;

[0012] The second scan enable voltage edge of the i-th scan signal in the m-th data writing phase is located before the second control enable voltage edge of the n-th control signal in the m+1-th data writing phase, |nj|<h, 1≤n≤h, m and n are positive integers.

[0013] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first aspect.

[0014] In an embodiment of the present invention, a display panel is provided to include a plurality of pixel units, a plurality of scan lines, a plurality of data lines, a multiplexer, and h control signal lines, wherein the i-th scan line among the plurality of scan lines is configured to transmit the i-th scan signal to the pixel units arranged in a row along a first direction, and within the enabling section of the i-th scan signal, the i-th scan signal can control all transistors on the data writing path of all pixel units electrically connected to the scan line to turn on, so as to write data signals to the transistors driving the light-emitting elements in the pixel units to emit light. The first data line among the plurality of data lines is electrically connected to the pixel units in odd rows in a column of pixel units, and the second data line is electrically connected to the pixel units in even rows in a column of pixel units, so that the first data line writes data signals to the pixel units in odd rows, and the second data line writes data signals to the pixel units in even rows. The selector output end of the multiplexer is electrically connected to the data line, and the control signal line is electrically connected to the selector control end, so that the j-th control signal line is configured to transmit the j-th control signal to select the multiplexer to write data signals to the data line. Thus, in the same data writing phase of the display panel, in the first phase, in the enable segment of the jth control signal, the data signal is written to the data line to charge the data line. In the second phase, the first scan enable voltage edge of the i-th scan signal is located after the first control enable voltage edge of the j-th control signal, and the data signal on the data line is written to the pixel unit, so that the pixel unit can emit light and display according to the written data signal. The second scan enable voltage edge of the i-th scan signal in the m-th data writing phase is located before the second control enable voltage edge of the n-th control signal in the m+1-th data writing phase, |nj|<h, 1≤n≤h, m, n are positive integers, so that in the phase where the power supply signal fluctuates, the overlapping time of the fluctuation signal of the power supply signal and the enable segment of the i-th scan signal in timing is reduced, thereby reducing the influence on the data signal written into the pixel unit, ensuring the normal light-emitting display of the pixel unit, so as to solve the problem of black lines or bright lines appearing at the junction of black and white screens of the display device, thereby improving the display effect of the display panel.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, although the drawings described below are some specific embodiments of the present invention, for those skilled in the art, the basic concepts of the device structure, driving method and manufacturing method disclosed and suggested by the various embodiments of the present invention can be expanded and extended to other structures and drawings, and there is no doubt that these should be within the scope of the claims of the present invention.

[0017] Figure 1 A schematic diagram of a display screen of an existing display panel;

[0018] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of the structure of a pixel unit provided by an embodiment of the present invention;

[0020] Figure 4 for Figure 3 The driving timing diagram;

[0021] Figure 5 A driving timing diagram of an existing display panel provided by an embodiment of the present invention;

[0022] Figure 6 A driving timing diagram of a display panel provided by an embodiment of the present invention;

[0023] Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0024] Figure 8 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0025] Fig. 9 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0026] Fig.10 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0027] Fig.11 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0028] Fig.12 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0029] Fig.13 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0030] Fig.14 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0031] Fig.15 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0032] Fig.16 A driving timing diagram of another display panel provided by an embodiment of the present invention;

[0033] Fig.17 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0034] Fig.18 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0035] Fig.19 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0036] Fig. 20 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0037] Fig.21 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0038] Fig. 22 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described through implementation methods with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the basic concepts disclosed and suggested by the embodiments of the present invention, all other embodiments obtained by those skilled in the art are within the scope of protection of the present invention.

[0040] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 3 A schematic diagram of a pixel unit structure provided by an embodiment of the present invention, referring to Figure 2 and Figure 3 As shown, the display panel 100 includes a plurality of pixel units 10. The pixel unit 10 generally includes a pixel driving circuit 11 and a light emitting element 12 that are electrically connected. Figure 3As shown, the pixel driving circuit 11 can be an existing 7T1C circuit, that is, the pixel driving circuit 11 includes a driving module 111, an initialization module 112, a data writing module 113, a threshold compensation module 114, a light emitting control module 115, a reset module 116 and a storage capacitor Cst, but is not limited thereto. The cathode of the light emitting element 12 can receive a negative voltage signal PVEE, so that the driving module 111 in the pixel driving circuit 11 can drive the light emitting element 12 to emit light under the action of the power signal PVDD (for example, a positive voltage signal) provided by the power signal terminal and the data signal written by the driving module, so that the display panel 100 presents a corresponding display screen.

[0041] For example, Figure 3 The driving module 111 in the pixel driving circuit 11 includes a third transistor M3, the initialization module 112 includes a fifth transistor M5, the data writing module 113 includes a second transistor M2, the threshold compensation module 114 includes a fourth transistor M4, the light emitting control module 115 includes a first transistor M1 and a sixth transistor M6, and the reset module 116 includes a seventh transistor M7, wherein the gate of the fifth transistor M5 and the gate of the seventh transistor M7 are both connected to the scanning signal terminal S1, the gate of the second transistor M2 and the gate of the fourth transistor M4 are both connected to the scanning signal terminal S2, and the gate of the first transistor M1 and the gate of the sixth transistor M6 are both connected to the light emitting control terminal Emit. Figure 3 All transistors in the example are P-channel transistors. When the scanning signal provided to the gate is at a high level, the transistor is turned off, and when the scanning signal is at a low level, the transistor is turned on. Figure 6 for Figure 3 The driving timing diagram, combined with the reference Figure 3 and Figure 6 As shown, the driving timing of the pixel unit 10 may include an initialization phase ta, a data writing phase tb (ie, the data writing phase t described below), and a light emitting phase tc.

[0042] In the initialization stage ta, the scanning signal terminal S1 provides a scanning signal s1 which changes from a high level to a low level. At this time, the fifth transistor M5 is turned on, and the reset signal Vref is written into the first node N1. At the same time, the seventh transistor M7 is turned on, and the reset signal Vref is written into the anode of the light emitting element 12 to avoid the influence of the voltage signal written in the previous frame.

[0043] In the data writing phase tb, the scan signal s2 provided by the scan signal terminal S2 changes from a high level to a low level. At this time, the second transistor M2 and the fourth transistor M4 are turned on, and the data signal Vdata provided by the data terminal Data flows into the first node N1 through the second transistor M2, the third transistor M3, and the fourth transistor M4 in sequence.

[0044] In the light-emitting stage tc, the light-emitting control signal emit provided by the light-emitting control signal terminal Emit jumps from a high level to a low level. At this time, the first transistor M1 and the sixth transistor M6 are turned on, and a path is formed from the positive power signal terminal PVDD to the negative power signal terminal PVEE, thereby driving the light-emitting element 12 to emit light for display.

[0045] Continue to refer Figure 2 As shown, the plurality of scan lines 20 include an i-th scan line, and the i-th scan line is configured to transmit an i-th scan signal Scani to the pixel units 10 arranged in rows along the first direction x. Figure 2 and Figure 3 It can be understood that the i-th scanning signal Scani can be a scanning signal s2 that controls the pixel driving circuit 11 to write the data signal to the driving module 111 (i.e., the gate of the third transistor M3) in the data writing phase t2. In this way, after the i-th scanning signal Scani controls all transistors on the data writing path of the pixel unit 10 electrically connected to the scanning line 20 to turn on, the data signal provided by the data line 30 is written to the first node N1 of the pixel driving circuit 11 in the pixel unit 10, so that the light-emitting element 12 in the pixel unit 10 can emit light and display according to the written data signal and the power supply signal PVDD in the light-emitting phase. The i-th scanning signal Scani includes a first scanning enable voltage edge and a second scanning enable voltage edge that appear in sequence. The period between the first scanning enable voltage edge and the second scanning enable voltage edge is the enable segment of the i-th scanning signal Scani, and i is a positive integer. It can be understood that the enable segment of the i-th scan signal Scani refers to the stage where the i-th scan signal Scani transmitted by the i-th scan line is an enable signal. In this stage, all transistors on the data write path of all pixel units 10 electrically connected to the i-th scan line are turned on, and the data signal can be written into the pixel driving circuit 11 of the pixel unit 10. On the contrary, when the i-th scan signal Scani transmitted by the i-th scan line is a non-enable signal, the transistors of all pixel units 10 electrically connected to the i-th scan line are turned off. Among them, the enable signal corresponding to the enable segment of the i-th scan signal Scani can be a low-level signal or a high-level signal. The embodiment of the present invention does not specifically limit this and can be set according to actual needs. Correspondingly, the first scan enable voltage edge can be the voltage edge where the i-th scan signal Scani jumps from a non-enable signal to an enable signal, and the second scan enable voltage edge can be the voltage edge where the i-th scan signal Scani jumps from an enable signal to a non-enable signal.

[0046] Exemplarily, the enable signal corresponding to the enable segment of the i-th scanning signal Scani is a low-level signal, and the non-enable signal is a high-level signal. Then, the first scanning enable voltage edge is the falling edge of the i-th scanning signal Scani that jumps from a high-level signal to a low-level signal, and the second scanning enable voltage edge is the rising edge of the i-th scanning signal Scani that jumps from a low-level signal to a high-level signal.

[0047] Continue to refer Figure 2 As shown, the plurality of data lines 30 are configured to transmit data signals to the pixel units 10 arranged in a column along the second direction y. The plurality of data lines 30 include a first data line 31 and a second data line 32, the first data line 31 is electrically connected to the pixel units 10 in the odd rows in a column of pixel units 10, the second data line 32 is electrically connected to the pixel units 10 in the even rows in a column of pixel units 10, and the first direction x intersects with the second direction y. Among them, the pixel units 10 in a column of pixel units 10 arranged in the second direction y in the display panel 100 include the pixel units 10 in the odd rows and the pixel units 10 in the even rows. The first data line 31 is electrically connected to the pixel units 10 in the odd rows in a column of pixel units 10, so that when the scanning signal transmitted by the scanning line 20 drives the pixel units 10 in the odd rows, the pixel units 10 will emit light and display according to the data signal transmitted by the first data line 31. The second data line 32 is electrically connected to the pixel units 10 in the even-numbered rows in a column of pixel units 10, so that when the scan signal transmitted by the scan line 20 drives the pixel units 10 in the even-numbered rows, the pixel units 10 will emit light and display according to the data signal transmitted by the second data line 32. It should be noted that the specific arrangement positions of the first data line 31 and the second data line 32 can be arranged according to actual needs. For example, the first data line 31 and the second data line 32 electrically connected to the same column of pixel units 10 can be located on the same side or both sides of the column of pixel units 10, and the embodiment of the present invention does not specifically limit this. Figure 2 It is shown for exemplary purposes only.

[0048] Continue to refer Figure 2 As shown, the multiplexer 40 includes a plurality of selector output terminals Y and a plurality of selector control terminals C, and the selector output terminals Y are electrically connected to the data line 30. Among them, the selector control terminals C can be 2, 4 or more, and the embodiment of the present invention does not specifically limit this. Under the control of the plurality of selector control terminals C, the multiplexer 40 can select the selector output terminal Y to write a data signal to the data line 30, charge the data line 30, and when the corresponding transistor in the pixel unit 10 electrically connected to the data line 30 is turned on, the data signal on the data line 30 is written into the pixel driving circuit 11 of the pixel unit 10 to drive the light-emitting element 12 of the pixel unit 10 to emit light for display.

[0049] The display panel 100 further includes h control signal lines 50, and the control signal lines 50 are electrically connected to the selector control terminal C. The display panel 100 includes a j-th control signal line 50, and the j-th control signal line is configured to transmit a j-th control signal Muxj, and the j-th control signal Muxj can control the multiplexer 40 to select the selector output terminal Y to write a data signal to the data line 30. The j-th control signal Muxj includes a first control enable voltage edge and a second control enable voltage edge that appear in sequence, and the period between the first control enable voltage edge and the second control enable voltage edge is the enable segment of the j-th control signal Muxj, 1≤j≤h, and j and h are positive integers. It can be understood that the enable segment of the j-th control signal Muxj refers to the stage when the j-th control signal Muxj transmitted by the j-th control signal line is an enable signal. In this stage, the j-th control signal line can select the corresponding selector output terminal Y to write the data signal to the data line 30. On the contrary, when the j-th control signal Muxj transmitted by the j-th control signal line is a non-enable signal, the selector output terminal Y corresponding to the j-th control signal line cannot write the data signal to the data line 30. Among them, the enable signal corresponding to the enable segment of the j-th control signal Muxj can be a low-level signal or a high-level signal. The embodiment of the present invention does not make specific limitations on this and can be set according to actual needs. Correspondingly, the first control enable voltage edge can be the voltage edge at which the j-th control signal Muxj jumps from a non-enable signal to an enable signal, and the second control enable voltage edge can be the voltage edge at which the j-th control signal Muxj jumps from an enable signal to a non-enable signal.

[0050] Exemplarily, the enable signal corresponding to the enable segment of the j-th control signal Muxj is a low-level signal, and the non-enable signal is a high-level signal, then the first control enable voltage edge is the falling edge of the j-th control signal Muxj jumping from a high-level signal to a low-level signal, and the second control enable voltage edge is the rising edge of the j-th control signal Muxj jumping from a low-level signal to a high-level signal.

[0051] Since the power supply line of the power signal PVDD provided for the normal operation of the pixel unit 10 is usually arranged in a grid shape throughout the display panel, it is easily affected by interference from other signal lines, resulting in fluctuations in the power supply signal PVDD. When the fluctuation signal of the power supply signal PVDD overlaps with the enable signals of other signal lines in timing, it is easy to have a coupling effect on other signals, such as coupling effect on the enable signal of the i-th scanning signal Scani transmitted by the i-th scanning line or the enable signal of the j-th control signal Muxj transmitted by the j-th control signal line, thereby affecting the data signal finally written into the pixel unit 10, and further affecting the normal luminous display of the display pixel unit 10.

[0052] Figure 5 A driving timing diagram of an existing display panel provided by an embodiment of the present invention, combined with Figure 2 to Figure 5 As shown, Figure 2 For example, the display panel 100 includes two control signal lines 50. Figure 5 The timing diagram of the first control signal Mux1, the second control signal Mux2, the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, the fourth scan signal Scan4 and the power signal PVDD is shown, and the enable signals corresponding to the enable segment of the j-th control signal Muxj and the enable segment of the i-th scan signal Scani are all low-level signals, and the non-enable signals are all high-level signals. Figure 2 and Figure 5 As shown, for the pixel unit 10 electrically connected to the second scan line 20, its corresponding data writing stage t includes a first stage t1 and a second stage t2. The first stage t1 includes an enabling segment of the second control signal Mux2. Under the control of the second control signal Mux2, the multiplexer 40 can select the data line 30 electrically connected to the second row of pixel units 10 to write data signals to the data line 30 and charge the data line 30. In this way, the first stage t1 can be considered as a data line charging stage. In the second stage t2, including the enabling section of the second scan signal Scan2, all transistors on the data writing path of the pixel driving circuit 11 in the second row of pixel units 10 can be controlled to turn on. At this time, the data signal on the data line 30 continues to be written to the first node N1 in the pixel driving circuit 11 of the pixel unit 10, so that the pixel driving circuit 11 in the pixel unit 10 can drive the light-emitting element 12 to emit light according to the written data signal. In this way, the second stage t2 can be considered as the pixel unit charging stage. It can be understood that charging the pixel unit is to write the data signal to the first node N1 in the pixel driving circuit 11. Since the power supply signal PVDD fluctuates in the second stage t2, it will affect the data signal written into the pixel unit 10 by the data line 30, thereby affecting the normal light-emitting display of the pixel unit 10.

[0053] Based on the same analysis, continue to refer to Figure 5, taking i=3 as an example, for the pixel unit 10 electrically connected to the third scan line 20, in the first stage of the corresponding data writing stage, under the control of the first control signal Mux1, the multiplexer 40 selects the data line 30 electrically connected to the pixel unit 10 in the third row, so as to write the data signal to the data line 30 and charge the data line 30. At this time, due to the fluctuation of the power signal PVDD, the data signal written to the data line 30 will be affected. Further, in the second stage, the third scan signal Scan3 controls the corresponding transistor in the pixel unit 10 in the third row to turn on. At this time, the abnormal data signal on the data line 30 continues to be written into the pixel unit 10, and becomes more abnormal under the coupling influence of the power signal PVDD, so that the pixel unit 10 emits light abnormally, thereby affecting the display effect of the display panel 100. In addition, since the data writing stage of the pixel unit 10 electrically connected to the first scan line 20 does not overlap with the period of fluctuation of the power signal PVDD, it does not affect the normal light emission display of the pixel unit 10 in the first row, and will not be described in detail here.

[0054] Based on this, the embodiment of the present invention is set in the same data writing stage. In the first stage, in the enable segment of the j-th control signal, the data signal is written to the data line. In the second stage, the first scan enable voltage edge of the i-th scan signal is located after the first control enable voltage edge of the j-th control signal, and the data signal on the data line is written to the pixel unit. The second scan enable voltage edge of the i-th scan signal in the m-th data writing stage is located before the second control enable voltage edge of the n-th control signal in the m+1-th data writing stage, |nj|<h, 1≤n≤h, m, n are positive integers.

[0055] For example, Figure 6 A driving timing diagram of a display panel provided by an embodiment of the present invention, such as Figure 6 As shown, taking the display panel 100 including two control signal lines 50 as an example, it can be understood that each row of pixel units 10 is electrically connected to the same scan line 20, so that each row of pixel units 10 corresponds to the same data writing phase t. For ease of understanding and explanation, Figure 6It is shown that the data writing phases t corresponding to the pixel units 10 in the first row to the pixel units 10 in the fourth row can be marked as t_1, t_2, t_3 and t_4, wherein each data writing phase t includes a first phase t1 and a second phase t2, that is, t_1 includes a first phase t1_1 and a second phase t2_1, t_2 includes a first phase t1_2 and a second phase t2_2, t_3 includes a first phase t1_3 and a second phase t2_3, t_4 includes a first phase t1_4 ​​and a second phase t2_4, and so on, the first phase t1_5, etc. The mth data writing phase t_m corresponding to the pixel units 10 in the mth row includes a first phase t1_m and a second phase t2_m, m=1, 2, 3...

[0056] Specifically, in the same data writing phase t, in the first phase t1, in the enabling segment of the jth control signal Muxj, that is, the low level signal period of the jth control signal Muxj, the jth control signal Muxj controls the multiplexer 40 to select the corresponding data line 30, so that the data line 30 is written with the data signal, and the data line 30 is charged. In the second phase t2, the first scanning enable voltage edge of the i-th scanning signal Scani is located after the first control enable voltage edge of the j-th control signal Muxj, that is, the falling edge of the i-th scanning signal Scani jumping from a high level signal to a low level signal is located after the falling edge of the j-th control signal Muxj jumping from a high level signal to a low level signal, and the data signal on the data line 30 is written into the pixel unit 10, so that the pixel unit 10 performs light-emitting display. It should be noted that the first scanning enable voltage edge of the i-th scanning signal Scani can be located at any time after the first control enable voltage edge of the j-th control signal Muxj, and the embodiment of the present invention does not specifically limit this, and can be set according to actual needs. Figure 6 It is only shown for exemplary purposes. In other embodiments, the first scan enable voltage edge of the i-th scan signal Scani and the second control enable voltage edge of the j-th control signal Muxj may be at the same time. In this way, the data line 30 is charged first, and then the pixel unit 10 is charged, so as to ensure the normal display of the display panel.

[0057] For further information, please refer to Figure 6 As shown, the second scan enable voltage edge of the ith scan signal Scani in the mth data writing phase t_m is located before the second control enable voltage edge of the nth control signal Muxn in the m+1th data writing phase t_m+1, |nj|<h, 1≤n≤h, m and n are positive integers.

[0058] For example, m=2, i=2, n=1, the rising edge of the second scanning signal Scan2 in the second data writing stage t_2 jumping from a low level signal to a high level signal is located before the second control enable voltage edge of the rising edge of the first control signal Mux1 jumping from a low level signal to a high level signal in the third data writing stage t_3. In this way, in the stage where the power signal PVDD fluctuates, the overlapping time of the fluctuation signal of the power signal PVDD and the enable segment of the i-th scanning signal Scani in timing is reduced, thereby reducing the impact on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and thereby improving the display effect of the display panel 100.

[0059] It should be noted that the enabling segments of the scan signals Scan corresponding to all the scan lines 20 in the display panel 100 may have the same width or different widths, which is not specifically limited in the embodiment of the present invention and may be set according to actual needs. Figure 6 This is shown for exemplary purposes only and is not intended to be limiting.

[0060] In addition, unless otherwise specified, to facilitate the description of the scheme, the following embodiments are described by taking the enable signal corresponding to the enable segment of the i-th scan signal Scani as a low-level signal and the enable signal corresponding to the enable segment of the j-th control signal Muxj as a low-level signal as an example.

[0061] In summary, in an embodiment of the present invention, a display panel is provided to include a plurality of pixel units, a plurality of scan lines, a plurality of data lines, a multiplexer, and h control signal lines, wherein the i-th scan line among the plurality of scan lines is configured to transmit the i-th scan signal to the pixel units arranged in a row along a first direction, and within the enabling section of the i-th scan signal, the i-th scan signal can control all transistors on the data writing path of all pixel units electrically connected to the scan line to turn on, so as to write data signals to the transistors driving the light-emitting elements in the pixel units to emit light. The first data line among the plurality of data lines is electrically connected to the pixel units in odd rows in a column of pixel units, and the second data line is electrically connected to the pixel units in even rows in a column of pixel units, so that the first data line writes data signals to the pixel units in odd rows, and the second data line writes data signals to the pixel units in even rows. The selector output end of the multiplexer is electrically connected to the data line, and the control signal line is electrically connected to the selector control end, so that the j-th control signal line is configured to transmit the j-th control signal to select the multiplexer to write data signals to the data line. Thus, in the same data writing phase of the display panel, in the first phase, in the enable segment of the jth control signal, the data signal is written to the data line to charge the data line. In the second phase, the first scanning enable voltage edge of the i-th scanning signal is located after the first control enable voltage edge of the j-th control signal, and the data signal on the data line is written to the pixel unit, so that the pixel unit can emit light and display according to the written data signal. The second scanning enable voltage edge of the i-th scanning signal in the m-th data writing phase is located before the second control enable voltage edge of the n-th control signal in the m+1-th data writing phase, |nj|<h, 1≤n≤h, m, n are positive integers, so that in the phase where the power signal PVDD fluctuates, the overlapping time of the fluctuation signal of the power signal PVDD and the enable segment of the i-th scanning signal in timing is reduced, thereby reducing the influence on the data signal written into the pixel unit, ensuring the normal light-emitting display of the pixel unit, so as to solve the problem of black lines or bright lines appearing at the junction of black and white screens of the display device, thereby improving the display effect of the display panel.

[0062] Optional, Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Figure 8 Another driving timing diagram of a display panel provided by an embodiment of the present invention, combined with Figure 7 and Figure 8 As shown, in the first stage t1, in the enable segment of the j+1th control signal Mux(j+1), the data signal is also written to the data line 30. In the second stage t2, the first scan enable voltage edge of the i-th scan signal Scani is located after the first control enable voltage edge of the j+1th control signal Mux(j+1).

[0063] Specifically, the display panel 100 includes four control signal lines 50. Figure 7 It is shown that in the enabling section of the first control signal Mux1 and the enabling section of the second control signal Mux2 in the first stage t1, or in the enabling section of the third control signal Mux3 and the enabling section of the fourth control signal Mux4 in the first stage t1, a data signal can be written to the data line 30 electrically connected to the pixel unit 10 in the same row, and the data line 30 can be charged. Among them, one of the first control signal Mux1 and the second control signal Mux2 can control the multiplexer 40 to select the writing of the data signal to the first data line 31 of the data line 30, and the other control signal can be used to control the multiplexer 40 to select the writing of the data signal to the second data line 32 of the data line 30. Similarly, one of the third control signal Mux3 and the fourth control signal Mux4 can be used to control the multiplexer 40 to select the writing of the data signal to the first data line 31 of the data line 30, and the other control signal can be used to control the multiplexer 40 to select the writing of the data signal to the second data line 32 of the data line 30.

[0064] Exemplarily, taking the pixel units 10 in the same row electrically connected to the second scan line as an example, in the first stage t1 (i.e., the first stage t1_2), in the enable segment of the third control signal Mux3 and the enable segment of the fourth control signal Mux4, the multiplexer 40 can select the corresponding data line 30 to write the data signal to the data line 30. In the second stage t2, the falling edge of the second scan signal Scan2 jumping from a high level signal to a low level signal is located after the falling edge of the fourth control signal Mux4 jumping from a high level signal to a low level signal. In this way, after charging at least part of the data line 30, the data signal on the data line 30 is written into the pixel unit 10, and the pixel unit 10 is charged to ensure the normal display of the pixel unit 10 and improve the display effect of the display panel.

[0065] Optional, continue to refer to Figure 8 As shown, in the data writing phase t of the pixel unit 10 in the 2k+1th row, the enable segment of the first control signal Mux1 and the enable segment of the second control signal Mux2 write the data signal to the first data line 31, where k is a positive integer. In the data writing phase t of the pixel unit 10 in the 2kth row, the enable segment of the third control signal Mux3 and the enable segment of the fourth control signal Mux4 write the data signal to the second data line 32. The second scan enable voltage edge of the 2k+1th scan signal Scan(2k+1) in the mth data writing phase t_m is located before the second control enable voltage edge of the fourth control signal in the m+1th data writing phase t_m+1.

[0066] Specifically, the first control signal Mux1 and the second control signal Mux2 control the multiplexer 40 to select the first data line 31, so that the data signal is written to the first data line 31. Figure 2 As shown, the first data line 31 is electrically connected to the pixel units 10 in the odd rows in a column of pixel units 10, so that the enable segment of the first control signal Mux1 and the enable segment of the second control signal Mux2 in the data writing phase t of the pixel units 10 in the odd rows write the data signal to the first data line 31. The third control signal Mux3 and the fourth control signal Mux4 control the multiplexer 40 to select the second data line 32, so that the data signal is written to the second data line 32, and the second data line 32 is electrically connected to the pixel units 10 in the even rows in a column of pixel units 10, and the enable segment of the third control signal Mux3 and the enable segment of the fourth control signal Mux4 in the data writing phase t of the pixel units 10 in the even rows write the data signal to the second data line 32.

[0067] Continue to refer Figure 8 , taking m=3, k=1, i.e. the third scan signal Scan3 in the third data writing stage t_3 as an example, the rising edge of the third scan signal Scan3 jumping from a low level to a high level is located before the rising edge of the fourth control signal Mux4 jumping from a low level to a high level in the fourth data writing stage t_4. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the third scan signal Scan3 in timing is reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0068] It should be noted that the enable segment of the scan signal Scan(2k) corresponding to the pixel unit 10 in the 2kth row and the enable segment of the scan signal Scan(2k+1) corresponding to the pixel unit 10 in the 2k+1th row can have the same width or different widths. The embodiment of the present invention does not make any specific limitation on this and can be set according to actual needs. Figure 8 This is only for illustrative purposes. Unless otherwise specified, all scanning signals in the following embodiments are illustrated as having the same width.

[0069] Optional, Fig. 9 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig. 9 As shown, the second scan enable voltage edge of the 2k+1th scan signal Scan(2k+1) in the mth data writing phase t_m is located before the first control enable voltage edge of the fourth control signal Mux4 in the m+1th data writing phase t_m+1.

[0070] For example, taking m=3, k=1, i.e. the third scan signal Scan3 in the third data writing stage t_3 as an example, the rising edge of the third scan signal Scan3 jumping from a low level to a high level is located before the falling edge of the fourth control signal Mux4 jumping from a high level to a low level in the fourth data writing stage t_4. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the third scan signal Scan3 in timing can be reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0071] Optional, Fig.10 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig.10 As shown, the second scan enable voltage edge of the 2k+1th scan signal Scan(2k+1) in the mth data writing phase t_m is located before the second control enable voltage edge of the third control signal Mux3 in the m+1th data writing phase t_m+1.

[0072] For example, taking the third scan signal Scan3 in the third data writing stage t_3 as an example, the rising edge of the third scan signal Scan3 jumping from a low level to a high level is located before the rising edge of the third control signal Mux3 jumping from a low level to a high level in the fourth data writing stage t_4. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the third scan signal Scan3 in timing can be reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0073] Optional, Fig.11 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig.11 As shown, the second scan enable voltage edge of the 2k+1th scan signal Scan(2k+1) in the mth data writing phase t_m is located before the first control enable voltage edge of the third control signal Mux3 in the m+1th data writing phase t_m+1.

[0074] For example, taking m=3, k=1, i.e. the third scan signal Scan3 in the third data writing stage t_3 as an example, the rising edge of the third scan signal Scan3 jumping from a low level to a high level is located before the falling edge of the third control signal Mux3 jumping from a high level to a low level in the fourth data writing stage t_4. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the third scan signal Scan3 in timing can be reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0075] Optional, Fig.12 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig.12 As shown, the second scan enable voltage edge of the 2kth scan signal Scan(2k) in the mth data writing phase t_m is located before the first control enable voltage edge of the second control signal Mux2 in the m+1th data writing phase t_m+1.

[0076] For example, taking m=2, k=1, i.e. the second scan signal Scan2 in the second data writing stage t_2 as an example, the rising edge of the second scan signal Scan2 jumping from a low level to a high level is located before the falling edge of the second control signal Mux2 jumping from a high level to a low level in the third data writing stage t_3. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the second scan signal Scan2 in timing can be reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0077] It should be noted that, in this embodiment, the enable segment of the 2kth scan signal Scan(2k) and the enable segment of the 2k+1th scan signal Scan(2k+1) may have the same width or different widths, which is not specifically limited in the embodiment of the present invention and may be set according to actual needs. Fig.12 This is shown for exemplary purposes only and is not intended to be limiting.

[0078] Optional, Fig.13 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig.11 As shown, the second scan enable voltage edge of the 2kth scan signal Scan(2k) in the mth data writing phase t_m is located before the second control enable voltage edge of the first control signal Mux1 in the m+1th data writing phase t_m+1.

[0079] For example, taking m=2, k=1, i.e. the second scan signal Scan2 in the second data writing stage t_2 as an example, the rising edge of the second scan signal Scan2 jumping from a low level to a high level is located before the rising edge of the first control signal Mux1 jumping from a low level to a high level in the third data writing stage t_3. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the second scan signal Scan2 in timing can be reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0080] Optional, Fig.14 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig.14 As shown, the second scan enable voltage edge of the 2kth scan signal Scan(2k) in the mth data writing phase t_m is located before the first control enable voltage edge of the first control signal Mux1 in the m+1th data writing phase t_m+1.

[0081] For example, taking m=2, k=1, i.e. the second scanning signal Scan2 in the second data writing stage t_2 as an example, the rising edge of the second scanning signal Scan2 jumping from a low level to a high level is located before the falling edge of the first control signal Mux1 jumping from a high level to a low level in the third data writing stage t_3. In this way, there is no overlap in timing between the fluctuation signal of the power signal PVDD and the enabling segment of the second scanning signal Scan2, thereby avoiding the influence of the fluctuation signal of the power signal PVDD on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0082] Optional, continue to refer to Figure 8 to Figure 14 As shown, the second scan enable voltage edge of the 2k-1th scan signal Scan(2k-1) in the mth data writing phase t_m is located before the first control enable voltage edge of the first control signal Mux1 in the m+2th data writing phase t_m+2.

[0083] Specifically, in the mth data writing phase t_m, the enable signal of the 2k-1th scan signal Scan(2k-1) transmitted by the 2k-1th scan line can control the transistor corresponding to the 2k-1th row of pixel units 10 to turn on, so as to write the data signal to the 2k-1th row of pixel units 10. In the m+2th data writing phase t_m+2, the enable segment of the first control signal Mux1 and the enable segment of the second control signal Mux2 will write the data signal to the first data line 31, and charge the first data line 31, that is, charge the first data line 31 electrically connected to the 2k+1th row of pixel units 10. In this way, the second scan enable voltage edge of the 2k-1th scan signal Scan(2k-1) in the mth data writing stage t_m is set before the first control enable voltage edge of the first control signal Mux1 in the m+2th data writing stage t_m+2, so that along the second direction y of the display panel 100, the multiple scan lines 20 electrically connected to the pixel units 10 of the odd rows are scanned row by row, and the data lines 30 electrically connected to the pixel units 10 of the next odd row are charged only after the pixel units 10 of the previous odd row are completely charged, so as to realize the row-by-row light display of the pixel units 10 of the odd rows in the display panel 100.

[0084] Exemplarily, taking m=1, k=1, i.e. the first scan signal Scan1 in the first data writing phase t_1 as an example, the rising edge of the first scan signal Scan1 jumping from a low level to a high level is before the falling edge of the first control signal Mux1 jumping from a high level to a low level in the third data writing phase t_3.

[0085] Optionally, the first scan enable voltage edge of the 2k+2 th scan signal Scan(2k+2) in the m th data writing phase t_m is located after the second control enable voltage edge of the fourth control signal Mux4 in the m th data writing phase t_m.

[0086] Specifically, in the enable segment of the fourth control signal Mux4 in the mth data writing phase t_m, the data signal is written to the second data line 32, that is, the second data line 32 electrically connected to the 2kth row of pixel units 10 is charged. The enable signal of the 2k+2th scan signal Scan(2k+2) transmitted by the 2k+2th scan line in the mth data writing phase t_m can control the transistor corresponding to the 2k+2th row of pixel units 10 to turn on, so as to write the data signal to the 2k+2th row of pixel units 10. In this way, the first scan enable voltage edge of the 2k+2 scan signal Scan(2k+2) in the mth data writing stage t_m is set to be located after the second control enable voltage edge of the fourth control signal Mux4 in the mth data writing stage t_m, which can reduce the timing overlap time of the fluctuation signal of the power supply signal PVDD and the enable segment of the 2k+2 scan signal Scan(2k+2), thereby reducing the impact on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0087] In other embodiments, optionally, reference Figure 6 As shown, in the data writing phase t of the 2k+1th row of pixel units 10, the data signal is written to the first data line 31 by the enable segment of the first control signal Mux1, where k is a positive integer. In the data writing phase t of the 2kth row of pixel units 10, the data signal is written to the second data line 32 by the enable segment of the second control signal Mux2. The second scan enable voltage edge of the 2k+1th scan signal Scan(2k+1) in the mth data writing phase t_m is located before the second control enable voltage edge of the second control signal Mux2 in the m+1th data writing phase t_m+1.

[0088] refer to Figure 2 The display panel 100 includes a control signal line 50. In the enable segment of the first control signal Mux1 in the data writing phase t, a data signal can be written to the first data line 31 electrically connected to the odd-numbered pixel unit 10. In the enable segment of the second control signal Mux2 in the data writing phase t, a data signal can be written to the second data line 32 electrically connected to the even-numbered pixel unit 10.

[0089] For example, taking m=3, k=1, i.e. the third scan signal Scan3 in the third data writing stage t_3 as an example, the rising edge of the third scan signal Scan3 jumping from a low level to a high level is located before the rising edge of the second control signal Mux2 jumping from a low level to a high level in the fourth data writing stage t_4. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the third scan signal Scan3 in timing is reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0090] Optional, Fig.15 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig.15 As shown, the second scan enable voltage edge of the 2k+1th scan signal Scan(2k+1) in the mth data writing phase t_m is located before the first control enable voltage edge of the second control signal Mux2 in the m+1th data writing phase t_m+1.

[0091] For example, taking m=3, k=1, i.e. the third scan signal Scan3 in the third data writing stage t_3 as an example, the rising edge of the third scan signal Scan3 jumping from a low level to a high level is located before the falling edge of the second control signal Mux2 jumping from a high level to a low level in the fourth data writing stage t_4. In this way, the overlapping time of the fluctuation signal of the power supply signal PVDD and the enabling segment of the third scan signal Scan3 in timing can be reduced, thereby reducing the influence on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0092] It should be noted that the enable segment of the 2k+1th scan signal Scan(2k+1) and the enable segment of the 2kth scan signal Scan(2k) may have the same width or different widths. The embodiment of the present invention does not make any specific limitation on this and may be set according to actual needs. Fig.15 It is shown for exemplary purposes only.

[0093] Optional, Fig.16 Another driving timing diagram of a display panel provided by an embodiment of the present invention is as follows: Fig.16 As shown, the second scan enable voltage edge of the 2kth scan signal in the mth data writing phase t_m is located before the first control enable voltage edge of the first control signal Mux1 in the m+1th data writing phase t_m+1.

[0094] For example, taking m=2, k=1, i.e. the second scanning signal Scan2 in the second data writing stage t_2 as an example, the rising edge of the second scanning signal Scan2 jumping from a low level to a high level is located before the falling edge of the first control signal Mux1 jumping from a high level to a low level in the third data writing stage t_3. In this way, there is no overlap in timing between the fluctuation signal of the power signal PVDD and the enabling segment of the second scanning signal Scan2, thereby avoiding the influence of the fluctuation signal of the power signal PVDD on the data signal written into the pixel unit 10, ensuring the normal light-emitting display of the pixel unit 10, and improving the display effect of the display panel 100.

[0095] Based on any of the above embodiments, optionally, all scanning signals have enable segments of the same width. In this way, the corresponding transistors in all pixel units 10 in the display panel 100 are turned on for the same length of time, that is, the data signals are written to the pixel units 10 at the same time, which can ensure the same display effect of the pixel units 10 and improve the display quality of the display panel 100.

[0096] Optional, Fig.17 A partial structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Fig.17 As shown, the display panel 100 also includes a source signal line 60, the multiplexer 40 includes h switching transistors T, the first electrodes of the h switching transistors T are all connected to the same source signal line 60, the second electrodes of the switching transistors T are connected to a first data line 31 or a second data line 32, and the gates of the h switching transistors T are electrically connected to h control signal lines 50 one by one.

[0097] Here, h can be any value, which is not specifically limited in the embodiment of the present invention. Fig.17 The display panel 100 is exemplarily shown to include 4 control signal lines 50 and h switching transistors T, the 4 control signal lines 50 are respectively a first control signal line MUX1, a second control signal line MUX2, a third control signal line MUX3 and a fourth control signal line MUX4, wherein the h switching transistors T include at least a first switching transistor T1, a second switching transistor T2, a third switching transistor T3 and a fourth switching transistor T4.

[0098] Specifically, the switch transistor T may be an N-channel transistor or a P-channel transistor, which is not specifically limited in the embodiment of the present invention and may be set according to actual needs. Fig.17The structural schematic diagram of the switching transistor T being a P-channel transistor is exemplarily shown. In this way, when the control signal Mux transmitted by the control signal line 50 is a low-level signal, the switching transistor T electrically connected to the control signal line 50 can be controlled to be turned on, and when the control signal Mux transmitted by the control signal line 50 is a high-level signal, the switching transistor T electrically connected to the control signal line 50 can be controlled to be turned off.

[0099] Optional, continue to refer to Fig.17 As shown, the h switch transistors T include a first switch transistor T1, a second switch transistor T2, a third switch transistor T3 and a fourth switch transistor T4; the second electrode of the first switch transistor T1 and the second electrode of the second switch transistor T2 are respectively connected to the two first data lines 31, and the second electrode of the third switch transistor T3 and the second electrode of the fourth switch transistor T4 are respectively connected to the two second data lines 32.

[0100] Specifically, the first control signal line MUX1 is electrically connected to the gate of the first switch transistor T1, the second control signal line MUX2 is electrically connected to the gate of the fourth switch transistor T4, the third control signal line MUX3 is electrically connected to the gate of the third switch transistor T3, and the fourth control signal line MUX4 is electrically connected to the gate of the second switch transistor T2. In this way, the first switch transistor T1 and the fourth switch transistor T4 can be controlled to be turned on during the enable section of the first control signal Mux1 transmitted by the first control signal line MUX1 and the enable section of the second control signal Mux2 transmitted by the second control signal line MUX2, so that the data signal provided by the source signal line 60 is written to the first data line 31 and the second data line 32. Similarly, the second switch transistor T2 and the third switch transistor T3 can be controlled to be turned on during the enable section of the third control signal Mux3 transmitted by the third control signal line MUX3 and the enable section of the fourth control signal Mux4 transmitted by the fourth control signal line MUX4, so that the data signal provided by the source signal line 60 is written to the first data line 31 and the second data line 32.

[0101] In an optional embodiment, the plurality of data lines 30 are arranged along the first direction x. Along the first direction x, two adjacent columns of pixel units 10 are spaced apart by two first data lines 31 or two second data lines 32 .

[0102] For details, please refer to Figure 2 , Figure 7 or Fig.17As shown, along the first direction x, two adjacent columns of pixel units 10 are separated by two first data lines 31 or two second data lines 32, that is, the first data lines 31 and the second data lines 32 electrically connected to the pixel units 10 in the same column are respectively located on both sides of the pixel units 10 in the column, and the first data lines 31 or the second data lines 32 electrically connected to each column of pixel units 10 are all located on the same side of the pixel unit 10.

[0103] In another alternative implementation, Fig.18 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.18 As shown, a plurality of data lines 30 are arranged along a first direction x. Along the first direction x, a first data line 31 and a second data line 32 are spaced between two adjacent columns of pixel units 10 . Fig.18 This is shown for exemplary purposes only and is not intended to be limiting.

[0104] Optional, Fig.19 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.19 As shown, a plurality of pixel units 10 are arranged in an array along a first direction x and a second direction y, including a first pixel column 01 and a second pixel column 02. Along the first direction x, one second pixel column 02 is spaced between two first pixel columns 01, and one first pixel column 01 is spaced between two second pixel columns 02. The first pixel column 01 includes first pixel units 101 and second pixel units 102 spaced one by one along the second direction y, and the second pixel column 02 includes a third pixel unit 103 arranged along the second direction y, and any two of the first pixel unit 101, the second pixel unit 102 and the third pixel unit 103 have different luminous colors.

[0105] The luminous colors of the first pixel unit 101, the second pixel unit 102, and the third pixel unit 103 include, but are not limited to, red, green, blue, yellow, white, cyan, or magenta, etc., which are not specifically limited in the embodiment of the present invention. For example, the luminous color of the first pixel unit 101 is red, the luminous color of the second pixel unit 102 is blue, and the luminous color of the third pixel unit 103 is green.

[0106] Optional, Fig. 20 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig. 20 As shown, the display panel 100 also includes a gate driving circuit 70, the gate driving circuit 70 includes a first sub-driving circuit 71 and a second sub-driving circuit 72, the first sub-driving circuit 71 and the second sub-driving circuit 72 each include a plurality of cascaded shift registers 700, at least some of the shift registers 700 are electrically connected to the scan line 20, and are configured to provide a scan signal to the scan line 20.

[0107] Among them, the first sub-driving circuit 71 and the second sub-driving circuit 72 can be located on both sides of the multiple pixel units 10 arranged in an array, that is, both are located on the same side of the multiple pixel units 10. The embodiment of the present invention is not limited to this and can be set according to actual needs.

[0108] For example, Fig. 20 The multiple cascaded shift registers 700 in the first sub-driving circuit 71 are electrically connected to the first ends of some scan lines 20 to provide scan signals to the scan lines 20, and the multiple cascaded shift registers 700 in the second sub-driving circuit 72 are electrically connected to the first ends of the remaining scan lines 20 to provide scan signals to the scan lines 20. Fig. 20 In the same sub-driving circuit, the signal input end of the first-stage shift register 700 receives the start pulse signal transmitted by the first start signal line STV1 or the second start signal line STV2. Except for the first-stage shift register 700, the signal input end of each stage of the shift register 700 is electrically connected to the signal output end of the previous stage of the shift register 700, and the enable signal of the scan signal output by the signal output end of each stage of the shift register 700 is shifted in sequence. It should be noted that the first start signal line STV1 electrically connected to the first sub-driving circuit 71 and the second start signal line STV2 electrically connected to the second sub-driving circuit 72 can be the same start signal line or different start signal lines, and the embodiment of the present invention does not specifically limit this.

[0109] Optional, continue to refer to Fig. 20 As shown, the shift register 700 in the first sub-driving circuit 71 is recorded as the first shift register 701, and the shift register 700 in the second sub-driving circuit 72 is recorded as the second shift register 702. Along the second direction y, there is a second shift register 702 between two adjacent first shift registers 701, and there is a first shift register 701 between two adjacent second shift registers 702. The first shift register 701 is electrically connected to the 2k-1th scanning line 20, and the second shift register 702 is electrically connected to the 2kth scanning line 20, where k is a positive integer.

[0110] Specifically, the first shift register 701 is electrically connected to the scan line 20 electrically connected to the odd-numbered row pixel unit 10, so that the output end of the first-stage first shift register 701 in the first sub-driving circuit 71 is electrically connected to the input end of the third-stage first shift register 701, the output end of the third-stage first shift register 701 is electrically connected to the input end of the fifth-stage first shift register 701, and so on. The second shift register 702 is electrically connected to the scan line 20 electrically connected to the even-numbered row pixel unit 10, so that the output end of the first-stage second shift register 702 in the second sub-driving circuit 72 is electrically connected to the input end of the fourth-stage second shift register 702, the output end of the fourth-stage second shift register 702 is electrically connected to the input end of the sixth-stage second shift register 702, and so on.

[0111] Therefore, on the basis of any of the above embodiments, according to the different widths of the enable signals of the scan signals respectively transmitted by the 2k-1 scan line 20 and the 2k scan line 20, the start time and end time of the output signals of the first shift register 701 in the first sub-driving circuit 71 and the second shift register 702 in the second sub-driving circuit 72 are respectively different, so that each level of shift register 700 starts to output the enable signal of the scan signal in turn, and stops outputting the enable signal of the scan signal in turn.

[0112] In another alternative embodiment, Fig.21 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.21 As shown, the shift register 700 in the first sub-driving circuit 71 is recorded as the first shift register 701, and the shift register 700 in the second sub-driving circuit 72 is recorded as the second shift register 702. The first sub-driving circuit 71 and the second sub-driving circuit 72 are arranged along the first direction x, the first shift register 701 in the first sub-driving circuit 71 is arranged along the second direction y, and the second shift register 702 in the second sub-driving circuit 72 is arranged along the second direction y. The i-th first shift register 701 is electrically connected to the i-th scanning line 20, or the i-th second shift register 702 is electrically connected to the i-th scanning line.

[0113] For example, Fig.21It is shown that multiple cascaded first shift registers 701 in the first sub-driving circuit 71 are electrically connected to the first end of the 2k-1th scan line 20, respectively, and multiple cascaded second shift registers 702 in the second sub-driving circuit 72 are electrically connected to the second end of the 2kth scan line 20, respectively, so as to realize that the multiple cascaded first shift registers 701 in the first sub-driving circuit 71 provide the 2k-1th scan signal to the 2k-1th scan line step by step, and the multiple cascaded second shift registers 702 in the second sub-driving circuit 72 provide the 2kth scan signal to the 2kth scan line step by step. The width of the enable segment of the 2k-1th scan signal may be the same as or different from the width of the enable segment of the 2kth scan signal. The embodiment of the present invention does not make any specific limitation on this and can be set according to actual needs.

[0114] In addition, an embodiment of the present invention further provides a display device, Fig. 22 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig. 22 As shown, the display device 200 includes the display panel 100 provided by any embodiment of the present invention. Therefore, the display device 200 provided by the embodiment of the present invention includes the technical features of the display panel 100 provided by the embodiment of the present invention, and can achieve the beneficial effects of the display panel 100 provided by the embodiment of the present invention. The similarities can refer to the above description of the display panel 100 provided by the embodiment of the present invention, which will not be repeated here. The display device 200 provided by the embodiment of the present invention can be a mobile phone, or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0115] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A plurality of pixel units; A plurality of scan lines, including an i-th scan line, wherein the i-th scan line is configured to transmit an i-th scan signal to the pixel units arranged in a row along a first direction; the i-th scan signal includes a first scan enable voltage edge and a second scan enable voltage edge that appear in sequence, and a period between the first scan enable voltage edge and the second scan enable voltage edge is an enable segment of the i-th scan signal; i is a positive integer; a plurality of data lines configured to transmit data signals to the pixel units arranged in a column along a second direction, including a first data line and a second data line, the first data line being electrically connected to the pixel units in odd rows in a column of the pixel units, the second data line being electrically connected to the pixel units in even rows in a column of the pixel units, the first direction intersecting the second direction; A multiplexer, comprising a plurality of selector output terminals and a plurality of selector control terminals, wherein the selector output terminals are electrically connected to the data lines; h control signal lines, the control signal lines are electrically connected to the selector control end, including a j-th control signal line, the j-th control signal line is configured to transmit a j-th control signal; the j-th control signal includes a first control enable voltage edge and a second control enable voltage edge that appear in sequence, and a period between the first control enable voltage edge and the second control enable voltage edge is an enable period of the j-th control signal; 1≤j≤h, j and h are positive integers; The driving timing of the display panel includes a data writing phase, and the data writing phase includes a first phase and a second phase; In the same data writing phase, in the first phase, in the enable segment of the j-th control signal, the data signal is written to the data line, and in the second phase, the first scan enable voltage edge of the i-th scan signal is located after the first control enable voltage edge of the j-th control signal, and the data signal on the data line is written to the pixel unit; The second scan enable voltage edge of the i-th scan signal in the m-th data writing phase is located before the second control enable voltage edge of the n-th control signal in the m+1-th data writing phase, |nj|<h, 1≤n≤h, m and n are positive integers; In the first stage, in the enable segment of the j+1th control signal, the data signal is also written to the data line, and in the second stage, the first scan enable voltage edge of the i-th scan signal is located after the first control enable voltage edge of the j+1th control signal; In the data writing phase of the pixel unit in the 2k+1th row, the data signal is written to the first data line during the enabling segment of the first control signal and the enabling segment of the second control signal; k is a positive integer; Writing the data signal to the second data line during the data writing phase of the pixel units in the 2kth row by the enable segment of the third control signal and the enable segment of the fourth control signal; The second scan enable voltage edge of the 2k+1th scan signal in the mth data writing phase is located before the second control enable voltage edge of the fourth control signal in the m+1th data writing phase; The second scan enable voltage edge of the 2k+1th scan signal in the mth data writing stage is located before the first control enable voltage edge of the fourth control signal in the m+1th data writing stage, or the second scan enable voltage edge of the 2kth scan signal in the mth data writing stage is located before the first control enable voltage edge of the second control signal in the m+1th data writing stage.

2. The display panel according to claim 1, characterized in that: The second scan enable voltage edge of the 2k+1th scan signal in the mth data writing phase is located before the second control enable voltage edge of the third control signal in the m+1th data writing phase.

3. The display panel according to claim 1, characterized in that: The second scan enable voltage edge of the 2k+1th scan signal in the mth data writing phase is located before the first control enable voltage edge of the third control signal in the m+1th data writing phase.

4. The display panel according to claim 1, characterized in that: The second scan enable voltage edge of the 2kth scan signal in the mth data writing phase is located before the second control enable voltage edge of the first control signal in the (m+1)th data writing phase.

5. The display panel according to claim 1, characterized in that: The second scan enable voltage edge of the 2kth scan signal in the mth data writing phase is located before the first control enable voltage edge of the first control signal in the (m+1)th data writing phase.

6. The display panel according to claim 1, characterized in that: The second scan enable voltage edge of the 2k-1th scan signal in the mth data writing phase is located before the first control enable voltage edge of the first control signal in the m+2th data writing phase.

7. The display panel according to claim 1, characterized in that: The first scan enable voltage edge of the 2k+2th scan signal in the mth data writing phase is located after the second control enable voltage edge of the fourth control signal in the mth data writing phase.

8. The display panel according to claim 1, characterized in that: In the enabling section of the first control signal in the data writing phase of the pixel unit in the 2k+1th row, the data signal is written to the first data line; k is a positive integer; Writing the data signal to the second data line during the enabling section of the second control signal in the data writing phase of the 2k-th row of pixel units; The second scan enable voltage edge of the 2k+1th scan signal in the mth data writing phase is located before the second control enable voltage edge of the second control signal in the m+1th data writing phase.

9. The display panel according to claim 8, characterized in that: The second scan enable voltage edge of the 2k+1th scan signal in the mth data writing phase is located before the first control enable voltage edge of the second control signal in the m+1th data writing phase.

10. The display panel according to claim 8, characterized in that: The second scan enable voltage edge of the 2kth scan signal in the mth data writing phase is located before the first control enable voltage edge of the first control signal in the (m+1)th data writing phase.

11. The display panel according to claim 1, characterized in that: All scan signals have enable segments of the same width.

12. The display panel according to claim 1, characterized in that: Also includes source signal lines; The multiplexer comprises h switch transistors, and the first electrodes of the h switch transistors are all connected to the same source signal line; The second electrode of the switch transistor is connected to one of the first data lines or one of the second data lines; The gates of the h switch transistors are electrically connected to the h control signal lines in a one-to-one correspondence.

13. The display panel according to claim 12, characterized in that: The h switching transistors include a first switching transistor, a second switching transistor, a third switching transistor and a fourth switching transistor; A second electrode of the first switch transistor and a second electrode of the second switch transistor are respectively connected to the two first data lines, and a second electrode of the third switch transistor and a second electrode of the fourth switch transistor are respectively connected to the two second data lines.

14. The display panel according to claim 1, characterized in that: A plurality of the data lines are arranged along the first direction; Along the first direction, two adjacent columns of the pixel units are spaced apart by two first data lines or two second data lines.

15. The display panel according to claim 1, characterized in that: A plurality of the data lines are arranged along the first direction; Along the first direction, there is one first data line and one second data line between two adjacent columns of the pixel units.

16. The display panel according to claim 1, characterized in that: The plurality of pixel units are arranged in an array along the first direction and the second direction, including a first pixel column and a second pixel column; Along the first direction, two of the first pixel columns are spaced apart by one of the second pixel columns, and two of the second pixel columns are spaced apart by one of the first pixel columns; The first pixel column includes first pixel units and second pixel units arranged one by one in the second direction, and the second pixel column includes third pixel units arranged along the second direction; Any two of the first pixel unit, the second pixel unit and the third pixel unit have different luminous colors.

17. The display panel according to claim 1, characterized in that: It also includes a gate driving circuit, which includes a first sub-driving circuit and a second sub-driving circuit, and the first sub-driving circuit and the second sub-driving circuit each include a plurality of cascaded shift registers, at least some of the shift registers are electrically connected to the scan line and are configured to provide a scan signal to the scan line.

18. The display panel according to claim 17, characterized in that: The shift register in the first sub-driving circuit is recorded as a first shift register, and the shift register in the second sub-driving circuit is recorded as a second shift register; Along the second direction, there is one second shift register between two adjacent first shift registers, and there is one first shift register between two adjacent second shift registers; The first shift register is electrically connected to the 2k-1th scan line, and the second shift register is electrically connected to the 2kth scan line, where k is a positive integer.

19. The display panel according to claim 17, characterized in that: The shift register in the first sub-driving circuit is recorded as a first shift register, and the shift register in the second sub-driving circuit is recorded as a second shift register; The first sub-driving circuit and the second sub-driving circuit are arranged along the first direction, the first shift register in the first sub-driving circuit is arranged along the second direction, and the second shift register in the second sub-driving circuit is arranged along the second direction; The i-th stage first shift register is electrically connected to the i-th scan line, or the i-th stage second shift register is electrically connected to the i-th scan line.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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