Pixel circuit, driving method thereof and display panel

Abstract

Embodiments of the present application disclose a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a current control module, a time control module and a voltage compensation module. The current control module comprises a first data writing end, a driving current output end and a first control end. The current control module is configured to write an amplitude data signal to the first control end. The time control module comprises a second data writing end, a time output end and a second control end. The time control module is configured to write a time data signal to the second control end. The voltage compensation module comprises a compensation input end and a compensation output end. The compensation input end is electrically connected with a compensation voltage signal line, and the compensation output end is electrically connected with the first control end or the second control end. The voltage compensation module is configured to adjust the voltage ranges of the first control end and the second control end to be different. Compared with the prior art, the embodiments of the present application reduce the voltage output range of a driving chip and reduce power consumption.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a pixel circuit, a driving method thereof and a display panel. BACKGROUND

[0002] With the continuous development of display technology, the technology of display panel is increasingly mature, and the application range of display panel is more and more extensive. However, the display panel is still in a high-speed development stage, and with the liquid crystal display panel (LCD) gradually being replaced by the organic light-emitting diode display panel (OLED), the micro light-emitting diode display panel (micro LED) and its related driving technology are being researched by major panel manufacturers. Among them, the pixel circuit driven by the analog pulse width modulation (PWM) method is considered to be a pixel circuit more suitable for driving the micro LED. However, the pixel circuit requires a larger voltage output range of the driving chip (IC), and requires a higher output capability of the driving chip. SUMMARY

[0003] Embodiments of the present application provide a pixel circuit, a driving method thereof and a display panel to reduce the voltage output range of the driving chip and reduce power consumption.

[0004] To achieve the above technical purpose, the embodiments of the present application provide the following technical solutions:

[0005] A pixel circuit comprises:

[0006] A current control module, the current control module comprises a first data write end, a driving current output end and a first control end; the first data write end is electrically connected with a data line, the data line transmits amplitude data signals and time data signals with the same voltage range at different times; the current control module is used for writing the amplitude data signals to the first control end; the driving current output end is electrically connected with a light-emitting device; the first control end is used for controlling whether the driving current output end outputs a first driving current;

[0007] A time control module, the time control module comprises a second data write end, a time output end and a second control end; the second data write end is electrically connected with the data line, and the time control module is used for writing the time data signals to the second control end; the time output end is electrically connected with the first control end; the time control module is used for controlling whether the time output end outputs a second driving current;

[0008] The voltage compensation module comprises a compensation input end and a compensation output end, the compensation input end is electrically connected with a compensation voltage signal line, and the compensation output end is electrically connected with the first control end or the second control end; the voltage compensation module is used for adjusting that the voltage ranges of the first control end and the second control end are different.

[0009] Further, the voltage compensation module comprises a first capacitor, a first pole plate of the first capacitor is used as the compensation input end of the voltage compensation module, and a second pole plate of the first capacitor is used as the compensation output end of the voltage compensation module. In this way, the circuit structure is simple and easy to implement.

[0010] Further, the compensation output end is electrically connected with the second control end.

[0011] The time control module comprises:

[0012] A time coupling unit, a first end of the time coupling unit is electrically connected with a time control signal line, and a second end of the time coupling unit is electrically connected with the second control end; the time coupling unit is multiplexed as the voltage compensation module, and the time control signal line is multiplexed as the compensation voltage signal line. In this way, the voltage compensation module is electrically connected with the second control end to adjust the potential of the second control end. Meanwhile, the time coupling unit is multiplexed as the voltage compensation module, which is beneficial to simplify the circuit structure.

[0013] Preferably, the time coupling unit comprises a second capacitor, a first pole plate of the second capacitor is electrically connected with the time control signal line, and a first pole plate of the second capacitor is electrically connected with the second control end. In this way, the circuit structure is simple and easy to implement.

[0014] Further, the current control module further comprises a first initialization end, the first initialization end is electrically connected with an initialization signal line; and the current control module is further used for writing the initialization signal into the first control end.

[0015] The time control module further comprises a second initialization end, the second initialization end is electrically connected with the initialization signal line; and the time control module is further used for writing the initialization signal into the second control end.

[0016] The initialization signal line is multiplexed as the compensation voltage signal line. In this way, the number of signal lines is reduced, which is beneficial to the wiring of the display panel.

[0017] Further, the current control module comprises:

[0018] The first driving unit comprises a control end, a first end and a second end, and the control end of the first driving unit serves as the first control end.

[0019] The first light-emitting control unit comprises a control end, a first end and a second end, the control end of the first light-emitting control unit is electrically connected with the light-emitting control signal line, the first end of the first light-emitting control unit is electrically connected with the first power supply line, and the second end of the first light-emitting control unit is electrically connected with the first end of the first driving unit.

[0020] The second light-emitting control unit comprises a control end, a first end and a second end, the control end of the second light-emitting control unit is electrically connected with the light-emitting control signal line, the first end of the second light-emitting control unit is electrically connected with the second end of the first driving unit, and the second end of the second light-emitting control unit serves as the driving current output end.

[0021] The first initialization unit comprises a control end, a first end and a second end, the control end of the first initialization unit is electrically connected with the first scan line, the first end of the first initialization unit is electrically connected with the initialization signal line, and the second end of the first initialization unit is electrically connected with the control end of the first driving unit.

[0022] The first data writing unit comprises a control end, a first end and a second end, the control end of the first data writing unit is electrically connected with the second scan line, the first end of the first data writing unit serves as the first data writing end, and the second end of the first data writing unit is electrically connected with the first end of the first driving unit.

[0023] The first data compensation unit comprises a control end, a first end and a second end, the control end of the first data compensation unit is electrically connected with the second scan line, the first end of the first data compensation unit is electrically connected with the second end of the first driving unit, and the second end of the first data compensation unit is electrically connected with the control end of the first driving unit.

[0024] The current control module is arranged in this way, so that the first driving unit has threshold compensation function, which is beneficial to improving the control precision of the first driving current.

[0025] The time control module comprises:

[0026] The second driving unit comprises a control end, a first end and a second end, and the control end of the second driving unit serves as the second control end.

[0027] The third light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the third light-emitting control unit is electrically connected to the light-emitting control signal line, the first terminal of the third light-emitting control unit is electrically connected to the first power line, and the second terminal of the third light-emitting control unit is electrically connected to the first terminal of the second driving unit.

[0028] The fourth light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth light-emitting control unit is electrically connected to the light-emitting control signal line. The first terminal of the fourth light-emitting control unit is electrically connected to the second terminal of the first driving unit. The second terminal of the fourth light-emitting control unit serves as the time output terminal.

[0029] The second data writing unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data writing unit is electrically connected to the third scan signal line. The first terminal of the second data writing unit serves as the second data writing terminal. The second terminal of the second data writing unit is electrically connected to the first terminal of the second driving unit.

[0030] The second initialization unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second initialization unit is electrically connected to the first scan line, the first terminal of the second initialization unit is electrically connected to the initialization signal line, and the second terminal of the second initialization unit is electrically connected to the control terminal of the second driving unit.

[0031] The second data compensation unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data compensation unit is electrically connected to the third scan signal line. The first terminal of the second data compensation unit is electrically connected to the second terminal of the second drive unit. The second terminal of the second data compensation unit is electrically connected to the control terminal of the second drive unit.

[0032] A time coupling unit, comprising a first end and a second end, wherein the first end of the time coupling unit is electrically connected to a time control signal line, and the second end of the time coupling unit is electrically connected to the control end of the second drive unit.

[0033] This configuration of the time control module enables the second drive unit to have a threshold compensation function, which helps to improve the control accuracy of the second drive current.

[0034] Furthermore, the current control module includes:

[0035] A first driving unit, the first driving unit includes a control terminal, a first terminal and a second terminal, the control terminal of the first driving unit serves as the first control terminal, and the second terminal of the first driving unit serves as the driving current output terminal;

[0036] The first light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the first light-emitting control unit is electrically connected to the light-emitting control signal line. The first terminal of the first light-emitting control unit is electrically connected to the first power line. The second terminal of the first light-emitting control unit is electrically connected to the first terminal of the first driving unit.

[0037] The first data writing unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the first data writing unit is electrically connected to the fourth scan line. The first terminal of the first data writing unit serves as the first data writing terminal, and the second terminal of the first data writing unit is electrically connected to the control terminal of the first driving unit.

[0038] This configuration of the current control module is simple in structure and helps to improve the resolution of the display panel.

[0039] And / or, the time control module includes:

[0040] The second drive unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second drive unit serves as the second control terminal, and the first terminal of the second drive unit is electrically connected to the first power line.

[0041] The second data writing unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data writing unit is electrically connected to the fifth scan line. The first terminal of the second data writing unit serves as the second data writing terminal. The second terminal of the second data writing unit is electrically connected to the control terminal of the second driving unit.

[0042] A time coupling unit, comprising a first end and a second end, wherein the first end of the time coupling unit is electrically connected to a time control signal line, and the second end of the time coupling unit is electrically connected to the control end of the second drive unit.

[0043] This design of the time control module is simple in structure and helps to improve the resolution of the display panel.

[0044] Accordingly, the present invention also provides a display panel, including: pixel circuits as described in any embodiment.

[0045] Accordingly, the present invention also provides a driving method for a pixel circuit, adapted to the pixel circuit described in any embodiment of the present invention; the driving method for the pixel circuit includes: a first data writing stage, a second data writing stage, and a light emission stage;

[0046] During the first data writing stage and the second data writing stage, the amplitude data signal is controlled to be written to the first control terminal of the current control module, and the time data signal is controlled to be written to the second control terminal of the time control module.

[0047] The amplitude data signal and the time data signal have the same voltage range; before or at the beginning of the emission stage, the control compensation voltage signal jumps to adjust the voltage of the first control terminal or the second control terminal.

[0048] Furthermore, in the first data writing stage, the amplitude data signal is controlled to be written to the first control terminal of the current control module; in the second data writing stage, the time data signal is controlled to be written to the second control terminal of the time control module.

[0049] The transition of the compensation voltage signal occurs between the second data writing stage and the light emission stage to adjust the voltage of either the first or second control terminal. This configuration allows adjustment of the first control terminal when the voltage compensation module is connected, and adjustment of the second control terminal when the voltage compensation module is connected.

[0050] Alternatively, the transition of the compensation voltage signal may occur during the second data writing phase to adjust the voltage at the first control terminal. This configuration is only applicable when the voltage compensation module is connected to the first control terminal, enabling adjustment of the first control terminal.

[0051] Furthermore, unlike the aforementioned embodiments, in the first data writing stage, a control time data signal is written to the second control terminal of the time control module; in the second data writing stage, a control amplitude data signal is written to the first control terminal of the current control module.

[0052] The transition of the compensation voltage signal occurs between the second data writing stage and the light emission stage to adjust the voltage of either the first or second control terminal. This configuration allows adjustment of the first control terminal when the voltage compensation module is connected, and adjustment of the second control terminal when the voltage compensation module is connected.

[0053] Alternatively, the transition of the compensation voltage signal may occur during the second data writing phase to adjust the voltage at the second control terminal. This configuration is only applicable when the voltage compensation module is connected to the second control terminal, enabling adjustment of the second control terminal.

[0054] Furthermore, the driving method also includes:

[0055] During the initialization phase, control initialization signals are written to the first control terminal of the current control module and the second control terminal of the time control module to initialize the first and second control terminals. This configuration initializes both the first and second control terminals, which helps improve the display effect.

[0056] Preferably, the initialization signal is multiplexed as the compensation voltage signal; and the initialization signal is a first voltage during the initialization phase; before or at the start of the light-emitting phase, the initialization signal is controlled to switch to a second voltage to adjust the voltage of the first control terminal or the second control terminal. This configuration helps reduce the number of signal lines, thereby facilitating the wiring of the display panel.

[0057] Therefore, this embodiment of the invention achieves voltage adjustment of the first or second control terminal by adding a voltage compensation module and a compensation voltage signal line to the pixel circuit. Thus, during the data writing phase, the amplitude data signal and time data signal being written can be controlled to be within the same voltage range. Before the light emission phase begins, the required voltage of the first or second control terminal is obtained through the coupling effect of the voltage compensation module. This embodiment of the invention achieves the beneficial effects of narrowing the voltage output range of the driver chip and reducing power consumption. Attached Figure Description

[0058] Figure 1 This is a schematic diagram of an existing pixel circuit structure;

[0059] Figure 2 for Figure 1 A timing diagram of the data signal DATA in the middle;

[0060] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0061] Figure 4 for Figure 3 The timing diagram of the pixel circuit shown is shown.

[0062] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0063] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0064] Figure 7 for Figure 6 The timing diagram of the pixel circuit shown is shown.

[0065] Figure 8 A schematic diagram of another pixel circuit provided as an example of the present invention;

[0066] Figure 9 for Figure 8 The timing diagram of the pixel circuit is shown below;

[0067] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0068] Figure 11 for Figure 10 The timing diagram of the pixel circuit is shown below;

[0069] Figure 12 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0070] Figure 13 for Figure 12 The timing diagram of the pixel circuit shown is shown.

[0071] Figure 14 for Figure 12 Another timing diagram of the pixel circuit shown. Detailed Implementation

[0072] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0073] As described in the background section, existing pixel circuits require a wide voltage output range from the driver chip, placing high demands on the driver chip's output capability. The inventors have discovered the following reasons for this problem.

[0074] Figure 1 This is a schematic diagram of an existing pixel circuit. Figure 2 for Figure 1 A timing diagram of the data signal DATA. See also... Figure 1 and Figure 2 The pixel circuit driven by the analog pulse width modulation method includes a current control module 110' and a time control module 120', both of which write relevant data signals DATA' in a time-division manner through the same data line. The pixel circuit is powered by a first power supply signal VDD.

[0075] Specifically, in the first writing stage t1', switch S1' is turned on and switch S2' is turned off, and the data line writes the time data signal Vw to the time control module 120' (node ​​A'). In the second writing stage t2', switch S1' is turned off and switch S2' is turned on, and the data line writes the amplitude data signal Va to the current control module 110' (node ​​B'). The time data signal Vw and the amplitude data signal Va are stored in nodes A' and B' respectively. After writing is completed, the light-emitting device 130' is controlled to emit light in the light-emitting stage t3'. In the light-emitting stage t3', the time control module 120' outputs a drive current after a preset time, and the current control module 110' stops generating drive current, and the light-emitting device 130' stops emitting light.

[0076] The time data signal Vw controls the corresponding transistor in the time control module 120' to turn off, while the amplitude data signal Va controls the corresponding transistor in the current control module 110' to turn on. Taking a P-type transistor as an example, for the circuit to function properly, Vw > VDD > Va must be satisfied. The voltage range of the time data signal Vw is (Vw_max ~ Vw_min); the voltage range of the amplitude data signal Va is (Va_max ~ Va_min). This indicates that a large voltage range needs to be provided by the same data line. On the one hand, this puts a strain on the output capability of the driver chip, making it difficult for the driver chip to provide support; on the other hand, the large voltage changes on the data line increase the power consumption of the panel. If a scheme is used to transmit the time data signal Vw and the amplitude data signal Va separately using two data lines, the number of data lines on the display panel will double, which is impractical.

[0077] In view of this, embodiments of the present invention provide a pixel circuit. Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 3 The pixel circuit includes: a current control module 110, a time control module 120, a voltage compensation module 140, a data line, and a compensation voltage signal line.

[0078] The data line is used to transmit the data signal DATA. Since the current control module 110 and the time control module 120 share a single data line, the data signal DATA includes two types: amplitude data signal Va and time data signal Vw. The data line transmits the amplitude data signal Va and the time data signal Vw in a time-division multiplexing manner. The compensation voltage signal line transmits the compensation voltage signal Vx. The current control module 110 and the time control module 120 can be any circuit structure, and this invention is not limited thereto. Specifically, the current control module 110 includes a first data writing terminal 111, a drive current output terminal 112, and a first control terminal (…). Figure 3(Not shown in the image). The first data writing terminal 111 is electrically connected to the data line, and the current control module 110 is used to write the amplitude data signal Va to the first control terminal. The drive current output terminal 112 is electrically connected to the light-emitting device 130; the first control terminal is used to control whether the drive current output terminal 112 outputs the first drive current. The time control module 120 includes a second data writing terminal 121, a time output terminal 122, and a second control terminal (not shown in the image). Figure 3 (not shown in the image); the second data writing terminal 121 is electrically connected to the data line; the time control module 120 is used to write the time data signal Vw to the second control terminal; the time output terminal 122 is electrically connected to the first control terminal; the time control module 120 is used to control whether the time output terminal 122 outputs the second drive current.

[0079] The voltage compensation module 140 includes a compensation input terminal 141 and a compensation output terminal 142. The compensation input terminal 141 is electrically connected to the compensation voltage signal line, and the compensation output terminal 142 is electrically connected to the first control terminal or the second control terminal. The voltage compensation module 140 is used to adjust the voltage range of the first control terminal and the second control terminal to be different. Figure 3 The example shows a compensation output terminal 142 electrically connected to a first control terminal to adjust the voltage range of the first control terminal.

[0080] Figure 4 for Figure 3 The timing diagram of the pixel circuit is shown. See also... Figure 3 and Figure 4For example, the pixel circuit operates as follows: In the first data writing stage t1, the control time data signal Vw is written to the second control terminal of the time control module 120. In the second data writing stage t2, the control amplitude data signal Va is written to the first control terminal of the current control module 110. The amplitude data signal Va and the time data signal Vw have the same voltage range, Vmax to Vmin, and the time data signal Vw is the voltage actually required by the second control terminal. In both the first data writing stage t1 and the second data writing stage t2, the voltage of the compensation voltage signal Vx is Vx1. At the start of the light emission stage t3, the control compensation voltage signal Vx changes from Vx1 to Vx2 to adjust the voltage of the first control terminal. Specifically, the voltage at the compensation input terminal 141 of the voltage compensation module 140 jumps from Vx1 to Vx2, with a change of Vx2 - Vx1. Due to the coupling effect of the voltage compensation module 140, the change at the compensation output terminal 142 (first control terminal) is also Vx2 - Vx1, and the voltage at the compensation output terminal 142 (first control terminal) jumps from Va to Va + Vx2 - Vx1. Va + Vx2 - Vx1 is the voltage actually required by the first control terminal. That is, by controlling the magnitudes of Vx2 and Vx1 provided by the compensation voltage signal Vx, the first control terminal can be made to jump from Va to Va + Vx2 - Vx1. The current control module 110 generates a first driving current in response to the potential of the first control terminal; the time control module 120 generates a second driving current after a preset time in response to the potential of the second control terminal. The second driving current is injected into the first control terminal to control the current control module 110 to disconnect and no longer generate the first driving current.

[0081] Therefore, this embodiment of the invention achieves voltage adjustment of the first control terminal or the second control terminal by adding a voltage compensation module 140 and a compensation voltage signal line to the pixel circuit. Thus, during the data writing phase, the amplitude data signal Va and the time data signal Vw can be controlled to be within the same voltage range. Before the light emission phase begins, the required voltage of the first control terminal or the second control terminal is obtained through the coupling effect of the voltage compensation module 140. This embodiment of the invention achieves the beneficial effects of narrowing the voltage output range of the driver chip and reducing power consumption.

[0082] It should be noted that, Figure 3 The example shows the voltage compensation module 140 being electrically connected to the first control terminal of the current control module 110 to adjust the voltage at the first control terminal, but this is not intended to limit the invention. In other embodiments, the voltage compensation module 140 may also be electrically connected to the second control terminal of the time control module 120, which can be configured as needed in practical applications.

[0083] Based on the above embodiments, there are various ways to configure the voltage compensation module 140. Any scheme that can adjust the potential of the first control terminal or the second control terminal before the light emission stage is within the protection scope of this invention. Several configuration methods of the voltage compensation module 140 will be described below, but these are not intended to limit the invention.

[0084] Figure 5 A schematic diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 5 In one embodiment of the present invention, optionally, the voltage compensation module 140 includes a first capacitor C1. The first plate of the first capacitor C1 serves as the compensation input terminal 141 of the voltage compensation module 140, and the second plate of the first capacitor C1 serves as the compensation output terminal 142 of the voltage compensation module 140. The first capacitor C1 has a voltage coupling function, enabling it to adjust the voltage change at its first plate to the same amount as the voltage change at its second plate. This configuration in the embodiment of the present invention results in a simple circuit structure that is easy to implement.

[0085] Based on the above embodiments, the voltage compensation module 140 can also be reused with other modules in the pixel circuit, which will be described below in conjunction with the specific structure of the pixel circuit.

[0086] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. See also... Figure 6 In one embodiment of the present invention, optionally, the current control module 110 includes:

[0087] The first driving unit 101 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first driving unit 101 is designated as the first control terminal A. The first driving unit 101 generates a driving current in response to the voltage of the first control terminal A.

[0088] A first light-emitting control unit 102 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first light-emitting control unit 102 is electrically connected to a light-emitting control signal line, the first terminal of the first light-emitting control unit 102 is electrically connected to a first power supply line, and the second terminal of the first light-emitting control unit 102 is electrically connected to the first terminal of the first driving unit 101. The light-emitting control signal line transmits a light-emitting control signal EM, and the first power supply line transmits a first power supply signal VDD. The first light-emitting control unit 102 is turned on or off under the control of the light-emitting control signal EM.

[0089] The second light-emitting control unit 103 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second light-emitting control unit 103 is electrically connected to the light-emitting control signal line. The first terminal of the second light-emitting control unit 103 is electrically connected to the second terminal of the first driving unit 101. The second terminal of the second light-emitting control unit 103 serves as a driving current output terminal and is electrically connected to the light-emitting device 130. Since the second light-emitting control unit 103 is also controlled by the light-emitting control signal EM, the first light-emitting control unit 102 and the second light-emitting control unit 103 have the same conduction state.

[0090] The first initialization unit 104 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first initialization unit 104 is electrically connected to the first scan line, the first terminal of the first initialization unit 104 is electrically connected to the initialization signal line, and the second terminal of the first initialization unit 104 is electrically connected to the control terminal of the first drive unit 101. The first scan line transmits a first scan signal S1, and the initialization signal line transmits an initialization signal VREF. The first initialization unit 104 is controlled by the first scan signal S1 and is used to initialize the first control terminal A. The current control module 110 also includes a first initialization terminal, with the first terminal of the first initialization unit 104 serving as the first initialization terminal.

[0091] The first data writing unit 105 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first data writing unit 105 is electrically connected to the second scan line. The first terminal of the first data writing unit 105 serves as the first data writing terminal and receives the data signal DATA. The second terminal of the first data writing unit 105 is electrically connected to the first terminal of the first driving unit 101. The second scan line transmits a second scan signal S2, and the first data writing unit 105 is controlled by the second scan signal S2.

[0092] The first data compensation unit 106 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first data compensation unit 106 is electrically connected to the second scan line, the first terminal of the first data compensation unit 106 is electrically connected to the second terminal of the first driving unit 101, and the second terminal of the first data compensation unit 106 is electrically connected to the control terminal of the first driving unit 101. The first data compensation unit 106 is also controlled by the second scan signal S2, and the conduction state of the first data compensation unit 106 is the same as that of the first data writing unit 105.

[0093] See also Figure 6 In one embodiment of the present invention, the time control module 120 may optionally have a structure similar to that of the current control module 110. The time control module 120 includes, in detail below:

[0094] The second drive unit 201 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second drive unit 201 is designated as the second control terminal B.

[0095] The third light-emitting control unit 202 includes a control terminal, a first terminal, and a second terminal. The control terminal of the third light-emitting control unit 202 is electrically connected to the light-emitting control signal line. The first terminal of the third light-emitting control unit 202 is electrically connected to the first power supply line. The second terminal of the third light-emitting control unit 202 is electrically connected to the first terminal of the second driving unit 201.

[0096] The fourth light-emitting control unit 203 includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth light-emitting control unit 203 is electrically connected to the light-emitting control signal line. The first terminal of the fourth light-emitting control unit 203 is electrically connected to the second terminal of the second driving unit 201. The second terminal of the fourth light-emitting control unit 203 serves as a time output terminal and is electrically connected to the first control terminal A. The third light-emitting control unit 202 and the fourth light-emitting control unit 203 are also controlled by the light-emitting control signal EM. The four light-emitting control units in the time control module 120 and the current control module 110 have the same conduction state.

[0097] The second initialization unit 204 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second initialization unit 204 is electrically connected to the first scan line, the first terminal of the second initialization unit 204 is electrically connected to the initialization signal line, and the second terminal of the second initialization unit 204 is electrically connected to the control terminal of the second drive unit 201. The second initialization unit 204 is also controlled by the first scan signal S1, and its conduction state is the same as that of the first initialization unit 104. The time control module 120 also includes a second initialization terminal, with the first terminal of the second initialization unit 204 serving as the second initialization terminal.

[0098] The second data writing unit 205 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data writing unit 205 is electrically connected to the third scan signal line. The first terminal of the second data writing unit 205 serves as the second data writing terminal and receives the data signal DATA. The second terminal of the second data writing unit 205 is electrically connected to the first terminal of the second driving unit 201. The third scan signal line transmits the third scan signal S3, and the second data writing unit 205 is controlled by the third scan signal S3.

[0099] The second data compensation unit 206 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data compensation unit 206 is electrically connected to the third scan signal line. The first terminal of the second data compensation unit 206 is electrically connected to the second terminal of the second drive unit 201, and the second terminal of the second data compensation unit 206 is electrically connected to the control terminal of the second drive unit 201. The second data compensation unit 206 is also controlled by the third scan signal S3, and its conduction state is the same as that of the second data writing unit 205.

[0100] The time coupling unit 207 includes a first terminal and a second terminal. The first terminal of the time coupling unit 207 is electrically connected to the time control signal line, and the second terminal of the time coupling unit 207 is electrically connected to the control terminal of the second drive unit 201. The time control signal line transmits a time control signal Vsweep, and the time coupling unit 207 adjusts the voltage of the second control terminal B in response to the time control signal Vsweep.

[0101] It should be noted that, Figure 6 The illustration shows the first end of the first light-emitting control unit 102 connected to the first power line via the third light-emitting control unit 202, which is not intended to limit the invention. In other embodiments, the first light-emitting control unit 102 may be directly electrically connected to the first power line; this can be configured as needed in practical applications.

[0102] See also Figure 6 In one embodiment of the present invention, optionally, the first driving unit 101 includes a first transistor M1, and the gate of the first transistor M1 serves as a first control terminal A.

[0103] The first light-emitting control unit 102 includes a second transistor M2. The gate of the second transistor M2 serves as the control terminal of the first light-emitting control unit 102 and is connected to the light-emitting control signal EM. The first electrode of the second transistor M2 serves as the first terminal of the first light-emitting control unit 102 and is electrically connected to the first power supply signal VDD. The second electrode of the second transistor M2 serves as the second terminal of the first light-emitting control unit 102 and is electrically connected to the first electrode of the first transistor M1.

[0104] The second light-emitting control unit 103 includes a third transistor M3. The gate of the third transistor M3 serves as the control terminal of the second light-emitting control unit 103 and is connected to the light-emitting control signal EM. The first electrode of the third transistor M3 serves as the first terminal of the second light-emitting control unit 103 and is electrically connected to the second electrode of the first transistor M1. The second electrode of the third transistor M3 serves as the second terminal of the second light-emitting control unit 103 and is electrically connected to the light-emitting device 130.

[0105] The first initialization unit 104 includes a fourth transistor M4. The gate of the fourth transistor M4 serves as the control terminal of the first initialization unit 104 and is connected to the first scan signal S1. The first electrode of the fourth transistor M4 serves as the first terminal of the first initialization unit 104 and is connected to the initialization signal VREF. The second electrode of the fourth transistor M4 serves as the second terminal of the first initialization unit 104 and is electrically connected to the first control terminal A.

[0106] The first data writing unit 105 includes a fifth transistor M5. The gate of the fifth transistor M5 serves as the control terminal of the first data writing unit 105 and is connected to the second scan signal S2. The first electrode of the fifth transistor M5 serves as the first terminal of the first data writing unit 105 and is connected to the data signal DATA. The second electrode of the fifth transistor M5 serves as the second terminal of the first data writing unit 105 and is electrically connected to the first electrode of the first transistor M1.

[0107] The first data compensation unit 106 includes a sixth transistor M6. The gate of the sixth transistor M6 serves as the control terminal of the first data compensation unit 106 and is connected to the second scan signal S2. The first electrode of the sixth transistor M6 serves as the first terminal of the first data compensation unit 106 and is electrically connected to the second electrode of the first transistor M1. The second electrode of the sixth transistor M6 serves as the second terminal of the first data compensation unit 106 and is electrically connected to the first control terminal A.

[0108] The second driving unit 201 includes a seventh transistor M7, the gate of which serves as the control terminal of the second driving unit 201 and is electrically connected to the second control terminal B.

[0109] The third light-emitting control unit 202 includes an eighth transistor M8. The gate of the eighth transistor M8 serves as the control terminal of the third light-emitting control unit 202 and is connected to the light-emitting control signal EM. The first electrode of the eighth transistor M8 serves as the first terminal of the third light-emitting control unit 202 and is connected to the first power supply signal VDD. The second electrode of the eighth transistor M8 serves as the second terminal of the third light-emitting control unit 202 and is electrically connected to the first electrode of the seventh transistor M7.

[0110] The fourth light-emitting control unit 203 includes a ninth transistor M9. The gate of the ninth transistor M9 serves as the control terminal of the fourth light-emitting control unit 203 and is connected to the light-emitting control signal EM. The first electrode of the ninth transistor M9 serves as the first terminal of the fourth light-emitting control unit 203 and is electrically connected to the second electrode of the seventh transistor M7. The second electrode of the ninth transistor M9 serves as the second terminal of the fourth light-emitting control unit 203 and is electrically connected to the first control terminal A.

[0111] The second initialization unit 204 includes a tenth transistor M10. The gate of the tenth transistor M10 serves as the control terminal of the second initialization unit 204 and is connected to the first scan signal S1. The first terminal of the tenth transistor M10 serves as the first terminal of the second initialization unit 204 and is connected to the initialization signal VREF. The second terminal of the tenth transistor M10 serves as the second terminal of the second initialization unit 204 and is electrically connected to the second control terminal B.

[0112] The second data writing unit 205 includes an eleventh transistor M11. The gate of the eleventh transistor M11 serves as the control terminal of the second data writing unit 205 and is connected to the third scan signal S3. The first terminal of the eleventh transistor M11 serves as the first terminal of the second data writing unit 205 and is connected to the data signal DATA. The second terminal of the eleventh transistor M11 serves as the second terminal of the second data writing unit 205 and is electrically connected to the first terminal of the seventh transistor M7.

[0113] The second data compensation unit 206 includes a twelfth transistor M12. The gate of the twelfth transistor M12 serves as the control terminal of the second data compensation unit 206 and is connected to the third scan signal S3. The first terminal of the twelfth transistor M12 serves as the first terminal of the second data compensation unit 206 and is electrically connected to the first terminal of the seventh transistor M7. The second terminal of the twelfth transistor M12 serves as the second terminal of the second data compensation unit 206 and is electrically connected to the second control terminal B.

[0114] The time coupling unit 207 includes a second capacitor C2. The first plate of the second capacitor C2 serves as the first terminal of the time coupling unit 207, connected to the time control signal Vsweep. The second plate of the second capacitor C2 serves as the second terminal of the time coupling unit 207, electrically connected to the second control terminal B. Since the second capacitor C2 also has a storage function and is electrically connected to the second control terminal B, the time control module 120 does not need to set up a storage unit for the second control terminal B.

[0115] In this embodiment of the invention, each unit is configured to include only one transistor or one capacitor. This configuration results in a simple circuit structure that is easy to implement.

[0116] The following section uses timing diagrams to illustrate... Figure 6 The working principle of the pixel circuit shown is analyzed. Figure 7 for Figure 6 The timing diagram of the pixel circuit is shown. (Combined with...) Figure 6 and Figure 7 The following explanation uses an example where all transistors are P-type transistors. The driving methods for pixel circuits include:

[0117] During the initialization phase t0, the first scan signal S1 is low, while the second scan signal S2, the third scan signal S3, and the light emission control signal EM are high. The first scan signal S1 controls the fourth transistor M4 and the tenth transistor M10 to conduct. The initialization signal VREF initializes the first control terminal A and the second control terminal B to ensure that the first transistor M1 and the seventh transistor M7 are conducted in the next phase.

[0118] During the first data writing phase t1, the third scan signal S3 is low, while the first scan signal S1, the second scan signal S2, and the light emission control signal EM are high. The data line transmits the time data signal Vw. The third scan signal S3 controls the eleventh transistor M11 and the twelfth transistor M12 to turn on. The time data signal Vw is written to the second control terminal B via the turned-on eleventh transistor M11, seventh transistor M7, and twelfth transistor M12, and simultaneously written to the second capacitor C2. The written value is Vw + Vth7, where Vth7 is the threshold voltage of the seventh transistor M7, and Vw > VDD.

[0119] In the second data writing stage t2, the second scan signal S2 is low, while the first scan signal S1, the third scan signal S3, and the light emission control signal EM are high. The data line transmits the amplitude data signal Va, and the voltage of the compensation voltage signal Vx is Vx1. The second scan signal S2 controls the fifth transistor M5 and the sixth transistor M6 to conduct. The amplitude data signal Va is written to the first control terminal A through the conducting fifth transistor M5, first transistor M1, and sixth transistor M6, and simultaneously written to the second plate of the first capacitor C1. The written value is Va + Vth1. Here, Vth1 is the threshold voltage of the first transistor M1. The voltage range of the amplitude data signal Va and the time data signal Vw is the same, i.e., Va > VDD.

[0120] During the light-emitting stage t3, the light-emitting control signal EM is at a low level, while the first scan signal S1, the second scan signal S2, and the third scan signal S3 are at a high level. The voltage of the compensation voltage signal Vx is Vx2, where Vx2 < Vx1. Due to the voltage drop at the first plate of the first capacitor C1 (Vx2 - Vx1), the voltage at its second plate also drops under the coupling effect of the first capacitor C1 (Vx2 - Vx1), ultimately becoming Va + Vth1 + Vx2 - Vx1, where Va + Vth1 + Vx2 - Vx1 < VDD. Since the first terminal of the first transistor M1 is connected to the first power supply signal VDD, the second terminal of the first transistor M1 is connected to the first terminal of the light-emitting device 130, and the second terminal of the light-emitting device 130 is connected to the second power supply signal VSS. The first transistor M1 generates a first driving current Id1, driving the light-emitting device 130 to emit light, and the driving current Id1 is obtained by the following formula:

[0121] Id1= μ eff C ox (Va+Vth1+Vx2-Vx1-VDD-Vth1) 2 = μ eff C ox (Va+Vx2-Vx1-VDD) 2

[0122] In the formula, W is the channel width, L is the channel length, and μ eff For electron mobility, C ox This represents the channel capacitance per unit area. Therefore, this embodiment of the invention achieves threshold voltage compensation for the first transistor M1.

[0123] Simultaneously, since Vw > VDD, the seventh transistor M7 cannot conduct. However, as the time control signal Vsweep decreases, the voltage of the first plate of the second capacitor C2 gradually decreases. Under the coupling effect of the second capacitor C2, the voltage of the second control terminal B also gradually decreases. Until the time control signal Vsweep drops to VDD + Vth7, the seventh transistor M7 conducts, generating the second driving current Id2. Under the action of the second driving current Id2, the first power signal VDD is written to the first control terminal A, and the voltage of the first control terminal A quickly rises to VDD, controlling the first transistor M1 to turn off, no longer generating the first driving current, and the light-emitting device 130 stops emitting light. Therefore, this embodiment of the invention can not only achieve brightness adjustment of the light-emitting device 130, but also achieve adjustment of the light-emitting time of the light-emitting device 130, realizing mixed-signal driving and making the brightness adjustment of the display panel more precise. The light emission time of the light-emitting device 130 can be adjusted by adjusting the slope of the time control signal Vsweep. The larger the slope of the time control signal Vsweep, the shorter the light emission time of the light-emitting device 130; conversely, the smaller the slope of the time control signal Vsweep, the longer the light emission time of the light-emitting device 130.

[0124] In summary, the embodiments of the present invention not only ensure that the amplitude data signal Va and the time data signal Vw are within the same voltage range, thus narrowing the voltage output range of the driver chip and reducing power consumption, but also achieve threshold voltage compensation for the first transistor M1 and the seventh transistor M7, making the magnitude and output time of the first driving current more accurate, which is beneficial to improving the uniformity of the display panel.

[0125] It should be noted that the above embodiments exemplify writing the time data signal Vw first, followed by writing the amplitude data signal Va, and are not intended to limit the invention. In other embodiments, the amplitude data signal Va may be written first, followed by writing the time data signal Vw. This can be configured as needed in practical applications, and will be explained in detail below.

[0126] Optionally, in the first data writing stage t1, the control time data signal Vw is written to the second control terminal B; in the second data writing stage t2, the control amplitude data signal Va is written to the first control terminal A. If the transition of the compensation voltage signal Vx occurs between the second data writing stage t2 and the emission stage t3, voltage adjustment of either the first control terminal A or the second control terminal B can be achieved. If the transition of the compensation voltage signal Vx occurs in the second data writing stage t2, voltage adjustment of the first control terminal A cannot be achieved, but voltage adjustment of the second control terminal B can be achieved.

[0127] Optionally, in the first data writing stage t1, the control amplitude data signal Va is written to the first control terminal A; in the second data writing stage t2, the control time data signal Vw is written to the second control terminal B. If the transition of the compensation voltage signal Vx occurs between the second data writing stage t2 and the light emission stage t3, the voltage of either the first control terminal A or the second control terminal B can be adjusted. If the transition of the compensation voltage signal Vx occurs in the second data writing stage t2, voltage adjustment of the second control terminal B cannot be achieved, but voltage adjustment of the first control terminal A can be achieved.

[0128] Figure 8 A schematic diagram of another pixel circuit provided as an example of the present invention. See also Figure 8 In one embodiment of the present invention, optionally, the time coupling unit 207 is multiplexed as a voltage compensation module 140, and the time control signal line is multiplexed as a compensation voltage signal line. This configuration electrically connects the voltage compensation module 140 to the second control terminal B to adjust the potential of the second control terminal B. Simultaneously, multiplexing the time coupling unit 207 as a voltage compensation module 140 simplifies the circuit structure.

[0129] Figure 9 for Figure 8 The timing diagram of the pixel circuit is shown. Combined with... Figure 8 and Figure 9 ,and Figure 6The driving method of the pixel circuit shown differs in that, in the first data writing stage t1, the time data signal Vw < VDD is written to the second control terminal B. Similarly, in the second data writing stage t2, the amplitude data signal Va < VDD is written to the first control terminal A. At this time, the voltage ranges of the time data signal Vw and the amplitude data signal Va are still the same, but the voltage adjustment needs to be performed on the second control terminal B. In the light emission stage t3, the voltage of the time control signal Vsweep jumps from Vx1 to Vx2. Due to the increase in voltage of the first plate of the second capacitor C2, the change is Vx2 - Vx1. Correspondingly, under the coupling effect of the second capacitor C2, the voltage of its second plate also increases, the change is Vx2 - Vx1, and finally becomes Vw + Vth7 + Vx2 - Vx1. Among them, Vw + Vth7 + Vx2 - Vx1 > VDD, and the seventh transistor M7 cannot be turned on because the conduction condition is not met.

[0130] It should be noted that, Figure 6 The example shows the voltage compensation module 140 electrically connected to the first control terminal A. In this case, the voltage compensation module 140 can also store the voltage of the first control terminal A; therefore, the current control module 110 does not need to have a separate storage unit. Figure 8 In the example shown, the voltage compensation module 140 is electrically connected to the second control terminal B. At this time, the current control module 110 also includes a first storage unit 107, which includes a first terminal and a second terminal. The first terminal of the first storage unit 107 is electrically connected to the first power line, and the second terminal of the first storage unit 107 is electrically connected to the control terminal of the first drive unit 101. The first storage unit 107 is used to store the voltage of the first control terminal A. Optionally, the first storage unit 107 includes a third capacitor C3. The first plate of the third capacitor C3 serves as the first terminal of the first storage unit 107 and is connected to the first power signal VDD; the second plate of the third capacitor C3 serves as the second terminal of the first storage unit 107 and is electrically connected to the first control terminal A.

[0131] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. In one embodiment, optionally, the initialization signal line is multiplexed as a compensation voltage signal line. This configuration helps reduce the number of signal lines, thereby facilitating the wiring of the display panel.

[0132] Figure 11 for Figure 10 The timing diagram of the pixel circuit is shown. Combined with... Figure 10 and Figure 11 ,and Figure 6Unlike the pixel circuit driving method described above, this embodiment of the invention multiplexes the initialization signal VREF into a compensation voltage signal Vx. During the initialization phase, the initialization signal is a first voltage Vx1; before or at the start of the light emission phase t3, the control initialization signal VREF jumps to a second voltage Vx2 to adjust the voltage of the first control terminal A. Similarly, this multiplexing method is also applicable to adjusting the voltage of the second control terminal B.

[0133] In the above embodiments, the technical solutions of the present invention are exemplarily shown to be applicable to pixel circuits with threshold compensation functions, and are not intended to limit the present invention. The embodiments of the present invention are also applicable to pixel circuits where the data signal DATA is directly written to the first control terminal A or the second control terminal B, as described in detail below.

[0134] Figure 12 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. See also... Figure 12 In one embodiment of the present invention, optionally, the current control module 110 includes:

[0135] The first driving unit 101 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first driving unit 101 serves as the first control terminal A, and the second terminal of the first driving unit 101 serves as the driving current output terminal and is electrically connected to the light-emitting device 130.

[0136] The first light-emitting control unit 102 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first light-emitting control unit 102 is electrically connected to the light-emitting control signal line. The first terminal of the first light-emitting control unit 102 is electrically connected to the first power supply line. The second terminal of the first light-emitting control unit 102 is electrically connected to the first terminal of the first driving unit 101.

[0137] The first data writing unit 105 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first data writing unit 105 is electrically connected to the fourth scan line, and the fourth scan line transmits the fourth scan signal S4. The first terminal of the first data writing unit 105 serves as the first data writing terminal and is electrically connected to the data line. The second terminal of the first data writing unit 105 is electrically connected to the control terminal of the first driving unit 101, that is, connected to the first control terminal A.

[0138] See also Figure 12 In one embodiment of the present invention, optionally, the time control module 120 includes:

[0139] The second drive unit 201 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second drive unit 201 serves as the second control terminal B. The first terminal of the second drive unit 201 is electrically connected to the first power line. The second terminal of the second drive unit 201 serves as the time output terminal of the time control module 120 and is electrically connected to the first control terminal A.

[0140] The second data writing unit 205 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data writing unit 205 is electrically connected to the fifth scan line, and the fifth scan line transmits the fifth scan signal S5. The first terminal of the second data writing unit 205 serves as the second data writing terminal and is electrically connected to the data line. The second terminal of the second data writing unit 205 is electrically connected to the control terminal of the second driving unit 201, that is, connected to the second control terminal B.

[0141] The time coupling unit 207 includes a first end and a second end. The first end of the time coupling unit 207 is electrically connected to the time control signal line, and the second end of the time coupling unit 207 is electrically connected to the control end of the second drive unit 201, that is, connected to the second control end B.

[0142] See also Figure 12 In one embodiment of the present invention, optionally, the first driving unit 101 includes a first transistor M1, the gate of the first transistor M1 serves as the control terminal of the first driving unit 101 and is electrically connected to the first control terminal A; the first electrode of the first transistor M1 serves as the first terminal of the first driving unit 101 and is connected to the first power signal VDD; the second electrode of the first transistor M1 serves as the second terminal of the first driving unit 101 and is electrically connected to the light-emitting device 130.

[0143] The first light-emitting control unit 102 includes a second transistor M2. The gate of the second transistor M2 serves as the control terminal of the first light-emitting control unit 102 and is connected to the light-emitting control signal EM. The first electrode of the second transistor M2 serves as the first terminal of the first light-emitting control unit 102 and is electrically connected to the first power supply signal VDD. The second electrode of the second transistor M2 serves as the second terminal of the first light-emitting control unit 102 and is electrically connected to the first electrode of the first transistor M1.

[0144] The first data writing unit 105 includes a fifth transistor M5. The gate of the fifth transistor M5 serves as the control terminal of the first data writing unit 105 and is connected to the fourth scan signal S4. The first electrode of the fifth transistor M5 serves as the first terminal of the first data writing unit 105 and is connected to the data signal DATA. The second electrode of the fifth transistor M5 serves as the second terminal of the first data writing unit 105 and is electrically connected to the first control terminal A.

[0145] Since the first capacitor C1 also has a storage function and is electrically connected to the first control terminal A, the current control module 110 does not need to set up a storage unit for the first control terminal A.

[0146] See also Figure 12 In one embodiment of the present invention, optionally, the second driving unit 201 includes a seventh transistor M7, the gate of the seventh transistor M7 serves as the control terminal of the second driving unit 201 and is electrically connected to the second control terminal B; the first electrode of the seventh transistor M7 serves as the first terminal of the second driving unit 201 and is connected to the first power supply signal VDD; the second electrode of the seventh transistor M7 serves as the second terminal of the second driving unit 201 and is electrically connected to the first control terminal A.

[0147] The second data writing unit 205 includes an eleventh transistor M11. The gate of the eleventh transistor M11 serves as the control terminal of the second data writing unit 205. The first terminal of the eleventh transistor M11 serves as the first terminal of the second data writing unit 205 and is connected to the data signal DATA. The second terminal of the eleventh transistor M11 serves as the second terminal of the second data writing unit 205 and is electrically connected to the second control terminal B.

[0148] The time coupling unit 207 includes a second capacitor C2. The first plate of the second capacitor C2 serves as the first terminal of the time coupling unit 207, connected to the time control signal Vsweep. The second plate of the second capacitor C2 serves as the second terminal of the time coupling unit 207, electrically connected to the second control terminal B. Since the second capacitor C2 also has a storage function and is electrically connected to the second control terminal B, the time control module 120 does not need to set up a storage unit for the second control terminal B.

[0149] In this embodiment of the invention, each unit is configured to include only one transistor or one capacitor. This configuration results in a simple circuit structure that is easy to implement.

[0150] The following section uses timing diagrams to illustrate... Figure 12 The working principle of the pixel circuit shown is analyzed. Figure 13 for Figure 12 The timing diagram of the pixel circuit is shown. (Combined with...) Figure 12 and Figure 13 The following explanation uses an example where all transistors are P-type transistors. The driving methods for pixel circuits include:

[0151] In the first data writing stage t1, the fourth scan signal S4 is low, while the fifth scan signal S5 and the light emission control signal EM are high. The data line transmits the amplitude data signal Va, and the voltage of the compensation voltage signal Vx is Vx1. The fourth scan signal S4 controls the fifth transistor M5 to turn on, and the amplitude data signal Va is written to the first control terminal A through the turned-on fifth transistor M5, and simultaneously written to the second plate of the first capacitor C1. The written value is Va, where Va > VDD.

[0152] During the second data writing phase t2, the fifth scan signal S5 is low, while the fourth scan signal S4 and the light emission control signal EM are high. The data line transmits the time data signal Vw. The fifth scan signal S5 controls the eleventh transistor M11 to conduct, and the time data signal Vw is written to the second control terminal B via the conducting eleventh transistor M11, and simultaneously written to the second capacitor C2. The written value is Vw, where Vw > VDD. The amplitude data signal Va has the same voltage range as the time data signal Vw.

[0153] During the light-emitting stage t3, the light-emitting control signal EM is at a low level, while the fourth scan signal S4 and the fifth scan signal S5 are at a high level. The voltage of the compensation voltage signal Vx is Vx2, where Vx2 < Vx1. Due to the voltage drop at the first plate of the first capacitor C1 (Vx2 - Vx1), the voltage at its second plate also drops under the coupling effect of the first capacitor C1 (Vx2 - Vx1), eventually becoming Va + Vx2 - Vx1, where Va + Vx2 - Vx1 < VDD. Furthermore, since the first terminal of the first transistor M1 is connected to the first power supply signal VDD, the first transistor M1 generates a first driving current Id1, driving the light-emitting device 130 to emit light.

[0154] Simultaneously, since Vw > VDD, the seventh transistor M7 cannot conduct. However, as the time control signal Vsweep decreases, the voltage of the first plate of the second capacitor C2 gradually decreases. Under the coupling effect of the second capacitor C2, the voltage of the second control terminal B also gradually decreases. Until the time control signal Vsweep drops to VDD + Vth7, the seventh transistor M7 conducts, generating the second driving current Id2. Under the action of the second driving current Id2, the first power signal VDD is written to the first control terminal A, and the voltage of the first control terminal A quickly rises to VDD, controlling the first transistor M1 to turn off, no longer generating the first driving current, and the light-emitting device 130 stops emitting light. Therefore, this embodiment of the invention can not only achieve brightness adjustment of the light-emitting device 130, but also achieve adjustment of the light-emitting time of the light-emitting device 130, realizing mixed-signal driving and making the brightness adjustment of the display panel more precise.

[0155] Figure 14 for Figure 12Another timing diagram of the pixel circuit shown. Combined with... Figure 12 and Figure 14 Unlike the above embodiments, this embodiment of the invention incorporates the second data writing stage t2 into the light-emitting stage t3. Specifically, in the light-emitting stage t3, the light-emitting control signal EM is at a low level, the fourth scanning signal S4 is at a high level, and the voltage of the compensation voltage signal Vx is Vx2. Where Vx2 < Vx1, due to the voltage drop of the first plate of the first capacitor C1 (Vx2 - Vx1), correspondingly, under the coupling effect of the first capacitor C1, the voltage of its second plate also drops (Vx2 - Vx1), ultimately becoming Va + Vx2 - Vx1. Where Va + Vx2 - Vx1 < VDD, and because the first terminal of the first transistor M1 is connected to the first power supply signal VDD, the first transistor M1 generates a first driving current Id1, driving the light-emitting device 130 to emit light.

[0156] For a short period at the beginning of the light-emitting phase t3, the fifth scan signal S5 is at a low level, and the data line transmits the time data signal Vw. The fifth scan signal S5 controls the eleventh transistor M11 to conduct, and the time data signal Vw is written to the second control terminal B through the conducting eleventh transistor M11, and simultaneously written to the second capacitor C2. The written value is Vw, where Vw > VDD, and the seventh transistor M7 cannot conduct. However, as the time control signal Vsweep decreases, the voltage of the first plate of the second capacitor C2 gradually decreases. Under the coupling effect of the second capacitor C2, the voltage of the second control terminal B also gradually decreases. Until the time control signal Vsweep decreases to VDD + Vth7, the seventh transistor M7 conducts, generating the second driving current Id2. Under the action of the second driving current Id2, the first power supply signal VDD is written to the first control terminal A, and the voltage of the first control terminal A quickly rises to VDD, controlling the first transistor M1 to turn off, no longer generating the first driving current Id1, and the light-emitting device 130 stops emitting light.

[0157] In this embodiment of the invention, only the first data writing stage t1 can be set before the light-emitting stage t3, thereby reducing the non-light-emitting time before the generation of the first driving current Id1. With the same scanning time for a row of pixel circuits, this extends the light-emitting time of the light-emitting device, further improving the grayscale expansion of the display panel and enhancing its display effect. Furthermore, with the same light-emitting stage t3 time, this improves the refresh rate and pixel density (PPI) of the display panel.

[0158] It should be noted that, in Figure 12The illustration exemplarily shows the first light-emitting control unit 102 disposed between the first driving unit 101 and the first power line, which is not intended to limit the invention. In other embodiments, the first light-emitting control unit 102 may also be disposed between the first driving unit 101 and the light-emitting device 130, and can be configured as needed in practical applications.

[0159] It should also be noted that, in the above embodiments, P-type transistors are used as examples for illustration, but this is not intended to limit the present invention. In other embodiments, each transistor may be an N-type transistor, or some transistors may be P-type transistors and others may be N-type transistors. In practical applications, the configuration can be made as needed.

[0160] This invention also provides a display panel, which may be a micro-LED display panel, an organic light-emitting diode display panel, or an LED display panel, etc. This display panel includes the pixel circuit provided in any embodiment of this invention, and its technical principles and effects are similar, so they will not be described again.

[0161] This invention also provides a driving method for a pixel circuit, applicable to the pixel circuits provided in any embodiment of this invention. The driving method for the pixel circuit includes: a first data writing stage, a second data writing stage, and a light-emitting stage;

[0162] In the first data writing stage and the second data writing stage, the amplitude data signal is controlled to be written to the first control terminal of the current control module, and the time data signal is controlled to be written to the second control terminal of the time control module, respectively.

[0163] The amplitude data signal and the time data signal have the same voltage range; before or at the beginning of the emission stage, the control compensation voltage signal jumps to adjust the voltage of the first control terminal or the second control terminal.

[0164] This invention achieves voltage adjustment of the first or second control terminal by controlling the transition of the compensation voltage signal. Therefore, during the data writing phase, the amplitude and timing data signals being written can be controlled to be within the same voltage range. Before the light emission phase begins, the required voltage of the first or second control terminal is obtained through the coupling effect of the voltage compensation module. This invention achieves the beneficial effects of narrowing the voltage output range of the driver chip and reducing power consumption.

[0165] Based on the above embodiments, optionally, in the first data writing stage, the amplitude data signal is written to the first control terminal of the current control module; in the second data writing stage, the time data signal is written to the second control terminal of the time control module.

[0166] The compensation voltage signal transition occurs between the second data writing stage and the light emission stage to adjust the voltage of the first control terminal or the second control terminal; or, the compensation voltage signal transition occurs during the second data writing stage to adjust the voltage of the first control terminal.

[0167] Alternatively, in the first data writing stage, a control time data signal is written to the second control terminal of the time control module; in the second data writing stage, a control amplitude data signal is written to the first control terminal of the current control module; wherein, the transition of the compensation voltage signal occurs between the second data writing stage and the light emission stage to adjust the voltage of the first or second control terminal; or, the transition of the compensation voltage signal occurs in the second data writing stage to adjust the voltage of the second control terminal. Preferably, the second data writing stage is incorporated into the light emission stage.

[0168] Optionally, based on the above embodiments, the driving method for the pixel circuit further includes:

[0169] During the initialization phase, a control initialization signal is written to the first control terminal of the current control module and the second control terminal of the time control module to initialize the first and second control terminals. The initialization signal is multiplexed as a compensation voltage signal, and it is the first voltage during the initialization phase. Before or at the start of the light emission phase, the control initialization signal switches to the second voltage to adjust the voltage of either the first or second control terminal.

[0170] In addition, it should be noted that in the various embodiments of the pixel circuit, specific descriptions of driving methods are provided for different pixel circuits. These driving methods are all considered to be the driving methods of the pixel circuits provided in the embodiments of the present invention, and repeated content will not be described here.

[0171] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: A current control module includes a first data writing terminal, a drive current output terminal, and a first control terminal; the first data writing terminal is electrically connected to a data line, and the data line transmits amplitude data signals and time data signals with the same voltage range in a time-division multiplexing manner. The current control module is used to write the amplitude data signal into the first control terminal; the drive current output terminal is electrically connected to the light-emitting device; the first control terminal is used to control whether the drive current output terminal outputs a first drive current. A time control module includes a second data writing terminal, a time output terminal, and a second control terminal; the second data writing terminal is electrically connected to the data line, and the time control module is used to write the time data signal to the second control terminal; the time output terminal is electrically connected to the first control terminal; the time control module is used to control whether the time output terminal outputs a second drive current. A voltage compensation module includes a compensation input terminal and a compensation output terminal. The compensation input terminal is electrically connected to a compensation voltage signal line, and the compensation output terminal is electrically connected to either the first control terminal or the second control terminal. The voltage compensation module is used to adjust the voltage ranges of the first control terminal and the second control terminal to be different.

2. The pixel circuit according to claim 1, characterized in that, The voltage compensation module includes: The first capacitor has its first plate serving as the compensation input terminal of the voltage compensation module, and its second plate serving as the compensation output terminal of the voltage compensation module.

3. The pixel circuit according to claim 1, characterized in that, The compensation output terminal is electrically connected to the second control terminal; The time control module includes: A time coupling unit, wherein a first end of the time coupling unit is electrically connected to a time control signal line, and a second end of the time coupling unit is electrically connected to a second control terminal; the time coupling unit is multiplexed as the voltage compensation module, and the time control signal line is multiplexed as the compensation voltage signal line.

4. The pixel circuit according to claim 3, characterized in that, The time coupling unit includes a second capacitor, the first plate of the second capacitor is electrically connected to the time control signal line, and the first plate of the second capacitor is electrically connected to the second control terminal.

5. The pixel circuit according to claim 1, characterized in that, The current control module further includes a first initialization terminal, which is electrically connected to an initialization signal line; the current control module is also used to write an initialization signal into the first control terminal. The time control module further includes a second initialization terminal, which is electrically connected to the initialization signal line; the time control module is also used to write the initialization signal into the second control terminal; The initialization signal line is multiplexed as the compensation voltage signal line.

6. The pixel circuit according to claim 1, characterized in that, The current control module includes: A first driving unit, the first driving unit includes a control terminal, a first terminal and a second terminal, the control terminal of the first driving unit serving as the first control terminal; The first light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the first light-emitting control unit is electrically connected to the light-emitting control signal line. The first terminal of the first light-emitting control unit is electrically connected to the first power line. The second terminal of the first light-emitting control unit is electrically connected to the first terminal of the first driving unit. The second light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second light-emitting control unit is electrically connected to the light-emitting control signal line. The first terminal of the second light-emitting control unit is electrically connected to the second terminal of the first driving unit. The second terminal of the second light-emitting control unit serves as the driving current output terminal. A first initialization unit, comprising a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first initialization unit is electrically connected to a first scan line, the first terminal of the first initialization unit is electrically connected to an initialization signal line, and the second terminal of the first initialization unit is electrically connected to the control terminal of the first driving unit. A first data writing unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the first data writing unit is electrically connected to the second scan line. The first terminal of the first data writing unit serves as the first data writing terminal. The second terminal of the first data writing unit is electrically connected to the first terminal of the first driving unit. A first data compensation unit, comprising a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first data compensation unit is electrically connected to the second scan line, the first terminal of the first data compensation unit is electrically connected to the second terminal of the first driving unit, and the second terminal of the first data compensation unit is electrically connected to the control terminal of the first driving unit. And / or, the time control module includes: The second drive unit includes a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second drive unit serves as the second control terminal. The third light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the third light-emitting control unit is electrically connected to the light-emitting control signal line, the first terminal of the third light-emitting control unit is electrically connected to the first power line, and the second terminal of the third light-emitting control unit is electrically connected to the first terminal of the second driving unit. The fourth light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth light-emitting control unit is electrically connected to the light-emitting control signal line. The first terminal of the fourth light-emitting control unit is electrically connected to the second terminal of the first driving unit. The second terminal of the fourth light-emitting control unit serves as the time output terminal. The second data writing unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data writing unit is electrically connected to the third scan signal line. The first terminal of the second data writing unit serves as the second data writing terminal. The second terminal of the second data writing unit is electrically connected to the first terminal of the second driving unit. The second initialization unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second initialization unit is electrically connected to the first scan line, the first terminal of the second initialization unit is electrically connected to the initialization signal line, and the second terminal of the second initialization unit is electrically connected to the control terminal of the second driving unit. The second data compensation unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data compensation unit is electrically connected to the third scan signal line. The first terminal of the second data compensation unit is electrically connected to the second terminal of the second drive unit. The second terminal of the second data compensation unit is electrically connected to the control terminal of the second drive unit. A time coupling unit, comprising a first end and a second end, wherein the first end of the time coupling unit is electrically connected to a time control signal line, and the second end of the time coupling unit is electrically connected to the control end of the second drive unit.

7. The pixel circuit according to claim 1, characterized in that, The current control module includes: A first driving unit, the first driving unit includes a control terminal, a first terminal and a second terminal, the control terminal of the first driving unit serves as the first control terminal, and the second terminal of the first driving unit serves as the driving current output terminal; The first light-emitting control unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the first light-emitting control unit is electrically connected to the light-emitting control signal line. The first terminal of the first light-emitting control unit is electrically connected to the first power line. The second terminal of the first light-emitting control unit is electrically connected to the first terminal of the first driving unit. A first data writing unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the first data writing unit is electrically connected to the fourth scan line. The first terminal of the first data writing unit serves as the first data writing terminal. The second terminal of the first data writing unit is electrically connected to the control terminal of the first driving unit. And / or, the time control module includes: The second drive unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second drive unit serves as the second control terminal, and the first terminal of the second drive unit is electrically connected to the first power line. The second data writing unit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second data writing unit is electrically connected to the fifth scan line. The first terminal of the second data writing unit serves as the second data writing terminal. The second terminal of the second data writing unit is electrically connected to the control terminal of the second driving unit. A time coupling unit, comprising a first end and a second end, wherein the first end of the time coupling unit is electrically connected to a time control signal line, and the second end of the time coupling unit is electrically connected to the control end of the second drive unit.

8. A display panel, characterized in that, include: The pixel circuit as described in any one of claims 1-7.

9. A driving method for a pixel circuit, characterized in that, Applied to the pixel circuit as described in claim 1; The pixel circuit includes: a current control module, a time control module, and a voltage compensation module; the driving method of the pixel circuit includes: a first data writing stage, a second data writing stage, and a light emission stage; During the first data writing stage and the second data writing stage, the amplitude data signal is controlled to be written to the first control terminal of the current control module, and the time data signal is controlled to be written to the second control terminal of the time control module. The amplitude data signal and the time data signal have the same voltage range; before or at the beginning of the emission stage, the control compensation voltage signal jumps to adjust the voltage of the first control terminal or the second control terminal.

10. The driving method for the pixel circuit according to claim 9, characterized in that, In the first data writing stage, the amplitude data signal is controlled to be written to the first control terminal of the current control module; in the second data writing stage, the time data signal is controlled to be written to the second control terminal of the time control module; wherein, the jump of the compensation voltage signal occurs between the second data writing stage and the light emission stage to adjust the voltage of the first control terminal or the second control terminal; or, the jump of the compensation voltage signal occurs in the second data writing stage to adjust the voltage of the first control terminal; Alternatively, during the first data writing phase, a control time data signal is written to the second control terminal of the time control module; during the second data writing phase, a control amplitude data signal is written to the first control terminal of the current control module; wherein, the transition of the compensation voltage signal occurs between the second data writing phase and the light emission phase to adjust the voltage of the first control terminal or the second control terminal; or, the transition of the compensation voltage signal occurs during the second data writing phase to adjust the voltage of the second control terminal.

11. The driving method for the pixel circuit according to claim 9, characterized in that, Also includes: During the initialization phase, a control initialization signal is written to the first control terminal of the current control module and the second control terminal of the time control module to initialize the first control terminal and the second control terminal.

12. The driving method for the pixel circuit according to claim 11, characterized in that, The initialization signal is multiplexed into the compensation voltage signal; and the initialization signal is a first voltage during the initialization phase. Before or at the start of the light emission phase, the initialization signal is controlled to switch to a second voltage to adjust the voltage of the first control terminal or the second control terminal.

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