Display panel and manufacturing method thereof, and display device

Abstract

A display panel and a preparation method thereof, and a display device, the display panel comprising a substrate (10), an effective area (100) arranged on the substrate (10), and a binding area (200) located on one side of the effective area (100); the binding area (200) comprises a binding pin area (206), the binding pin area (206) comprises a binding pin (83), a virtual pin (84), and a test signal line (81); the orthographic projection of at least one test signal line (81) on the substrate (10) is located within the range of the orthographic projection of the virtual pin (84) on the substrate (10), and the orthographic projection of the virtual pin (84) on the substrate (10) does not overlap with the orthographic projection of the binding pin (83) on the substrate (10).

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to the field of display technology, and in particular to a display panel and a method for manufacturing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED as a light-emitting device and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. According to the requirements of products such as flexible folding and narrow bezels, the existing OLED-based touch structure adopts a flexible covering surface structure. The flexible touch substrate is set on the encapsulation layer of the OLED backplane. It has the advantages of being light, thin, and foldable, and can meet the requirements of products such as flexible folding and narrow bezels. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] An embodiment of the present disclosure provides a display panel, comprising a substrate, an effective area arranged on the substrate, and a binding area located on one side of the effective area; the binding area comprises a binding pin area, and the binding pin area comprises binding pins, virtual pins, and test signal lines; the orthographic projection of at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the virtual pin on the substrate, and the orthographic projection of the virtual pin on the substrate does not overlap with the orthographic projection of the binding pin on the substrate.

[0005] In an exemplary embodiment, the effective area includes a substrate and a display unit and a touch unit stacked on the substrate, the display unit includes a plurality of data lines and a plurality of gate lines, the plurality of data lines and the plurality of gate lines intersecting to define a plurality of sub-pixels, the touch unit includes a plurality of touch electrodes and touch leads connected to the touch electrodes; the display panel also includes an array test area located on a side of the binding area away from the effective area, the array test area includes a test pin, the test signal line is connected to the test pin, and is configured to test one or more of the display unit and the touch unit.

[0006] In an exemplary embodiment, the virtual pin includes a first virtual pin and a second virtual pin, the orthographic projection of the first virtual pin on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate, the orthographic projection of at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the first virtual pin on the substrate, and the orthographic projection of the test signal line on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate.

[0007] In an exemplary embodiment, in a plane perpendicular to the display panel, the display panel includes: a first conductive layer arranged on the substrate, a second conductive layer arranged on the first conductive layer, a third conductive layer arranged on the second conductive layer, and a fourth conductive layer arranged on the third conductive layer; the test signal line is arranged on the same layer as at least one of the first conductive layer and the second conductive layer; the first virtual pin is arranged on the same layer as the fourth conductive layer; the binding pin and the second virtual pin are arranged on the same layer as the third conductive layer and the fourth conductive layer.

[0008] In an exemplary embodiment, in a plane perpendicular to the display panel, the display panel includes: a driving circuit layer, a light-emitting structure layer, a packaging layer and a touch electrode layer stacked in sequence on the substrate, the driving circuit layer includes a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source and drain metal layer stacked on the substrate, the touch electrode layer includes a touch insulating layer, a touch electrode layer and a touch protection layer stacked on the packaging layer; the first conductive layer is arranged on the same layer as the first gate metal layer, the second conductive layer is arranged on the same layer as the second gate metal layer, the third conductive layer is arranged on the same layer as the first source and drain metal layer, and the fourth conductive layer is arranged on the same layer as the touch electrode layer.

[0009] In an exemplary embodiment, the width of the orthographic projection of the first virtual pin on the substrate along the first direction is equal to the width of the orthographic projections of the M test signal lines on the substrate along the first direction, the distance between two adjacent pins is greater than the width of the N test signal lines along the first direction, M is a natural number greater than or equal to 1, and N is a natural number greater than or equal to 1.

[0010] In an exemplary embodiment, M is 3 and N is 1.

[0011] In an exemplary embodiment, x first virtual pins are arranged between two second virtual pins, where x is a natural number between 1 and 3.

[0012] In an exemplary embodiment, a height of a side of the second dummy pin away from the substrate from the substrate is greater than a height of a side of the first dummy pin away from the substrate from the substrate.

[0013] In an exemplary embodiment, the test signal line includes: a first test signal line and a second test signal line, the first test signal line is located on the first conductive layer, and the second test signal line is located on the second conductive layer; an orthographic projection of the first test signal line on the substrate does not overlap with an orthographic projection of the second test signal line on the substrate, the first test signal line and the second test signal line extend along a second direction, the first test signal line and the second test signal line are alternately arranged along a first direction, and the first direction intersects with the second direction.

[0014] In an exemplary embodiment, a width of the first test signal line along the first direction is equal to a width of the second test signal line along the first direction, and distances between adjacent first test signal lines and second test signal lines are equal.

[0015] In an exemplary embodiment, a width of the first test signal line along the first direction is between 7 micrometers and 17 micrometers, and a distance between adjacent first test signal lines and second test signal lines is between 8 micrometers and 18 micrometers.

[0016] In an exemplary embodiment, the width of the binding pin along the first direction is equal to the width of the dummy pin along the first direction, and the distances between two adjacent pins are equal.

[0017] In an exemplary embodiment, the width of the binding pin along the first direction is between 45 micrometers and 75 micrometers, and the distance between two adjacent pins is between 25 micrometers and 55 micrometers.

[0018] In an exemplary embodiment, the length of the binding pin along the second direction is equal to the length of the dummy pin along the second direction, and the length of the binding pin along the second direction is between 900 micrometers and 1000 micrometers.

[0019] In an exemplary embodiment, the display panel also includes a first power line and a second power line, the test signal line includes 2n lines, the binding pins include multiple first binding pins and multiple second binding pins, the multiple first binding pins are connected to the first power line, the multiple second binding pins are connected to the second power line, the 2n test signal lines are arranged between the multiple second binding pins, the multiple second binding pins are arranged between the multiple first binding pins, the 2n test signal lines are symmetrically arranged along the center line of the binding area, the multiple first binding pins are symmetrically arranged along the center line of the binding area, and the multiple second binding pins are symmetrically arranged along the center line of the binding area.

[0020] In an exemplary embodiment, on one side of the center line of the binding area, the n test signal lines are divided into at least two test signal line groups, and at least one dummy pin is disposed between two adjacent test signal line groups.

[0021] In an exemplary embodiment, a width of an orthographic projection of the test signal line group on the substrate along the first direction is between 150 micrometers and 300 micrometers.

[0022] An embodiment of the present disclosure further provides a display device, comprising a display panel as described in any of the preceding items.

[0023] The embodiment of the present disclosure further provides a method for preparing a display panel, wherein the display panel includes a substrate, an effective area disposed on the substrate, and a binding area located on one side of the effective area, wherein the binding area includes a binding pin area, and the preparation method includes:

[0024] A test signal line, a binding pin and a virtual pin are formed in the binding pin area, and the orthographic projection of at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the virtual pin on the substrate, and the orthographic projection of the virtual pin on the substrate does not overlap with the orthographic projection of the binding pin on the substrate.

[0025] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0027] Figure 1 It is a structural schematic diagram of an OLED display panel;

[0028] Figure 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0029] Figure 3 is a working timing diagram of a pixel driving circuit;

[0030] Figure 4 A schematic structural diagram of a display motherboard according to an exemplary embodiment of the present disclosure;

[0031] Figure 5 A schematic structural diagram of a peripheral area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0032] Figure 6a and Figure 6b Schematic diagram of the cross-sectional structure of two display panels in the effective area of ​​the exemplary embodiment of the present disclosure;

[0033] Figure 6c and Figure 6d Schematic diagram of the planar structure of two touch control units according to the exemplary embodiments of the present disclosure;

[0034] Figure 7 A schematic diagram of a planar structure of a display panel binding pin area according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 for Figure 7 Schematic diagram of the cross-sectional structure of the middle AA region;

[0036] Fig. 9 A schematic diagram of the width of a pin and a test signal line and the distance between them according to an exemplary embodiment of the present disclosure;

[0037] Fig.10 This is a schematic diagram of an exemplary structure of a display panel binding pin area after a semiconductor layer is formed according to the present disclosure;

[0038] Fig.11 This is a schematic diagram of an exemplary structure of a display panel binding pin area after forming a first gate metal layer according to the present disclosure;

[0039] Fig.12 This is a schematic diagram of an exemplary structure of a display panel binding pin area after forming a second gate metal layer according to the present disclosure;

[0040] Fig.13 This is a schematic diagram of an exemplary structure of a display panel binding pin area after forming a fourth insulating layer according to the present disclosure;

[0041] Fig.14 This is a schematic diagram of an exemplary structure of a display panel binding pin area after forming a first source-drain metal layer according to the present disclosure;

[0042] Fig.15This is a schematic diagram of an exemplary structure of a display panel binding pin area after a flat layer is formed according to the present disclosure;

[0043] Fig.16 This is a schematic diagram of an exemplary structure of a display panel binding pin area after a touch insulating layer is formed according to the present disclosure;

[0044] Fig.17 The present invention is a schematic diagram of an exemplary structure of a display panel binding pin area after a touch electrode layer is formed. DETAILED DESCRIPTION

[0045] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual design.

[0046] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0047] In the present specification, ordinal numbers such as “first”, “second”, “third”, 1st, 2nd, 3rd, etc. are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0048] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0049] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0050] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0051] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0052] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0053] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0054] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0055] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0056] Capacitive On Cell touch panels are mainly divided into mutual capacitance and self capacitance. The mutual capacitance structure is composed of the overlapping driving electrodes and sensing electrodes to form mutual capacitance, and the change of mutual capacitance is used for position detection. The self capacitance structure is composed of the touch electrodes and the human body to form self capacitance, and the change of self capacitance is used for position detection. The self capacitance touch panel is a single-layer structure with the characteristics of low power consumption and simple structure, while the mutual capacitance touch panel is a multi-layer structure with the characteristics of multi-touch.

[0057] The display device of the exemplary embodiment of the present disclosure may include a display unit disposed on a substrate and a touch unit disposed on the display unit. The display unit may be a liquid crystal display (LCD) substrate, or may be an organic light emitting diode (OLED) display substrate, or may be a plasma display device (PDP) display substrate, or may be an electrophoretic display (EPD) display substrate. In an exemplary embodiment, the display unit is an OLED display substrate, and the OLED display substrate may include a substrate, a driving circuit layer disposed on the substrate, a light emitting structure layer disposed on the driving circuit layer, and an encapsulation layer disposed on the light emitting structure layer. The touch unit is disposed on the encapsulation layer of the display unit to form a structure of a touch structure on a thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The display structure and the touch structure are integrated together, and have the advantages of being light, thin, and foldable, and can meet product requirements such as flexible folding and narrow bezels.

[0058] At present, the Touch on TFE structure mainly includes the Flexible Multi Layer On Cell (FMLOC) structure and the Flexible Single Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0059] Figure 1 Schematic diagram of the structure of an OLED display panel. Figure 1As shown, the OLED display panel may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal suitable for the specification of the scan signal driver, a scan start signal, etc. to the scan signal driver, and a clock signal suitable for the specification of the light emitting signal driver, an emission stop signal, etc. to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal having an off-level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may sequentially transmit a luminous stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij, at least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting device, the pixel driving circuit may be connected to a corresponding data signal line, a corresponding scanning signal line and a corresponding light-emitting signal line, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device, the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel, i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which the pixel driving circuit is connected to the i-th scanning signal line and to the j-th data signal line.

[0060] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 2 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 2 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0061] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0062] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0063] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0064] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0065] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.

[0066] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0067] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0068] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0069] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0070] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.

[0071] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0072] Figure 3 This is a working timing diagram of a pixel driving circuit. Figure 2 The operation process of the pixel driving circuit of the example is described in detail. Figure 2 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.

[0073] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0074] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0075] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0076] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0077] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0078] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0079] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0080] Currently, the preparation of a flexible OLED display device is to first prepare a display motherboard, and then cut the display motherboard so that the display motherboard is separated into a plurality of display panels, and the separated display panels can all be used to form a single OLED display device. Figure 4 FIG. 1 is a schematic diagram showing the arrangement of multiple display panels on a display motherboard. Figure 4 As shown, multiple substrate regions 300 on the display motherboard are arranged in a periodic and regular manner, and the cutting region 400 is located outside the substrate region 300. The substrate region 300 includes at least an active region 100 and a binding region 200, the active region 100 includes a plurality of pixels arranged in a matrix, and the binding region 200 is arranged on one side of the active region 100. A first cutting line 601 and a second cutting line 602 are arranged in the cutting region 400. After all the film layers of the display motherboard are prepared, the cutting equipment performs rough cutting and fine cutting along the first cutting line 601 and the second cutting line 602, respectively, to form a display panel.

[0081] In an exemplary embodiment, if Figure 5As shown, the binding area 200 may include a first fan-out area 201, a bending area 202, a second fan-out area 203, an anti-static area 204, a driver chip area 205 and a binding pin area 206 which are sequentially arranged in a direction away from the effective area 100. The first fan-out area 201 may be provided with a signal transmission line of the display unit and a touch lead of the touch unit. The signal transmission line of the display unit at least includes a first power line (VDD), a second power line (VSS) and a plurality of data transmission lines. The plurality of data transmission lines are configured to connect the data line (Data Line) of the display unit in a fan-out routing manner. The first power line VDD and the second power line VSS are configured to respectively connect the high-level power line and the low-level power line of the display unit. The plurality of touch leads of the touch unit are configured to be connected to the plurality of pins of the binding pin area 206 in correspondence. The bending area 202 may be provided with a groove, and the groove is configured to bend the second fan-out area 203, the anti-static area 204, the driver chip area 205 and the binding pin area 206 to the back of the effective area 100. The second fan-out area 203 may be provided with a plurality of touch leads and a plurality of data transmission lines led out in a fan-out routing manner. The antistatic area 204 may be provided with an antistatic circuit, and the antistatic circuit is configured to eliminate static electricity. The driver chip area 205 may be provided with a source driver circuit (Driver IC), and the source driver circuit is configured to be connected to a plurality of data transmission lines of the second fan-out area 203. In some possible implementations, the driver chip area 205 may be provided with a touch and display driver integrated circuit (Touch and Display Driver Integration, referred to as TDDI). The binding pin area 206 may be provided with a plurality of pins (PINs), and the plurality of pins are correspondingly connected to a plurality of touch leads and a plurality of signal transmission lines of the source driver circuit, and connected to an external control device through a bound flexible circuit board (FPC).

[0082] In an exemplary embodiment, during the preparation of the display unit and the touch unit, an array test (Array Test) area is further provided on the side of the binding area 200 away from the effective area 100, and the array test area includes an array test unit 207, and the array test unit 207 includes a plurality of test terminals (ET Pad), and the plurality of test terminals are correspondingly connected to a plurality of pins or test signal lines of the binding pin area 206 through interface lines, and are configured to test the display unit and the touch unit to check whether there are problems such as short circuit and open circuit.

[0083] In an exemplary embodiment, a first cutting line 601 and a second cutting line 602 are further provided on the outside of the binding area 200. The second cutting line 602 is a fine cutting line located at the periphery of the binding area 200. The shape of the second cutting line 602 is the same as the outline of the binding area 200. The first cutting line 601 is a rough cutting line located at the periphery of the second cutting line 602. The shape of the first cutting line 601 is substantially the same as the outline of the second cutting line 602. However, only the second cutting line 602 is provided between the binding area 200 and the array test unit 207. At least one first cutting line 601 is further provided on the side of the array test unit 207 away from the binding area 200. After the film layer process is completed, the cutting device cuts along the first cutting line 601 (rough cutting line). After the test is completed, the cutting device cuts along the second cutting line 602 (fine cutting line) to form a display panel.

[0084] Compared with the method of driving touch and display separately, TDDI product design often encounters the problem of limited space. Therefore, it is necessary to design the wiring of the signal lines after the touch display is integrated. In the wiring design of the binding area 200, some test signal lines need to pass through the binding pin area 206 and lead to the array test unit 207 for test connection. However, the test signal lines are easily broken during the binding process, and the film peeling (Peeling) is easy to occur at the test signal line position during the process.

[0085] An exemplary embodiment of the present disclosure provides a display panel, which may include an effective area and a binding area located on one side of the effective area, the binding area including a binding pin area, the binding pin area including binding pins, virtual pins and test signal lines; the orthographic projection of at least one test signal line on a substrate is located within the range of the orthographic projection of the virtual pin on the substrate, and the orthographic projection of the virtual pin on the substrate does not overlap with the orthographic projection of the binding pin on the substrate.

[0086] In some exemplary embodiments, the effective area includes a substrate and a display unit and a touch unit stacked on the substrate, the display unit includes a plurality of data lines and a plurality of gate lines, the plurality of data lines and the plurality of gate lines intersecting to define a plurality of sub-pixels, and the touch unit includes a plurality of touch electrodes and touch leads connected to the touch electrodes.

[0087] The display panel also includes an array test area located on a side of the binding area away from the effective area. The array test area includes test pins, and test signal lines are connected to the test pins, and are configured to test one or more of the display unit and the touch unit.

[0088] Figure 6a and Figure 6bFIG. 1 is a schematic diagram of the cross-sectional structure of the effective area of ​​two display panels of the exemplary embodiment of the present disclosure, illustrating the structure of three sub-pixels in the OLED display panel. Figure 6a and Figure 6b As shown, on a plane perpendicular to the display panel, the display panel may include a driving circuit layer 12 arranged on a substrate 10, a light-emitting structure layer 13 arranged on a side of the driving circuit layer 12 away from the substrate 10, an encapsulation layer 14 arranged on a side of the light-emitting structure layer 13 away from the substrate 10, and a touch structure layer 15 arranged on a side of the encapsulation layer 14 away from the substrate 10. The touch structure layer 15 may include a touch insulating layer 51 arranged on a side of the encapsulation layer 14 away from the substrate 10, a touch electrode layer 52 arranged on a side of the touch insulating layer 51 away from the substrate 10, and a touch protection layer 53 arranged on a side of the touch electrode layer 52 away from the substrate 10.

[0089] At present, the Touch on TFE structure mainly includes a flexible multi-layer surface covering type (Flexible Multi Layer On Cell, FMLOC) structure and a flexible single layer surface covering type (Flexible Single Layer On Cell, FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode. The touch structure layer 15 in the embodiment of the present disclosure can be an FMLOC structure or a FSLOC structure.

[0090] In some exemplary embodiments, Figure 6c As shown, the active area 100 includes a plurality of regularly arranged touch electrodes 301. Exemplarily, the touch electrodes 301 may be rectangular and arranged in a matrix of M rows and N columns. The active area 100 may be divided into N electrode areas 110 and N lead areas 120. The electrode areas 110 and the lead areas 120 are strip-shaped extending along the second direction Y. The strip-shaped electrode areas 110 and the strip-shaped lead areas 120 are alternately arranged along the first direction X, that is, except for the electrode areas and lead areas at the edge positions, one lead area 120 is arranged between two electrode areas 110, and one electrode area 110 is arranged between two lead areas 120. Each electrode area 110 includes M touch electrodes 301 arranged in sequence along the second direction Y, and each lead area 120 includes M touch leads 310 arranged in sequence along the first direction X. The first end of each touch lead 310 is connected to a touch electrode 300, and the second end extends to the binding area 200 along the second direction Y.

[0091] In some exemplary embodiments, the touch electrode 301 may be a regular pattern of about 4 mm*4 mm or 5 mm*5 mm, and the regular pattern may be a rectangle, a diamond, a triangle, or a polygon, etc. During operation, the touch of a human finger may cause the self-capacitance of the corresponding touch electrode to change, and the external control device may determine the position of the finger according to the capacitance change of the touch electrode.

[0092] In other exemplary embodiments, Figure 6d As shown, the touch structure layer includes a plurality of first touch units 401 and a plurality of second touch units 501, the first touch units 401 have a linear shape extending along a first direction X, the plurality of first touch units 401 are sequentially arranged along a second direction Y, the second touch units 501 have a linear shape extending along the second direction Y, the plurality of second touch units 501 are sequentially arranged along the first direction X, and the first direction X intersects with the second direction Y.

[0093] Each first touch control unit 401 includes a plurality of first touch control electrodes 41 and a first connection portion 42 arranged in sequence along a first direction X, and the plurality of first touch control electrodes 41 and the plurality of first connection portions 42 are alternately arranged and connected in sequence. Each second touch control unit 501 includes a plurality of second touch control electrodes 51 arranged in sequence along a second direction Y, and the plurality of second touch control electrodes 51 are arranged at intervals, and adjacent second touch control electrodes 51 are connected to each other through second connection portions 52. The layer where the second connection portion 52 is located is different from the layer where the first touch electrode 41 and the second touch electrode 51 are located. The first touch electrodes 41 and the second touch electrodes 51 are alternately arranged in a third direction Z, and the third direction D3 intersects the first direction X and the second direction Y.

[0094] The first touch unit 401 and the second touch unit 501 are connected to the touch pins of the binding area 200 through the touch leads 310. In an exemplary embodiment, the touch pins of the binding area 200 are connected to a driver, and the driver can apply a driving signal to the second touch electrode 51 and receive an output signal from the first touch electrode 41, or the driver can apply a driving signal to the first touch electrode 41 and receive an output signal from the second touch electrode 51. The driver can determine the position where the touch occurs by detecting the sensing signals generated in the multiple electrodes when different electrodes transmit touch signals.

[0095] In an exemplary embodiment, the touch electrode layer 52 includes a first touch electrode layer (i.e., a bridge layer), a sixth insulating layer, and a second touch electrode layer stacked on the touch insulating layer 51. A plurality of first touch electrodes 41, a plurality of second touch electrodes 51, and a plurality of first connecting portions 42 can be arranged in the same layer on the second touch electrode layer, and can be formed by the same patterning process. The first touch electrodes 41 and the first connecting portions 42 can be an integral structure connected to each other. The second connecting portion 52 can be arranged in the first touch electrode layer, and the adjacent second touch electrodes 51 are connected to each other through vias, and an insulating layer is arranged between the second touch electrode layer and the first touch electrode layer. In some possible implementations, a plurality of first touch electrodes 41, a plurality of second touch electrodes 51, and a plurality of second connecting portions 52 can be arranged in the same layer on the second touch electrode layer, and the second touch electrodes 51 and the second connecting portions 52 can be an integral structure connected to each other, and the first connecting portion 42 can be arranged in the first touch electrode layer, and the adjacent first touch electrodes 41 are connected to each other through vias. In an exemplary embodiment, the first touch electrode may be a driving electrode (Tx) and the second touch electrode may be a sensing electrode (Rx), or the first touch electrode may be a sensing electrode (Rx) and the second touch electrode may be a driving electrode (Tx).

[0096] Figure 7 This is a schematic diagram of a planar structure of a display panel binding pin area according to an exemplary embodiment of the present disclosure. Figure 8 for Figure 7 Schematic diagram of the cross-sectional structure of the AA area, combined with Figure 5 , Figure 7 and Figure 8 As shown, an embodiment of the present disclosure provides a display panel, including an active area 100, a binding area 200 located at one side of the active area 100, and an array test area located at a side of the binding area 200 away from the active area 100, wherein the active area 100 includes a substrate 10 and a display unit and a touch unit stacked on the substrate 10, wherein the display unit includes a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels, and the touch unit includes a plurality of touch electrodes and touch leads connected to the touch electrodes; the binding area 200 includes a binding pin area 206, the binding pin area 206 includes a binding pin 83, a virtual pin 84, and a test signal line 81, and the array test area includes a test pin (not shown in the figure), and the test signal line 81 is connected to the test pin and is configured to test the display unit and / or the touch unit;

[0097] The orthographic projection of at least one test signal line 81 on the substrate 10 is within the range of the orthographic projection of the virtual pin 84 on the substrate 10 , and the orthographic projection of the virtual pin 84 on the substrate 10 does not overlap with the orthographic projection of the binding pin 83 on the substrate 10 .

[0098] In an exemplary embodiment, if Figure 7 and Figure 8 As shown, the virtual pin 84 includes a first virtual pin 84a and a second virtual pin 84b, the orthographic projection of the first virtual pin 84a on the substrate 10 does not overlap with the orthographic projection of the second virtual pin 84b on the substrate 10, and the orthographic projection of at least one test signal line 81 on the substrate 10 is located within the range of the orthographic projection of the first virtual pin 84a on the substrate 10, and the orthographic projection of the test signal line 81 on the substrate 10 does not overlap with the orthographic projection of the second virtual pin 84b on the substrate 10.

[0099] In an exemplary embodiment, if Figure 7 and Figure 8 As shown, in a plane perpendicular to the display panel, the display panel includes: a first conductive layer disposed on the substrate 10, a second conductive layer disposed on the first conductive layer, a third conductive layer disposed on the second conductive layer, and a fourth conductive layer disposed on the third conductive layer;

[0100] The test signal line 81 is disposed in the same layer as at least one of the first conductive layer and the second conductive layer;

[0101] The first virtual pin 84a is disposed on the same layer as the fourth conductive layer;

[0102] The binding pin and the second dummy pin 84 b are disposed on the same layer as the third conductive layer and the fourth conductive layer.

[0103] In an exemplary embodiment, in combination with Figure 6a , Figure 7 and Figure 8 As shown, the driving circuit layer 12 may include a substrate 10 and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the substrate 10;

[0104] The first conductive layer may be disposed on the same layer as the first gate metal layer, the second conductive layer may be disposed on the same layer as the second gate metal layer, the third conductive layer may be disposed on the same layer as the first source-drain metal layer, and the fourth conductive layer may be disposed on the same layer as the touch electrode layer.

[0105] In an exemplary embodiment, when the touch electrode layer includes a first touch electrode layer, a sixth insulating layer, and a second touch electrode layer stacked on the touch insulating layer, the fourth conductive layer may be disposed in the same layer as the first touch electrode layer and the second touch electrode layer, or the fourth conductive layer may be disposed in the same layer as the second touch electrode layer. Since the thickness of the first touch electrode layer and the second touch electrode layer may be different, and the second touch electrode layer is generally thicker than the first touch electrode layer, the fourth conductive layer is disposed in the same layer as the second touch electrode layer, so that the height of the binding pin and the second virtual pin 84b can be increased, and the test signal line at the bottom of the first virtual pin will not be crushed.

[0106] In an exemplary embodiment, in combination with Figure 6b , Figure 7 and Figure 8 As shown, the driving circuit layer 12 may include a substrate 10 and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer, a first source-drain metal layer, a fifth insulating layer, and a second source-drain metal layer stacked on the substrate 10;

[0107] The first conductive layer can be arranged on the same layer as the first gate metal layer, the second conductive layer can be arranged on the same layer as the second gate metal layer, the third conductive layer can be arranged on the same layer as one or more layers of the first source-drain metal layer and the second source-drain metal layer, and the fourth conductive layer can be arranged on the same layer as the touch electrode layer.

[0108] In an exemplary embodiment, if Figure 7 and Figure 8 As shown, the test signal line 81 includes: a first test signal line 81a and a second test signal line 81b, the first test signal line 81a is located on the first conductive layer, and the second test signal line 81b is located on the second conductive layer;

[0109] The orthographic projection of the first test signal line 81a and the orthographic projection of the second test signal line 81b on the substrate 10 do not overlap, the first test signal line 81a and the second test signal line 81b both extend along the second direction Y, the first test signal line 81a and the second test signal line 81b are alternately arranged along the first direction X, and the first direction X intersects with the second direction Y.

[0110] In an exemplary embodiment, if Fig. 9 As shown, the width a1 of the first test signal line 81a along the first direction X is equal to the width a2 of the second test signal line 81b along the first direction X, and the distances c between adjacent first test signal lines 81a and second test signal lines 81b are equal.

[0111] In this embodiment, the stability and consistency of the binding process are ensured by arranging the first test signal line 81a and the second test signal line 81b with equal width and equal spacing. However, in actual products, due to the existence of process errors, the width of the first test signal line 81a and the second test signal line 81b is compared with the standard signal line width, or the interval between the first test signal line 81a and the second test signal line 81b is compared with the standard signal line interval, and a certain process error range is allowed. Exemplarily, the process error range can be 0.1 micron to 0.8 micron. Therefore, as long as the width of the first test signal line 81a and the second test signal line 81b is within the process error range, or the interval between the first test signal line 81a and the second test signal line 81b is within the process error range, it is considered that the first test signal line 81a and the second test signal line 81b are arranged with equal width or equal spacing.

[0112] In an exemplary embodiment, the width of the first test signal line 81 a along the first direction X is between 7 micrometers and 17 micrometers, and the distance between adjacent first test signal lines 81 a and second test signal lines 81 b is between 8 micrometers and 18 micrometers.

[0113] In an exemplary embodiment, if Fig. 9 As shown, the width b1 of the binding pin 83 along the first direction X, the width b2 of the first virtual pin 84a along the first direction X, and the width b3 of the second virtual pin 84b along the first direction X are equal, and the distances between two adjacent pins are equal. Fig. 9 As shown, two adjacent pins refer to any two pins that are adjacent in physical position.

[0114] In this embodiment, the stability and consistency of the binding process are ensured by arranging the binding pins 83 and the virtual pins 84 with equal width and equal spacing. However, in actual products, due to the existence of process errors, the width of the binding pins 83 and the virtual pins 84 is compared with the standard pin width, or the spacing between the binding pins 83 and the virtual pins 84 is compared with the standard pin spacing, and a certain process error range is allowed. Exemplarily, the process error range can be 0.1 microns to 0.8 microns. Therefore, as long as the width of the binding pins 83 and the virtual pins 84 is within the process error range, or the spacing between the binding pins 83 and the virtual pins 84 is within the process error range, it is considered that the binding pins 83 and the virtual pins 84 are arranged with equal width or equal spacing.

[0115] In an exemplary embodiment, a width b1 of the binding pin 83 along the first direction X is between 45 micrometers and 75 micrometers, and a distance between two adjacent pins is between 25 micrometers and 55 micrometers.

[0116] In an exemplary embodiment, the length of the binding pin 83 along the second direction Y is equal to the length of the dummy pin 84 along the second direction Y, and the length of the binding pin 83 along the second direction Y is between 900 micrometers and 1000 micrometers.

[0117] In an exemplary embodiment, if Fig. 9 As shown, the width of the orthographic projection of the first virtual pin 84a on the substrate 10 along the first direction X is equal to the width of the orthographic projection of the M test signal lines 81 on the substrate 10 along the first direction X, and the distance between two adjacent pins is greater than the width of the N test signal lines 81 along the first direction X, M is a natural number greater than or equal to 1, and N is a natural number greater than or equal to 1. In this embodiment, the width of the orthographic projection of the M test signal lines 81 on the substrate 10 along the first direction X includes the sum of the widths of the M test signal lines 81 themselves and the widths of the intervals between two adjacent test signal lines 81 among the M test signal lines 81. The width of the N test signal lines 81 along the first direction X includes the sum of the widths of the N test signal lines 81 themselves and the widths of the intervals between two adjacent test signal lines 81 among the N test signal lines 81.

[0118] In an exemplary embodiment, M is 3 and N is 1.

[0119] In an exemplary embodiment, x first virtual pins 84 a are disposed between two second virtual pins 84 b , where x is a natural number between 1 and 3.

[0120] In an exemplary embodiment, if Figure 7 As shown, the display panel also includes a first power line VDD and a second power line VSS, the test signal lines include 2n lines, the binding pins 83 include multiple first binding pins 831 and multiple second binding pins 832, the multiple first binding pins 831 are connected to the first power line VDD, the multiple second binding pins 832 are connected to the second power line VSS, the 2n test signal lines are arranged between the multiple second binding pins 832, the multiple second binding pins 832 are arranged between the multiple first binding pins 831, the 2n test signal lines are symmetrically arranged along the center line O of the binding area, the multiple first binding pins 831 are symmetrically arranged along the center line O of the binding area, and the multiple second binding pins 832 are symmetrically arranged along the center line O of the binding area.

[0121] In an exemplary embodiment, if Figure 7 As shown, on one side of the center line O of the binding area, the n test signal lines are divided into at least two test signal line groups, and at least one virtual pin 84 is arranged between two adjacent test signal line groups.

[0122] In an exemplary embodiment, if Figure 7As shown, the width L of the orthographic projection of at least one test signal line group on the substrate along the first direction X is between 150 micrometers and 300 micrometers.

[0123] In this embodiment, the width of the orthographic projection of the test signal line group on the substrate along the first direction X includes the sum of the widths of all the test signal lines 81 in the test signal line group and the width of the interval between two adjacent test signal lines 81 .

[0124] The following is an exemplary description of the preparation process of the display panel. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display panel. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0125] In an exemplary embodiment, the manufacturing process of the display panel includes the following operations.

[0126] (1) Prepare a substrate 10 on a glass carrier. In an exemplary embodiment, the substrate 10 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si). In an exemplary embodiment, the substrate 10 may be a hard substrate. After this process, the binding pin area 206 includes the substrate 10.

[0127] (2) Forming a pattern of the driving circuit layer 12 on the substrate 10. In an exemplary embodiment, forming the pattern of the driving circuit layer may include:

[0128] A first insulating film and a semiconductor film are sequentially deposited on the substrate 10, and the semiconductor film is patterned by a patterning process to form a first insulating layer covering the substrate 10 and a semiconductor layer pattern disposed on the first insulating layer, wherein the semiconductor layer pattern includes at least an active layer located in each display sub-pixel. Fig.10 As shown, the bonding pin region 206 includes a first insulating layer 91 disposed on the substrate 10 .

[0129] Subsequently, a second insulating film and a first metal film are deposited in sequence, and the first metal film is patterned by a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first gate metal layer pattern disposed on the second insulating layer, wherein the first gate metal layer pattern at least includes a gate electrode and a first capacitor electrode located in each sub-pixel, and a first test signal line located in the binding pin area. Fig.11 As shown, the binding pin area 206 includes a first insulating layer 91 , a second insulating layer 92 and a first test signal line 81 a stacked on the substrate 10 .

[0130] Subsequently, a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer covering the first gate metal layer pattern, and a second gate metal layer pattern disposed on the third insulating layer, wherein the second gate metal layer pattern at least includes a second capacitor electrode located in each sub-pixel and a second test signal line located in the binding pin area. In an exemplary embodiment, Fig.12As shown, in the binding pin area 206, the orthographic projections of the first test signal line 81a and the second test signal line 81b on the substrate 10 have no overlapping area. In an exemplary embodiment, the first test signal line 81a and the second test signal line 81b are alternately arranged along the first direction. In the exemplary embodiment of the present disclosure, by arranging the adjacent first test signal lines 81a and the second test signal lines 81b in two film layers respectively, and the first test signal lines 81a and the second test signal lines 81b are alternately arranged in the first direction, the spacing between the adjacent first test signal lines 81a and the second test signal lines 81b is effectively reduced, and the connection reliability is effectively improved. At the same time, the compression of the spacing between the first test signal lines and the second test signal lines effectively narrows the width of the entire binding area, making the product appearance more beautiful.

[0131] Subsequently, a fourth insulating film is deposited and patterned by a patterning process to form a fourth insulating layer covering the second gate metal layer pattern, wherein the fourth insulating layer is provided with a first via hole. Fig.13 As shown, the binding pin area 206 includes a first insulating layer 91 , a second insulating layer 92 , a first test signal line 81 a , a third insulating layer 93 , a second test signal line 81 b and a fourth insulating layer 94 stacked on the substrate 10 .

[0132] Subsequently, a third metal film is deposited, and the third metal film is patterned by a patterning process to form a first source-drain metal layer pattern on the fourth insulating layer, wherein the first source-drain metal layer pattern at least includes a source electrode and a drain electrode located in each sub-pixel, and a first sub-binding pin and a first sub-dummy pin located in the binding pin area, and the source electrode and the drain electrode are respectively connected to the active layer through a first via hole, such as Fig.14 As shown, the orthographic projections of the first sub-binding pin 83 a , the first sub-dummy pin 84 b 1 , the first test signal line 81 a , and the second test signal line 81 b on the substrate 10 have no overlapping area.

[0133] Subsequently, a flat film is deposited and patterned by a patterning process to form a flat layer covering the pattern of the first source and drain metal layer. The flat layer is provided with an anode via, a second via K2 and a third via K3. The anode via is arranged in the effective area, and the anode via exposes the surface of the drain electrode. Fig.15 As shown, the second via hole K2 and the third via hole K3 are disposed in the binding area 206 , the second via hole K2 exposes the surface of the first sub-binding pin 83 a , and the third via hole K3 exposes the surface of the first sub-dummy pin 84 b 1 .

[0134] At this point, the driving circuit layer pattern is prepared.

[0135] (3) Forming a light emitting structure layer pattern on the driving circuit layer. In an exemplary embodiment, forming the light emitting structure layer pattern may include:

[0136] A conductive film is deposited on the substrate 10 with the aforementioned pattern formed thereon, and the conductive film is patterned through a patterning process to form an anode pattern, and the anode is connected to the drain electrode through the anode via.

[0137] Subsequently, a pixel definition film is coated on the substrate 10 with the aforementioned pattern, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern. A pixel opening is opened on the pixel definition layer, and the pixel opening exposes the surface of the anode.

[0138] Subsequently, an organic light-emitting layer pattern is formed on the substrate 10 with the aforementioned pattern formed thereon by evaporation or inkjet printing, and the organic light-emitting layer is connected to the anode through the pixel opening.

[0139] Subsequently, a cathode pattern is formed on the substrate 10 with the aforementioned pattern by evaporation, and the cathode is connected to the organic light-emitting layer.

[0140] At this point, the light emitting structure layer pattern is completed. After this patterning process, the film layer structure of the binding pin area 206 does not change.

[0141] (4) Forming an encapsulation layer pattern on the light emitting structure layer. In an exemplary embodiment, forming the encapsulation layer pattern may include:

[0142] On the substrate 10 formed with the aforementioned pattern, a first encapsulation film is first deposited to form a first encapsulation layer. Then, an organic encapsulation film is formed by inkjet printing, and the organic encapsulation layer is formed after solidification. Then, a third encapsulation film is deposited to form a third encapsulation layer, forming an inorganic material / organic material / inorganic material laminated structure, in which the organic material layer is arranged between the two inorganic material layers, so as to ensure that external water vapor cannot enter the light-emitting structure layer.

[0143] At this point, the packaging layer pattern is completed. After this patterning process, the film layer structure of the binding pin area 206 does not change.

[0144] (5) Forming a touch electrode layer pattern on the encapsulation layer. In an exemplary embodiment, forming the touch electrode layer pattern may include:

[0145] A touch insulating film is deposited, and the touch insulating film is patterned by a patterning process to form a touch insulating (TLD) layer, wherein the touch insulating layer is formed with a touch via, a fourth via K4, and a fifth via K5, and the touch via is formed in an effective area, such as Fig.16As shown, the fourth via K4 and the fifth via K5 are formed in the binding pin area 206, the fourth via K4 is connected with the second via K2, the fifth via K5 is connected with the third via K3, the fourth via K4 and the second via K2 expose the surface of the first sub-binding pin 83a, and the fifth via K5 and the third via K3 expose the surface of the first sub-dummy pin 84b1. In an exemplary embodiment, the touch insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer.

[0146] Subsequently, a touch metal film is deposited, and the touch metal film is patterned by a patterning process to form a touch electrode layer pattern on the touch insulating layer. The touch electrode layer pattern at least includes a touch electrode and a touch wiring located in the effective area, a signal lead located in the frame area, and a second sub-binding pin 83b, a second sub-virtual pin 84b2 and a first virtual pin 84a located in the binding pin area 206. The touch electrode and the touch wiring are in the form of a metal mesh. The signal lead is connected to the signal electrode in the display unit through a touch via. The second sub-binding pin 83b is connected to the first sub-binding pin 83a through a fourth via K4 and a second via K2. The second sub-binding pin 83b and the first sub-binding pin 83a constitute a binding pin 83. The second sub-virtual pin 84b2 is connected to the first sub-virtual pin 84b1 through a fifth via K5 and a third via K3. The second sub-virtual pin 84b2 and the first sub-virtual pin 84b1 constitute a second virtual pin 84b, as shown in FIG. Figure 8 In an exemplary embodiment, the touch metal film may have a single-layer structure, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or may have a stacked-layer structure, such as Ti / Al / Ti.

[0147] Then, a protective film is coated to form a touch protection layer covering the touch electrode layer pattern. In an exemplary embodiment, the touch protection layer may be made of polyimide (PI) or the like. After this patterning process, the film structure of the binding pin area 206 remains unchanged.

[0148] At this point, the touch electrode layer pattern is completed.

[0149] like Figure 7 and Figure 8 As shown, in the embodiment of the present disclosure, the film layer stacking structures of the binding pin, the first virtual pin and the second virtual pin are similar, which reduces the relative step difference and avoids the problem of film layer peeling (Peeling) that is easy to occur in the process engineering.

[0150] In the embodiment of the present disclosure, the test signal line is routed using the first gate metal layer and the second gate metal layer instead of the first source and drain metal layer. This can reduce the height of the first virtual pin so that during the binding process, the test signal line at the bottom of the first virtual pin will not become a direct pressure point, thereby preventing it from being broken.

[0151] In the disclosed embodiment, second virtual pins are further provided on both sides of the first virtual pin. The second virtual pins are used to provide support during the binding process. The second virtual pins become direct pressure points in the binding process, further ensuring that the test signal line at the bottom of the first virtual pin will not be broken.

[0152] The structure of the display panel and its preparation process of the exemplary embodiment of the present disclosure are merely exemplary. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0153] In an exemplary embodiment, if Fig.17 As shown, the height of the second dummy pin 84 b away from the substrate 10 is greater than the height of the first dummy pin 84 a away from the substrate 10 .

[0154] The present disclosure also provides a method for preparing a display panel, wherein the display panel comprises an active area and a binding area located on one side of the active area; the binding area comprises a binding pin area, and the preparation method comprises:

[0155] A test signal line, a binding pin and a virtual pin are formed in the binding pin area, and the orthographic projection of at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the virtual pin on the substrate, and the orthographic projection of the virtual pin on the substrate does not overlap with the orthographic projection of the binding pin on the substrate.

[0156] In an exemplary embodiment, the virtual pin includes a first virtual pin and a second virtual pin, the orthographic projection of the first virtual pin on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate, the orthographic projection of at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the first virtual pin on the substrate, and the orthographic projection of the test signal line on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate.

[0157] In an exemplary embodiment, in a plane perpendicular to the display panel, the display panel includes: a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer, a third conductive layer disposed on the second conductive layer, and a fourth conductive layer disposed on the third conductive layer;

[0158] The test signal line is disposed in the same layer as at least one of the first conductive layer and the second conductive layer;

[0159] The first virtual pin is arranged on the same layer as the fourth conductive layer;

[0160] The binding pin and the second dummy pin are arranged in the same layer as the third conductive layer and the fourth conductive layer.

[0161] The present disclosure also provides a display device, including the display panel of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0162] The drawings in this application only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0163] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of this application.

Claims

1. A display panel, comprising a substrate, an effective area arranged on the substrate, and a binding area located on one side of the effective area; the binding area comprises a binding pin area, and the binding pin area comprises a binding pin, a dummy pin, and a test signal line; The orthographic projection of at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the virtual pin on the substrate, and the orthographic projection of the virtual pin on the substrate does not overlap with the orthographic projection of the binding pin on the substrate; The virtual pin includes a first virtual pin and a second virtual pin, the orthographic projection of the first virtual pin on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate, the orthographic projection of at least one test signal line on the substrate is located within the range of the orthographic projection of the first virtual pin on the substrate, and the orthographic projection of the test signal line on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate.

2. The display panel according to claim 1, wherein: The active area includes a substrate and a display unit and a touch unit stacked on the substrate, the display unit includes a plurality of data lines and a plurality of gate lines, the plurality of data lines and the plurality of gate lines intersect to define a plurality of sub-pixels, and the touch unit includes a plurality of touch electrodes and touch leads connected to the touch electrodes; The display panel also includes an array test area located on a side of the binding area away from the effective area, the array test area includes a test pin, the test signal line is connected to the test pin, and is configured to test one or more of the display unit and the touch unit.

3. The display panel according to claim 1, wherein: The width of the orthographic projection of the first virtual pin on the substrate along the first direction is equal to the width of the orthographic projections of the M test signal lines on the substrate along the first direction, the distance between two adjacent pins is greater than the width of the N test signal lines along the first direction, M is a natural number greater than or equal to 1, and N is a natural number greater than or equal to 1.

4. The display panel according to claim 3, wherein: M is 3 and N is 1.

5. The display panel according to claim 1, wherein: X first virtual pins are arranged between two second virtual pins, where x is a natural number between 1 and 3.

6. The display panel according to claim 1, wherein: A height of a side of the second dummy pin away from the substrate from the substrate is greater than a height of a side of the first dummy pin away from the substrate from the substrate.

7. The display panel according to claim 1, wherein: In a plane perpendicular to the display panel, the display panel comprises: a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer, a third conductive layer disposed on the second conductive layer, and a fourth conductive layer disposed on the third conductive layer; The test signal line is disposed in the same layer as at least one of the first conductive layer and the second conductive layer; The first virtual pin is arranged on the same layer as the fourth conductive layer; The binding pin and the second dummy pin are arranged in the same layer as the third conductive layer and the fourth conductive layer.

8. The display panel according to claim 7, wherein: In a plane perpendicular to the display panel, the display panel includes: a driving circuit layer, a light emitting structure layer, a packaging layer and a touch electrode layer stacked on the substrate in sequence, the driving circuit layer includes a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the substrate, and the touch electrode layer includes a touch insulating layer, a touch electrode layer and a touch protection layer stacked on the packaging layer; The first conductive layer is disposed on the same layer as the first gate metal layer, the second conductive layer is disposed on the same layer as the second gate metal layer, the third conductive layer is disposed on the same layer as the first source-drain metal layer, and the fourth conductive layer is disposed on the same layer as the touch electrode layer.

9. The display panel according to claim 7, wherein: The test signal line comprises: a first test signal line and a second test signal line, the first test signal line is located on the first conductive layer, and the second test signal line is located on the second conductive layer; The orthographic projection of the first test signal line on the substrate does not overlap with the orthographic projection of the second test signal line on the substrate, the first test signal line and the second test signal line extend along the second direction, the first test signal line and the second test signal line are alternately arranged along the first direction, and the first direction intersects with the second direction.

10. The display panel according to claim 9, wherein: The width of the first test signal line along the first direction is equal to the width of the second test signal line along the first direction, and the distances between adjacent first test signal lines and second test signal lines are equal.

11. The display panel according to claim 10, wherein: The width of the first test signal line along the first direction is between 7 micrometers and 17 micrometers, and the distance between adjacent first test signal lines and second test signal lines is between 8 micrometers and 18 micrometers.

12. The display panel according to any one of claims 1 to 11, wherein: The width of the binding pin along the first direction is equal to the width of the virtual pin along the first direction, and the distances between two adjacent pins are equal.

13. The display panel according to claim 12, wherein: The width of the binding pin along the first direction is between 45 micrometers and 75 micrometers, and the distance between two adjacent pins is between 25 micrometers and 55 micrometers.

14. The display panel according to claim 12, wherein: The length of the binding pin along the second direction is equal to the length of the dummy pin along the second direction, and the length of the binding pin along the second direction is between 900 micrometers and 1000 micrometers.

15. The display panel according to any one of claims 1 to 11 further includes a first power line and a second power line, the test signal lines include 2n lines, the binding pins include multiple first binding pins and multiple second binding pins, the multiple first binding pins are connected to the first power line, the multiple second binding pins are connected to the second power line, the 2n test signal lines are arranged between the multiple second binding pins, the multiple second binding pins are arranged between the multiple first binding pins, the 2n test signal lines are symmetrically arranged along the center line of the binding area, the multiple first binding pins are symmetrically arranged along the center line of the binding area, and the multiple second binding pins are symmetrically arranged along the center line of the binding area.

16. The display panel according to claim 15, wherein: On one side of the center line of the binding area, the n test signal lines are divided into at least two test signal line groups, and at least one dummy pin is arranged between two adjacent test signal line groups.

17. The display panel according to claim 16, wherein: The width of the orthographic projection of the test signal line group on the substrate along the first direction is between 150 micrometers and 300 micrometers.

18. A display device comprising the display panel according to any one of claims 1 to 17.

19. A method for preparing a display panel, the display panel comprising a substrate, an effective area arranged on the substrate, and a binding area located on one side of the effective area, the binding area comprising a binding pin area, the preparation method comprising: A test signal line, a binding pin and a virtual pin are formed in the binding pin area, the orthographic projection of at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the virtual pin on the substrate, and the orthographic projection of the virtual pin on the substrate does not overlap with the orthographic projection of the binding pin on the substrate; the virtual pin includes a first virtual pin and a second virtual pin, the orthographic projection of the first virtual pin on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate, at least one of the test signal lines on the substrate is located within the range of the orthographic projection of the first virtual pin on the substrate, and the orthographic projection of the test signal line on the substrate does not overlap with the orthographic projection of the second virtual pin on the substrate.

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