Method, device, computer device and readable storage medium for chip grading

Abstract

This disclosure provides a method, apparatus, computer device, and readable storage medium for chip grading. The method includes: acquiring chip probe test results and final test results of a test chip, wherein the chip probe test results include the measured values ​​of the test chip under each test item, and the final test result of the test chip is either a pass or a fail; determining a label for the test chip based on the final test result, wherein the label indicates a pass chip or a fail chip; obtaining a target control value based on the measured values ​​of the test chip under each test item and its label; acquiring chip probe test results of a chip to be graded, wherein the chip probe test results of the chip to be graded include the measured values ​​of the chip to be graded under each test item; and determining the target chip grade of the chip to be graded based on the measured values ​​of the chip to be graded under each test item and the target control value. The chip grading results obtained by the method of this disclosure are more objective and accurate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, and in particular to a method, apparatus, computer device, and readable storage medium for chip grading. Background Technology

[0002] After production, chips undergo testing to verify their quality. This testing includes chip probe testing to classify the chips. In actual chip probe testing, chip classification is often based on expert experience, which introduces subjective factors, thus requiring improvement in the objectivity and accuracy of the classification.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a method for chip grading, comprising: acquiring chip probe test results and final test results of a test chip, wherein the chip probe test results of the test chip include the measured values ​​of the test chip under each test item, and the final test result of the test chip is either a test pass or a test failure; determining a label for the test chip based on the final test result of the test chip, wherein the label is a test pass chip or a test failure chip; acquiring a target control value based on the measured values ​​of the test chip under each test item and its label; acquiring chip probe test results of a chip to be graded, wherein the chip probe test results of the chip to be graded include the measured values ​​of the chip to be graded under each test item; and determining a target chip grade of the chip to be graded based on the measured values ​​of the chip to be graded under each test item and the target control value.

[0005] According to some embodiments of this disclosure, obtaining a target control value based on the measured values ​​and labels of the test chip under each test item includes: obtaining the number of first test-failed chips in the test chip according to the label of the test chip; obtaining the first maximum measured value of the first test-failed chips in the test chip among the measured values ​​under each test item; obtaining a first filter value for each test item based on the first maximum measured value under each test item and the number of test chips; obtaining a first failure filter value for each test item based on the first maximum measured value under each test item and the number of first test-failed chips; obtaining a first boundary value for each test item based on the first filter value and the first failure filter value for each test item; and obtaining the target control value based on the first boundary value for each test item.

[0006] According to some embodiments of this disclosure, obtaining the target control value based on the first boundary value of each test item includes: obtaining the first maximum boundary value among the first boundary values ​​of each test item; taking the first maximum measurement value under the test item corresponding to the first maximum boundary value as the first candidate control value, and taking the test item corresponding to the first candidate control value as the first control test item; and determining the target control value based on the first candidate control value and its corresponding first control test item.

[0007] According to some embodiments of this disclosure, determining the target card control value based on the first candidate card control value and its corresponding first card control test item includes: determining the number of chips to be removed and the number of chips to be removed that failed the test among the measured values ​​of the test chips under the first card control test item that are greater than or equal to the first candidate card control value; obtaining a first failure screening ratio based on the number of chips removed and the number of chips to be removed that failed the test; and determining that the target card control value includes the first candidate card control value if the first failure screening ratio is greater than a preset threshold.

[0008] According to some embodiments of this disclosure, determining the target card control value based on the first candidate card control value and its corresponding first card control test item includes: determining a first screened chip from the test chips whose measured value under the first card control test item is greater than or equal to the first candidate card control value; obtaining the number of second test failure chips among the remaining test chips excluding the first screened chips; obtaining the second maximum measured value among the measured values ​​of the second test failure chips among the remaining test chips under each test item; obtaining a second filter value for each test item based on the second maximum measured value under each test item and the number of remaining test chips; obtaining a second failure filter value for each test item based on the second maximum measured value under each test item and the number of second test failure chips; obtaining a second boundary value for each test item based on the second filter value and the second failure filter value for each test item; and obtaining the target card control value based on the second boundary value for each test item.

[0009] According to some embodiments of this disclosure, obtaining the target control value based on the second boundary value of each test item includes: obtaining the second maximum boundary value among the second boundary values ​​of each test item; taking the second maximum measured value under the test item corresponding to the second maximum boundary value as the second candidate control value, and taking the test item corresponding to the second candidate control value as the second control test item; determining a second rejection chip from the remaining test chips whose measured value under the second control test item is greater than or equal to the second candidate control value; if all the test chips except the first rejection chip and the second rejection chip are test-passed chips, then determining the target control value based on the first candidate control value and the second candidate control value.

[0010] According to some embodiments of this disclosure, obtaining a first filter value for each test item based on a first maximum measured value under each test item and the number of test chips includes: obtaining the number of pre-screened chips among the test chips whose measured values ​​under each test item are greater than or equal to the first maximum measured value under the corresponding test item; and obtaining the first filter value for each test item based on the number of pre-screened chips under each test item and the number of test chips.

[0011] According to some embodiments of this disclosure, obtaining a first failure filter value for each test item based on a first maximum measured value under each test item and the number of test failure chips includes: obtaining the number of pre-screened test failure chips among the test failure chips whose measured values ​​under each test item are greater than or equal to the first maximum measured value under the corresponding test item; and obtaining a first failure filter value for each test item based on the number of pre-screened test failure chips under each test item and the total number of test failure chips.

[0012] According to some embodiments of this disclosure, determining the target chip level of the chip to be graded based on the measured values ​​of the chip under each test item and the target control value includes: determining the target test item corresponding to the target control value from the test items; obtaining the target measured value of the chip under the target test item from the measured values ​​of the chip under each test item; and determining the target chip level of the chip to be graded based on the target measured value and the target control value.

[0013] According to some embodiments of this disclosure, determining the target chip level of the chip to be graded based on the target measurement value and the target control value includes: determining the chip to be graded as a first-level chip whose target measurement value under the target test item is less than the target control value; and determining the remaining chips to be graded other than the first-level chips as second-level chips.

[0014] This disclosure also provides an apparatus for chip grading, including an acquisition unit, a determination unit, a processing unit, and a grading unit.

[0015] The acquisition unit is used to acquire the chip probe test results and the final test results of the test chip. The chip probe test results of the test chip include the measurement values ​​of the test chip under each test item, and the final test result of the test chip is either test pass or test failure.

[0016] The determining unit is used to determine the label of the test chip based on the final test result of the test chip, wherein the label is a chip that has passed the test or a chip that has failed the test.

[0017] The processing unit is used to obtain the target card control value based on the measured values ​​and labels of the test chip under each test item.

[0018] The acquisition unit is also used to acquire the chip probe test results of the chip to be graded, which include the measured values ​​of the chip under each test item.

[0019] The grading unit is used to determine the target chip grade of the chip to be graded based on the measured values ​​of the chip under each test item and the target control value.

[0020] According to some embodiments of this disclosure, the processing unit is further configured to: obtain the number of first test-failed chips in the test chip according to the label of the test chip; obtain the first maximum measurement value of the first test-failed chips in the test chip among the measurement values ​​under each test item; obtain a first filter value for each test item according to the first maximum measurement value under each test item and the number of test chips; obtain a first failure filter value for each test item according to the first maximum measurement value under each test item and the number of first test-failed chips; obtain a first boundary value for each test item according to the first filter value and the second failure filter value for each test item; and obtain the target card control value according to the first boundary value for each test item.

[0021] According to some embodiments of this disclosure, the processing unit is further configured to: obtain a first maximum boundary value among the first boundary values ​​of each test item; take the first maximum measurement value under the test item corresponding to the first maximum boundary value as a first candidate check control value, and take the test item corresponding to the first candidate check control value as a first check control test item; and determine the target check control value based on the first candidate check control value and its corresponding first check control test item.

[0022] This disclosure also provides a computer device, including a processor, a memory, and an input / output interface; the processor is connected to the memory and the input / output interface respectively, wherein the input / output interface is used to receive data and output data, the memory is used to store a computer program, and the processor is used to call the computer program so that the computer device executes the method described in any of the above embodiments.

[0023] This disclosure also provides a computer-readable storage medium storing a computer program adapted to be loaded and executed by a processor, such that a computer device having the processor performs the methods described in any of the above embodiments.

[0024] As can be seen from the above technical solutions, the chip classification method of this disclosure has at least one of the following advantages and positive effects:

[0025] In this embodiment, a target control value is obtained through training based on the measured values ​​and labels of the test chip under each test item. This target control value is then used to control the measured values ​​of the chip probes of the chip to be graded, thereby achieving grading. Since the target control value is obtained through objective analysis of a large amount of test data, it is objective and free from subjective factors. Using this target control value to grade the chip will yield a more objective and accurate grading result. Attached Figure Description

[0026] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0027] Figure 1 This is a flowchart illustrating a method for chip classification according to some embodiments of this disclosure;

[0028] Figure 2 This is a flowchart illustrating a method for obtaining a target control value based on measured values ​​and tags, as shown in some embodiments of this disclosure;

[0029] Figure 3 This is a schematic diagram illustrating the ratio of remaining chips for single-card control and multiple-card control, as shown in some embodiments of this disclosure;

[0030] Figure 4 This is a flowchart illustrating the optimization of candidate control values ​​according to some embodiments of this disclosure;

[0031] Figure 5 This is a block diagram illustrating an apparatus for chip grading according to some embodiments of this disclosure;

[0032] Figure 6 This is a schematic diagram of the structure of a computer device shown in some embodiments of this disclosure;

[0033] Figure 7 This is a schematic diagram of a computer-readable storage medium illustrating some embodiments. Detailed Implementation

[0034] The exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore their detailed description will be omitted.

[0035] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0036] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0037] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0038] After chip production, it undergoes testing to verify its quality. The main chip tests include chip probe testing and final testing. Chip probe testing primarily assesses the chip's electrical performance. Testing experts categorize each chip based on its test results, classifying chips with better electrical performance into higher grades and those with slightly worse performance into lower grades, ensuring that different grades of chips are used in products with varying electrical performance requirements. After chip probe testing and categorization, the chips are packaged and subjected to final testing. Final testing determines whether each chip passes the test, thus providing the final yield rate.

[0039] Since the classification of chips affects the development of subsequent chips, the classification is particularly important. However, in related technologies, each chip is classified based on the experience of testing experts, which involves subjective factors and affects the objectivity and accuracy of chip classification.

[0040] Based on this, embodiments of this disclosure provide a method for chip grading, which can classify chips more objectively and accurately. For example... Figure 1 As shown, the method for chip classification in this embodiment of the present disclosure includes steps S110 to S150.

[0041] S110: Obtain the chip probe test results and final test results of the test chip. The chip probe test results of the test chip include the measured values ​​of the test chip under each test item. The final test result of the test chip is either test pass or test failure.

[0042] In this embodiment, the test chip undergoes chip probing and final testing using testing methods from related technologies, classifying the chip into grades. For example, after chip probing, the chip is classified into grades 1 to 6. The chip probing can include multiple test items, such as test item 1 being a maximum temperature test, test item 2 a relatively high temperature test, test item 3 a low temperature test, and test item 4 a chip repair quantity test. The temperatures of the maximum temperature test, relatively high temperature test, and low temperature test decrease sequentially, and the specific test temperature values ​​can be set according to actual conditions. The repair quantity refers to the amount of performance repair performed on the chip during the testing process; this repair quantity can be recorded as a measurement value for the test item. After chip probing, the measurement value for each test item can be obtained, and the measurement values ​​for multiple test items are stored in a database.

[0043] The test items are not limited to the four mentioned above; there may be more or fewer. Those skilled in the art can select the required test items based on the chip and the actual test situation, without any special limitations here.

[0044] After the chips are classified, a final test is conducted. The final test result is either that the chip passes or fails the test, and the test result is stored in the database.

[0045] S120: Based on the final test results of the test chip, determine the label of the test chip, which is either a chip that passed the test or a chip that failed the test.

[0046] Data is extracted from the database and cleaned. The measured values ​​for each test item in the chip probe test results for each chip are integrated to provide the most intuitive representation of each test item and its measured value. Based on the final test results, each chip is labeled: chips that pass the test are labeled "Test Passed" (e.g., 1); chips that fail the test are labeled "Test Failed" (e.g., 0). Please refer to Table 1 below:

[0047] Table 1. Chip probe testing and final test results

[0048] Test Item 1 Test Item 2 Test item 3 …… Test item n Chip Tag 4 39 16 …… 16 1 5 24 11 …… 27 0 5 28 25 …… 20 0 …… …… …… …… …… 0

[0049] Table 1 shows the measurement values ​​after data integration and chip labeling. The number of chip probe tests is n, where n is a positive integer. The value under each test item represents the measurement value for that test item. The last column of the table shows the label assigned to the chip based on the final test results. To simplify the table, 1 represents a chip that passed the test, and 0 represents a chip that failed the test.

[0050] S130: Obtain the target control value based on the measured values ​​and labels of the test chip under each test item.

[0051] Based on the measured values ​​and labels in the above test results, obtain the target control value. For example... Figure 2 As shown, in some embodiments, S130 may include steps S210 to S260.

[0052] S210: Based on the label of the test chip, obtain the number of the first failed test chips in the test chip.

[0053] Specifically, as shown in Table 1 above, the number of chips with a chip label of 0 is counted; this number represents the number of chips that failed the first test. For a clearer explanation, please refer to Table 2.

[0054] Table 2. Chip probe testing and final test results

[0055] Test Item 1 Test Item 2 Test item 3 Test item 4 Chip Tag 4 39 16 16 1 5 24 11 27 0 5 28 10 20 0

[0056] Table 2 uses the first three rows of data from Table 1 and n=4 as an example for illustration. Therefore, according to Table 2, the number of first-failed chips is 2. In actual testing, the number of test chips may be in the tens of thousands, and the number of failed chips may be in the hundreds or thousands. For simplicity, in this embodiment, Table 2 only uses a few chips as examples for illustration.

[0057] S220: Obtain the first maximum measurement value among the measurement values ​​of the first failed test chip in the test chip under each test item.

[0058] Among them, the first failed test chip refers to the chip that failed the test among the test chips, and its label is the test failed chip, such as the chip with label 0 in Table 1 and Table 2.

[0059] As shown in Table 2, the first maximum measurement value of the chip that failed the first test was 5 in test item 1, 28 in test item 2, 11 in test item 3, and 27 in test item 4.

[0060] S230: Obtain the first filter value for each test item based on the first maximum measured value and the number of test chips.

[0061] The number of test chips refers to the total number of chips tested, including both those that passed and those that failed. In Table 2, the number of test chips is 3.

[0062] In some embodiments, S230 may include A1 to A2 as described below.

[0063] A1: Obtain the number of pre-screened chips whose measured values ​​under each test item are greater than or equal to the first maximum measured value under the corresponding test item in the test chip.

[0064] In S220, the first maximum measurement value of the first failed chip in each test item has been obtained. In each test item, test chips with measurement values ​​greater than or equal to the first maximum measurement value of that test item are selected. These test chips are called pre-screened chips, and the number of pre-screened chips is counted.

[0065] Taking Table 2 as an example, the first maximum measurement value of test item 1 is 5, and the measurement value greater than or equal to 5 is 5. Therefore, the chips to be pre-screened for test item 1 are the test failure chips corresponding to the second and third rows, and the number of chips to be pre-screened for test item 1 is 2. The first maximum measurement value of test item 2 is 28, and the measurement values ​​greater than or equal to 28 are 39 and 28. Therefore, the chips to be pre-screened for test item 2 are the test pass chips corresponding to the first row and the test failure chips corresponding to the third row, and the number of chips to be pre-screened for test item 2 is 2. The first maximum measurement value of test item 3 is 11, and the measurement values ​​greater than or equal to 11 are 16 and 11. Therefore, the chips to be pre-screened for test item 3 are the test pass chips corresponding to the first row and the test failure chips corresponding to the second row, and the number of chips to be pre-screened for test item 3 is 2. The first maximum measurement value of test item 4 is 27, and the measurement value greater than or equal to 27 is 27. Therefore, the chips to be pre-screened for test item 4 are the test failure chips corresponding to the second row, and the number of chips to be pre-screened for test item 3 is 1.

[0066] A2: Based on the number of pre-screened chips and the number of test chips under each test item, obtain the first filter value for each test item.

[0067] In some embodiments, the first filter value for each test item is the ratio of the number of pre-screened chips to the number of test chips under each test item. Let ΔY represent the first filter value, R represent the number of pre-screened chips under each test item, and T represent the number of test chips. The first filter value can then be obtained using the following formula (1):

[0068]

[0069] In Table 2, the first filter value of test item 1 is ΔY1 = 2 / 3 = 1, the first filter value of test item 2 is ΔY2 = 2 / 3, the first filter value of test item 3 is ΔY3 = 2 / 3, and the first filter value of test item 4 is ΔY4 = 1 / 3.

[0070] S240: Based on the first maximum measured value and the number of chips that failed the first test under each test item, obtain the first failure filter value under each test item.

[0071] In some embodiments, S240 may include the following contents B1 to B2.

[0072] B1: Among the failed test chips, the number of chips that have been pre-screened and whose measured values ​​under each test item are greater than or equal to the first maximum measured value under the corresponding test item.

[0073] In other words, from the measured values ​​of the failed chips under each test item, select the failed chips that are greater than or equal to the first maximum measured value under that test item, and call the failed chips pre-screened as failed test chips, and count the number of pre-screened failed test chips.

[0074] In Table 2, the first maximum measurement value for test item 1 is 5. The number of pre-screened failed test chips greater than or equal to 5 is 2. Therefore, the pre-screened failed test chips for test item 1 are the failed test chips corresponding to the second and third rows. The first maximum measurement value for test item 2 is 28. The number of pre-screened failed test chips greater than or equal to 28 is 1. Therefore, the pre-screened failed test chips for test item 2 are the failed test chips corresponding to the third row. The first maximum measurement value for test item 3 is 11. The number of pre-screened failed test chips greater than or equal to 11 is 1. Therefore, the pre-screened failed test chips for test item 3 are the failed test chips corresponding to the second row. The first maximum measurement value for test item 4 is 27. The number of pre-screened failed test chips greater than or equal to 27 is 1. Therefore, the pre-screened failed test chips for test item 4 are the failed test chips corresponding to the second row.

[0075] B2: Based on the number of chips that failed the test and the number of chips that failed the test under each test item, obtain the first failure filter value for each test item.

[0076] In some embodiments, the first failure filter value for each test item is the ratio of the number of pre-screened failed test chips to the total number of failed test chips under each test item. Let ΔF represent the first failure filter value, R0 represent the number of pre-screened failed test chips under each test item, and R represent the total number of failed test chips. f If this is true, then the first failure filter value can be obtained by the following formula (2):

[0077]

[0078] In Table 2, the first failure filter value ΔF1 = 2 / 2 = 1 for test item 1, the first failure filter value ΔF2 = 1 / 2 for test item 2, the first failure filter value ΔF3 = 1 / 2 for test item 3, and the first failure filter value ΔF4 = 1 / 2 for test item 4.

[0079] S250: Obtain the first boundary value of each test item based on the first filter value and the first failure filter value of each test item.

[0080] In some embodiments, the first threshold value for each test item is the ratio of the first failure filter value ΔF to the first filter value ΔY under the corresponding test item. Let ΔL represent the first threshold value, then the first threshold value can be obtained by the following formula (3):

[0081]

[0082] In Table 2, the first boundary value of test item 1 is ΔL1 = 3 / 2, the first boundary value of test item 2 is ΔL2 = 3 / 4, the first boundary value of test item 3 is ΔL3 = 3 / 4, and the first boundary value of test item 1 is ΔL4 = 3 / 2.

[0083] S260: Obtain the target control value based on the first boundary value of each test item.

[0084] In some embodiments, S260 may include the following contents C1 to C3.

[0085] C1: Obtain the first maximum boundary value among the first boundary values ​​of each test item.

[0086] The first maximum boundary value is the largest of the first boundary values ​​under all test items. As shown in S250, the first maximum boundary value is 3 / 2, which is the first boundary value corresponding to test item 1 and test item 4.

[0087] C2: Take the first maximum measured value under the test item corresponding to the first maximum boundary value as the first candidate control value, and take the test item corresponding to the first candidate control value as the first control test item.

[0088] For example, in Table 2, the test items corresponding to the first maximum threshold value are test item 1 and test item 4. The first maximum measurement value of test item 1 is 5, so 5 can be used as the first candidate control value, and test item 1 can be used as the first control test item. The first maximum measurement value of test item 4 is 27, so 27 can also be used as the first candidate control value, and test item 4 can be used as the first control test item.

[0089] C3: Determine the target control value based on the first candidate control value and its corresponding first control test item.

[0090] In some embodiments, determining the target card control value in C3 based on the first candidate card control value and its corresponding first card control test item may further include the following contents C31 to C37.

[0091] C31: The first screening chip determined from the test chips whose measured value under the first card control test item is greater than or equal to the first candidate card control value.

[0092] The first screened chip refers to the test chip whose measured value is greater than or equal to the first candidate card control value under the first card control test item. The first screened chip can be a chip that passes the test or a chip that fails the test, as long as its measured value is greater than or equal to the first candidate card control value.

[0093] For example, in Table 2, if the first control test item is selected as test item 1, and the first candidate control value is 5, then the test chips with a measured value greater than or equal to 5 are the test failure chips in the second and third rows. These test failure chips are the first screened-out chips. These first screened-out chips are then removed. See Table 3 for reference.

[0094] Table 3 shows the test results after removing the first-stage screened chips.

[0095] Test Item 1 Test Item 2 Test item 3 Test item 4 Chip Tag 4 39 16 16 1 / / / / / / / / / /

[0096] If the first control test item is selected as test item 4, and the first candidate control value is 27, then the test chips with a measured value greater than or equal to 27 are the test failure chips in the second row, and these test failure chips are the first screened-out chips. These first screened-out chips are then removed. See Table 4 for reference.

[0097] Table 4. Test results after removing the first screened-out chips.

[0098] Test Item 1 Test Item 2 Test item 3 Test item 4 Chip Tag 4 39 16 16 1 / / / / / 5 28 10 20 0

[0099] C32: Get the number of second test failure chips among the remaining test chips excluding the first screened chips.

[0100] Since the failed chips have been completely screened out in Table 3, only the chips that passed the test remain. For ease of explanation, the following description of the embodiments of this disclosure will use the data in Table 4 as an example.

[0101] The second failed test chip refers to the test chip that failed to pass the test after the first rejected chip was removed.

[0102] Referring to Table 4, among the remaining test chips, the number of chips that failed the test is 1, that is, the number of chips that failed the second test is 1.

[0103] C33: Obtain the second maximum measured value among the measured values ​​of the second failed test chip in the remaining test chips under each test item.

[0104] This step is similar to S220. As shown in Table 4, the second maximum measurement value of the second test failure chip is 5 in test item 1, 28 in test item 2, 10 in test item 3, and 20 in test item 4.

[0105] C34: Obtain the second filter value for each test item based on the second maximum measured value under each test item and the number of remaining test chips.

[0106] The second filter value has the same meaning as the first filter value, which is the ratio of the number of pre-screened chips to the number of test chips under each test item. In Table 4, the number of remaining test chips is 2. Specifically, among the remaining test chips, the number of pre-screened chips whose measured values ​​under each test item are greater than or equal to the second maximum measured value under the corresponding test item is obtained.

[0107] As shown in Table 4, the second maximum measurement value of the chip that failed the second test in test item 1 is 5. Since the measurement value is greater than or equal to 5, the chip pre-screened for test item 1 is the chip that failed the test, and the number of chips pre-screened for test item 1 is 1. The second maximum measurement value of test item 2 is 28. Since the measurement values ​​are greater than or equal to 28, there are 28 and 39. Therefore, the chips pre-screened for test item 2 are the chip that passed the test and the chip that failed the test, and the number of chips pre-screened for test item 2 is 2. The second maximum measurement value of test item 3 is 10. Since the measurement values ​​are greater than or equal to 10, there are 10 and 16. Therefore, the chips pre-screened for test item 3 are the chip that passed the test and the chip that failed the test, and the number of chips pre-screened for test item 3 is 2. The second maximum measurement value of test item 4 is 20. Since the measurement value is greater than or equal to 20, there is 20. Therefore, the chip pre-screened for test item 4 is the chip that failed the test, and the number of chips pre-screened for test item 4 is 1.

[0108] Based on the number of pre-screened chips and the number of remaining test chips under each test item, obtain the second filter value for each test item.

[0109] Specifically, the second filter value is the ratio of the number of pre-screened chips to the number of remaining test chips under each test item. Referring to the above calculation formula (1), the second filter value of test item 1 is 1 / 2, the second filter value of test item 2 is 1, the second filter value of test item 3 is 1, and the second filter value of test item 4 is 1 / 2.

[0110] C35: Obtain the second failure filter value for each test item based on the second maximum measured value and the number of chips that failed the second test.

[0111] The second failure filter value has the same meaning as the first failure filter value. That is, it is the ratio of the number of pre-screened failed chips to the number of failed chips in the remaining chips for each test item.

[0112] Among the failed test chips, the number of chips that are pre-screened out from those whose measured values ​​under each test item are greater than or equal to the second maximum measured value under the corresponding test item.

[0113] As shown in Table 4, since only one test failure chip remains, the number of pre-screened test failure chips with a value greater than or equal to the second maximum measurement value under each test item is 1. Since the number of test failure chips among the remaining chips is also 1, the second failure filter value under each test item is 1.

[0114] C36: Obtain the second boundary value of each test item based on the second filter value and the second failure filter value of each test item.

[0115] The meaning of the second cutoff value is the same as that of the first cutoff value. The second cutoff value for each test item is the ratio of the second failure filter value to the second filter value for that test item. For test item 1, the second failure filter value is 1, the second filter value is 1 / 2, and its second cutoff value is 2. For test item 2, the second failure filter value is 1, the second filter value is 1, and its second cutoff value is 1. For test item 3, the second failure filter value is 1, the second filter value is 1, and its second cutoff value is 1. For test item 4, the second failure filter value is 1, the second filter value is 1 / 2, and its second cutoff value is 2.

[0116] C37: Obtain the target control value based on the second boundary value of each test item.

[0117] In some embodiments, C37 may include the following contents C371 to C374.

[0118] C371: Obtain the second maximum boundary value among the second boundary values ​​of each test item.

[0119] Specifically, the second maximum boundary value among the second boundary values ​​of each test item is obtained. The second maximum boundary value refers to the maximum value among the second boundary values. As shown in C36, the second maximum boundary value is 2, corresponding to test item 1 and test item 4.

[0120] C372: The maximum measured value under the test item corresponding to the second maximum threshold value is taken as the second candidate control value, and the test item corresponding to the second candidate control value is taken as the second control test item.

[0121] In Table 4, the test items corresponding to the second maximum threshold value are test item 1 and test item 4. The first maximum measurement value of test item 1 is 5, so 5 can be used as the second candidate control value, and test item 1 can be used as the second control test item. The first maximum measurement value of test item 4 is 20, so 20 can also be used as the second candidate control value, and test item 4 can be used as the second control test item.

[0122] C373: Determine the second screened chip from the remaining test chips whose measured value under the second control test item is greater than or equal to the second candidate control value.

[0123] The second screened chip refers to the test chip whose measured value is greater than or equal to the second candidate control value under the second control test item. This second screened chip can be a chip that passes the test or a chip that fails the test, as long as its measured value is greater than or equal to the second candidate control value.

[0124] In Table 4, regardless of whether test item 1 or test item 4 is selected as the second card control test item, the second screened chip is the test failure chip in the table, and the second screened chip is screened out.

[0125] C374: If all the chips in the test except for the first and second screened chips are chips that have passed the test, then the target control value is determined based on the first candidate control value and the second candidate control value.

[0126] As shown in Table 4, after the second screening chip is removed, only one chip that passes the test remains. In other words, after the above-mentioned screening of candidate chip control values, only the chip that passes the test remains. Therefore, the above screening is no longer performed, and the first and second candidate chip control values ​​are the final candidate chip control values.

[0127] Of course, Table 4 is just an example. In actual testing, there may be hundreds, thousands, or even tens of thousands of chips being tested. The method described above for obtaining the first and second candidate control values ​​will be used to continue controlling the chips until the Nth candidate control value (N is a positive integer greater than 2) is obtained. This process continues until all failed chips are eliminated and only chips that have passed the test remain. Please refer to Table 5 below.

[0128] Table 5: Multiple Control Record Values

[0129] Test Items Maximum measurement value Pre-screened wafers Failed wafers ratio Single card remaining ratio Multicalorie Remaining Ratio Test Item 1 3168 1 1 100 99.99995 99.99995 Test Item 2 1988 1 1 100 99.99995 99.99991 Test item 3 421 1 1 100 99.99995 99.99986 Test item 4 580 1 1 100 99.99995 99.99982 Test item 5 -632 1 1 100 99.99995 99.99977 Test item 6 1000 1 1 100 99.99995 99.99973 Test item 7 1000 1 1 100 99.99995 99.99973 …….. …….. …….. …….. …….. …….. …….. …….. …….. …….. …….. …….. …….. …….. Test item 39 16317 1 1 100 99.99995 99.99872 Test item 40 2621 1 1 100 99.99995 99.99872 Test item 41 145 1 1 100 99.99995 99.99867 Test item 42 41 1 1 100 99.99995 99.99863 Test item 43 1367.9 1 1 100 99.99995 99.99858 Test item 44 5 3 3 100 99.99986 99.99845 Test item 45 716 3 2 67 99.99986 99.99831 Test item 46 2 4 3 75 99.99982 99.99813 Test item 47 0.75 6 5 83 99.99973 99.99785 Test item 48 8 12 8 67 99.99945 99.99730 Test item 49 3 85 74 87 99.99612 99.99342 Test Item 50 5 543 357 66 99.97519 99.96865 Test item 51 10.5 1230 938 76 99.94380 99.91268 Test item 52 6 7971 6531 82 99.63578 99.55162 Test item 53 195 8800 7288 83 99.59790 99.15281 Test item 54 4 8991 8390 93 99.58918 98.75844 Test item 55 4 14887 12003 81 99.31977 98.45344 Test item 56 105 20957 13758 66 99.04242 97.90366

[0130] As shown in Table 5 and Figure 3As shown in Table 5, the maximum measured value is the highest measured value among the failed chips under each test item, which can be understood as the first maximum measured value mentioned above. Pre-screened chips are chips whose measured value under each test item is greater than or equal to the corresponding first maximum measured value. Failed chips are test-failed chips whose measured value under each test item is greater than or equal to the corresponding first maximum measured value; here, failed chips can be understood as the pre-screened failed chips mentioned above. The ratio is the ratio of failed chips to pre-screened chips, that is, the proportion of failed chips among the pre-screened chips whose measured value is greater than or equal to the first maximum measured value. The single-card remaining ratio is the proportion of chips remaining after control using the maximum measured value of the corresponding test item. The multi-card remaining ratio refers to the proportion of chips remaining after further control using the candidate control values ​​obtained by the above method. (Based on Table 5 and...) Figure 3 It can be seen that using candidate control values ​​can increase the probability of failing chips being eliminated, resulting in more objective and accurate results.

[0131] All the candidate card control values ​​obtained can be used to classify the chips to be classified. In other words, these candidate card control values ​​can be used as target card control values ​​to classify the chips to be classified.

[0132] Since the number of test chips in actual testing is huge, the number of candidate card control values ​​may be large. Therefore, it is necessary to optimize the candidate card control values, that is, to select the target card control value that can be more accurately classified from multiple candidate card control values.

[0133] In some embodiments, such as Figure 4 As shown, in step C3 of S260, the target card control value is determined based on the first candidate card control value and its corresponding first card control test item, including the following steps S410 to S430.

[0134] S410: Determine the number of chips to be removed and the number of chips to be removed that failed the test, based on the measured values ​​of the first card control test item.

[0135] Here, "removing chips" can be understood as test chips under the first card control test item whose measured value is greater than or equal to the first candidate card control value. This removal of chips can include chips that passed the test and chips that failed the test. Removing test-failed chips can be understood as measurement-failed chips under the first card control test item whose measured value is greater than or equal to the first candidate card control value.

[0136] For example, in Table 2, the first card control test item is test item 1, and the first candidate card control value is 5. Then, in the test item, the number of chips to be removed is 2, and the number of chips to be removed that failed the test is 2.

[0137] S420: Obtain the first failure screening ratio based on the number of chips removed and the number of chips that failed the test.

[0138] In some embodiments, the first failure screening ratio is the ratio of the number of chips that failed to be removed in the first card control test item to the number of chips that were removed.

[0139] In Table 2, the first failure screening ratio for the first card control test item is 1.

[0140] S430: If the first failure screening ratio is greater than the preset threshold, then the target control value is determined to include the first candidate control value.

[0141] In some embodiments, the preset threshold can be 40% to 80%. Specifically, in addition to the two values ​​mentioned above, the preset threshold can also be 45%, 48%, 50%, 55%, 60%, 65%, 70%, or 75%. Those skilled in the art can choose according to the actual situation, and no special limitation is made here. If the first failure screening ratio is greater than the preset threshold, it indicates that the first candidate control value can screen out more test failure chips, and the candidate control value can be used as the target control value.

[0142] In one embodiment, if a preset threshold of 50% is selected, the first failure screening ratio in Table 2 is 100%. If the first failure screening ratio is greater than 50%, the first candidate control value 5 can be used as the target control value.

[0143] Following the method described above, the second candidate control values ​​are filtered to determine if their corresponding second failure screening ratio is greater than a preset threshold. If it is, it is retained as the target control value; otherwise, it is deleted and not used as a target control value. Of course, if there are other candidate control values, the relationship between the failure screening value corresponding to the threshold and the preset threshold can be determined using the same method. The candidate control values ​​that ultimately exceed the preset threshold are retained as the final target control values.

[0144] By determining whether the failure screening ratio is greater than a preset threshold, it can be determined whether a candidate control value can be used as a target control value. In other words, the candidate control values ​​are optimized, retaining only those test items with a failure screening ratio greater than the preset threshold. This optimization of candidate control values ​​allows for the selection of more precise target control values. Using these target control values ​​to classify the chips to be graded enables more objective and accurate grading.

[0145] In some embodiments, if there are multiple target control values, the target control value with the largest failure screening ratio can be used preferentially for grading the chip to be graded.

[0146] S140: Obtain the chip probe test results of the chip to be graded. The chip probe test results of the chip to be graded include the measured values ​​of the chip under each test item.

[0147] After obtaining the target control value, the chip to be graded can be graded. Before grading, chip probe testing is performed on the chip to be graded, and the results of the chip probe testing are obtained. These results include the measured values ​​of the chip to be graded under each test item. Specifically, this may include the following contents D1 to D3.

[0148] D1: Determine the target test item corresponding to the target control value from the test items.

[0149] Specifically, if the test item corresponding to the target control value is test item 1, then test item 1 is taken as the target test item. In other words, the test item corresponding to the target control value is the target test item.

[0150] D2: Obtain the target measurement value of the chip to be graded under the target test item from the measurement values ​​of the chip under each test item;

[0151] D3: Determine the target chip grade of the chip to be graded based on the target measurement value and the target control value.

[0152] S150: Determine the target chip grade of the chip to be graded based on the measured values ​​and target control values ​​of the chip under each test item.

[0153] Specifically, the chips to be graded are identified as first-level chips whose target measurement values ​​under the target test items are less than the target control values; the remaining chips to be graded, excluding the first-level chips, are identified as second-level chips.

[0154] After the chips are graded, they undergo final testing to identify chips that pass and chips that fail. The yield of each grade is determined based on the number of chips that pass and fail. Please refer to the table below, which shows the yield of chips after grading using the target control value of this disclosure embodiment and the yield of chips after grading in related technologies.

[0155] Table 6. Test results after chip grading using target control values.

[0156] grade Number of wafers ratio Yield A 1306499 99.3％ 97.3％ B 8560 0.7％ 59.5％

[0157] Table 7. Test results after chip grading using target control values.

[0158] grade Number of wafers ratio Yield A 559845 99.33％ 97.35％ B 3753 0.67％ 59.3％

[0159] Table 8 shows the test results after chip grading in related technologies.

[0160] grade Number of wafers ratio Yield A 554493 98.4％ 97.4％ B 9105 1.62％ 80.3％

[0161] Tables 6 and 7 show the results of grading chips using the target control values ​​obtained through the methods of this disclosure and conducting final testing on the graded chips. Table 8 shows the results of grading chips based on expert experience and conducting final testing on the graded chips in related technologies. In the tables, "ratio" represents the percentage of chips of different grades after grading, and "yield" represents the yield of chips of each grade.

[0162] As shown in Tables 6, 7, and 8, after classifying the chips using the target control values ​​of this disclosure, the proportion of high-grade chips is slightly higher than that in Table 8, and the yield of high-grade chips is basically the same as that in Table 8. This indicates that using the target control values ​​of this disclosure can more accurately classify chips that are actually high-grade into high-grade categories, that is, it reduces the probability of classifying high-grade chips as low-grade chips, making the classification more accurate. Therefore, the yield of low-grade chips will be lower in Tables 6 and 7.

[0163] In summary, in this embodiment, since the target control value is obtained through objective analysis of a large amount of test data, it is objective and free from subjective factors. Using this target control value to classify chips yields more objective and accurate classification results. This allows chips of different grades to be applied to devices with different performance requirements, improving chip utilization.

[0164] This disclosure also provides an apparatus 500 for chip classification, such as... Figure 5 As shown, the device 500 includes an acquisition unit 501, a determination unit 502, a processing unit 503, and a classification unit 504.

[0165] The acquisition unit 501 is used to acquire the chip probe test results and the final test results of the test chip. The chip probe test results of the test chip include the measured values ​​of the test chip under each test item, and the final test result of the test chip is either test pass or test failure.

[0166] The determining unit 502 is used to determine the label of the test chip based on the final test result of the test chip. The label is either a chip that passed the test or a chip that failed the test.

[0167] The processing unit 503 is used to obtain the target card control value based on the measured value and label of the test chip under each test item.

[0168] The acquisition unit 501 is also used to acquire the chip probe test results of the chip to be graded, which include the measured values ​​of the chip under each test item.

[0169] The grading unit 504 is used to determine the target chip grade of the chip to be graded based on the measured values ​​and target control values ​​of the chip under each test item.

[0170] In some embodiments, the processing unit 503 is further configured to: obtain the number of first test failure chips in the test chip according to the label of the test chip; obtain the first maximum measurement value of the first test failure chips in the test chip among the measurement values ​​under each test item; obtain the first filter value of each test item according to the first maximum measurement value under each test item and the number of test chips; obtain the first failure filter value of each test item according to the first maximum measurement value under each test item and the number of first test failure chips; obtain the first boundary value of each test item according to the first filter value of each test item and the second failure filter value of each test item; and obtain the target control value according to the first boundary value of each test item.

[0171] In some embodiments, the processing unit 503 is further configured to obtain a first maximum boundary value among the first boundary values ​​of each test item; take the maximum measurement value under the test item corresponding to the first maximum boundary value as a first candidate control value, and take the test item corresponding to the first candidate control value as a first control test item; and determine the target control value based on the first candidate control value and its corresponding first control test item.

[0172] In some embodiments, the processing unit 503 is further configured to determine the number of chips to be removed and the number of chips to be removed that failed the test, among the measured values ​​of the first card control test item; to obtain a first failure screening ratio based on the number of chips removed and the number of chips to be removed that failed the test; and to determine that the target card control value includes the first candidate card control value if the first failure screening ratio is greater than a preset threshold.

[0173] In some embodiments, the processing unit 503 is further configured to: determine a first screened chip whose measured value under a first control test item is greater than or equal to a first candidate control value; obtain the number of second test failure chips among the remaining test chips excluding the first screened chips; obtain the second maximum measured value among the measured values ​​of the second test failure chips among the remaining test chips under each test item; obtain a second filter value for each test item based on the second maximum measured value under each test item and the number of remaining test chips; obtain a second failure filter value for each test item based on the second maximum measured value under each test item and the second test failure chip number; obtain a second boundary value for each test item based on the second filter value and the second failure filter value for each test item; and obtain a target control value based on the second boundary value for each test item.

[0174] In some embodiments, the processing unit 503 is further configured to obtain the second maximum boundary value among the second boundary values ​​of each test item; take the maximum measured value under the test item corresponding to the second maximum boundary value as the second candidate control value, and take the test item corresponding to the second candidate control value as the second control test item; determine the second screening chip from the remaining test chips whose measured value under the second control test item is greater than or equal to the second candidate control value; if all the test chips except the first screening chip and the second screening chip are test-passed chips, then determine the target control value according to the first candidate control value and the second candidate control value.

[0175] In some embodiments, the processing unit 503 is further configured to obtain the number of pre-screened chips in the test chip whose measured values ​​under each test item are greater than or equal to the first maximum measured value under the corresponding test item; and to obtain the first filter value of each test item based on the number of pre-screened chips under each test item and the number of test chips.

[0176] In some embodiments, the processing unit 503 is further configured to obtain the number of pre-screened test failure chips among the measured values ​​of each test item that are greater than or equal to the maximum measured value of the corresponding test item; and to obtain the first failure filter value of each test item based on the number of pre-screened test failure chips and the number of test failure chips.

[0177] In some embodiments, the grading unit 504 is further configured to determine the target test item corresponding to the target control value from the test items; obtain the target measurement value of the chip to be graded under the target test item from the measurement values ​​of the chip to be graded under each test item; and determine the target chip grade of the chip to be graded based on the target measurement value and the target control value.

[0178] In some embodiments, the grading unit 504 is further configured to determine first-level chips whose target measurement values ​​under the target test item are less than the target control value; and to determine the remaining chips to be graded, excluding the first-level chips, as second-level chips.

[0179] In summary, the target card control value obtained by the device in this embodiment is derived from the objective analysis of a large amount of test data. Therefore, the target card control value is objective and free from subjective factors. Using the target card control value to classify the chip to be classified will result in a more objective and accurate classification result.

[0180] This disclosure also provides a computer device. For example... Figure 6 As shown, the computer device in this embodiment may include one or more processors 601, a memory 602, and an input / output interface 603. The processor 601 is connected to the memory 602 and the input / output interface 603, respectively. Figure 6As shown, the processor 601, memory 602, and input / output interface 603 are connected via a bus 604. The memory 602 stores computer programs, including program instructions. The input / output interface 603 receives and outputs data, such as for data interaction between the host machine and computer devices, or for data interaction between various virtual machines within the host machine. The processor 601 executes the program instructions stored in the memory 602.

[0181] The processor 601 can perform the following operations: acquire the chip probe test results and final test results of the test chip, wherein the chip probe test results of the test chip include the measured values ​​of the test chip under each test item, and the final test result of the test chip is either a pass or a fail; determine the label of the test chip based on the final test result of the test chip, wherein the label is a pass chip or a fail chip; acquire the target control value based on the measured values ​​of the test chip under each test item and its label; acquire the chip probe test results of the chip to be graded, wherein the chip probe test results of the chip to be graded include the measured values ​​of the chip to be graded under each test item; and determine the target chip grade of the chip to be graded based on the measured values ​​of the chip to be graded under each test item and the target control value.

[0182] In some feasible implementations, the processor 601 may be a central processing unit (CPU) 1620. The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0183] The memory 602 may include read-only memory and random access memory, and provides instructions and data to the processor 601 and the input / output interface 603. A portion of the memory 602 may also include non-volatile random access memory. For example, the memory 602 may also store device type information.

[0184] In practice, the computer device can execute the implementation methods provided by each step in any of the above method embodiments through its built-in functional modules. For details, please refer to the implementation methods provided by each step in the figure shown in the above method embodiments, which will not be repeated here.

[0185] This disclosure provides a computer device including a processor 601, an input / output interface 603, and a memory 602. The processor 601 retrieves a computer program from the memory 602 and executes the steps of the method shown in any of the above embodiments.

[0186] This disclosure also provides a computer-readable storage medium 700, such as... Figure 7 As shown, the computer-readable storage medium 700 stores a computer program that is adapted to be loaded by the processor 601 and executed by the method for chip classification provided in each step of any of the above embodiments. For details, please refer to the implementation of each step in any of the above embodiments, which will not be repeated here.

[0187] Furthermore, the beneficial effects of using the same method will not be repeated here. For technical details not disclosed in the embodiments of the computer-readable storage medium involved in this disclosure, please refer to the description of the method embodiments of this disclosure. As an example, a computer program may be deployed to execute on a single computer device, or on multiple computer devices located in one location, or on multiple computer devices distributed in multiple locations and interconnected via a communication network.

[0188] The computer-readable storage medium 700 can be an internal storage unit of the computer device provided in any of the foregoing embodiments, such as a hard disk or memory of the computer device. The computer-readable storage medium 700 can also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., provided on the computer device. Further, the computer-readable storage medium 1000 can include both internal and external storage units of the computer device. The computer-readable storage medium 700 is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium 700 can also be used to temporarily store data that has been output or will be output.

[0189] This disclosure also provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium 700. A processor of a computer device reads the computer instructions from the computer-readable storage medium 700 and executes the computer instructions, causing the computer device to perform the methods provided in various alternative embodiments described above.

[0190] The computer device, computer-readable storage medium, and computer program product or computer program provided in this disclosure obtain target control values ​​through training based on the measured values ​​and labels of the test chip under each test item. These target control values ​​are then used to control the measured values ​​of the chip probes of the chip to be graded, thereby achieving grading. Since the target control values ​​are obtained through objective analysis of a large amount of test data, they are objective and free from subjective factors. Therefore, using these target control values ​​to grade the chip results in a more objective and accurate grading outcome.

[0191] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to utilize this disclosure.

Claims

1. A method for chip classification, characterized in that, include: Obtain the chip probe test results and final test results of the test chip. The chip probe test results of the test chip include the measured values ​​of the test chip under each test item. The final test result of the test chip is either test pass or test failure. Based on the final test results of the test chip, the label of the test chip is determined, and the label indicates whether the chip passed the test or failed the test. Based on the measured values ​​and labels of the test chip under each test item, the target card control value is obtained; Obtain the chip probe test results of the chip to be graded, wherein the chip probe test results of the chip to be graded include the measured values ​​of the chip under each test item; The target chip grade of the chip to be graded is determined based on the measured values ​​of the chip under each test item and the target control value. Specifically, the target card control value is obtained based on the measured values ​​and labels of the test chip under each test item, including: Based on the label of the test chip, obtain the number of the first test failure chips among the test chips; Obtain the first maximum measured value among the measured values ​​of the first failed test chip in the test chips under each test item; Based on the first maximum measured value under each test item and the number of test chips, obtain the first filter value for each test item; Based on the first maximum measured value under each test item and the number of chips that failed the first test, obtain the first failure filter value under each test item; Based on the first filter value of each test item and the first failure filter value of each test item, obtain the first boundary value of each test item; The target control value is obtained based on the first boundary value of each test item.

2. The method according to claim 1, characterized in that, Based on the first boundary value of each test item, the target control value is obtained, including: Obtain the first maximum boundary value among the first boundary values ​​of each test item; The first maximum measured value under the test item corresponding to the first maximum boundary value is taken as the first candidate control value, and the test item corresponding to the first candidate control value is taken as the first control test item; The target card control value is determined based on the first candidate card control value and its corresponding first card control test item.

3. The method according to claim 2, characterized in that, Determining the target card control value based on the first candidate card control value and its corresponding first card control test item includes: Determine the number of chips to be removed and the number of chips to be removed that failed the test, based on the measured values ​​of the first card control test item that are greater than or equal to the first candidate card control value. Based on the number of chips removed and the number of chips that failed the removal test, a first failure screening ratio is obtained; If the first failure screening ratio is greater than a preset threshold, then the target control value is determined to include the first candidate control value.

4. The method according to claim 2, characterized in that, Determining the target card control value based on the first candidate card control value and its corresponding first card control test item includes: The first screened chip is determined from the test chips whose measured value under the first card control test item is greater than or equal to the first candidate card control value; Obtain the number of second test failure chips among the remaining test chips excluding the first screened chips; Obtain the second maximum measured value among the measured values ​​of the second failed test chip in each test item among the remaining test chips; Based on the second maximum measured value under each test item and the number of remaining test chips, obtain the second filter value for each test item; Based on the second maximum measured value under each test item and the number of chips that failed the second test, obtain the second failure filter value under each test item; Based on the second filter value of each test item and the second failure filter value of each test item, obtain the second boundary value of each test item; The target control value is obtained based on the second boundary value of each test item.

5. The method according to claim 4, characterized in that, The target control value is obtained based on the second boundary value of each test item, including: Obtain the second maximum boundary value among the second boundary values ​​of each test item; The second maximum measured value under the test item corresponding to the second maximum boundary value is taken as the second candidate control value, and the test item corresponding to the second candidate control value is taken as the second control test item; From the remaining test chips, determine the second screened chip whose measured value under the second card control test item is greater than or equal to the second candidate card control value; If all the test chips except for the first and second screening chips are test-passed, then the target control value is determined based on the first candidate control value and the second candidate control value.

6. The method according to any one of claims 1 to 5, characterized in that, Based on the first maximum measured value under each test item and the number of test chips, obtain the first filter value for each test item, including: Obtain the number of pre-screened chips whose measured values ​​under each test item are greater than or equal to the first maximum measured value under the corresponding test item in the test chip; Based on the number of pre-screened chips under each test item and the number of test chips, obtain the first filter value for each test item.

7. The method according to any one of claims 1 to 5, characterized in that, Based on the first maximum measured value under each test item and the number of chips that failed the test, obtain the first failure filter value under each test item, including: Among the failed test chips, the number of pre-screened failed test chips whose measured values ​​under each test item are greater than or equal to the first maximum measured value under the corresponding test item is obtained. Based on the number of pre-screened failed chips under each test item and the number of failed chips, obtain the first failure filter value for each test item.

8. The method according to claim 1, characterized in that, Based on the measured values ​​of the chip to be graded under each test item and the target control value, the target chip grade of the chip to be graded is determined, including: Determine the target test item corresponding to the target control value from the test items; The target measurement value of the chip to be graded under the target test item is obtained from the measurement values ​​of the chip to be graded under each test item; The target chip grade of the chip to be graded is determined based on the target measurement value and the target control value.

9. The method according to claim 8, characterized in that, Based on the target measurement value and the target control value, the target chip level of the chip to be graded is determined, including: The chip to be graded is identified as a first-level chip whose target measurement value under the target test item is less than the target control value; The remaining chips to be graded, excluding the first-level chips, are identified as second-level chips.

10. An apparatus for chip classification, characterized in that, include: The acquisition unit is used to acquire the chip probe test results and the final test results of the test chip. The chip probe test results of the test chip include the measurement values ​​of the test chip under each test item, and the final test result of the test chip is either test pass or test failure. A determining unit is used to determine the label of the test chip based on the final test result of the test chip, wherein the label is a chip that has passed the test or a chip that has failed the test; The processing unit is used to obtain the target card control value based on the measured values ​​and labels of the test chip under each test item; The acquisition unit is also used to acquire the chip probe test results of the chip to be graded, the chip probe test results of the chip to be graded include the measured values ​​of the chip under each test item; The grading unit is used to determine the target chip grade of the chip to be graded based on the measured values ​​of the chip under each test item and the target control value. The processing unit is further configured to: Based on the label of the test chip, obtain the number of the first test failure chips among the test chips; Obtain the first maximum measured value among the measured values ​​of the first failed test chip in the test chips under each test item; Based on the first maximum measured value under each test item and the number of test chips, obtain the first filter value for each test item; Based on the first maximum measured value under each test item and the number of chips that failed the first test, obtain the first failure filter value under each test item; Based on the first filter value and the second failure filter value of each test item, obtain the first boundary value of each test item; The target control value is obtained based on the first boundary value of each test item.

11. The apparatus according to claim 10, characterized in that, The processing unit is also used for: Obtain the first maximum boundary value among the first boundary values ​​of each test item; The first maximum measured value under the test item corresponding to the first maximum boundary value is taken as the first candidate control value, and the test item corresponding to the first candidate control value is taken as the first control test item; The target card control value is determined based on the first candidate card control value and its corresponding first card control test item.

12. A computer device, characterized in that, Includes processor, memory, and input / output interfaces; The processor is connected to the memory and the input / output interface respectively, wherein the input / output interface is used to receive data and output data, the memory is used to store computer programs, and the processor is used to call the computer programs so that the computer device executes the method described in claims 1 to 9.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program adapted to be loaded and executed by a processor to cause a computer device having the processor to perform the method of any one of claims 1 to 9.

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