Asynchronous debugging method, device and storage medium for device and process simulation

Abstract

The application provides a device and process simulation asynchronous debugging method, device and storage medium, wherein the device and process simulation asynchronous debugging method comprises the following steps: performing a device simulation process of a semiconductor device according to a process simulation result of the semiconductor device; when data of the device simulation process does not converge, describing a simplified structure of the semiconductor device according to the process simulation result; re-performing the device simulation process according to the simplified structure; and evaluating according to the re-performed device simulation process. The method can realize diagnosis of device and process joint simulation calculation, so as to help users locate the reason why numerical calculation does not converge when directly applying the process simulation result to device physical property simulation calculation; and the method can quickly construct a device structure based on the process simulation result by using the provided tool and verify the numerical calculation convergence of the structure in the device simulation process, so as to determine the rationality of the process simulation result.

Description

Technical Field

[0001] This invention relates to the field of semiconductor industry technology, and more specifically, to an asynchronous debugging method, apparatus, and storage medium for device and process simulation. Background Technology

[0002] The semiconductor industry needs to design and fabricate semiconductor devices at the micrometer and nanometer scale. The long design and fabrication cycles, often involving trial and verification, are costly and require continuous improvement. To shorten development cycles and reduce costs, the semiconductor industry typically uses process simulation software to rationally plan the process flow, which consists of etching, deposition, implantation, oxidation, diffusion, and other steps. Numerical simulations are then used to obtain data on the distribution of electrons, holes, and dopant atoms within the device. The simulation results are then used to simulate device-level physical properties, verifying whether the device performance meets design expectations and allowing for further improvements.

[0003] The core of numerical simulation is to iteratively solve relevant partial differential equations and ordinary differential equations within a certain region by setting materials, configuring parameters, and selecting methods. The convergence of the numerical simulation process often depends on the rationality of the structure and simulation data. However, when the process simulation results are input into the device simulation process, the numerical iteration process may not converge, and currently, various simulation software programs struggle to accurately diagnose the reasons for non-convergence. Summary of the Invention

[0004] The problem addressed by this invention is: how to achieve diagnosis of joint simulation calculations of devices and processes, so as to help users locate the reasons for the non-convergence of numerical calculations when directly applying process simulation results to device physical characteristic simulation calculations.

[0005] To address the above problems, this invention provides an asynchronous debugging method for device and process simulation, comprising:

[0006] The device simulation process of the semiconductor device is performed based on the process simulation results of the semiconductor device;

[0007] When data non-convergence occurs during the device simulation process, a simplified structure of the semiconductor device is described based on the process simulation results.

[0008] The device simulation process is repeated based on the simplified structure described above.

[0009] The evaluation is based on the re-performed device simulation process.

[0010] Optionally, when data non-convergence occurs during the device simulation process, describing the simplified structure of the semiconductor device based on the process simulation results includes:

[0011] When the data fails to converge during the device simulation process, the process simulation results are visualized.

[0012] Optionally, when the device simulation process encounters data non-convergence, after visualizing the process simulation results, the step of describing the simplified structure of the semiconductor device based on the process simulation results further includes:

[0013] When the visualized process simulation results are reasonable, a description language tool is used to describe the visualized process simulation results to obtain the simplified structure.

[0014] Optionally, when the visualized process simulation results are reasonable, the simplified structure is obtained by using a description language tool to describe the visualized process simulation results, including:

[0015] The device structure of the semiconductor device in the visualized process simulation results is judged by manual or machine methods to determine whether it is reasonable.

[0016] If so, the simplified structure is obtained by describing the visualized process simulation results using the TCL language.

[0017] Optionally, after determining whether the device structure of the semiconductor device in the visualized process simulation result is reasonable through manual or machine judgment, the step of describing the visualized process simulation result using a description language tool to obtain the simplified structure when the visualized process simulation result is reasonable further includes:

[0018] If not, modify the process steps of the semiconductor device process simulation and re-perform the process simulation.

[0019] Optionally, after performing the device simulation process of the semiconductor device based on the process simulation results, the asynchronous debugging method of the device and process simulation further includes:

[0020] When the data non-convergence does not occur during the device simulation process, the process of the semiconductor device is adjusted according to the device simulation process.

[0021] Optionally, the evaluation based on the re-performed device simulation process includes:

[0022] When the data fails to converge during the device simulation process, the device structure and simplified structure of the semiconductor device are deemed unreasonable; when the data fails to converge during the device simulation process, the doping concentration data of the semiconductor device are deemed unreasonable.

[0023] To address the above problems, the present invention also provides an asynchronous debugging device for device and process simulation, comprising:

[0024] The first device simulation unit is used to perform the device simulation process of the semiconductor device based on the process simulation results of the semiconductor device.

[0025] The process simulation result description unit is used to describe the simplified structure of the semiconductor device based on the process simulation results when the data does not converge during the device simulation process.

[0026] The second device simulation unit is used to re-perform the device simulation process based on the simplified structure.

[0027] An evaluation unit is used to evaluate the device based on the re-performed device simulation process.

[0028] To address the aforementioned issues, the present invention also provides an asynchronous debugging device for device and process simulation, comprising a computer-readable storage medium storing a computer program and a processor, wherein the computer program is read and executed by the processor to implement the aforementioned asynchronous debugging method for device and process simulation.

[0029] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when read and executed by a processor, implements the asynchronous debugging method for device and process simulation described above.

[0030] Compared with existing technologies, this invention has the following advantages: This method can diagnose the joint simulation calculation of devices and processes, helping users to locate the reasons for numerical calculation non-convergence when directly applying process simulation results to device physical characteristic simulation calculations. Furthermore, this method can quickly construct device structures based on process simulation results using the provided tools and verify the numerical calculation convergence of the structure during device simulation, thereby determining the rationality of the process simulation results. Attached Figure Description

[0031] Figure 1 This is a flowchart of the asynchronous debugging method for device and process simulation in an embodiment of the present invention;

[0032] Figure 2 This is a sub-flowchart of step 210 in an embodiment of the present invention;

[0033] Figure 3 This is a sub-flowchart of step 212 in an embodiment of the present invention;

[0034] Figure 4 This is a partial flowchart of an asynchronous debugging method for device and process simulation in another embodiment of the present invention;

[0035] Figure 5 This is a partial flowchart of an asynchronous debugging method for device and process simulation in another embodiment of the present invention. Detailed Implementation

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0038] To shorten the R&D cycle and reduce the cost of semiconductor devices, the semiconductor industry typically uses process simulation software to rationally plan the process consisting of etching, deposition, implantation, oxidation, diffusion, and other process steps. Numerical simulation is used to obtain the distribution data of elements such as electrons, holes, and doped atoms in the device. Then, the process simulation results are used to simulate the device-level physical characteristics to verify whether the device performance meets the design expectations and to make improvements.

[0039] Combination Figure 1 As shown in the embodiments of the present invention, in order to shorten the R&D cycle of semiconductor devices and reduce their R&D costs, the semiconductor industry usually uses process simulation software to rationally compile a process consisting of etching, deposition, implantation, oxidation, diffusion and other process steps. The distribution data of elements such as electrons, holes and doped atoms in the device are obtained through numerical calculation simulation. Then, the process simulation results are used to simulate the device-level physical characteristics to verify whether the device performance meets the design expectations and to make improvements.

[0040] This invention provides an asynchronous debugging method for device and process simulation, comprising the following steps:

[0041] Step 100: Perform the device simulation process of the semiconductor device based on the process simulation results of the semiconductor device.

[0042] Specifically, after the semiconductor device completes the process simulation through the corresponding process simulation software, the obtained process simulation results are input into the corresponding device simulation software to simulate the device-level physical characteristics, so as to verify whether the device performance of the semiconductor device meets the design expectations and provide directions for process improvement (based on the device simulation process or results).

[0043] Step 210: When data non-convergence occurs during device simulation, describe the simplified structure of the semiconductor device based on the process simulation results.

[0044] Specifically, when the numerical (data) iteration process fails to converge during device simulation, corresponding descriptive tools (such as visualization tools, structural description language tools, etc.) are used to describe the process simulation results in order to obtain a simplified structure of the semiconductor device.

[0045] Step 300: Re-perform the device simulation process based on the simplified structure.

[0046] Specifically, the simplified structure obtained from the description is used as input to the corresponding device simulation software, and the device simulation process is repeated to check whether the numerical calculation process converges during the device simulation.

[0047] Step 400: Evaluate based on the re-performed device simulation process.

[0048] Specifically, the evaluation is based on the device simulation process (such as the numerical calculation process in step 300) to determine whether the structure of the semiconductor device is reasonable, whether process improvement is needed, etc.

[0049] This method enables the diagnosis of joint simulation calculations of devices and processes, helping users pinpoint the reasons for numerical non-convergence when directly applying process simulation results to device physical characteristic simulation calculations. It utilizes visualization tools to describe the structure of process simulation results, helping users directly build a complete simplified structure using languages ​​such as TCL and bind materials and doping concentrations. By inputting the simplified structure into device simulation software and viewing its numerical convergence, the cause of numerical non-convergence in the joint simulation can be located, thus shortening diagnostic time and improving debugging efficiency.

[0050] The key feature of this method is its ability to rapidly construct device structures based on process simulation results using provided tools and verify the numerical convergence of the structures during device simulation, thereby determining the rationality of the process simulation results. The simplified structure description process is based on a WYSIWYG approach, utilizing languages ​​such as TCL to describe the visualized process simulation data and assuming a uniform concentration distribution.

[0051] Furthermore, this method utilizes the data file interface between process simulation software and device simulation software to establish a data visualization scene. With built-in color configuration, it visually displays the concentration distribution of various doped particles after the process, providing an intuitive representation of the process simulation structure, including various boundary locations. Based on this, users can use languages ​​such as TCL to describe the basic device structure and add sources, gates, and drains to obtain a complete device with a simplified structure. The rationality of the process simulation results can be judged by the numerical convergence of the simplified structure after inputting it into the device simulation software. This makes the method applicable to the joint simulation of process and device, helping to quickly locate the cause of numerical non-convergence and significantly reducing debugging time. In addition, this method introduces a visualization plugin and structural description language into the interface between process simulation and device simulation software to achieve asynchronous linkage debugging of the process and device simulation processes. The overall process is clear, simple, and easy to operate.

[0052] Optionally, combined Figure 1 , Figure 2 As shown, step 210 includes:

[0053] Step 211: When data non-convergence occurs during the device simulation process, visualize the process simulation results.

[0054] Specifically, when the numerical (data) iteration process fails to converge during device simulation, the process simulation results of the semiconductor device are visualized using appropriate visualization tools. For example, the device structure of the semiconductor device can be visualized based on the process simulation results, so as to facilitate the subsequent judgment of the rationality of the device structure based on the visualized device structure.

[0055] For example, this method visualizes process results and simplifies device structure description. It requires that the process simulation results be organized into a data file with a specific structure according to a specified format, and that the device simulation software supports the input format of the specific structure. The visualization process in step 211 takes the structured data file of the process simulation results as input, displays the region and sub-regions where the device is located according to the position of the physical points in the file, and renders the corresponding regions with different colors according to the material and doping concentration of each physical point in the file, so as to achieve the purpose of characterizing the device structure and realizing the visualization of the device structure.

[0056] Optionally, combined Figure 1 , Figure 2 As shown, after step 211, step 210 further includes:

[0057] Step 212: When the visualized process simulation results are reasonable, use a description language tool to describe the visualized process simulation results and obtain a simplified structure of the semiconductor device.

[0058] Optionally, combined Figure 2, Figure 3 As shown, step 212 includes:

[0059] Step 212a: Determine whether the device structure of the semiconductor device in the visualized process simulation results is reasonable, either manually or by machine.

[0060] Specifically, based on the corresponding regions, sub-regions, boundary positions, and doping concentrations identified by the visualization results, the rationality of the device structure is determined manually or by machine.

[0061] Step 212b: If so, use TCL language to describe the visualized process simulation results to obtain a simplified structure of the semiconductor device.

[0062] If step 212a determines that the semiconductor device structure in the visualized process simulation results is reasonable, then a description language tool, such as TCL (Tool Command Language), is used to describe the device structure and adjacency relationships displayed in the visualization results. Based on the colors in the visualization results, the doping concentration in the corresponding regions is specified as a constant value to simplify the structure and obtain a simplified structure of the semiconductor device. Specifically, the device structure given in the visualized process simulation results is described using TCL language, describing the corresponding regions and sub-regions, binding materials to each region and sub-region, and specifying the dopant particle type and constant concentration for the doped regions. The constant can be the minimum, maximum, or average concentration of the doping concentration in the corresponding region.

[0063] Optionally, combined Figure 2 , Figure 3 As shown, after step 212a, step 212 further includes:

[0064] Step 212e: If not, modify the process steps of the semiconductor device process simulation and re-perform the process simulation.

[0065] For example, if step 212a determines that the device structure of the semiconductor device in the visualized process simulation result is unreasonable, the process steps of the semiconductor device process simulation can be modified according to the reason for the unreasonableness, and the process simulation can be performed again.

[0066] Optionally, combined Figure 1 , Figure 4 As shown, after step 100, this method further includes:

[0067] Step 250: When no data non-convergence occurs during the device simulation process, adjust the semiconductor device process according to the device simulation process.

[0068] Specifically, when the numerical (data) iteration process does not fail to converge during device simulation, it indicates that the device performance and structure of the semiconductor device meet design expectations. Further adjustments to the semiconductor device's process can then be made based on the device simulation results to further optimize the device performance and structure.

[0069] Step 400 includes:

[0070] When data non-convergence occurs during device simulation, the device structure and simplified structure of the semiconductor device are deemed unreasonable; when data non-convergence does not occur during device simulation, the doping concentration data of the semiconductor device is deemed unreasonable.

[0071] Specifically, the simplified structure of the semiconductor device is input into the device simulation software. The rationality of the result is determined by whether the numerical simulation process converges. In turn, it is determined whether the numerical non-convergence during the process of process and device linkage debugging is caused by unreasonable structure or unreasonable doping concentration distribution.

[0072] Optionally, combined Figure 1 , Figure 5 As shown, after step 400, this method further includes:

[0073] Step 500: Modify the process steps of the semiconductor device process simulation based on the evaluation results, and re-perform the process simulation.

[0074] Specifically, the operational steps of the process are adjusted based on the evaluation results in step 400 to achieve a cyclical, linked debugging process. In this way, asynchronous, linked debugging compensates for insufficient software diagnostic information, significantly shortens the linked debugging time, and improves debugging efficiency.

[0075] Optionally, after step 500, this method further includes:

[0076] Proceed to step 100.

[0077] Specifically, after the process simulation is completed in step 500, steps 100 to 500 of this method are repeated.

[0078] In this way, this method realizes asynchronous debugging that separates device structure and process, provides a way to intuitively display the structure and density of process simulation results, and a device structure description language based on TCL. This allows the device structure to be quickly and conveniently described using the structure description language based on the intuitive structure and density obtained from the process results when numerical iteration fails to converge in the device simulation software. The structure description can then be directly applied to the device simulation software to verify the numerical convergence of the structure, ultimately determining whether the numerical non-convergence is caused by the rationality of the structure or the rationality of the process data. Thus, in addition to the prompts output by the software, this method provides a new method and tool for joint process and device simulation diagnosis (an asynchronous debugging device for device and process simulation), improving debugging efficiency and significantly shortening the time required to locate problems.

[0079] Another embodiment of the present invention also provides an asynchronous debugging device for device and process simulation, comprising:

[0080] The first device simulation unit is used to perform device simulation of semiconductor devices based on the process simulation results of semiconductor devices.

[0081] The process simulation result description unit is used to describe the simplified structure of the semiconductor device based on the process simulation results when data non-convergence occurs during the device simulation process.

[0082] The second device simulation unit is used to re-perform the device simulation process based on the simplified structure;

[0083] The evaluation unit is used to evaluate based on the re-performed device simulation process.

[0084] In this embodiment, the coordination of the first device simulation unit, the process simulation result description unit, the second device simulation unit, and the evaluation unit of the asynchronous debugging device for device and process simulation ensures that the asynchronous debugging method for device and process simulation can be executed smoothly and stably, and can realize the diagnosis of joint simulation calculation of device and process, so as to help users locate the reason for the non-convergence of numerical calculation when directly applying the process simulation results to the simulation calculation of device physical characteristics.

[0085] In some embodiments, the first device simulation unit and the second device simulation unit may also be of the same structure.

[0086] Another embodiment of the present invention provides an asynchronous debugging device for device and process simulation, including a computer-readable storage medium storing a computer program and a processor. The computer program is read and run by the processor to implement the above-described asynchronous debugging method for device and process simulation.

[0087] In this way, by coordinating the processor, computer-readable storage medium, and other structures of the asynchronous debugging device for device and process simulation, the asynchronous debugging method for device and process simulation is executed, ensuring that the asynchronous debugging method for device and process simulation can be executed smoothly and stably, and enabling the diagnosis of joint simulation calculation of device and process, so as to help users locate the reason for the non-convergence of numerical calculation when directly applying the process simulation results to the simulation calculation of device physical characteristics.

[0088] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, which is read and executed by a processor to implement the above-described asynchronous debugging method for device and process simulation.

[0089] The technical solutions of the embodiments of the present invention, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0090] By storing the corresponding computer program for the asynchronous debugging method of device and process simulation on a computer-readable storage medium, the stability of the computer program being read and run by the corresponding processor can be guaranteed. This ensures the smooth and stable execution of the asynchronous debugging method for device and process simulation, and enables the diagnosis of joint device and process simulation calculations, helping users to pinpoint the reasons for numerical calculation non-convergence when directly applying process simulation results to device physical characteristic simulation calculations.

[0091] While the disclosure is as stated above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of this disclosure, and all such changes and modifications will fall within the protection scope of this invention.

Claims

1. An asynchronous debugging method for device and process simulation, characterized in that, include: The device simulation process of the semiconductor device is performed based on the process simulation results of the semiconductor device; When data non-convergence occurs during the device simulation process, a simplified structure of the semiconductor device is described based on the process simulation results. The device simulation process is repeated based on the simplified structure described above. The evaluation is based on the re-performed device simulation process; Wherein, when the device simulation process encounters a data non-convergence situation, describing the simplified structure of the semiconductor device based on the process simulation results includes: When the data fails to converge during the device simulation process, the process simulation results are visualized. When the visualized process simulation results are reasonable, a description language tool is used to describe the visualized process simulation results to obtain the simplified structure; The evaluation based on the re-performed device simulation process includes: When the data fails to converge during the device simulation process, the device structure and simplified structure of the semiconductor device are deemed unreasonable; when the data fails to converge during the device simulation process, the doping concentration data of the semiconductor device are deemed unreasonable.

2. The asynchronous debugging method for device and process simulation as described in claim 1, characterized in that, When the visualized process simulation results are reasonable, a description language tool is used to describe the visualized process simulation results, resulting in the simplified structure, which includes: The device structure of the semiconductor device in the visualized process simulation results is judged by manual or machine methods to determine whether it is reasonable. If so, the simplified structure is obtained by describing the visualized process simulation results using the TCL language.

3. The asynchronous debugging method for device and process simulation as described in claim 2, characterized in that, After determining whether the device structure of the semiconductor device in the visualized process simulation result is reasonable through manual or machine judgment, the step of describing the visualized process simulation result using a description language tool to obtain the simplified structure when the visualized process simulation result is reasonable further includes: If not, modify the process steps of the semiconductor device process simulation and re-perform the process simulation.

4. The asynchronous debugging method for device and process simulation as described in any one of claims 1-3, characterized in that, After the semiconductor device simulation process based on the semiconductor device process simulation results is performed, the asynchronous debugging method between the device and the process simulation further includes: When the data non-convergence does not occur during the device simulation process, the process of the semiconductor device is adjusted according to the device simulation process.

5. An asynchronous debugging device for device and process simulation, characterized in that, include: The first device simulation unit is used to perform the device simulation process of the semiconductor device based on the process simulation results of the semiconductor device. The process simulation result description unit is used to describe the simplified structure of the semiconductor device based on the process simulation results when the data does not converge during the device simulation process. The second device simulation unit is used to re-perform the device simulation process based on the simplified structure. An evaluation unit is used to evaluate based on the re-performed device simulation process; Wherein, when the device simulation process encounters a data non-convergence situation, describing the simplified structure of the semiconductor device based on the process simulation results includes: When the data fails to converge during the device simulation process, the process simulation results are visualized. When the visualized process simulation results are reasonable, a description language tool is used to describe the visualized process simulation results to obtain the simplified structure; The evaluation based on the re-performed device simulation process includes: When the data fails to converge during the device simulation process, the device structure and simplified structure of the semiconductor device are deemed unreasonable; when the data fails to converge during the device simulation process, the doping concentration data of the semiconductor device are deemed unreasonable.

6. An asynchronous debugging device for device and process simulation, characterized in that, It includes a computer-readable storage medium storing a computer program and a processor, wherein the computer program is read and executed by the processor to implement an asynchronous debugging method for device and process simulation as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is read and executed by a processor to implement the asynchronous debugging method for device and process simulation as described in any one of claims 1-4.

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