Memory error correction techniques
By combining ECC and refresh operations in the memory device, error correction of the memory array is performed periodically, solving the problem of SBE becoming DBE or MBE in the prior art, and realizing efficient error correction and low-power operation of the memory device.
CN115910185BActive Publication Date: 2026-07-03MICRON TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2022-08-03
- Publication Date
- 2026-07-03
Smart Images
Figure CN115910185B_ABST
Abstract
This application relates to memory error correction. The memory system can support refresh operations utilizing Error Correction Code (ECC). The refresh using ECC operations can be instructed in a command from the host device to the memory device, or the memory device can support autonomously performing the refresh using ECC operations, for example, as part of a self-refresh operation. The refresh using ECC operations causes the memory system to perform an error correction operation on at least a portion of a row of the memory array as part of a refresh operation for that row. The error correction operation can correct bit errors in the dataset before additional bits in the dataset are corrupted. The address of the portion of the row can be determined using one or more counters associated with an ECC patrol block.
Need to check novelty before this filing date? Find Prior Art