Process for the production of semiconductors
By configuring photoresist and oxide layers, the complexity of controlling metal linewidth with carbon layers in existing technologies is solved, enabling precise etching of metal linewidth and reducing contamination, thus simplifying the process flow.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU FULLSEMI SEMICON CO LTD
- Filing Date
- 2022-11-28
- Publication Date
- 2026-06-16
Smart Images
Figure CN115910775B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor process. Background Technology
[0002] As electronic devices become smaller and functional requirements increase, the size of transistors needs to be reduced accordingly, leading to a reduction in transistor linewidth. In current semiconductor processes, linewidth control is commonly achieved through carbon layer deposition. This involves forming a carbon layer on a metal substrate and then partially etching it to control the linewidth. However, carbon layer deposition is a specialized process in semiconductor manufacturing, requiring additional deposition equipment. Furthermore, etching the carbon layer requires specific etching solutions. Therefore, both forming and etching the carbon layer are extremely troublesome and difficult processes for production line personnel. Summary of the Invention
[0003] Based on the foregoing, this application provides a semiconductor process that solves the problem of needing a carbon layer to control the metal linewidth, thereby reducing the difficulty of metal linewidth etching.
[0004] To achieve the above objectives, this application provides a semiconductor process comprising: forming a metal layer on a substrate; forming an oxide layer on the metal layer; forming a photoresist layer having a first opening on the oxide layer; partially etching the oxide layer such that the first opening penetrates the oxide layer to expose the metal layer, wherein the etched oxide layer includes a first oxide region and a second oxide region, and the first opening is located between the first oxide region and the second oxide region; performing an adjustment process on the photoresist layer to expose the first oxide region or the second oxide region, wherein after the adjustment process, the photoresist layer partially covers the metal layer; and partially etching the metal layer such that the metal layer has a second opening, wherein the width of the second opening is smaller than the width of the first opening.
[0005] In embodiments of this application, the width of the second opening is defined based on the area of the metal layer covered by the photoresist layer.
[0006] In the embodiments of this application, the photoresist layer includes a first photoresist layer and a second photoresist layer, a first opening is located between the first photoresist layer and the second photoresist layer, the first photoresist layer is located on a first oxide region, and the second photoresist layer is located on a second oxide region. The adjustment process for the photoresist layer includes: performing a deposition process on the photoresist layer and partially etching the photoresist layer after the deposition process, so that the first photoresist layer after etching partially fills the first opening between the first oxide region and the second oxide region.
[0007] In the embodiments of this application, after the adjustment process, the width of the first photoresist layer projected onto the substrate is greater than the width of the first oxide region projected onto the substrate.
[0008] In the embodiments of this application, after the adjustment process, the first photoresist layer seals the side of the first oxide region.
[0009] In the embodiments of this application, after the adjustment process, the width of the second photoresist layer projected onto the substrate is smaller than the width of the second oxide region projected onto the substrate.
[0010] In an embodiment of this application, the photoresist layer includes a first photoresist layer and a second photoresist layer. A first opening is located between the first photoresist layer and the second photoresist layer. The first photoresist layer is located on a first oxide region, and the second photoresist layer is located on a second oxide region. The adjustment process of the photoresist layer includes: forming a third photoresist layer to partially fill the first opening between the first oxide region and the second oxide region, and partially etching the first photoresist layer or the second photoresist layer.
[0011] In embodiments of this application, the third photoresist layer is located close to the first photoresist layer or the second photoresist layer.
[0012] In the embodiments of this application, when the third photoresist layer is close to the first photoresist layer, the second photoresist layer is partially etched; when the third photoresist layer is close to the second photoresist layer, the first photoresist layer is partially etched.
[0013] In the embodiments of this application, the width of the second opening ranges from 30nm to 60nm.
[0014] In summary, the semiconductor process of this application, through the configuration of photoresist and oxide layers, can successfully etch a metal layer to form an opening in the metal layer, and use the width of the opening as the metal linewidth, without the need for a carbon layer to assist in etching the metal layer, thereby reducing the process difficulty of metal linewidth etching and reducing pollution caused by carbon.
[0015] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the following describes the application in detail with reference to the preferred embodiments and accompanying drawings. Attached Figure Description
[0016] Figure 1 A flowchart illustrating a semiconductor process according to an embodiment of this application is provided.
[0017] Figures 2A to 2F Cross-sectional views illustrating various stages of a semiconductor process according to an embodiment of this application are shown.
[0018] Figure 3A and Figure 3B Cross-sectional views illustrating the various stages of the adjustment process according to another embodiment of this application are shown.
[0019] Explanation of reference numerals in the attached figures:
[0020] 10: Substrate
[0021] 20: Metal layer
[0022] 30: Oxide layer
[0023] 31: First Oxidation Zone
[0024] 32: Second oxidation zone
[0025] 40: Photoresist layer
[0026] 41: First photoresist layer
[0027] 42: Second photoresist layer
[0028] 50: Third photoresist layer
[0029] H1: First opening
[0030] H2: Second opening
[0031] S11~S16: Steps Detailed Implementation
[0032] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0033] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and embodiments. To enable those skilled in the art to better understand the solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.
[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.
[0035] Please see Figure 1 This is a flowchart illustrating a semiconductor process according to an embodiment of this application. Figure 1 As shown, the semiconductor process of this application includes steps S11 to S16.
[0036] Step S11: Form a metal layer 20 on the substrate 10. For example... Figure 2A As shown, a metal layer 20 is formed on the substrate 10 by sputtering or vapor deposition to cover the surface of the substrate 10.
[0037] The substrate 10 is made of silicon and may be of a first doping type, wherein the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. To form an N-type semiconductor layer or region, an N-type dopant may be implanted into the substrate 10, such as phosphorus (P) or arsenic (As). To form a P-type semiconductor layer or region, a P-type dopant may be doped into the substrate 10, such as boron (B). In one embodiment, the substrate 10 is N-type.
[0038] The material of the metal layer 20 may include indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllium nitride (AuBe), germanium beryllium nitride (BeGe), nickel (Ni), lead tin nitride (PbSn), chromium (Cr), gold zinc nitride (AuZn), titanium (Ti), tungsten (W), or titanium tungsten nitride (TiW).
[0039] Step S12: Form an oxide layer 30 on the metal layer 20. For example... Figure 2B As shown, an oxide layer 30 covers the surface of the metal layer 20. The oxide layer 30 can be formed using methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electron beam evaporation, sputtering, or thermal oxidation. The material of the oxide layer 30 includes silicon oxide (SiO2). x ), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), aluminum oxide (AlO) x ), hafnium dioxide (HfO2) or a combination thereof.
[0040] Step S13: Form a photoresist layer 40 with a first opening H1 on the oxide layer 30. For example... Figure 2C As shown, a photoresist layer 40 with a first opening H1 is formed on the oxide layer 30 by coating. The photoresist layer 40 includes a first photoresist layer 41 and a second photoresist layer 42, and the first opening H1 is disposed between the first photoresist layer 41 and the second photoresist layer 42.
[0041] In one embodiment, the width of the first photoresist layer 41 projected onto the substrate 10 is greater than the width of the second photoresist layer 42 projected onto the substrate 10. In another embodiment, the width of the first photoresist layer 41 projected onto the substrate 10 is less than the width of the second photoresist layer 42 projected onto the substrate 10.
[0042] Step S14: Partially etch the oxide layer 30 so that the first opening H1 penetrates the oxide layer 30 to expose the metal layer 20. (Example) Figure 2D As shown, through reactive ion etching, the first opening H1 is partially etched, causing the first opening H1 to extend towards the substrate 10 and penetrate the oxide layer 30, terminating at the surface of the metal layer 20, thereby exposing the metal layer 20. Due to the etching of the first opening H1, the etched oxide layer 30 includes a first oxide region 31 and a second oxide region 32. The first photoresist layer 41 is located on the first oxide region 31, the second photoresist layer 42 is located on the second oxide region 32, and the first opening H1 is located between the first oxide region 31 and the second oxide region 32.
[0043] In one embodiment, the width of the first oxide region 31 projected onto the substrate 10 is greater than the width of the second oxide region 32 projected onto the substrate 10. In another embodiment, the width of the first oxide region 31 projected onto the substrate 10 is less than the width of the second oxide region 32 projected onto the substrate 10.
[0044] Step S15: Perform an adjustment process on the photoresist layer 40 to expose the first oxide region 31 or the second oxide region 32. Specifically, perform a deposition process on the photoresist layer 40 (the deposition process can be achieved by coating), and partially etch the photoresist layer 40 after the deposition process, so that the etched photoresist layer 40 partially fills the first opening H1 between the first oxide region 31 and the second oxide region 32 to partially cover the metal layer 20, and exposes the first oxide region 31 or the second oxide region 32.
[0045] In one implementation sample, such as Figure 2E As shown, a deposition process is performed on the first photoresist layer 41, causing the first photoresist layer 41 to partially fill the first opening H1 between the first oxide region 31 and the second oxide region 32 to partially cover the metal layer 20, and the second photoresist layer 42 is partially etched to expose the second oxide region 32. After the adjustment process, the first photoresist layer 41 seals the side of the first oxide region 31, and after the adjustment process, the width of the first photoresist layer 41 projected onto the substrate 10 is greater than the width of the first oxide region 31 projected onto the substrate 10. After the adjustment process, the width of the second photoresist layer 42 projected onto the substrate 10 is less than the width of the second oxide region 32 projected onto the substrate.
[0046] In another embodiment, a deposition process is performed on the second photoresist layer 42, causing the second photoresist layer 42 to partially fill the first opening H1 between the first oxide region 31 and the second oxide region 32 to partially cover the metal layer 20, and the first photoresist layer 41 is partially etched to expose the first oxide region 31. After the adjustment process, the second photoresist layer 42 seals the side of the second oxide region 32. After the adjustment process, the width of the second photoresist layer 42 projected onto the substrate 10 is greater than the width of the second oxide region 32 projected onto the substrate 10, and the width of the first photoresist layer 41 projected onto the substrate 10 is less than the width of the first oxide region 31 projected onto the substrate.
[0047] Step S16: Partially etch the metal layer 20 to create a second opening H2 in the metal layer 20. (Example:...) Figure 2F As shown, based on the distance between the side of the first photoresist layer 41 near the first opening H1 and the side of the second oxide region 32 near the first opening H1 after the adjustment process, the metal layer 20 is etched by reactive ion etching to form the second opening H2. The second opening H2 extends towards the substrate 10 and terminates on the surface of the substrate 10. The width of the second opening H2 ranges from 30 nm to 60 nm.
[0048] Because the first photoresist layer 41 partially covers the first opening H1 after the adjustment process, the size of the opening etched in the metal layer 20 is smaller than the size of the opening etched in the oxide layer 30. That is, the width of the second opening H2 is smaller than the width of the first opening H1, and the width of the second opening H2 is used as the metal linewidth. In other words, the width of the second opening H2 is defined based on the area of the metal layer 20 covered by the first photoresist layer 41, and the width of the second opening H2 can be adjusted by adjusting the area of the metal layer 20 covered by the first photoresist layer 41.
[0049] Please see Figure 3A and Figure 3B It is a cross-sectional view illustrating the various stages of the adjustment process according to another embodiment of this application; wherein Figure 3A and Figure 3B For the corresponding Figure 1 Step S15 is shown.
[0050] In one implementation sample, such as Figure 3A As shown, a third photoresist layer 50 is formed by coating to partially fill the first opening H1 between the first oxide region 31 and the second oxide region 32. The third photoresist layer 50 is close to the second photoresist layer 42, and the first photoresist layer 41 is partially etched to expose the first oxide region 31. Figure 3BAs shown, with the distance between the side of the first oxide region 31 near the first opening H1 and the side of the third photoresist layer 50 as a reference, the metal layer 20 is etched through reactive ion etching to form a second opening H2. The second opening H2 extends toward the substrate 10 and terminates on the surface of the substrate 10. The width of the second opening H2 is smaller than the width of the first opening H1.
[0051] In another embodiment, a third photoresist layer 50 is formed by coating to partially fill the first opening H1 between the first oxide region 31 and the second oxide region 32. The third photoresist layer 50 is adjacent to the first photoresist layer 41, and the second photoresist layer 42 is partially etched to expose the second oxide region 32. Based on the distance between the side of the second oxide region 32 near the first opening H1 and the side of the third photoresist layer 50, the metal layer 20 is partially etched by reactive ion etching to form a second opening H2. The second opening H2 extends toward the substrate 10 and terminates on the surface of the substrate 10. The width of the second opening H2 is smaller than the width of the first opening H1.
[0052] In summary, the semiconductor process of this application, through the configuration of photoresist and oxide layers, can successfully etch a metal layer to form an opening in the metal layer, and use the width of the opening as the metal linewidth, without the need for a carbon layer to assist in etching the metal layer, thereby reducing the process difficulty of metal linewidth etching and reducing pollution caused by carbon.
Claims
1. A semiconductor process, characterized in that, include: A metal layer (20) is formed on a substrate (10); an oxide layer (30) is formed on the metal layer (20); A photoresist layer (40) with a first opening (H1) is formed on the oxide layer (30); the oxide layer (30) is partially etched so that the first opening (H1) penetrates the oxide layer (30) to expose the metal layer (20), wherein the etched oxide layer (30) includes a first oxide region (31) and a second oxide region (32), and the first opening (H1) is located between the first oxide region (31) and the second oxide region (32); an adjustment process is performed on the photoresist layer (40) to expose the first oxide region (31) or the second oxide region (32), wherein after the adjustment process, the photoresist layer (40) partially covers the metal layer (20); and the metal layer (20) is partially etched so that the metal layer (20) has a second opening (H2), wherein the width of the second opening (H2) is smaller than the width of the first opening (H1).
2. The semiconductor process according to claim 1, wherein the width of the second opening (H2) is defined according to the area of the photoresist layer (40) covering the metal layer (20).
3. The semiconductor process according to claim 1, wherein the photoresist layer (40) comprises a first photoresist layer (41) and a second photoresist layer (42), the first opening (H1) is located between the first photoresist layer (41) and the second photoresist layer (42), the first photoresist layer (41) is located on the first oxide region (31), the second photoresist layer (42) is located on the second oxide region (32), and the adjustment process performed on the photoresist layer (40) comprises: A deposition process is performed on the photoresist layer (40), and the photoresist layer (40) after the deposition process is partially etched, so that the first photoresist layer (41) after etching partially fills the first opening (H1) between the first oxide region (31) and the second oxide region (32).
4. The semiconductor process according to claim 3, wherein after the adjustment process, the width of the first photoresist layer (41) projected onto the substrate (10) is greater than the width of the first oxide region (31) projected onto the substrate (10).
5. The semiconductor process according to claim 3, wherein after the adjustment process, the first photoresist layer (41) seals the side of the first oxide region (31).
6. The semiconductor process according to claim 3, wherein after the adjustment process, the width of the second photoresist layer (42) projected onto the substrate (10) is smaller than the width of the second oxide region (32) projected onto the substrate (10).
7. The semiconductor process according to claim 1, wherein the photoresist layer (40) comprises a first photoresist layer (41) and a second photoresist layer (42), the first opening (H1) is located between the first photoresist layer (41) and the second photoresist layer (42), the first photoresist layer (41) is located on the first oxide region (31), the second photoresist layer (42) is located on the second oxide region (32), and the adjustment process performed on the photoresist layer (40) comprises: A third photoresist layer (50) is formed to partially fill the first opening (H1) between the first oxide region (31) and the second oxide region (32), and the first photoresist layer (41) or the second photoresist layer (42) is partially etched.
8. The semiconductor process according to claim 7, wherein the third photoresist layer (50) is adjacent to the first photoresist layer (41) or the second photoresist layer (42); wherein, The third photoresist layer (50) is adjacent to the first photoresist layer (41) or the second photoresist layer (42) which is not etched.
9. The semiconductor process according to claim 7, wherein when the third photoresist layer (50) is close to the first photoresist layer (41), the second photoresist layer (42) is partially etched; and when the third photoresist layer (50) is close to the second photoresist layer (42), the first photoresist layer (41) is partially etched.
10. The semiconductor process according to claim 1, wherein the width of the second opening (H2) is in the range of 30 nm to 60 nm.