Display panel, display device and driving method

Abstract

A display panel, a display device and a driving method. The display panel includes a display area and a peripheral area. The display area includes a sub-pixel unit array having multiple rows and columns of sub-pixel units, a gate driving circuit is arranged in the peripheral area, the display area also includes multiple gate lines and multiple data lines, the gate driving circuit includes multiple shift register units arranged in sequence, the multiple gate lines are arranged in sequence and electrically connected to the multiple shift register units arranged in sequence; the gate driving circuit includes two shift register unit scanning groups, in each shift register unit scanning group, the k+1th shift register unit and the kth shift register unit are cascaded to form a shift register unit group; the kth shift register unit in one shift register unit scanning group is connected to the k+1th shift register unit in another shift register unit scanning group, k≥1 and k is a positive integer.

Description

[0001] This application is a divisional application of the invention patent application with application date of July 31, 2019, application number 201980001200.X, and invention name “Display panel, display device and driving method”. Technical Field

[0002] Embodiments of the present disclosure relate to a display panel, a display device, and a driving method. Background Art

[0003] In the field of display technology, in order to improve the quality of display images and enhance user experience, the realization of high PPI (Pixels Per Inch, number of pixels per inch) and narrow borders has gradually become a research direction. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the driving circuit can be directly integrated on the thin film transistor array substrate to form GOA (Gate driver On Array) to drive the display panel. GOA technology helps to achieve a narrow border design of the display panel and can reduce the production cost of the display panel. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display panel, including a display area and a peripheral area. The display area includes a sub-pixel unit array having multiple rows and columns of sub-pixel units, a gate driving circuit is arranged in the peripheral area, and the display area also includes multiple gate lines and multiple data lines for driving the sub-pixel unit array, each sub-pixel unit is driven to display by a scanning signal provided by a gate line and a data signal provided by a data line, and the same data line connects at least two sub-pixel units of the same color that are not adjacent to each other; the gate driving circuit includes a plurality of shift register units arranged in sequence, the plurality of gate lines are arranged in sequence and are electrically connected to the plurality of shift register units arranged in sequence in a one-to-one correspondence; the gate driving circuit is configured to receive a clock signal and generate the scanning signal so that the at least two sub-pixel units of the same color that are not adjacent to each other and connected to the same data line are displayed continuously in timing.

[0005] For example, in a display panel provided in an embodiment of the present disclosure, a plurality of sub-pixel units sequentially connected to the same data line are divided into G driving groups when being driven, the number of the clock signals is H, each of the driving groups includes F sub-pixel units, F=[H / G], [H / G] represents rounding H / G; the gate driving circuit is further configured to drive the F sub-pixel units in the Bth driving group in the following order: A d =B+(d-1)*G, where A drepresents the sequential number of the sub-pixel unit driven for the dth time, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.

[0006] For example, in a display panel provided in an embodiment of the present disclosure, the plurality of sub-pixel units connected in sequence to the same data line include at least a first color and a second color. Among the plurality of sub-pixel units connected in sequence to the same data line, the minimum arrangement period of the sub-pixel units of the first color is G1, and the minimum arrangement period of the sub-pixel units of the second color is G2, then G is the least common multiple of G1 and G2.

[0007] For example, in a display panel provided in an embodiment of the present disclosure, the plurality of shift register units are divided into at least one shift register unit scanning group, each of the shift register unit scanning group includes a plurality of shift register unit groups consisting of adjacent and cascaded shift register units, and no two adjacent shift register unit groups are cascaded.

[0008] For example, in the display panel provided in an embodiment of the present disclosure, each of the shift register unit scanning groups includes 16 shift register units, and in each of the shift register unit scanning groups, the k+1th shift register unit and the kth shift register unit are cascaded to form one shift register unit group, and the k+1th shift register unit and the k+2th shift register unit are not cascaded, and k is 1, 3, 5, 7, 9, 11, 13, or 15.

[0009] For example, in a display panel provided in an embodiment of the present disclosure, the gate driving circuit includes multiple shift register unit scanning groups. In two adjacent shift register unit scanning groups, the kth shift register unit in one shift register unit scanning group is connected to the k+1th shift register unit in another shift register unit scanning group, where k is 1, 3, 5, 7, 9, 11, 13, or 15.

[0010] For example, in a display panel provided in an embodiment of the present disclosure, the clock signals received by the 16 shift register units in each of the shift register unit scanning groups are respectively the first clock signal to the sixteenth clock signal, and the periods and duty cycles of the sixteen clock signals are equal.

[0011] For example, in the display panel provided in one embodiment of the present disclosure, the period is 16 time units, and the first clock signal, the fifth clock signal, the ninth clock signal, the thirteenth clock signal, the third clock signal, the seventh clock signal, the eleventh clock signal and the fifteenth clock signal are adjacent to each other in timing; the second clock signal, the sixth clock signal, the tenth clock signal, the fourteenth clock signal, the fourth clock signal, the eighth clock signal, the twelfth clock signal and the sixteenth clock signal are adjacent to each other in timing; the first clock signal and the second clock signal differ by 8 time units in timing.

[0012] For example, in a display panel provided in an embodiment of the present disclosure, the duty cycle is 9 / 20.

[0013] For example, in a display panel provided in an embodiment of the present disclosure, the sub-pixel unit array is divided into at least one sub-pixel unit scanning group, and the at least one sub-pixel unit scanning group corresponds one-to-one to the at least one shift register unit scanning group.

[0014] For example, in the display panel provided in an embodiment of the present disclosure, each of the shift register unit scanning groups includes 16 shift register units, and each of the sub-pixel unit scanning groups includes 8 rows of sub-pixel units adjacent to each other; in each of the sub-pixel unit scanning groups, the qth row of sub-pixel units and the 2q-1th shift register unit and the 2qth shift register unit in the shift register unit scanning group corresponding to the sub-pixel unit scanning group are electrically connected, and q is an integer greater than or equal to 1 and less than or equal to 8.

[0015] For example, in a display panel provided by an embodiment of the present disclosure, a gate line is disposed on both sides of each row of sub-pixel units, and the row of sub-pixel units is connected to the two gate lines disposed on both sides.

[0016] For example, in a display panel provided in one embodiment of the present disclosure, the display panel also includes a data driving circuit arranged in the peripheral area, wherein the data driving circuit is connected to the plurality of data lines, and the data driving circuit is configured to provide the data signal to the sub-pixel unit array in a 2-point polarity switching manner.

[0017] For example, in a display panel provided by an embodiment of the present disclosure, the polarity of the data signal provided by any one of the plurality of data lines is the same, and the routing shape of the data line is a zigzag shape.

[0018] For example, in a display panel provided in an embodiment of the present disclosure, in each shift register unit scanning group, the Lth shift register unit is arranged on a first side of the display area, and the Rth shift register unit is arranged on a second side of the display area, the second side is opposite to the first side, L is 1, 2, 3, 4, 9, 10, 11, 12; R is 5, 6, 7, 8, 13, 14, 15, 16.

[0019] For example, in a display panel provided by an embodiment of the present disclosure, all shift register units in each shift register unit scanning group are arranged on the same side of the display area.

[0020] At least one embodiment of the present disclosure further provides a display device, comprising any display panel provided by the embodiments of the present disclosure.

[0021] At least one embodiment of the present disclosure also provides a method for driving a display panel as provided in the embodiment of the present disclosure, comprising: providing the clock signal to the gate driving circuit so that the gate driving circuit generates the scanning signal, so that the at least two non-adjacent sub-pixel units of the same color connected to the same data line are displayed continuously in time sequence.

[0022] For example, in a driving method provided in an embodiment of the present disclosure, a plurality of sub-pixel units sequentially connected to the same data line are divided into G driving groups when being driven, the number of the clock signals is H, each of the driving groups includes F sub-pixel units, F=[H / G], [H / G] represents rounding H / G, and the driving method further includes driving the F sub-pixel units in the B-th driving group in the following order: A d =B+(d-1)*G, where A d represents the sequential number of the sub-pixel unit driven for the dth time, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.

[0023] For example, in a driving method provided in an embodiment of the present disclosure, the plurality of sub-pixel units connected in sequence to the same data line include at least a first color and a second color, and among the plurality of sub-pixel units connected in sequence to the same data line, the minimum arrangement period of the sub-pixel units of the first color is G1, and the minimum arrangement period of the sub-pixel units of the second color is G2, and the driving method further includes: taking the least common multiple of G1 and G2 as G.

[0024] For example, in the driving method provided in one embodiment of the present disclosure, G=4, H=16, and the driving method also includes driving the multiple sub-pixel units connected in sequence to the same data line in the following sequence: 1, 5, 9, 13, 3, 7, 11, 15, 2, 6, 10, 14, 4, 8, 12, 16.

[0025] At least one embodiment of the present disclosure also provides a driving method for a display panel as provided in the embodiment of the present disclosure, wherein the sub-pixel unit array is divided into at least one sub-pixel unit scanning group, the at least one sub-pixel unit scanning group corresponds one-to-one to the at least one shift register unit scanning group, and each of the sub-pixel unit scanning groups includes 8 rows of sub-pixel units adjacent to each other; for each shift register unit scanning group and the corresponding sub-pixel unit scanning group, the driving method includes: making the shift register unit scanning group provide the scanning signal to the sub-pixel unit scanning group corresponding to the shift register unit scanning group, so that the sub-pixel unit scanning group scans and displays in the following order: row 1, row 3, row 5, row 7, row 2, row 4, row 6, row 8, row 1, row 3, row 5, row 7, row 2, row 4, row 6, row 8. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0027] Figure 1 is a schematic diagram of a display panel;

[0028] Figure 2A For use Figure 1 A schematic diagram showing the relationship between a clock signal and a shift register unit of a display panel;

[0029] Figure 2B is an exemplary circuit diagram of a shift register unit;

[0030] Figure 3 For use Figure 1 A signal timing diagram of a clock signal of the display panel shown;

[0031] Figure 4 A schematic diagram for explaining the principle of an embodiment of the present disclosure;

[0032] Figure 5 A schematic diagram of a display panel provided by at least one embodiment of the present disclosure;

[0033] Figure 6A schematic diagram of a gate driving circuit provided in at least one embodiment of the present disclosure;

[0034] Figure 7 A schematic diagram of a shift register unit scanning group provided by at least one embodiment of the present disclosure;

[0035] Figure 8 A schematic diagram of the connection relationship between multiple shift register unit scanning groups provided by at least one embodiment of the present disclosure;

[0036] Fig. 9 For use Figure 5 A schematic diagram showing the relationship between a clock signal and a shift register unit of a display panel;

[0037] Fig.10 For use Figure 5 A signal timing diagram of a clock signal of the display panel shown;

[0038] Fig.11 A schematic diagram of another display panel provided for at least one embodiment of the present disclosure;

[0039] Fig.12 A schematic diagram of a connection relationship between a shift register unit scanning group and a sub-pixel unit scanning group provided by at least one embodiment of the present disclosure;

[0040] Fig.13 A schematic diagram of another display panel provided for at least one embodiment of the present disclosure;

[0041] Fig.14 A schematic diagram of another display panel provided for at least one embodiment of the present disclosure; and

[0042] Fig.15 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantitative restrictions, but indicate the existence of at least one. "Include" or "comprises" and other similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0045] Figure 1 A display panel is shown, which includes a plurality of sub-pixel units PU arranged in an array, for example, including sub-pixel units PU of three colors (red sub-pixel unit R, green sub-pixel unit G, blue sub-pixel unit B) to achieve color display. It should be noted that Figure 1 Only 5 rows and 12 columns of sub-pixel units PU are shown, and the embodiments of the present disclosure include but are not limited to this. The number of sub-pixel units PU can be set according to actual conditions. In addition, there is no limitation on the color types of the sub-pixel units PU. The display panel provided in the embodiments of the present disclosure is described by taking three types of sub-pixel units PU of RGB as an example, for example, the display panel is a liquid crystal display (LCD) panel.

[0046] like Figure 1 As shown, the display panel is a dual gate driven display panel, that is, one row of sub-pixel units is connected to two gate lines, and for example, two adjacent sub-pixel units in the row are connected to different gate lines. <1> And the gate line GL <2> Connect the second row of sub-pixel units PU and gate lines GL <3> And the gate line GL <4> Connect the third row of sub-pixel units PU and gate lines GL <5> And the gate line GL <6> Connect the fourth row of sub-pixel units PU and gate lines GL <7> And the gate line GL <8> Connect the fifth row of sub-pixel units PU and gate lines GL <9> And the gate line GL <10> connect.

[0047] like Figure 1 As shown, the display panel further includes a plurality of data lines DL (eg, DL <n-1>、DL <n>,DL<n+1> For example, in a dual-gate line driven display panel, two sub-pixel units in a row that are adjacent to each other and connected to different gate lines are respectively connected to the same data line. The routing shapes of the multiple data lines DL are all zigzag, and the polarities of the data signals received by the multiple sub-pixel units PU connected to any data line DL are the same. For example, the display panel can use a data driving circuit to provide data signals to the sub-pixel units PU through the data lines DL.

[0048] In addition, if Figure 1 As shown, the dual-gate line driven display panel adopts a 2-point polarity switching data driving method, that is, in the same row of sub-pixel units PU, the polarity of the data signals received by each two adjacent sub-pixel units PU is the same, and in the same column of sub-pixel units PU, the polarity of the data signals received by each two adjacent sub-pixel units PU is different.

[0049] For example, Figure 1 The display panel in the embodiment can be driven by a gate driving circuit. Figure 2A 1 shows a portion of the shift register units (first shift register unit SR1 to sixteenth shift register unit SR16) included in the gate drive circuit and clock signals (first clock signal CLK1 to sixteenth clock signal CLK16) for the gate drive circuit, and these clock signals are provided by a timing controller (Timing Controller, not shown in the figure) through corresponding clock signal lines. For example, Figure 2A As shown, the first shift register unit SR1 receives the first clock signal CLK1, the second shift register unit SR2 receives the second clock signal CLK2, and so on, the sixteenth shift register unit SR16 receives the sixteenth clock signal CLK16. In addition, the ninth shift register unit SR9 is cascaded with the first shift register unit SR1, the tenth shift register unit SR10 is cascaded with the second shift register unit SR2, and so on, the sixteenth shift register unit SR16 is cascaded with the eighth shift register unit SR8.

[0050] It should be noted that, in the embodiments of the present disclosure, the cascade connection of the shift register unit A and the shift register unit B means that the output signal of the shift register unit A is provided as an input signal to the shift register B to trigger the shift register B, or the output signal of the shift register unit B is provided as an input signal to the shift register A to trigger the shift register A. The following embodiments are the same as this and will not be described in detail.

[0051] Figure 2B FIG. 6 is a circuit diagram of an exemplary shift register unit 600, for example, the shift register unit 600 is the nth stage of the gate driving circuit. Figure 2B As shown, the shift register unit 600 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a storage capacitor C1.

[0052] The first transistor T1 in the shift register unit 600 is an output transistor of the signal output end of the shift register unit 600. For example, the first electrode of the first transistor T1 is connected to the clock signal CLK, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 to obtain the output end of the shift register unit 600, and can output the scan signal Gn and the input signal for the next stage shift register unit 600. The gate of the first transistor T1 is connected to the pull-up node PU, thereby connecting the first electrode of the third transistor T3 and the second electrode of the fourth transistor T4.

[0053] The second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the low level signal VGL. The gate of the second transistor T2 is connected to the gate of the third transistor T3 and the output terminal of the shift register unit 600 in the next row, i.e., the n+1th row, to receive the scan signal G(n+1) as the output pull-down control signal. The first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, so that it can be turned on under the control of the output pull-down control signal, and the output signal of the output terminal is pulled down to the low level signal VGL when the scan signal Gn is not needed.

[0054] The first electrode of the third transistor T3 is also connected to the pull-up node PU, thereby being electrically connected to the second electrode of the fourth transistor T4 and the gate of the first transistor T1. The second electrode of the third transistor T3 is connected to the low level signal VGL. The gate of the third transistor T3 is also connected to the output end of the shift register unit 600 of the next row, i.e., the n+1th row, to receive the scan signal G(n+1) as a reset control signal (which is also an output pull-down control signal), so that it can be turned on under the control of the reset control signal, and the pull-up node PU is reset to the low level signal VGL, thereby turning off the first transistor T1.

[0055] The first electrode of the fourth transistor T4 is connected to its own gate, and is connected to the output end of the shift register unit 600 in the previous row, i.e., the n-1th row, to receive the scan signal G(n-1) as an input signal (and an input control signal), and the second electrode of the fourth transistor T4 is connected to the pull-up node PU, so that when the fourth transistor T4 is turned on, the pull-up node PU can be charged, so that the voltage of the pull-up node PU can turn on the first transistor T1, so that the clock signal CLK is output through the output end. One end of the storage capacitor C1 is connected to the gate of the first transistor T1, i.e., the pull-up node PU, and the other end is connected to the second electrode of the first transistor T1, so that the level of the pull-up node PU can be stored, and when the first transistor T1 is turned on for output, the level of the pull-up node PU can be continuously pulled up through its own bootstrap effect to improve the output performance.

[0056] Depend on Figure 2B When the gate drive circuit formed by the cascade connection of the shift register units 600 shown in the figure works, when the scan signal G(n-1) is at a high level, the fourth transistor T4 is turned on and charges the pull-up node PU, and the level of the pull-up node PU is increased so that the first transistor T1 is turned on, so the clock signal CLK can be output at the output end through the first transistor T1, that is, the scan signal Gn is equal to the clock signal CLK. When the clock signal CLK is at a high level, the scan signal Gn also outputs a high level. When the scan signal Gn is at a high level, the shift register unit 600 of the gate drive circuit inputs the high level signal Gn to the gate line GL of the corresponding row, so that the gates of the thin film transistors in all the sub-pixel units corresponding to the gate line GL of the row are applied with the signal, so that these thin film transistors are all turned on, and the data signal is input to the liquid crystal capacitor of the corresponding sub-pixel unit through the thin film transistor in each sub-pixel unit, so as to charge the liquid crystal capacitor in the corresponding sub-pixel unit, thereby realizing the writing and maintenance of the signal voltage of the sub-pixel unit. When the scanning signal G(n+1) is at a high level, the second transistor T2 and the third transistor T3 are turned on, thereby resetting the pull-up node PU and pulling down the output terminal. Therefore, through the gate driving circuit, for example, a row-by-row scanning driving function can be realized.

[0057] It should be noted that in each embodiment of the present disclosure, the structure of the shift register unit of the gate drive circuit is not limited to the structure described above. The shift register unit of the gate drive circuit can be any applicable structure and can also include more or fewer transistors and / or capacitors. For example, sub-circuits for realizing functions such as pull-up node control, pull-down node control, noise reduction, etc. are added. The embodiments of the present disclosure do not limit this.

[0058] Figure 3 Shows Figure 2A The timing relationship of the clock signals (the first clock signal CLK1 to the sixteenth clock signal CLK16) in FIG. Figure 3 As shown, the duty cycle (i.e., the ratio of the duration of the high level to the period) and the period of the first clock signal CLK1 to the sixteenth clock signal CLK16 are equal. The time when the sixteen clock signals are at the high level covers the entire time range, so the sixteen sub-clock signals can form a cycle group.

[0059] In addition, if Figure 3 As shown, the time that any two adjacent clock signals are staggered in timing can be defined as a time unit TU, and the period of the clock signal is 16*TU. Based on the definition of the time unit TU, the timing of two clock signals being adjacent means that the two clock signals are staggered in timing by one time unit TU. The descriptions of the time unit TU and the timing proximity in the following embodiments are the same and will not be repeated.

[0060] For example, a display panel needs to be tested after completing the manufacturing process, for example, to make the entire display panel display the same color, such as red, green or blue.

[0061] For example, Figure 1 As shown, the data line DL <n-1>The order of the connected sub-pixel units PU is R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G. Assuming that all red sub-pixel units R need to be lit, the data line DL <n-1>The order of the polarity of the data signal to be provided is +-+-+-+-+-+-+-+- (the red sub-pixel unit R needs to light up corresponding to the polarity +, and other colors correspond to the polarity -), and the number of polarity reversals (polarity changes from + to - or from - to + are both called polarity reversals) of the data signal provided is 16 times; for another example, the data line DL <n>The order of the connected sub-pixel units PU is R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G. Assuming that all red sub-pixel units R need to be lit, the data line DL <n>The order of the polarity of the data signal to be provided is +---+---+---+--- (the red sub-pixel unit R needs to light up corresponding to the polarity +, and other colors correspond to the polarity -), then the number of polarity reversals of the data signal provided is 8 times; for another example, the data line DL<n+1> The order of the connected sub-pixel units PU is B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B. Assuming that all red sub-pixel units R need to be lit, the data line DL<n+1> The order of polarity of the data signal that needs to be provided is --+---+---+---+- (the red sub-pixel unit R needs to light up corresponding to the polarity +, and other colors correspond to the polarity -), and the number of polarity reversals of the provided data signal is 8 times.

[0062] From the above, we can see that when Figure 1 When the display panel shown displays red, the data driving circuit needs to switch more times when providing data signals, which increases the power consumption of the display panel.

[0063] In order to reduce the number of polarity reversals when the data driving circuit provides data signals, the inventors have thought of making sub-pixel units of the same color connected to the same data line DL display continuously in timing, which can reduce the number of polarity reversals and thus reduce the power consumption of the display panel.

[0064] As can be seen from the above, the sub-pixel units PU connected to the same data line DL are arranged in a cycle of four. <n-1>The connected sub-pixel units PU can make the lighting order of each sub-pixel unit PU be R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G. In this case, the polarity reversal times when the data driving circuit provides the data signal is 2 times. For another example, for the data line DL <n>The sub-pixel units PU connected together can make the lighting order of each sub-pixel unit PU be B->B->B->B->R->R->R->R->G->G->G->G->B->B->B->B->B. In this case, the number of polarity reversals when the data driving circuit provides the data signal is 3 times. For another example, for the data line DL<n+1> The connected sub-pixel units PU can make the lighting order of each sub-pixel unit PU be R->R->R->R->B->B->B->B->G->G->G->G->G->G->G->G->G. In this case, the number of polarity reversals when the data driving circuit provides the data signal is 2. Therefore, the number of polarity reversals can be greatly reduced, thereby reducing the power consumption of the display panel.

[0065] In order to make Figure 1 The display panel shown in FIG. 1 lights up the sub-pixel unit PU in the above order, as shown in FIG. Figure 4 As shown, the connection relationship between the shift register unit (SR) and the gate line (GL) is staggered, which increases the design difficulty and may cause problems such as poor process and low product yield.

[0066] At least one embodiment of the present disclosure provides a display panel, including a display area and a peripheral area. The display area includes a sub-pixel unit array having multiple rows and columns of sub-pixel units, a gate driving circuit is arranged in the peripheral area, and the display area also includes multiple gate lines and multiple data lines for driving the sub-pixel unit array, each sub-pixel unit is driven to display by a scanning signal provided by a gate line and a data signal provided by a data line, and the same data line connects at least two sub-pixel units of the same color that are not adjacent to each other; the gate driving circuit includes a plurality of shift register units arranged in sequence, and the plurality of gate lines are arranged in sequence and are electrically connected to the plurality of shift register units arranged in sequence in a one-to-one correspondence; the gate driving circuit is configured to receive a clock signal and generate a scanning signal so that at least two sub-pixel units of the same color that are not adjacent to each other and connected to the same data line are displayed continuously in timing.

[0067] At least one embodiment of the present disclosure also provides a display device and a driving method corresponding to the above-mentioned display panel.

[0068] The display panel, display device and driving method provided by some embodiments of the present disclosure can avoid the problems of poor process and low product yield caused by the staggered wiring between the gate driving circuit and the gate line, and can also reduce power consumption.

[0069] The embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0070] At least one embodiment of the present disclosure provides a display panel 10, such as Figure 5 As shown, the display panel 10 includes a display region DR and a peripheral region PR.

[0071] The display region DR includes a sub-pixel unit array 100 having multiple rows and columns of sub-pixel units PU. It should be noted that: Figure 5 Only 5 rows and 12 columns of sub-pixel units PU are schematically shown, and the embodiments of the present disclosure include but are not limited to this, and the number of sub-pixel units PU included in the display panel 10 can be set as needed. For example, Figure 5 The arrangement of the sub-pixel unit array 100 shown in FIG. 1 may be performed in the form of Figure 1 The arrangement shown in .

[0072] The gate driving circuit 200 is disposed in the peripheral region PR, and the display region DR further includes a plurality of gate lines GL (eg, GL <1> GL <2> etc.) and a plurality of data lines DL (eg, DL <1> ,DL <2> ,DL <3> , etc.), for driving the sub-pixel unit array 100, each sub-pixel unit PU is driven to display by a scanning signal provided by a gate line GL and a data signal provided by a data line DL, and the same data line DL connects at least two sub-pixel units PU of the same color that are not adjacent to each other. For example, the data line DL <1> The order of connected sub-pixel units PU (from top to bottom and from right to left in the figure, the same below) is R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G->R->G, and the data line DL <2> The order of connected sub-pixel units PU is R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G, and the data line DL <3> The order of the connected sub-pixel units PU is B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B.

[0073] It should be noted that in Figure 5 In the embodiment shown, among the multiple sub-pixel units PU connected to each data line DL, any sub-pixel unit PU of the same color are not adjacent. The embodiments of the present disclosure include but are not limited to this. For example, it is also possible to make only the sub-pixel unit PU of one color non-adjacent while the sub-pixel unit PU of the other two colors adjacent; for another example, it is also possible to make only the sub-pixel unit PU of two colors non-adjacent while the sub-pixel unit PU of the other color adjacent.

[0074] The gate driving circuit 200 includes a plurality of sequentially arranged shift register units S1 to S10, and a plurality of gate lines GL are sequentially arranged and electrically connected to the plurality of sequentially arranged shift register units (S1 to S10, etc.) in a one-to-one correspondence. Figure 5 As shown, there is no staggered wiring when the multiple shift register units in the gate driving circuit 200 in the display panel 10 are connected to the multiple gate lines GL, thereby avoiding the problem of poor process and low product yield caused by staggered wiring between the gate driving circuit 200 and the gate lines GL. It should be noted that Figure 5 Only 10 shift register units in the gate drive circuit 200 are schematically shown. The embodiments of the present disclosure include but are not limited to this. The number of shift register units included in the gate drive circuit 200 can be set as needed. For example, in a display panel driven by dual gate lines, the number of shift register units can be set to twice the number of rows of sub-pixel units PU.

[0075] For example, the gate driving circuit 200 is configured to receive a clock signal and generate a scanning signal so that at least two non-adjacent sub-pixel units PU of the same color connected to the same data line DL are displayed sequentially in timing. <1> The display order of the connected sub-pixel units PU can be R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G, and the data line DL <2> The display order of the connected sub-pixel units PU can be B->B->B->B->R->R->R->R->G->G->G->G->B->B->B->B->B, and the data line DL <3> The display order of the connected sub-pixel units PU may be R->R->R->R->B->B->B->B->G->G->G->G->G->G->G->G->G. That is, under the drive of the scanning signal provided by the gate driving circuit 200, among the multiple sub-pixel units PU connected to any data line DL, the sub-pixel units PU of the same color are displayed continuously in timing.

[0076] In the display panel 10 provided in the embodiment of the present disclosure, the sub-pixel unit array 100 in the display area DR is driven by the gate driving circuit 200 so that at least two sub-pixel units PU of the same color that are not adjacent to each other and connected to the same data line DL are displayed continuously in timing, for example, all sub-pixel units PU of the same color that are not adjacent to each other and connected to the same data line DL are displayed continuously in timing. In this way, the number of polarity flips of the data signal provided to the sub-pixel unit array 100 can be reduced, thereby reducing the power consumption of the display panel 10. For example, a data driving circuit can be used to provide a data signal to the sub-pixel unit array 100.

[0077] For example, in some embodiments of the present disclosure, multiple sub-pixel units PU connected in sequence to the same data line DL are divided into G driving groups when being driven, the number of clock signals is H, each driving group includes F sub-pixel units, F = [H / G], [H / G] represents H / G rounded. Then the gate driving circuit 200 is further configured to make the F sub-pixel units PU in the Bth driving group be driven in the following order: A d =B+(d-1)*G,A d represents the sequential number of the sub-pixel unit PU driven for the dth time, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.

[0078] For example, multiple sub-pixel units PU connected in sequence to the same data line DL include at least a first color and a second color. Among the multiple sub-pixel units PU connected in sequence to the same data line DL, the minimum arrangement period of the sub-pixel unit PU of the first color is G1, and the minimum arrangement period of the sub-pixel unit PU of the second color is G2, then G is the least common multiple of G1 and G2.

[0079] For example, Figure 5 As shown below, the data line DL <1> The sub-pixel unit PU connected is taken as an example. And the data line DL <1> The order of the connected sub-pixel units PU is R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G; for example, the first color is red and the second color is green, then the minimum arrangement period of the sub-pixel unit PU of the first color is 2, that is, G1 is 2, and the minimum arrangement period of the sub-pixel unit PU of the second color is 4, that is, G2 is 4, then the least common multiple of G1 and G2 is 4, that is, G = 4. It should be noted that because the arrangement period of the blue sub-pixel unit PU is also 4, the two colors are used as an example here for explanation, but when the arrangement periods of the three colors are different, the value of G is the least common multiple of the arrangement periods of the sub-pixel units PU of the three colors.

[0080] For example, in some embodiments, the number of clock signals received by the gate driving circuit is 16, that is, H=16, so the number of sub-pixel units included in each driving group is F=[H / G]=4. Then in the first driving group (B=1), the sequence number of the sub-pixel unit PU driven for the first time (d=1) is A1=1+(1-1)*4=1, the sequence number of the sub-pixel unit PU driven for the second time (d=2) is A2=1+(2-1)*4=5, the sequence number of the sub-pixel unit PU driven for the third time (d=3) is A3=1+(3-1)*4=9, and the sequence number of the sub-pixel unit PU driven for the fourth time (d=4) is A4=1+(4-1)*4=13; similarly, in the second driving group, the sequence numbers of the sub-pixel units PU driven in sequence are 2, 6, 10, and 14; in the third driving group, the sequence numbers of the sub-pixel units PU driven in sequence are 3, 7, 11, and 15; in the fourth driving group, the sequence numbers of the sub-pixel units PU driven in sequence are 4, 8, 12, and 16.

[0081] It should be noted that the embodiments of the present disclosure do not limit the order between the above-mentioned driving groups. For example, in some embodiments, the gate driving circuit 200 is configured so that the driving groups are driven in the order of: the first driving group, the third driving group, the second driving group, and the fourth driving group. In other words, for the 16 sub-pixel units PU connected to the same data line, they are driven in the order of: 1, 5, 9, 13, 3, 7, 11, 15, 2, 6, 10, 14, 4, 8, 12, and 16. Figure 5 The gate driving circuit 200 shown in FIG. 1 is further described.

[0082] For example, Figure 6 As shown, a plurality of shift register units PU are divided into at least one shift register unit scanning group 210, each shift register unit scanning group 210 includes a plurality of shift register unit groups 220 composed of adjacent and cascaded shift register units PU, and two adjacent shift register unit groups 220 are not cascaded. Figure 6 As shown, each shift register unit group 220 includes m adjacent and cascaded shift register units PU, where m is an integer greater than or equal to 2.

[0083] It should be noted that, for the sake of clarity, Figure 6 Only one shift register unit scanning group 210 included in the gate driving circuit 200 is schematically shown, and the embodiments of the present disclosure include but are not limited to this. The number of shift register unit scanning groups 210 included in the gate driving circuit 200 in the embodiments of the present disclosure can be set as needed.

[0084] In some embodiments of the present disclosure, for example, Figure 7 As shown, each shift register unit scanning group 210 includes 16 shift register units (S <1> To S <16> ), in each shift register unit scanning group 210, the k+1th shift register unit and the kth shift register unit are cascaded to form a shift register unit group 220, and the k+1th shift register unit and the k+2th shift register unit are not cascaded, k is 1, 3, 5, 7, 9, 11, 13, 15.

[0085] For example, Figure 7 As shown, the second shift register unit S <2> and the first shift register unit S <1> The cascade connection forms a shift register unit group 220, and the second shift register unit S <2> and the third shift register unit S <3> Not cascaded; the fourth shift register unit S <4> and the third shift register unit S <3> The cascade connection forms a shift register unit group 220, and the fourth shift register unit S <4> and the fifth shift register unit S <5> No cascade; the sixth shift register unit S <6> and the fifth shift register unit S <5> The cascade connection forms a shift register unit group 220, and the sixth shift register unit S <6> and the 7th shift register unit S <7> Not cascaded; the 8th shift register unit S <8> and the 7th shift register unit S <7> The cascade connection forms a shift register unit group 220, and the eighth shift register unit S <8> and the 9th shift register unit S <9> No cascade; the 10th shift register unit S <10> and the 9th shift register unit S <9> The cascade connection forms a shift register unit group 220, and the tenth shift register unit S <10> and the 11th shift register unit S <11> Not cascaded; the 12th shift register unit S <12> and the 11th shift register unit S <11> The cascade connection forms a shift register unit group 220, and the 12th shift register unit S <12> and the 13th shift register unit S <13> Not cascaded; the 14th shift register unit S <14> and the 13th shift register unit S <13> The cascade connection forms a shift register unit group 220, and the 14th shift register unit S <14> and the 15th shift register unit S <15> Not cascaded; the 16th shift register unit S <16> and the 15th shift register unit S <15> The cascade connection forms a shift register unit group 220.

[0086] Combine the following Figure 8 When the gate driving circuit 200 includes a plurality of shift register unit scanning groups 210 , the plurality of shift register unit scanning groups 210 are cascaded.

[0087] In some embodiments of the present disclosure, for example, Figure 8 As shown, the gate driving circuit 200 includes a plurality of shift register unit scanning groups 210. It should be noted that, for the sake of clarity, Figure 8 Only two shift register unit scanning groups 210 included in the gate driving circuit 200 are shown, for example, respectively represented as 210 <1> and 210 <2> In the two adjacent shift register unit scanning groups 210, one shift register unit scanning group 210 <2> The kth shift register unit and another shift register unit scanning group 210 <1> The k+1th shift register unit in is connected, and k is 1, 3, 5, 7, 9, 11, 13, 15. In addition, it should be noted that, Figure 8 The relative position relationship between the two shift register unit scanning groups 210 shown does not represent the actual position relationship. It is only for the convenience of description. <2> Plotted in the shift register unit scanning group 210 <1> on the right side.

[0088] For example, Figure 8 As shown, the shift register unit scanning group 210 <2> The first shift register unit S in <1> and shift register unit scanning group 210 <1> The second shift register unit S in <2> Connection; shift register unit scanning group 210 <2> The third shift register unit S in <3> and shift register unit scanning group 210 <1> The fourth shift register unit S in <4> Connection; shift register unit scanning group 210 <2> The fifth shift register unit S in <5> and shift register unit scanning group 210 <1> The sixth shift register unit S in <6> Connection; shift register unit scanning group 210 <2> The seventh shift register unit S in <7> and shift register unit scanning group 210 <1> The 8th shift register unit S in <8> Connection; shift register unit scanning group 210 <2> The ninth shift register unit S in <9> and shift register unit scanning group 210 <1> The 10th shift register unit S in <10> Connection; shift register unit scanning group 210 <2> The 11th shift register unit S in <11> and shift register unit scanning group 210 <1> The 12th shift register unit S in <12> Connection; shift register unit scanning group 210 <2> The 13th shift register unit S in <13> and shift register unit scanning group 210 <14> The second shift register unit S in <14> Connection; shift register unit scanning group 210 <2> The 15th shift register unit S in <15> and shift register unit scanning group 210 <1> The 16th shift register unit S in <16> connect.

[0089] In the display panel 10 provided in some embodiments, as Fig. 9 As shown, each shift register unit scans 16 shift register units (S <1> To S <16> ) receive clock signals respectively from the first clock signal CK1 to the sixteenth clock signal CK16, and the periods and duty cycles of the sixteen clock signals are equal.

[0090] For example, Fig.10 FIG. 1 shows a signal timing diagram of a clock signal for a display panel 10 provided in an embodiment of the present disclosure. Fig.10 As shown, the first clock signal CK1 to the sixteenth clock signal CK16 are provided by the timing controller, and their periods and duty cycles are equal. For example, the period of each clock signal is 16 time units TU, i.e., 16TU, and the ratio of the time at a high level in each clock signal to the period is 7.2 / 16, i.e., the duty cycle of each clock signal is 9 / 20. It should be noted that Fig.10 The duty cycle shown is only illustrative, and the clock signal in the embodiment of the present disclosure may also adopt other duty cycles. For example, the time when the clock signal is at a low level may be slightly longer than the time when the clock signal is at a high level.

[0091] For example, Fig.10 As shown, the first clock signal CK1, the fifth clock signal CK5, the ninth clock signal CK9, the thirteenth clock signal CK13, the third clock signal CK3, the seventh clock signal CK7, the eleventh clock signal CK11 and the fifteenth clock signal CK15 are adjacent to each other in timing.

[0092] The second clock signal CK2, the sixth clock signal CK6, the tenth clock signal CK10, the fourteenth clock signal CK14, the fourth clock signal CK4, the eighth clock signal CK8, the twelfth clock signal CK12 and the sixteenth clock signal CK16 are adjacent to each other in timing. The first clock signal CK1 and the second clock signal CK2 differ in timing by 8 time units TU.

[0093] That is, the first clock signal CK1 to the sixteenth clock signal CK16 are provided to the gate driving circuit 200 in the following order: CK1->CK5->CK9->CK13->CK3->CK7->CK11->CK15->CK2->CK6->CK10->CK14->CK4->CK8->CK12->CK16. For example, the above-mentioned order of providing clock signals can be stored in the form of program code (algorithm) in a timing controller (Timing Controller) or other devices of the display panel 10, and the program code can be directly executed when needed to generate the required clock signal.

[0094] In the display panel 10 provided in some embodiments, for example, Fig.11 As shown, the sub-pixel unit array 100 is divided into at least one sub-pixel unit scanning group 110, and at least one sub-pixel unit scanning group 110 corresponds to at least one shift register unit scanning group 210. For example, Fig.11 Two sub-pixel unit scanning groups 110 and corresponding two shift register unit scanning groups 210 are shown respectively, but the embodiments of the present disclosure include but are not limited to this. The number of sub-pixel unit scanning groups 110 in the embodiments of the present disclosure can be set as needed.

[0095] For example, in the display panel 10 provided in some embodiments, as Fig.12 As shown, each shift register unit scanning group 110 includes 16 shift register units (S <1> To S <16> ), each sub-pixel unit scanning group 110 includes 8 rows of sub-pixel units adjacent to each other, for example, the first row of sub-pixel units PUL <1> To the eighth row of sub-pixel units PUL <8> .

[0096] For example, in each sub-pixel unit scanning group 110, the qth row of sub-pixel units and the 2q-1th shift register unit and the 2qth shift register unit in the shift register unit scanning group 210 corresponding to the sub-pixel unit scanning group 110 are electrically connected, where q is an integer greater than or equal to 1 and less than or equal to 8. Fig.12 As shown, the first row of sub-pixel units PUL <1> and the first shift register unit S <1> and the second shift register unit S <2> Electrical connection: second row sub-pixel unit PUL <2> and the third shift register unit S <3> And the fourth shift register unit S <4> Electrical connection: third row sub-pixel unit PUL <3> and the fifth shift register unit S <5> and the sixth shift register unit S <6> Electrical connection: fourth row sub-pixel unit PUL <4> and the seventh shift register unit S <7> and the eighth shift register unit S <8> Electrical connection: Fifth row sub-pixel unit PUL <5> and the ninth shift register unit S <9> and the tenth shift register unit S <10> Electrical connection: sixth row sub-pixel unit PUL <6> and the eleventh shift register unit S <11> and the twelfth shift register unit S <12> Electrical connection: seventh row sub-pixel unit PUL <7> and the thirteenth shift register unit S <13> and the fourteenth shift register unit S <14> Electrical connection: Eighth row sub-pixel unit PUL <8> and the fifteenth shift register unit S <15> and the sixteenth shift register unit S <16> Electrical connection.

[0097] For example, the shift register unit can be electrically connected to the corresponding sub-pixel unit row through the gate line. Fig.12 As shown, a gate line GL is disposed on both sides of each row of sub-pixel units, and the row of sub-pixel units is connected to the two gate lines GL disposed on both sides. Fig.13 Schematic diagram of a connection mode between a gate line GL, a shift register unit and a corresponding sub-pixel unit.

[0098] In the display panel 10 provided in some embodiments, as Fig.13 As shown, the display panel 10 includes a gate driving circuit 200 disposed in the peripheral region PR, and also includes a data driving circuit 300 disposed in the peripheral region PR. The gate driving circuit 200 is connected to a plurality of gate lines, and is also connected to a timing controller 400 through a clock signal line to receive a clock signal; the data driving circuit 300 is connected to a plurality of data lines DL, and the data driving circuit 300 is configured to provide a data signal to the sub-pixel unit array 100 in a 2-point polarity switching manner. For information about the 2-point polarity switching, please refer to Figure 1 The corresponding description in will not be repeated here.

[0099] For example, Fig.13 As shown, the polarity of the data signal provided by any one of the plurality of data lines DL is the same, and the routing shape of the data line DL is a zigzag shape.

[0100] Combine the following Fig.10 The signal timing diagram shown is Fig.13 The working principle of the display panel 10 shown in FIG. <1> The connected sub-pixel unit PU is taken as an example for explanation.

[0101] Since the first clock signal CK1 is the earliest in timing, the first shift register unit S <1> Through the gate line GL <1> Provides a scan signal, and the data driving circuit 300 transmits a scan signal through the data line DL <1> Provides data signal, so the data line DL <1> A connected red sub-pixel unit R is driven by the scanning signal and the data signal to display.

[0102] Then, since the fifth clock signal CK5 is adjacent to the first clock signal CK1 in timing, the fifth shift register unit S <5> Through the gate line GL <5> Provides a scan signal, and the data driving circuit 300 transmits a scan signal through the data line DL <1> Provides data signal, so the data line DL <1> Another connected red sub-pixel unit R is driven by the scanning signal and the data signal to display.

[0103] Then, since the ninth clock signal CK9 is adjacent to the fifth clock signal CK5 in timing, the ninth shift register unit S <9> Through the gate line GL <9> Provides a scan signal, and the data driving circuit 300 transmits a scan signal through the data line DL <1> Provides data signal, so the data line DL <1> Another connected red sub-pixel unit R is driven by the scanning signal and the data signal to display.

[0104] Then, since the thirteenth clock signal CK13 is adjacent to the ninth clock signal CK9 in timing, the thirteenth shift register unit S <13> Through the gate line GL <13> Provides scanning signal ( Fig.13 S is not shown <13> and grid line GL <13> ), and at the same time the data driving circuit 300 drives the data line DL <1> Provides data signal, so the data line DL <1> Another connected red sub-pixel unit R is driven by the scanning signal and the data signal to display.

[0105] Similarly, the gate driving circuit 200 provides a scanning signal to the sub-pixel unit array 100 according to the timing of the received clock signal, and the data driving circuit 300 transmits a scanning signal to the sub-pixel unit array 100 through the data line DL <1> The data signal is provided to the turned-on sub-pixel unit PU, thereby connecting to the data line DL. <1> The connected sub-pixel units PU are displayed in the following order: R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G, so that the data line DL <1> Among the multiple connected sub-pixel units PU, sub-pixel units PU of the same color are displayed continuously in time sequence, so that the number of polarity inversions of the data signal provided to the sub-pixel unit array 100 can be reduced, thereby reducing the power consumption of the display panel 10.

[0106] In the display panel 10 provided in some embodiments, as Fig.14 As shown, in each shift register unit scanning group 210, the Lth shift register unit is arranged on the first side of the display region DR, and the Rth shift register unit is arranged on the second side of the display region DR, the second side is opposite to the first side, L is 1, 2, 3, 4, 9, 10, 11, 12; R is 5, 6, 7, 8, 13, 14, 15, 16. For example, the first side is the left side of the display region DR, and the second side is the right side of the display region DR; or, the first side is the right side of the display region DR, and the second side is the left side of the display region DR. That is to say, the shift register units in the gate driving circuit 200 in the display panel 10 provided in the embodiment of the present disclosure can be respectively arranged on both sides of the display region DR.

[0107] For another example, in the display panel 10 provided in some other embodiments, the shift register units in the gate driving circuit 200 in the display panel 10 may also all be arranged on one side of the display region DR.

[0108] Compared with setting all the shift register units in the gate driving circuit 200 on one side of the display region DR, setting the shift register units in the gate driving circuit 200 on both sides of the display region DR can better reduce the frame size of the display panel and more easily achieve a narrow frame.

[0109] At least one embodiment of the present disclosure further provides a display device 1, such as Fig.15 As shown, the display device 1 includes any display panel 10 provided by the embodiments of the present disclosure.

[0110] It should be noted that the display device 1 in this embodiment can be: a liquid crystal panel, a liquid crystal TV, a monitor, an OLED panel, an OLED TV, electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0111] The technical effects of the display device 1 provided by the embodiments of the present disclosure may refer to the corresponding description about the display panel 10 in the above embodiments, which will not be repeated here.

[0112] At least one embodiment of the present disclosure also provides a driving method for a display panel. For example, the driving method can be used for any display panel 10 provided in the embodiments of the present disclosure. The driving method includes: providing a clock signal to the gate driving circuit 200 so that the gate driving circuit 200 generates a scanning signal, so that at least two non-adjacent sub-pixel units PU of the same color connected to the same data line DL are displayed continuously in timing.

[0113] In the driving method provided in some embodiments of the present disclosure, for example, a plurality of sub-pixel units PU sequentially connected to the same data line DL are divided into G driving groups when being driven, the number of clock signals is H, each driving group includes F sub-pixel units, F = [H / G], [H / G] represents rounding H / G, and the driving method further includes driving the F sub-pixel units PU in the B-th driving group in the following order: A d =B+(d-1)*G,A d represents the sequential number of the sub-pixel unit driven for the dth time, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.

[0114] In the driving methods provided in some embodiments of the present disclosure, for example, a plurality of sub-pixel units PU connected in sequence to the same data line DL include at least a first color and a second color, and among the plurality of sub-pixel units PU connected in sequence to the same data line DL, the minimum arrangement period of the sub-pixel unit PU of the first color is G1, and the minimum arrangement period of the sub-pixel unit PU of the second color is G2, and the driving method also includes: taking the least common multiple of G1 and G2 as G.

[0115] In the driving methods provided in some embodiments of the present disclosure, for example, G=4, H=16, the driving method also includes driving 16 sub-pixel units connected to the same data line in sequence according to the following sequence: 1, 5, 9, 13, 3, 7, 11, 15, 2, 6, 10, 14, 4, 8, 12, 16.

[0116] At least one embodiment of the present disclosure also provides a method for driving a display panel. For example, the sub-pixel unit array 100 of the display panel 10 is divided into at least one sub-pixel unit scanning group 110. At least one sub-pixel unit scanning group 110 corresponds one-to-one to at least one shift register unit scanning group 210, and each sub-pixel unit scanning group 110 includes 8 rows of sub-pixel units PU adjacent to each other.

[0117] For each shift register unit scanning group 210 and the corresponding sub-pixel unit scanning group 110, the driving method includes the following operation steps.

[0118] The shift register unit scanning group 210 provides a scanning signal to the sub-pixel unit scanning group 110 connected to the shift register unit scanning group 210, so that the sub-pixel unit scanning group 110 performs scanning and display in the following order:

[0119] Row 1, row 3, row 5, row 7, row 2, row 4, row 6, row 8, row 1, row 3, row 5, row 7, row 2, row 4, row 6, row 8.

[0120] It should be noted that for the detailed description of the above driving method and the technical effects, reference may be made to the above corresponding description of the display panel 10 .

[0121] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.< / n> < / n> < / n> < / n>

Claims

1. A display panel, comprising a display area and a peripheral area, wherein: The display area includes a sub-pixel unit array having multiple rows and columns of sub-pixel units, and a gate driving circuit is arranged in the peripheral area. The display area further comprises a plurality of gate lines and a plurality of data lines, the gate driving circuit comprises a plurality of sequentially arranged shift register units, the plurality of gate lines are sequentially arranged and electrically connected to the plurality of sequentially arranged shift register units; The gate drive circuit includes two shift register unit scanning groups, In each of the shift register unit scanning groups, the k+1th shift register unit and the kth shift register unit are cascaded to form a shift register unit group; The kth shift register unit in one shift register unit scanning group is connected to the k+1th shift register unit in another shift register unit scanning group, where k is 1, 3, 5, 7, 9, 11, 13, or 15.

2. The display panel according to claim 1, wherein: A gate line is respectively arranged on both sides of each row of sub-pixel units, and each row of sub-pixel units is connected to the two gate lines arranged on both sides.

3. The display panel according to claim 2, wherein: The plurality of sub-pixel units sequentially connected to the same data line include at least a first color and a second color.

4. The display panel according to claim 1, wherein: The shift register unit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a clock signal, and a second electrode of the first transistor is connected to a first electrode of the second transistor; The first electrode of the third transistor, the second electrode of the fourth transistor and the gate of the first transistor are connected to a pull-up node; The first electrode of the fourth transistor is connected to the gate of the fourth transistor.

5. The display panel according to claim 4, wherein: The first electrode of the fourth transistor is connected to the output end of the previous row of shift register units to receive a scan signal as an input signal and an input control signal, and the gate of the second transistor and the gate of the third transistor are connected to the output end of the next row of shift register units to receive a scan signal as a reset control signal.

6. The display panel according to claim 4, wherein: The shift register unit further includes a storage capacitor, One end of the storage capacitor is connected to the gate of the first transistor and the pull-up node, and the other end of the storage capacitor is connected to the second electrode of the first transistor; the gate of the third transistor is electrically connected to the gate of the second transistor; and the second electrode of the second transistor is connected to a low-level signal.

7. A display panel comprising a display area and a peripheral area, wherein: The display area includes a sub-pixel unit array having multiple rows and columns of sub-pixel units, and a gate driving circuit is arranged in the peripheral area. The display area further comprises a plurality of gate lines and a plurality of data lines for driving the sub-pixel unit array, each sub-pixel unit is driven for display by a scanning signal provided by a gate line and a data signal provided by a data line, and the same data line connects at least two sub-pixel units of the same color that are not adjacent to each other; The gate driving circuit comprises a plurality of sequentially arranged shift register units, the plurality of gate lines are sequentially arranged and electrically connected to the plurality of sequentially arranged shift register units, and the plurality of sequentially arranged shift register units are divided into at least one shift register unit scanning group; The gate driving circuit is configured to receive a clock signal and generate the scanning signal so that the at least two non-adjacent sub-pixel units of the same color connected to the same data line are displayed continuously in time sequence; The sub-pixel unit array is divided into at least one sub-pixel unit scanning group, and the at least one sub-pixel unit scanning group corresponds to the at least one shift register unit scanning group one by one; In each sub-pixel unit scanning group, the qth row of sub-pixel units and the 2q-1th shift register unit and the 2qth shift register unit in the shift register unit scanning group corresponding to the sub-pixel unit scanning group are electrically connected, and q is an integer greater than or equal to 1 and less than or equal to 8.

8. The display panel according to claim 7, wherein: When multiple sub-pixel units connected in sequence to the same data line are driven, they are divided into G driving groups, the number of the clock signals is H, each of the driving groups includes F sub-pixel units, F = [H / G], [H / G] represents rounding H / G; The gate driving circuit is further configured to drive the F sub-pixel units in the Bth driving group in the following order: A d =B+(d-1)*G, where A d represents the sequential number of the sub-pixel unit driven for the dth time, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.

9. The display panel according to claim 8, wherein: The plurality of sub-pixel units sequentially connected to the same data line include at least a first color and a second color, In the plurality of sub-pixel units sequentially connected to the same data line, the minimum arrangement period of the sub-pixel units of the first color is G1, and the minimum arrangement period of the sub-pixel units of the second color is G2, and G is the least common multiple of G1 and G2.

10. The display panel according to claim 7, wherein: Each of the shift register unit scanning groups includes 16 shift register units. The clock signals received by the 16 shift register units are respectively the first clock signal to the sixteenth clock signal, and the periods and duty cycles of the sixteen clock signals are equal.

11. The display panel according to claim 10, wherein: The cycle is 16 time units, and the first clock signal, the fifth clock signal, the ninth clock signal, the thirteenth clock signal, the third clock signal, the seventh clock signal, the eleventh clock signal and the fifteenth clock signal are adjacent to each other in timing; The second clock signal, the sixth clock signal, the tenth clock signal, the fourteenth clock signal, the fourth clock signal, the eighth clock signal, the twelfth clock signal and the sixteenth clock signal are adjacent to each other in timing; The first clock signal and the second clock signal differ in timing by 8 time units.

12. The display panel according to claim 11, wherein: The duty cycle is 9 / 20.

13. The display panel according to claim 7, wherein: The display panel further includes a data driving circuit disposed in the peripheral region, wherein the data driving circuit is connected to the plurality of data lines, and the data driving circuit is configured to provide the data signal to the sub-pixel unit array in a 2-point polarity switching manner.

14. The display panel according to claim 13, wherein: The polarity of the data signal provided by any one of the plurality of data lines is the same, and the routing shape of the data line is a sawtooth shape.

15. The display panel according to claim 9, wherein: In each shift register unit scanning group, the Lth shift register unit is arranged at a first side of the display area, and the Rth shift register unit is arranged at a second side of the display area, the second side being opposite to the first side. Among them, L is 1, 2, 3, 4, 9, 10, 11, 12; R is 5, 6, 7, 8, 13, 14, 15, 16.

16. A display device comprising the display panel according to any one of claims 1 to 15.

17. A method for driving a display panel according to any one of claims 7, 10-15, comprising: providing the clock signal to the gate driving circuit so that the gate driving circuit generates the scanning signal, So that the at least two non-adjacent sub-pixel units of the same color connected to the same data line are displayed continuously in time sequence.

18. The driving method according to claim 17, wherein: When multiple sub-pixel units connected in sequence to the same data line are driven, they are divided into G driving groups, the number of the clock signals is H, each of the driving groups includes F sub-pixel units, F = [H / G], [H / G] represents the integer of H / G, The driving method further includes driving the F sub-pixel units in the B-th driving group in the following order: A d =B+(d-1)*G, where A d represents the sequential number of the sub-pixel unit driven for the dth time, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.

19. The driving method according to claim 18, wherein: The plurality of sub-pixel units sequentially connected to the same data line include at least a first color and a second color, Among the plurality of sub-pixel units sequentially connected to the same data line, the minimum arrangement period of the sub-pixel units of the first color is G1, and the minimum arrangement period of the sub-pixel units of the second color is G2. The driving method further includes: taking the least common multiple of G1 and G2 as G.

20. The driving method according to claim 18 or 19, wherein: G=4, H=16, the driving method further comprises driving the plurality of sub-pixel units sequentially connected to the same data line according to the following sequence number: 1、5、9、13、3、7、11、15、2、6、10、14、4、8、12、16。

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