Page buffer, memory device including the same, and operating method thereof

Abstract

The present application relates to a page buffer, a memory device including the same, and an operating method thereof. An electronic device is provided, and more particularly, a page buffer. The page buffer includes a sense node configured to sense a potential of a bit line coupled to a memory cell, a pre-charge circuit coupled to the sense node and configured to pre-charge a potential of the sense node to a first voltage during an evaluation operation on the memory cell, a discharge circuit coupled to the sense node and configured to discharge the potential of the sense node from the first voltage to a second voltage, and a latch circuit coupled to the discharge circuit and configured to store therein data sensed from the memory cell based on a comparison result of the potential of the sense node with a reference voltage after the potential of the sense node is discharged to the second voltage and a predetermined period of time elapses.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to electronic devices, and more specifically, to page buffers, memory devices including page buffers, and methods of operating the memory devices. Background Technology

[0002] Storage devices can store data in response to control by a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Generally, there are two types of memory devices: volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices can store data only when powered on, and the data stored therein can be lost when power is not supplied. Examples of volatile memory devices include static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices.

[0004] Even if the power supply is interrupted or blocked, non-volatile memory devices can retain the stored data. Examples of non-volatile memory devices include read-only memory (ROM) devices, programmable ROM (PROM) devices, electrically programmable ROM (EPROM) devices, electrically erasable programmable ROM (EEPROM) devices, flash memory devices, etc. Summary of the Invention

[0005] Various embodiments of this disclosure relate to page buffers and memory devices including such page buffers that mitigate bit line voltage overshoot and reduce evaluation time during read or verification operations.

[0006] According to embodiments of this disclosure, a page buffer may include: a sensing node configured to sense the potential of a bit line connected to a memory cell; a precharge circuit connected to the sensing node and configured to precharge the potential of the sensing node to a first voltage during an evaluation operation of the memory cell; a discharge circuit connected to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage; and a latch circuit connected to the discharge circuit and configured to store data sensed from the memory cell therein based on a comparison result of the potential of the sensing node and a reference voltage after the potential of the sensing node has been discharged to the second voltage and a predetermined period of time has elapsed, wherein the evaluation operation is an operation of sensing a threshold voltage of the memory cell by comparing the potential of the sensing node with the reference voltage and sensing a threshold voltage.

[0007] According to embodiments of this disclosure, a memory device may include: a plurality of memory cells; peripheral circuitry including a plurality of page buffers connected to the plurality of memory cells via bit lines and configured to perform a read operation on a selected memory cell among the plurality of memory cells; and control logic configured to control the peripheral circuitry to sense data stored in the selected memory cell during the read operation, wherein each of the plurality of page buffers includes: a first switch connected between a bit line connected to the memory cell and a first sensing node; a second switch connected between the first sensing node and a second sensing node; and a precharge circuit connected to the first sensing node. The system includes a second sensing node configured to precharge the bit line to a precharge voltage during a bit line precharge operation of a read operation and to precharge the second sensing node to a first voltage during an evaluation operation of a read operation; a discharge circuit connected to the second sensing node and configured to discharge the potential of the second sensing node from the first voltage to a second voltage during an evaluation operation; and a latch circuit connected to the discharge circuit and the second sensing node and configured to, after the potential of the second sensing node has been discharged to the second voltage and a predetermined period of time has elapsed, store data of the selected memory cell therein based on a comparison result of the potential of the second sensing node with a reference voltage.

[0008] According to embodiments of the present disclosure, a method of operating a memory device may include: precharging a bit line connected to a memory cell to a precharge voltage; precharging a potential of a sensing node connected to the bit line to a first voltage; discharging the potential of the sensing node from the first voltage to a second voltage; and after the potential of the sensing node has been discharged to the second voltage and a predetermined period of time has elapsed, storing data of the memory cell in a latch circuit based on a comparison result of the potential of the sensing node and a reference voltage, wherein the first voltage is a default voltage used to precharge the sensing node to sense a threshold voltage of the memory cell. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure;

[0010] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram showing the structure of the memory device;

[0011] Figure 3A This is a diagram illustrating the construction and operation of a page buffer according to an embodiment of the present disclosure;

[0012] Figure 3B This is a diagram illustrating the construction and operation of a page buffer according to an embodiment of the present disclosure;

[0013] Figure 4AThis is a diagram illustrating overshoot during pre-charging of an in-situ line according to an embodiment of the present disclosure;

[0014] Figure 4B This is a diagram illustrating overshoot mitigation according to an embodiment of the present disclosure;

[0015] Figure 5 This is a diagram illustrating a read operation according to an embodiment of the present disclosure;

[0016] Figure 6 This is a diagram illustrating the adjustment of the evaluation time during a read operation according to an embodiment of the present disclosure;

[0017] Figure 7 This is a diagram illustrating the discharge effect of a transistor connected to a second sensing node during a readout operation, according to an embodiment of the present disclosure; and

[0018] Figure 8 This is a flowchart illustrating a read operation of a memory cell according to an embodiment of the present disclosure. Detailed Implementation

[0019] Specific structural and functional features of this disclosure are disclosed in the context of the following embodiments. However, this disclosure may be configured, arranged, or implemented in ways other than those disclosed herein. Therefore, this disclosure is not limited to any particular embodiment, nor to any particular detail. Furthermore, throughout the specification, references to “implementation,” “another embodiment,” etc., do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. Additionally, the use of indefinite articles (i.e., “a” or “an”) indicates one or more unless clearly intended to be only one. Similarly, the terms “comprising,” “including,” “having,” etc., when used herein, do not exclude the presence or addition of one or more other elements besides those mentioned.

[0020] It should be understood that the accompanying drawings are simplified schematic diagrams of the described apparatus and may not include well-known details to avoid obscuring the features of the invention.

[0021] It should also be noted that a feature present in one embodiment may be used in conjunction with one or more features in another embodiment without departing from the scope of the invention.

[0022] It should also be noted that in the various figures, similar reference numerals refer to similar elements.

[0023] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0024] Figure 1This is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

[0025] Reference Figure 1 Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device 100. Storage device 50 may store data in response to control by a host. Examples of a host may include a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game player, TV, tablet PC, or in-vehicle infotainment system.

[0026] Depending on the host interface corresponding to the communication method with the host, the storage device 50 can be manufactured as one of various types of storage devices. The storage device 50 can be configured as one of various types of storage devices such as a solid-state drive (SSD); a multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), and micro MMC; a secure digital card (SD) card, a mini SD card, or a micro SD card; a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a PCMCIA card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI-e card-type storage device, a compact flash memory (CF) card, a smart media card, and a memory stick.

[0027] Storage device 50 can be manufactured as one of various types of packages. For example, storage device 50 can be manufactured as one of various package types such as point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0028] The memory device 100 can store data. The memory device 100 can operate in response to control by the memory controller 200. The memory device 100 may include a memory cell array comprising a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. According to an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data. According to embodiments, memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM). By way of example, in the context of the following description, memory device 100 is NAND flash memory.

[0029] Memory device 100 can receive commands and addresses from memory controller 200 and access the region selected by the address in the memory cell array of memory device 100. That is, memory device 100 can perform an operation corresponding to the command on the region selected in response to the address. For example, memory device 100 can perform write operations (or programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the region selected by the address. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase data from the region selected by the address.

[0030] The memory controller 200 can control the general operation of the storage device 50.

[0031] When power is supplied to storage device 50, memory controller 200 can execute instructions such as firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can execute firmware such as flash translation layer (FTL) to control communication between the host and storage device 100.

[0032] According to the implementation, the memory controller 200 can receive data and logical block addresses (LBAs) from the host and convert the LBAs into physical block addresses (PBAs) that indicate the addresses of memory cells in the memory device 100 where data is to be stored.

[0033] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to a request from the host. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, a PBA, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with reading commands and a PBA. During an erasing operation, the memory controller 200 can provide the memory device 100 with erasing commands and a PBA.

[0034] According to one implementation, the memory controller 200 can autonomously generate programming commands, addresses, and data without receiving requests from the host and send them to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0035] According to the implementation, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operational performance.

[0036] The host can communicate with the storage device 50 using at least one of various communication standards or interfaces such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI-e, High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Lightweight DIMM (LRDIMM).

[0037] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram showing the structure of the memory device 100.

[0038] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0039] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 123 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. According to an embodiment, the multiple memory cells may be non-volatile memory cells. Among the multiple memory cells, memory cells connected to the same word line can be defined as a physical page. In other words, the memory cell array 110 may include multiple physical pages.

[0040] Each memory cell of the memory device 100 may be a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a three-level cell (TLC) storing three bits of data, or a four-level cell (QLC) storing four bits of data.

[0041] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, and a data input / output circuit 124.

[0042] The peripheral circuitry 120 can drive the memory cell array 110. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform programming operations, reading operations, and erasing operations.

[0043] Address decoder 121 can be connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments of this disclosure, row lines RL may also include pipe select lines.

[0044] Address decoder 121 can be configured to operate in response to control of control logic 130. Address decoder 121 can receive address ADDR from control logic 130.

[0045] Address decoder 121 can be configured to decode block addresses in received address ADDR. Address decoder 121 can select at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can also be configured to decode row addresses in received address ADDR. Address decoder 121 can select at least one word line of the selected memory block by applying a voltage supplied from voltage generator 122 to at least one word line based on the decoded row address.

[0046] During programming operations, address decoder 121 may apply a programming voltage to the selected word lines and a pass voltage with a lower level than the programming voltage to the unselected word lines. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word lines and a verification pass voltage with a higher level than the verification voltage to the unselected word lines.

[0047] During a read operation, the address decoder 121 may apply a read voltage to the selected word line and a pass voltage with a higher level than the read voltage to the unselected word line.

[0048] According to embodiments of this disclosure, the erase operation of the memory device 100 can be performed on a block-by-block basis. The address ADDR input to the memory device 100 during the erase operation may include a block address. The address decoder 121 can decode the block address and select a memory block in response to the decoded block address. During the erase operation, the address decoder 121 may apply a ground voltage to the word line connected to the selected memory block.

[0049] According to embodiments of this disclosure, address decoder 121 can be configured to decode column addresses in received address ADDR. The decoded column addresses can be transmitted to read / write circuitry 123. For example, address decoder 121 may include components such as row decoders, column decoders, and address buffers.

[0050] Voltage generator 122 can be configured to generate multiple voltages by using an external power supply voltage provided to memory device 100. Voltage generator 122 can operate in response to control of control logic 130.

[0051] According to the embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 can be used as the operating voltage of the memory device 100.

[0052] According to the implementation, voltage generator 122 can generate multiple voltages by using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple selected read voltages, and multiple unselected read voltages.

[0053] The voltage generator 122 may include a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of voltages having various voltage levels, and the plurality of pumping capacitors may be selectively activated in response to control of control logic 130 to generate a plurality of voltages.

[0054] The generated voltages can be provided to the memory cell array 110 by the address decoder 121.

[0055] The read / write circuit 123 may include a first page buffer PB1 to a page m buffer PBm. The first page buffer PB1 to the page m buffer PBm may be connected to the memory cell array 110 in a one-to-one manner via a first bit line BL1 to a page m line BLm. The first page buffer PB1 to the page m buffer PBm may operate in response to the control of the control logic 130.

[0056] Page buffers PB1 through PBm can communicate data DATA with data input / output circuit 124. During programming operations, page buffers PB1 through PBm can receive the data DATA to be stored via data input / output circuit 124 and data line DL.

[0057] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA to be stored, received via the data input / output circuit 124, to the selected memory cell through bit lines BL1 to BLm. The memory cell of the selected page can be programmed based on the transmitted data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm can read the data DATA stored in the selected memory cell through bit lines BL1 to BLm.

[0058] During a read operation, the read / write circuit 123 can read data DATA from the memory cell of the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0059] During the erase operation, the read / write circuit 123 can float bit lines BL1 to BLm. According to one embodiment, the read / write circuit 123 may include column select circuitry.

[0060] The data input / output circuit 124 can be connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0061] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 may output the data DATA transferred from the first page buffer PB1 to the m-th page buffer PBm in the read / write circuit 123 to the external controller.

[0062] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit VRYBIT signal generated by the control logic 130, and can output a pass or fail signal PASS / FAIL to the control logic 130 by comparing the voltage VPB received from the read / write circuit 123 with the reference voltage generated by the reference current.

[0063] Control logic 130 can be connected to address decoder 121, voltage generator 122, read / write circuit 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can be configured to control the general operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0064] Control logic 130 can control peripheral circuit 120 by generating various signals in response to command CMD and address ADDR. For example, in response to command CMD and address ADDR, control logic 130 can generate operation signal OPSIG, address ADDR, read / write circuit control signal PBSIGNALS, and enable bit VRYBIT. Control logic 130 can output operation signal OPSIG to voltage generator 122, address ADDR to address decoder 121, read / write circuit control signal PBSIGNALS to read / write circuit 123, and enable bit VRYBIT to sensing circuit 125. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to pass / fail signal PASS / FAIL output from sensing circuit 125.

[0065] Figure 3A This is a diagram illustrating the construction and operation of a page buffer according to an embodiment of the present disclosure.

[0066] Reference Figure 3APage buffer PB1 can be connected to a memory cell via bit line BL. Page buffer PB1 may include first transistor T1 to fourth transistor T4 and sixth transistor T6 to twelfth transistor T12. First transistor T1, second transistor T2, and seventh transistor T7 may be P-MOS transistors. Third transistor T3, fourth transistor T4, sixth transistor T6, and eighth transistor T8 to twelfth transistor T12 may be N-MOS transistors. Each transistor can be turned on or off in response to a signal applied to its gate.

[0067] Page buffer PB1 may include a precharge circuit 301, a bit line connection control circuit 302, a discharge circuit 303, and a latch circuit 304. The precharge circuit 301 can be connected to the bit line connection control circuit 302 via a first sensing node CSO and a second sensing node SO. The precharge circuit 301 can be connected to the latch circuit 304 via a first node QS.

[0068] Bit line connection control circuit 302 can be connected to bit line BL. Bit line connection control circuit 302 can be connected to pre-charge circuit 301 through first sensing node CSO and second sensing node SO. Bit line connection control circuit 302 can be connected to discharge circuit 303 through second sensing node SO. Bit line connection control circuit 302 can be connected to latch circuit 304 through second sensing node SO.

[0069] The discharge circuit 303 can be connected to the bit line connection control circuit 302 via the second sensing node SO. The discharge circuit 303 can also be connected to the latch circuit 304 via the first node QS.

[0070] The latch circuit 304 can be connected to the discharge circuit 303 via the first node QS. The latch circuit 304 can be connected to the bit line connection control circuit 302 via the second sensing node SO.

[0071] The precharge circuit 301 may include a first transistor T1, a second transistor T2, a seventh transistor T7, and an eighth transistor T8. More specifically, the seventh transistor T7 may be controlled by a pre-sensing signal SA_PRE_N. The eighth transistor T8 may be controlled by a first precharge signal SA_CSOC. The first transistor T1 may be controlled by the potential of the first node QS. The potential of the first node QS may indicate the data value stored in the latch. The second transistor T2 may be controlled by a second precharge signal SA_PRECH_N.

[0072] The precharge circuit 301 can perform a precharge operation on the first sensing node CSO in response to the first precharge signal SA_CSOC and the pre-sensing signal SA_PRE_N. When the sixth transistor T6 is turned on by the page buffer sensing signal PBSENSE, the bit line BL can be precharged. The precharge circuit 301 can also perform a precharge operation on the second sensing node SO in response to the potential of the first node QS and the second precharge signal SA_PRECH_N.

[0073] Bit-line connection control circuit 302 may include a sixth transistor T6 and a ninth transistor T9. More specifically, the sixth transistor T6 may be controlled by the page buffer sensing signal PBSENSE. The ninth transistor T9 may be controlled by the control signal SA_SENSE.

[0074] The bit line BL connected to the memory cell can be precharged by turning on the sixth transistor T6, which is connected to the first sensing node CSO, in response to the page buffer sensing signal PBSENSE. The first sensing node CSO can be connected to the second sensing node SO by turning on the ninth transistor T9 with the control signal SA_SENSE.

[0075] The discharge circuit 303 may include a third transistor T3 and a fourth transistor T4. More specifically, the fourth transistor T4 may be controlled by a first discharge signal DSCH_1. The third transistor T3 may be controlled by the potential of the first node QS. The potential of the first node QS may indicate the data value stored in the latch.

[0076] The latch circuit 304 may include tenth transistor T10 through twelfth transistor T12 and latch assembly LATCH. More specifically, the eleventh transistor T11 may be controlled by the transfer signal TRANSN. The tenth transistor T10 may be controlled by the potential of the second node QS_N. The twelfth transistor T12 may be controlled by the page buffer reset signal PBRST1.

[0077] The latch component LATCH can sense and store the potential of the second sensing node SO, thereby storing the result of sensing the threshold voltage of the memory cell. More specifically, in response to the page buffer sensing signal PBSENSE, the potential of bit line BL, determined based on the threshold voltage of the memory cell during sensing operation, can be transmitted to the first sensing node CSO. The potential of bit line BL transmitted to the first sensing node CSO can be transmitted to the second sensing node SO in response to the control signal SA_SENSE. During the transmission of the potential of bit line BL to the second sensing node SO, the potential of bit line BL, as a result of sensing the threshold voltage of the memory cell, can be amplified. The latch circuit 304 can store the result of sensing the potential of the second sensing node SO in the latch component LATCH in response to the transmission signal TRANSN. According to various embodiments, the latch component LATCH can store the result of sensing the current of the second sensing node SO.

[0078] Figure 3B This is a diagram illustrating the construction and operation of a page buffer according to an embodiment of the present disclosure.

[0079] References above Figure 3A Compared to the page buffer PB1 described, the page buffer PB1′ according to embodiments of this disclosure may further include a fifth transistor T5 connected to the second sensing node SO of the discharge circuit 303. The fifth transistor T5 may be a P-MOS device that is turned on when a negative voltage is applied. More specifically, the fifth transistor T5 may be controlled in response to the second discharge signal DSCH_2.

[0080] According to embodiments of this disclosure, the page buffer PB1′ can precisely control the voltage level of the second sensing node SO by applying a negative voltage to the gate of the second sensing node SO and the fifth transistor T5 and discharging the potential of the second sensing node SO.

[0081] Figure 4A This is a diagram illustrating overshoot when the bit line is precharged according to an embodiment of the present disclosure.

[0082] Reference Figure 3B During the operation of the memory device, the bit line BL can be precharged to a predetermined voltage level by the precharge circuit 301.

[0083] More specifically, a voltage may be applied to the bit line BL during programming operations for storing data in a memory device or during read operations for retrieving data stored in a memory device.

[0084] During programming operations used to store data in a memory device, a programming enable voltage can be applied to the bit line BL connected to the selected memory cell. A programming disable voltage can be applied to the bit line BL connected to the unselected memory cell.

[0085] During a read operation for reading data stored in a memory device, a pre-charge voltage may be applied to the bit line BL connected to the memory cell to be sensed in order to pre-charge the bit line BL connected to the memory cell to be sensed.

[0086] During the pre-charge of bit line BL, the page buffer PB1 operates as follows.

[0087] Reference Figure 3A This can be achieved by applying a power supply voltage V to the bit line BL. CORE The bit line BL is precharged. More specifically, the sixth transistor T6, the eighth transistor T8, and the seventh transistor T7 can be turned on by the page buffer sensing signal PBSENSE, the first precharge signal SA_CSOC, and the pre-sensing signal SA_PRE_N, respectively. By turning on the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, the bit line BL can be precharged to the target level.

[0088] Reference Figure 4A The first precharge signal SA_CSOC applied to the gate of the eighth transistor T8 can be applied in two steps. More specifically, it can be applied in t a1 and t a2 A first voltage V1 is applied during the time interval between t and t. a2 and t a3 A second voltage V2 is applied during the period between the first voltage V1 and the second voltage V2. When the first voltage V1 and the second voltage V2 are applied, overshoot of the bit line may occur, that is, the potential level V of the bit line may increase. BL The phenomenon where the bit line potential level becomes higher than the target level. When a bit line overshoot occurs, the bit line potential level V... BL It may take a settling time t to reach the target level. settling_1 .

[0089] Figure 4B This is a diagram illustrating overshoot mitigation according to an embodiment of the present disclosure.

[0090] Reference Figure 4B , in t b1 and t b2 During the time interval between these two points, the first voltage V1 can be applied as the first pre-charge signal SA_CSOC to the gate of the eighth transistor T8. The first pre-charge signal SA_CSOC during t b2 and t b3 During the time interval, the voltage can drop to the third voltage V3, thereby turning off the eighth transistor T8. The third voltage V3 can be ground. b2 and t b3During the time interval, the ninth transistor T9 and the third transistor T3 can be turned on by the control signal SA_SENSE and the voltage level of the first node QS, respectively. The fourth voltage V4 can be applied to the gate of the fifth transistor T5 as the second discharge signal DSCH_2. The fourth voltage V4 can be a negative voltage. When the fourth voltage V4 is applied to the gate of the fifth transistor T5, the fifth transistor T5 can be turned on. Therefore, the voltage for pre-charging the bit line BL can be... b2 and t b3 During the interval between charges, the voltage of bit line BL is discharged by discharge circuit 303, thus mitigating overshoot. The setup time t required for the potential of bit line BL to reach the target level is 100% when the voltage of bit line BL is discharged after pre-charging. settling_2 It can be less than the establishment time t settling_1 In t b3 and t b4 During the time interval, a second voltage V2 can be applied to the gate of the eighth transistor T8 as a first precharge signal SA_CSOC. The second voltage V2 can correspond to a voltage that can maintain the voltage level of the bit line BL at a target level. As described in embodiments of this disclosure, a negative voltage with a predetermined level can be applied to the gate of the fifth transistor T5 connected to the second sensing node SO, thereby mitigating overshoot and reducing the time required for the potential of the bit line BL to reach the target level.

[0091] Figure 5 This is a diagram illustrating a read operation according to an embodiment of the present disclosure.

[0092] The read operation according to embodiments of this disclosure may include a bit line precharge period (BL precharge), an evaluation period (Evaluation), and a latching period (Latching).

[0093] Reference Figure 3A The bit line BL can be precharged to the precharge voltage during the bit line precharge period BL precharge. More specifically, it is connected in series with the power supply voltage V. CORE The seventh transistor T7 and the eighth transistor T8 between the node and the first sensing node CSO can be turned on. The sixth transistor T6 connected between the bit line BL and the first sensing node CSO can be turned on, thereby pre-charging the bit line BL to the pre-charge voltage. In addition, the transistor connected in series with the power supply voltage V CORE The first transistor T1 and the second transistor T2 between the node and the second sensing node SO can be turned on, thereby pre-charging the second sensing node SO.

[0094] During the evaluation period, the voltage level of the second sensing node SO can be changed or maintained based on the threshold voltage of the memory cell. When the memory cell is on and the source selection transistor connected between the memory cell and the ground node is on, the charge charged to bit line BL can be discharged to the ground node through the source line. Therefore, after a first duration, the potential of bit line BL can decrease. When the memory cell is off, the potential of bit line BL can be maintained because bit line BL and the source line are floating. After a first duration of a predetermined length, the ninth transistor T9 connected between the first sensing node CSO and the second sensing node SO can be turned on, thereby connecting the first sensing node CSO to the second sensing node SO. When the memory cell is on, the potential of the second sensing node SO can be discharged to the potential of bit line BL. Therefore, after a second duration of a predetermined length, the potential of the second sensing node SO can decrease to the potential of bit line BL. When the memory cell is off, the potential of the second sensing node SO can be maintained.

[0095] After the evaluation period ends, a latching operation can be performed to sense the voltage of the second sensing node SO and store the sensing result in the latch component LATCH. Before storing the sensing result of the memory cell in the latch component LATCH, an initialization operation of the latch can be performed. The latch component LATCH can sense and store the potential of the second sensing node SO, thereby storing the result of sensing the threshold voltage of the memory cell. More specifically, the latch circuit 304 can store the result of sensing the potential of the second sensing node SO in the latch component LATCH in response to the transmission signal TRANSN. According to various embodiments, the latch component LATCH can store the result of sensing the current of the second sensing node SO.

[0096] Figure 6 This is a diagram illustrating the adjustment of the evaluation time during a read operation according to an embodiment of the present disclosure.

[0097] Reference Figures 3A to 6 V SO Indicates the voltage level at the second sensing node SO.

[0098] V trip This indicates the level of the reference voltage used to determine whether a memory cell is a conducting cell. When the threshold voltage of the memory cell is lower than the reference voltage V... trip At this time, the memory cell can be identified as a conducting cell.

[0099] Reference Figure 3BThe ninth transistor T9 can be turned on during the evaluation period, thereby connecting the first sensing node CSO to the second sensing node SO. In the case of the first memory cell MC1, when charge discharges from the second sensing node SO, V SO It can be reduced. In the case of the second memory cell MC2, when charge discharges from the second sensing node SO through leakage current, V SO This can be reduced. The discharge rate of the charge in the second memory cell MC2 can be lower than the discharge rate of the charge in the first memory cell MC1.

[0100] In the case of the first memory unit MC1, after a time period t... default Then measure V SO At that time, V SO Below V trip Therefore, the first memory cell MC1 can be sensed as a conducting cell. In the case of the second memory cell MC2, after a time period t... default V was then measured immediately. SO At that time, V SO Higher than V trip Therefore, the second memory cell MC2 can be sensed as a cutoff cell.

[0101] In the case of the first memory unit MC1, after a time period t... default Then measure V SO At that time, V SO Below V trip Therefore, the first memory cell MC1 can be read as a conducting cell. In the case of the first memory cell MC1, after a time period t... eval_2 Then measure V SO At that time, V SO Higher than V trip Therefore, the first memory cell MC1 can be read as the cutoff cell. Thus, when the evaluation time is shorter than the time interval t... default At that time, V SO Possibly higher than V trip Furthermore, although the first memory cell MC1 is actually a conducting cell, it may be incorrectly read as a cut-off cell.

[0102] In the case of the second memory unit MC2, after a time period t... default Then measure V SO At that time, V SO Higher than V trip Therefore, the second memory cell MC2 can be read as the cutoff cell. In the case of the second memory cell MC2, when time period t has elapsed... eval_1 Then measure VSO At that time, V SO Below V trip Therefore, the second memory cell MC2 can be read as a conducting cell. That is, when the evaluation time increases to a length greater than the time period t... default At that time, V SO It may decrease to the ratio of V trip It has a smaller value, and although the second memory cell MC2 is actually a cutoff cell, the second memory cell MC2 may be incorrectly read as a conduction cell.

[0103] V R1 Indicates the read voltage applied to the word line of the memory cell to be sensed by the read operation. (See reference...) Figure 6 When the evaluation time is a time period t eval_1 At that time, although the actual reading voltage is V R1 However, by applying V R1 The sensing result as the read voltage can be compared with that obtained by applying V. R2 The sensing result is the same as the read voltage. According to this example, although a memory cell in region C1 is actually a conducting cell, it may be incorrectly sensed as a cut-off cell. When the evaluation time is a time interval t... eval_2 At that time, although the actual voltage read was V R1 However, by applying V R1 The sensing result as the read voltage can be compared with that obtained by applying V. R3 The sensing result for the read voltage is the same. According to this example, although the memory cell in region C2 is actually a cutoff cell, the memory cell in region C2 may be incorrectly sensed as a conduction cell.

[0104] As referenced above Figure 6 As described, it may be necessary to set an appropriate evaluation time to correctly determine whether the memory cell to be sensed is an on or off cell.

[0105] Figure 7 This is a diagram illustrating the discharge effect of a transistor connected to a second sensing node SO during a readout operation, according to an embodiment of the present disclosure.

[0106] V SO1 This indicates the voltage level of the second sensing node SO when it is not discharged. V SO1 It can be the voltage level to which the second sensing node SO is pre-charged in order to sense the threshold voltage without discharging.

[0107] V SO2 Indicates the voltage level of the second sensing node SO when the second sensing node SO discharges.

[0108] V trip This indicates the level of the reference voltage used to determine whether a memory cell is a conducting cell. A memory cell can be determined to be a conducting cell when its threshold voltage level is lower than the reference voltage. When the voltage level at the second sensing node SO does not reach V... trip When sensing a memory cell in a certain state, even though the memory cell is actually a conducting cell, it may be incorrectly identified as a cut-off cell. Therefore, to correctly determine whether a memory cell is a conducting cell or a cut-off cell, the voltage level after passing through the second sensing node SO can reach V. trip The voltage of the second sensing node SO is sensed after the required time.

[0109] Time period t eval This indicates that the voltage level of the second sensing node SO reaches V when the second sensing node SO is not discharged. trip The required time period.

[0110] Time period t eval The indicator, according to an embodiment of this disclosure, states that when the second sensing node SO is discharged, the voltage level of the second sensing node SO reaches V. trip The required time period.

[0111] Reference Figure 3A , Figure 5 and Figure 7 The second sensing node SO can be precharged to the power supply voltage V during the bit line precharge period BL precharge. CORE When the ninth transistor T9 is turned on via the control signal SA_SENSE during the evaluation period, the second sensing node SO can be connected to the first sensing node CSO. When the memory cell connected to the bit line BL is a conducting cell, a time period t can be spent. eval To make the voltage level of the second sensing node SO reach V trip .

[0112] Reference Figure 3B , Figure 5 and Figure 7 The second sensing node SO can be precharged to V during the bit line precharge period BL precharge. SO1 At the second sensing node SO, it is pre-charged to V. SO1 Subsequently, the fifth transistor T5 can be turned on by the negative voltage second discharge signal DSCH_2, thereby discharging the voltage of the second sensing node SO. The voltage of the second sensing node SO can drop below V. SO1 V SO2 When the memory cell connected to bit line BL is a conducting cell, it can take a time period t.eval To make the voltage level of the second sensing node SO reach V trip Because V SO2 Below V SO1 Therefore, the time period t eval ′ can be shorter than the time period t eval .

[0113] As described above in the embodiments of this disclosure, during the evaluation operation, the voltage level of the second sensing node SO can be adjusted to a predetermined voltage level by discharging the P-MOS transistor connected to the second sensing node SO. trip The time required.

[0114] V can be achieved by reducing the voltage level of the second sensing node SO. trip The required time is reduced to the time required to perform read operations.

[0115] Reference above Figure 6 and Figure 7 The described features can also be applied in the same way to the programming verification operation of memory cells. When these features are applied to the programming verification operation, the total time tPROG required to perform the programming operation can be reduced by decreasing the time required to perform the programming verification operation.

[0116] Figure 8 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0117] When operating S801, the memory device can discharge the bit lines to the pre-charge voltage.

[0118] During operation S803, the memory device can store the potential (V) of the second sensing node. SO Precharge to the first voltage.

[0119] During operation S805, the memory device can store the potential (V) of the second sensing node. SO Discharge to the second voltage.

[0120] During operation S807, the memory device can store the potential (V) of the second sensing node. SO ) and reference voltage (V trip (Compare)

[0121] The memory device can be based on the potential (V) of the second sensing node SO. SO ) and reference voltage (V trip The results of the comparison are used to store the data in the latch circuit.

[0122] More specifically, in operation S809, when the potential (V) of the second sensing node SO... SO ) greater than the reference voltage (V trip When a memory device reads a memory cell as a cutoff cell, it can store the result in a latch circuit.

[0123] During operation S811, when the potential (V) of the second sensing node SO... SO ) less than or equal to the reference voltage (V) trip When the memory device reads the memory cell as an active cell, it can store the result in the latch circuit.

[0124] According to embodiments of the present disclosure, a page buffer and a memory device including the page buffer can be provided to mitigate bit line voltage overshoot and reduce evaluation time during read or verification operations.

[0125] The present disclosure described above is not limited to the foregoing embodiments and drawings. It will be apparent to those skilled in the art to which this disclosure pertains that the present disclosure can be substituted, modified, and altered in various ways without departing from the technical spirit of the present disclosure and the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

[0126] Cross-references to related applications

[0127] This application claims priority to Korean Patent Application No. 10-2021-0104892, filed on August 9, 2021, the entirety of which is incorporated herein by reference.

Claims

1. A page buffer, the page buffer comprising: A sensing node that senses the potential of a bit line connected to a memory cell; A pre-charge circuit is connected to the sensing node and pre-charges the potential of the sensing node to a first voltage during the evaluation operation of the memory cell; A discharge circuit is connected to the sensing node and discharges the potential of the sensing node from the first voltage to the second voltage; as well as A latch circuit, connected to the discharge circuit, stores data sensed from the memory cell in the latch circuit after the potential of the sensing node has been discharged to the second voltage and a predetermined period of time has elapsed. This data is based on a comparison between the potential of the sensing node and a reference voltage. The evaluation operation involves sensing the threshold voltage of the memory cell by comparing the potential of the sensing node with the reference voltage. The pre-charge circuit includes a first transistor and a second transistor connected in series between the power supply voltage node and the sensing node. The discharge circuit includes a third transistor, a fourth transistor, and a fifth transistor connected between the sensing node and the ground node. The fourth transistor and the fifth transistor are connected in parallel. The third transistor is connected in series with the fourth transistor and the fifth transistor. The first transistor and the second transistor are turned on during the first time period and turned off during the second time period. The third transistor and the fifth transistor are turned on during the second time period. The fourth transistor is turned off during the second time period.

2. The page buffer according to claim 1, in, The potential of the sensing node is pre-charged to the first voltage during the first time period and discharged to the second voltage during the second time period.

3. The page buffer according to claim 1, wherein, The fifth transistor is a P-MOS device and the fourth transistor is an N-MOS device.

4. The page buffer according to claim 1, in, The first transistor is controlled by the data value stored in the latch circuit. The second transistor is controlled by the first precharge signal. The third transistor is controlled by the data value stored in the latch circuit. The fourth transistor is controlled by the first discharge signal, and The fifth transistor is controlled by the second discharge signal.

5. The page buffer according to claim 1, wherein, The reference voltage is used to determine whether the memory cell is a conducting cell or a cut-off cell.

6. The page buffer according to claim 1, wherein, The latch circuit stores the data by reading the memory cell as a cutoff cell when the potential of the sensing node is higher than the reference voltage and reading the memory cell as a conduction cell when the potential of the sensing node is lower than the reference voltage.

7. A memory device, the memory device comprising: Multiple memory units; The peripheral circuitry includes multiple page buffers connected to the plurality of memory cells via bit lines, and performs read operations on selected memory cells among the plurality of memory cells. as well as Control logic that controls the peripheral circuitry to sense data stored in the selected memory cell during the read operation. Each of the plurality of page buffers includes: A first switch is connected between a bit line connected to a memory cell and a first sensing node. A second switch is connected between the first sensing node and the second sensing node; A pre-charge circuit is connected to the first sensing node and the second sensing node, and pre-charges the bit line to a pre-charge voltage during the bit line pre-charge operation of the read operation and pre-charges the second sensing node to a first voltage during the evaluation operation of the read operation. A discharge circuit, connected to the second sensing node, discharges the potential of the second sensing node from the first voltage to the second voltage during the evaluation operation; and A latch circuit is connected to the discharge circuit and the second sensing node. After the potential of the second sensing node is discharged to the second voltage and a predetermined period of time has elapsed, the selected memory cell's data is stored in the latch circuit based on a comparison between the potential of the second sensing node and a reference voltage. The pre-charging circuit pre-charges the first sensing node during the bit line pre-charging operation. The first switch is turned on after the first sensing node is pre-charged, and connects the bit line to the first sensing node. The second switch is turned on after the second sensing node is discharged to the second voltage, and connects the first sensing node to the second sensing node.

8. The memory device according to claim 7, in, The pre-charge circuit includes a first transistor and a second transistor connected in series between the power supply voltage node and the second sensing node. The discharge circuit includes a third transistor, a fourth transistor, and a fifth transistor connected between the second sensing node and the ground node. The fourth transistor and the fifth transistor are connected in parallel, and The third transistor is connected in series with the fourth transistor and the fifth transistor.

9. The memory device according to claim 8, in, The first transistor and the second transistor are turned on during the first time period and turned off during the second time period. The third transistor and the fifth transistor are turned on during the second time period. The fourth transistor is turned off during the second time period, and The potential of the second sensing node is pre-charged to the first voltage during the first time period and discharged to the second voltage during the second time period.

10. The memory device according to claim 8, wherein, The fourth transistor is an N-MOS device, and the fifth transistor is a P-MOS device.

11. The memory device according to claim 7, wherein, The reference voltage is used to read whether the selected memory cell is an on or off cell.

12. A method of operating a memory device, the method comprising the steps of: The bit lines connected to the memory cells are precharged to the precharge voltage; The potential of the sensing node connected to the bit line is pre-charged to a first voltage; Discharge the potential of the sensing node from the first voltage to the second voltage; as well as After the potential of the sensing node is discharged to the second voltage and a predetermined period of time has elapsed, the data of the memory cell is stored in the latch circuit based on the comparison result between the potential of the sensing node and the reference voltage. Wherein, the first voltage is a default voltage used to precharge the sensing node to sense the threshold voltage of the memory cell. The discharge of the potential of the sensing node includes discharging the default voltage to the second voltage by turning on the transistor connected between the sensing node and the ground node.

13. The method according to claim 12, wherein, The transistor is a P-MOS device.

14. The method according to claim 12, wherein, The reference voltage is used to determine whether the memory cell is a conducting cell or a cut-off cell.

15. The method according to claim 12, wherein, The step of storing the memory cell data in the latch circuit includes the following steps: when the potential of the sensing node is higher than the reference voltage, the memory cell is read as a cutoff cell, and when the potential of the sensing node is lower than the reference voltage, the memory cell is read as a conduction cell.

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