Method and system for combined lossless and lossy encoding

Abstract

The decoder includes circuitry configured to receive a bitstream in which a current frame is identified, wherein the current frame includes a first region and a third region, detect in the bitstream an indication that the first region is encoded according to a lossless encoding protocol, and decode the current frame, wherein decoding the current frame further includes decoding the first region using a lossless decoding protocol corresponding to the lossless encoding protocol.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. non-provisional patent application filed April 13, 2021, entitled “METHODS AND SYSTEMS FOR COMBINED LOSSLESS AND LOSSY CODING”, serial number 17 / 229,210, the entire contents of which are incorporated herein by reference, and also claims priority to U.S. provisional patent application filed April 13, 2020, entitled “METHODS AND SYSTEMS FOR COMBINED LOSSLESS AND LOSSY CODING”, serial number 63 / 009,370, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention generally relates to the field of video compression. In particular, this invention relates to methods and systems for lossless and lossy coding for combining. Background Technology

[0004] A video codec can include electronic circuitry or software that compresses or decompresses digital video. It can convert uncompressed video into a compressed format and vice versa. In the context of video compression, a device that compresses video (and / or performs some of its functions) is generally called an encoder, and a device that decompresses video (and / or performs some of its functions) is called a decoder.

[0005] The format of compressed data can conform to standard video compression specifications. Compression may be lossy because compressed video lacks some information present in the original video. The result may include decompressed video having lower quality than the original uncompressed video because there is insufficient information to accurately reconstruct the original video.

[0006] There can be complex relationships between video quality, the amount of data used to represent the video (e.g., determined by bit rate), the complexity of encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, end-to-end latency (e.g., waiting time), and so on.

[0007] Motion compensation can include methods for predicting a video frame or a portion thereof by taking into account the motion of objects in the camera and / or video, given a reference frame (such as a previous and / or future frame). It can be used in the encoding and decoding of video data used for video compression, for example, in the encoding and decoding of the Advanced Video Coding (AVC) standard (also known as H.264) using the Moving Picture Experts Group (MPEG). Motion compensation can describe an image based on the transformation from a reference image to the current image. The reference image can be earlier in time when compared to the current image, and later in time when compared to the current image. Compression efficiency can be improved when images can be accurately synthesized from previously transmitted and / or stored images. Summary of the Invention

[0008] In one aspect, a decoder includes circuitry configured to receive an encoded video bitstream, identify a current frame in the bitstream, wherein the current frame includes a first region, a second region, and a third region, detect that the first region in the bitstream is encoded using block differential pulse code modulation, detect that the second region in the bitstream is encoded using transform skip residual coding, and detect that the third region in the bitstream is encoded using lossy coding, wherein the lossy coding includes at least one of inter-frame prediction and intra-frame prediction.

[0009] On the other hand, a method combining lossless and lossy coding includes: receiving an encoded video bitstream by a decoder; identifying a current frame in the bitstream by the decoder, wherein the current frame includes a first region, a second region, and a third region; detecting in the bitstream by the decoder that the first region is encoded using block differential pulse code modulation; detecting in the bitstream by the decoder that the second region is encoded using transform skip residual coding; and detecting in the bitstream by the decoder that the third region is encoded using lossy coding, wherein the lossy coding includes at least one of inter-frame prediction and intra-frame prediction.

[0010] In another aspect, a decoder includes circuitry configured to receive an encoded bitstream, identify a current frame in the bitstream, wherein the current frame includes a first sub-image and a second sub-image, detect an indication in the bitstream that the first sub-image is encoded according to a lossless encoding protocol, and decode the current frame, wherein decoding the current frame further includes decoding the first sub-image using a lossless decoding protocol corresponding to the lossless encoding protocol.

[0011] On the other hand, a method combining lossless and lossy encoding includes: receiving a bitstream at a decoder; identifying a current frame in the bitstream by the decoder, wherein the current frame includes a first sub-image and a second sub-image; detecting an indication in the bitstream that the first sub-image is encoded according to a lossless encoding protocol by the decoder; and decoding the current frame by the decoder, wherein decoding the current frame further includes decoding the first sub-image using a lossless decoding protocol corresponding to the lossless encoding protocol.

[0012] These and other aspects and features of the invention will become apparent to those skilled in the art when reading the following description of specific non-limiting embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0013] For the purpose of illustrating the invention, the accompanying drawings show aspects of one or more embodiments of the invention. However, it should be understood that the invention is not limited to the precise arrangements and means shown in the drawings, wherein:

[0014] Figure 1 This is a block diagram illustrating an exemplary embodiment of a frame having multiple sub-images;

[0015] Figure 2 This is an illustration of an exemplary embodiment of a frame having two sub-images;

[0016] Figure 3 This is a process flowchart illustrating an example process for decoding video according to some implementations of the current topic;

[0017] Figure 4 This is a system block diagram illustrating an example decoder capable of decoding bitstreams according to some implementations of the present topic;

[0018] Figure 5 This is a process flowchart illustrating an example process for encoding video according to some implementations of the current topic; and

[0019] Figure 6 It is a block diagram of a computational system that can be used to implement any one or more methods disclosed herein and any one or more parts thereof.

[0020] The accompanying drawings are not necessarily drawn to scale and may be shown using dashed lines, diagrams, and partial views. In some cases, details that are not essential for understanding the embodiments or that make other details difficult to perceive may have been omitted. Detailed Implementation

[0021] In traditional video coding systems, video sequences are divided into Groups of Pictures (GOPs). Each GOP is self-contained in a temporal and spatial predictive sense. Typically, the first picture in a group is used as a reference picture for subsequent pictures. The temporal and spatial relationships between pictures allow for very efficient compression using predictive coding.

[0022] Traditional encoding systems typically operate using lossy encoding, where some information from the encoded frame is omitted during the encoding process and not recovered during decoding. Such lossy processes may sacrifice a degree of detail and / or resolution in the decoded frames and / or video images to achieve a higher degree of efficiency, for example, but not limited to, by reducing the amount of data transmitted from the encoder to the decoder in the bitstream, the processing time used for encoding and / or decoding frames or groups of images, and / or memory resources.

[0023] Alternatives to the above process may include lossless coding, where frames are encoded and decoded with no or negligible information loss; this can result in greater resolution and / or other detail in the output frames and / or video pictures. However, while lossless coding and decoding may sometimes be more efficient for certain types of image processing, as further detailed below, it can also be very expensive in terms of memory resources and processing time. This is particularly evident in Ultra High Definition (UHD) video coding, where picture or image sizes can be as high as 8k × 4k (7680 × 4320); large picture sizes can pose significant challenges to chip and / or module design. One reason for this is that UHD requires a larger search range in motion estimation and necessitates on-chip or other processing memory to buffer reference blocks used for motion estimation and compensation. UHD processing can even present challenges for lossy coding and decoding due to the larger picture sizes involved.

[0024] The embodiments disclosed herein use a combination of lossless and lossy video compression coding to achieve more efficient signaling, decoding, and encoding. In these embodiments, a picture can first be divided into sub-pictures based on quality and computational requirements. The encoder can create as many sub-pictures as the CPU or other devices, circuits, or components performing the encoding and / or decoding of pictures and / or GOPs. Since each sub-picture can be encoded independently, this form of task partitioning allows for efficient encoding and / or decoding by effectively utilizing all available computational resources. Furthermore, lossless coding can provide better compression than lossy coding using transforms and quantization, for example, for certain sub-pictures of an entire frame; as a result, the combination of lossless and lossy coding can lead to performance superior to lossless coding alone.

[0025] Now for reference Figure 1This illustrates an exemplary embodiment of a current frame divided into multiple sub-images. A sub-image may contain any portion of the current frame smaller than the current frame; sub-images of the current frame may be combined to cover all parts of the current frame. Although... Figure 1 An exemplary current frame divided into two or four sub-images is shown, but those skilled in the art who have viewed the full contents of this disclosure will understand that any number of sub-images may be appropriately used for resolution, efficiency, or any other considerations.

[0026] Still referencing Figure 1 Sub-images can have any suitable shape, including but not limited to square and / or rectangular shapes, shapes defined by combinations of two or more blocks having square and / or rectangular shapes, etc. Each block can be identified and / or signaled using coordinates of one or more portions and / or features of the block, where the coordinates may indicate the number of pixels across the frame and / or image, such as measurements from one or more corners and / or sides of the frame and / or image. For example, but not limited to, the coordinates of vertices (such as two x-coordinates and two y-coordinates used to identify a rectangular block) can be used to identify a sub-image and / or portions thereof, alternatively or additionally using any suitable geometric description of points, lines, and / or shapes, including but not limited to geometric partitions using one or more line segments, such as those defined by linear equations or mathematical equivalents (such as line segment endpoints), using one or more curved edges (such as those defined using exponential or other curves), etc.

[0027] Continue to refer to Figure 1 Sub-images can be encoded separately from each other. For example, but not limited to, a first processor thread can be used to encode and / or decode a first region of multiple sub-images, and a second processor thread can be used to decode elements of a third region. As used herein, "processor thread" can include any processor core and / or other hardware element capable of executing multi-threaded parallel processes, such processor cores and / or other hardware elements will be apparent to those skilled in the art upon reading the full scope of this disclosure. In embodiments where each sub-image is encoded independently, this form of task partitioning allows for efficient encoding by effectively utilizing all available computational resources.

[0028] Still referencing Figure 1Lossless coding can be selectively applied to a subset of images where it is desirable to preserve the source video without any loss for one or more of the reasons mentioned above. As a non-limiting example, the subset of images used for lossless coding may be selected for coding efficiency reasons. In such cases, the lossless coding mode decision can be made after evaluating the rate distortion (RD) cost of encoding the CTU in both lossy and lossless modes. In some use cases, portions of video may be selected by the user to be encoded in a lossless mode for reasons determined by the application. A non-limiting example could include a portion of a frame where preserving the source quality is desired by the user. When such a user selection is made, the entire region can be marked for lossless coding without performing any RD analysis.

[0029] Alternatively or otherwise, and further reference Figure 1 Sub-images can be identified by encoders and / or other hardware and / or software components and / or processes as regions, areas and / or subdivisions of images in which significant motion is detected and / or present; such regions can be identified because sub-images can be considered important and encoded using lossless coding, while sub-images with little or no motion can be encoded using lossy coding. Figure 2 An example is shown where image 200 is divided into two sub-images: a first region 204 with motion and a third region 208 without motion. As mentioned above, in some cases, lossless coding can provide better compression compared to lossy coding using transform and quantization. In alternative or additional examples, image 200 may be divided into a first region 204 encoded using a first lossless protocol, a second region (not shown) encoded using a second lossless protocol, and a third region encoded using a lossy protocol.

[0030] Refer again Figure 1A picture can be divided into subpictures, slices, and tiles. A block (CTU) can be a coding unit that can be encoded in intra-frame or inter-frame coding modes. A subpicture can contain a single CTU and / or multiple CTUs. In an embodiment, each CTU in a subset of CTUs can be signaled to indicate whether lossless coding is used in the CTU; alternatively or additionally, a set of CTUs, such as, but not limited to, a set of consecutively located CTUs, can be signaled together. Lossless and / or lossy coding can be signaled in one or more headers provided to the bitstream. For example, and without limitation, CTUs can be encoded in lossless coding mode by signaling lossless and / or lossy coding modes in the CTU header. Alternatively or additionally, the selective use of lossless coding for a subset of blocks (CTUs) can be signaled at higher-level syntax units. For example, slice, slice, and / or subpicture headers can signal to indicate the use of lossless coding modes for all CTUs in the syntax unit. A mechanism can be used to explicitly present or include a sub-picture header by referencing an identifier such as another header (e.g., a picture header from a previous signaling notification).

[0031] As a non-limiting example, and further reference... Figure 1 The data and / or logic within the subpicture header, CTU header, and / or other headers may include (but are not limited to) a first bit indicating whether lossless mode signaling is enabled, or in other words, whether the encoder and / or decoder applies signaling to notify and / or receives signals indicating whether lossless and / or lossy modes are being used for the relevant CTU, subpicture, etc. The data and / or logic within the subpicture header, CTU header, and / or other headers may include (but are not limited to) a second bit indicating lossless and / or lossy modes, where the lossless mode is the mode used to encode and decode the relevant CTU, subpicture, etc., using the lossless encoding and decoding protocol as described above. The following are non-limiting and illustrative examples of the logic and data that may be used.

[0032] Sub_picture_header{ ... ...... ......

[0036] ...lossless_mode_signaling [1-bit]

[0037] if(lossless_mode_signaling){

[0038] lossless_mode [1 bit];

[0039] } ... ...... ......

[0043] }

[0044] Alternatively or additionally, the lossless_coding_contraint_flag or similar signaling in headers (such as PPS, SPS, block, subblock or other headers) can be used to notify lossy or lossless modes.

[0045] Still referencing Figure 1 The encoder and / or decoder configured to perform the processes described in this disclosure can be configured to signal and / or detect the lossless encoding protocol used, for example, by using identifiers and / or bits corresponding to the lossless encoding protocol. Alternatively or additionally, the encoder and / or decoder can be configured to operate specific lossless encoding and decoding protocols, such as conforming to a given standard, version, or other method employing a unified standard. Two or more standard protocols may exist, and a sufficient number of bits can be used in the bitstream to signal the selection of one of them to encode two or more potential options.

[0046] Continue to refer to Figure 1 Lossless coding protocols can include any protocol used for lossless coding of images, videos, frames, pictures, subpictures, etc. As a non-limiting example, the encoder and / or decoder can perform lossless coding to bypass the transform coding stage and directly encode the residual. This method, which may be referred to as "transform-skipped residual coding" in this invention, can be implemented by applying a transform from the discrete cosine transform (DCT) family to skip the transformation of the residual from the spatial domain to the frequency domain, as described in further detail below, such as in some forms of block-based hybrid video coding. Lossless encoding and decoding can be performed according to one or more alternative processes and / or protocols, including but not limited to the processes and / or protocols proposed in JVET-Q00069 core experiment CE3-1 (involving rules and TS residual coding (RRC, TSRC) for lossless encoding and modifications to RRC and TSRC for lossless and lossy operating modes), JVET-Q0080 core experiment CE3-2 (involving the implementation of block differential pulse code modulation (BDPCM) and advanced techniques for lossless encoding), and combinations of BDPCM with different RRC / TSRC techniques.

[0047] Further reference Figure 1The encoder described in this invention can be configured to encode one or more fields using TS residual coding, wherein the one or more fields may include (but are not limited to) any picture, subpicture, coding unit, coding tree unit, tree unit, block, strip, slice, and / or any combination thereof. The decoder described in this disclosure can be configured to decode one or more fields based on and / or using TS residual coding. In transform skip mode, the residual of the field can be encoded as a non-overlapping sub-block or other subdivision unit of a given size (such as, but not limited to, a size of four pixels by four pixels). The quantization index of each scan position in the field to be transformed can be encoded instead of the last valid scan position; the final sub-block and / or subdivision position can be inferred based on the level of previous subdivision. TS residual coding can perform diagonal scanning in a forward rather than backward manner. The forward scan order can be applied to sub-blocks within a scan transform block and positions within sub-blocks and / or subdivisions; in embodiments, there may be no signaling for the final (x, y) position. As a non-restrictive example, when all previous flags are equal to 0, the `coded_sub_block_flag` can be encoded for each sub-block except the final sub-block. The context modeling of `sig_coeff_flag` can use a simplified template. The context model of `sig_coeff_flag` can depend on the top and left adjacent values; the context model of `abs_level_gt1_flag` can also depend on the left and top `sig_coeff_flag` values.

[0048] Still referencing Figure 1Furthermore, as a non-restrictive example, during the first scan pass in the TS residual coding process, the validity flag (sig_coeff_flag), the sign flag (coeff_sign_flag), the absolute level flag (abs_level_gtx_flag[0]) greater than 1, and the parity flag (par_level_flag) can be encoded. For a given scan position, if sig_coeff_flag equals 1, then coeff_sign_flag can be encoded, followed by abs_level_gtx_flag[0] (which specifies whether the absolute level is greater than 1). If abs_level_gtx_flag[0] equals 1, then par_level_flag is encoded separately to specify the parity of the absolute level. During the second or subsequent scan passes, for each scan position where the absolute level is greater than 1, up to four abs_level_gtx_flag[i] (i=1...4) can be encoded to indicate whether the absolute level at the given position is greater than 3, 5, 7, or 9, respectively. During the third or final "remainder" scan pass, the remainder, which can be stored as an absolute level `abs_remainder`, can be encoded in bypass mode. The absolute level remainder can be binarized using a fixed `rice` parameter value of 1.

[0049] Further reference Figure 1 The context-encoded binary numbers (bins) in the first scan pass and the second or "greater than x" scan passes can be continued until the maximum number of context-encoded binary numbers in the exhausted field (e.g., but not limited to TU) is reached. In a non-restrictive instance, the maximum number of context-encoded binary numbers in the residual block may be limited to 1.75. block_width `block_height`, or equivalently, an average of 1.75 context-encoded binary numbers per sample position. The binary numbers in the last scan pass (e.g., the remaining scan passes as described above) can be bypassed and encoded. Variables such as, but not limited to, `RemCcbs` can initially be set to the maximum number of context-encoded binary numbers for a block or other field, and can be reduced by one each time the context-encoded binary numbers are encoded. In a non-limiting instance, when `RemCcbs` is greater than or equal to 4, syntax elements in the first encoding pass (which may include `sig_coeff_flag`, `coeff_sign_flag`, `abs_level_gt1_flag`, and `par_level_flag`) can be encoded using the context-encoded binary numbers. In some embodiments, if `RemCcbs` becomes less than 4 when encoding the first pass, remaining coefficients that were not yet encoded in the first pass can be encoded in the remaining scan passes and / or the third pass.

[0050] Still referencing Figure 1 After the first pass of encoding, if RemCcbs is greater than or equal to four, the syntax elements in the second pass of encoding can be encoded using the binary number of the context encoding, which may include abs_level_gt3_flag, abs_level_gt5_flag, abs_level_gt7_flag, and abs_level_gt9_flag. If RemCcbs becomes less than 4 during the second pass of encoding, the remaining coefficients not yet encoded in the second pass can be encoded in the remaining and / or third scan passes. In some embodiments, blocks encoded using TS residual encoding may not be encoded using BDPCM encoding. For blocks not encoded in BDPCM mode, a level mapping mechanism can be applied to transform skipping residual encoding until the maximum number of binary numbers of the context encoding has been reached. The level mapping can use the top and left adjacent coefficient levels to predict the current coefficient level in order to reduce signaling costs. For a given residual position, absCoeff can be represented as the absolute coefficient level before mapping, and absCoeffMod can be represented as the coefficient level after mapping. As a non-restrictive example, where X0 represents the absolute coefficient level of the left adjacent position and X1 represents the absolute coefficient level of the upper adjacent position, the level mapping can be performed as follows:

[0051]

[0052]

[0053]

[0054] The absCoeffMod value can then be encoded as described above. After all the binary numbers encoded for the context have been exhausted, level mapping can be deactivated for all remaining scan positions in the current block and / or field and / or subdivision. If coded_subblock_flag equals 1, which indicates that there is at least one non-zero quantization residual in the subblock, then the three scan passes described above can be performed on each subblock and / or other subdivision.

[0055] In some embodiments, and still referencing Figure 1 When transform skip mode is used for large blocks, the entire block can be used without setting any values ​​to zero. Additionally, transform shifts can be removed in transform skip mode. The statistical properties of the signal in TS residual coding can differ from those of the transform coefficients. The residual coding used for transform skip mode can specify the maximum luma and / or chroma block size; as a non-limiting example, the setting may permit transform skip mode for luma blocks up to MaxTsSize multiplied by MaxTsSize, where the value of MaxTsSize is signaled in the PPS and can have a globally maximum possible value, such as, but not limited to, 32. When the CU encodes in transform skip mode, its prediction residuals can be quantized and encoded using the transform skip residual coding process.

[0056] Continue to refer to Figure 1 The encoder described in this invention can be configured to encode one or more fields using BDPCM, wherein the one or more fields may include (but are not limited to) any picture, subpicture, coding unit, coding tree unit, tree unit, block, strip, slice and / or any combination thereof. The decoder described in this invention can be configured to decode one or more fields according to and / or using BDPCM. BDPCM can maintain complete reconstruction at the pixel level. As a non-limiting example, the prediction process for each pixel using BDPCM may include four main steps that can predict each pixel using an intra-block reference for each pixel and then reconstruct it for use as an intra-block reference for subsequent pixels in the remainder of the block: (1) intra-block pixel prediction, (2) residual calculation, (3) residual quantization, and (4) pixel reconstruction.

[0057] Still referencing Figure 1 Intra-block pixel prediction can use multiple reference pixels to predict each pixel; as a non-limiting example, the multiple reference pixels may include the pixel α to the left of the pixel p to be predicted, the pixel β above p, and the pixels γ above and to the left of p. The prediction of p can be expressed non-limitingly as follows:

[0058]

[0059] Still referencing Figure 1Once the predicted values ​​are calculated, their residuals can be computed. Since the residuals at this stage are likely lossless and inaccessible on the decoder side, they can be represented as... And it is calculated as the predicted p minus the original pixel value o:

[0060]

[0061] Further reference Figure 1 Pixel-level independence can be achieved by skipping the residual transform and integrating the spatial domain quantization. This can be performed by a linear quantizer Q, which computes the quantization residual value r as follows:

[0062]

[0063] To accommodate the correct rate-distortion ratio imposed by the quantizer parameters (QP), BDPCM can employ spatial domain normalization used in transmission skip mode methods, for example, but not limited to, as described above. The quantization residual value r can be sent by the encoder.

[0064] Still referencing Figure 1 Another state of BDPCM can include pixel reconstruction using p and r from previous steps, which can be performed, for example but not limited to, at the decoder or by the decoder, as follows:

[0065]

[0066] Once reconstructed, the current pixel can be used as an intra-block reference for other pixels within the same block.

[0067] When the original pixel value deviates significantly from its prediction, the prediction scheme in the BDPCM algorithm can be used even with relatively large residuals. In screen content, this can occur when the intra-block reference belongs to the background layer while the current pixel belongs to the foreground layer, and vice versa. In this case, which can be referred to as a "layer transition," the available information in the reference may be insufficient for accurate prediction. At the sequence level, a BDPCM enable flag can be signaled in the SPS; this flag can be signaled (but is not limited to) only when transform skip mode is enabled in the SPS (e.g., but not limited to, as described above). When BDPCM is enabled, a flag can be emitted at the CU level if the CU size is less than or equal to MaxTsSize multiplied by MaxTsSize in terms of luminance samples, and if the CU is intra-coded, where MaxTsSize is the maximum block size allowed for transform skip mode. This flag can indicate whether regular intra-coding or BDPCM is used. If BDPCM is used, a BDPCM prediction direction flag can be sent to indicate whether the prediction is horizontal or vertical. The block can then be predicted using a regular horizontal or vertical intra-prediction process with unfiltered reference samples.

[0068] Now for reference Figure 3 This illustrates an exemplary embodiment of a method 300 for combining lossless and lossy encoding. At step 305, the decoder receives a bitstream. At step 310, the decoder identifies the current frame in the bitstream. The current frame may include a first region, a second region, and a third region, any of which may include any region as described above; regions may be marked using frame header information and / or described using coordinates, geometric information, identifiers of blocks and / or CTUs contained in each region, or otherwise. In embodiments, the decoder may identify only two of the first, second, and third regions in the current frame, while the remaining regions may be identified as remaining slices, stripes, blocks, CTUs, etc., of the current frame. More than three regions may exist; method 300 may include any processing steps performed with respect to any additional regions as described in this disclosure.

[0069] At step 315, and continuing to refer to Figure 3 The decoder detects the first region in the bitstream as an indication encoded according to block differential pulse code modulation; this can be, but is not limited to, the above reference. Figures 1 to 2Perform as described. Detection may include detection of Block Differential Pulse Code Modulation (BPD) being enabled and / or prior to detection of BPD being enabled, such as as described above. In embodiments, the bitstream may include a sub-picture header corresponding to a first region. Detection may include detecting an indication in the sub-picture and / or region-specific headers that the headers encode at least a first region according to BPD. The sub-picture header may be explicitly included in the data corresponding to the current frame. For example, but not limited to, if BPDCM is enabled for a sequence, the sps_bdpcm_enabled_flag may be set to 1 in the SPS and / or other headers. The sps_bdpcm_enabled_flag being equal to 1 may specify that the intra_bdpcm_luma_flag and / or intra_bdpcm_chroma_flag may exist in coding units and / or other field-specific syntaxes for intra-coding units and / or other fields. A `sps_bdpcm_enabled_flag` equal to 0 can specify that `intra_bdpcm_luma_flag` and / or `intra_bdpcm_chroma_flag` do not exist in the coding unit and / or other field-specific syntax for intra coding units and / or other fields. When they do not exist, it can be inferred that the value of `sps_bdpcm_enabled_flag` is equal to 0. In an embodiment, a `gci_no_bdpcm_constraint_flag` equal to 1 can specify that the `sps_bdpcm_enabled_flag` (which can be defined by the OlsInScope parameter without restriction) should be equal to 0 for all images in a given set. A `gci_no_bdpcm_constraint_flag` equal to 0 does not impose such a constraint. As another non-restrictive example, `intra_bdpcm_luma_flag` equal to 1 can specify that BDPCM can be applied to the current luma coding block and / or other fields at position (x0, y0), i.e., skip the transform; the luma intra-frame prediction mode can be specified by `intra_bdpcm_luma_dir_flag`. For example and without restriction, `intra_bdpcm_luma_flag` equal to 0 can specify that BDPCM is not applied to the current luma coding block and / or other fields at position (x0, y0). When `intra_bdpcm_luma_flag` does not exist, it can be inferred that it is equal to 0. For x = x0..x0 + cbwidth - 1, y = y0..y0 + cbheight - 1, and cidx = 0, the variable `bdpcmFlag[x][y][cidx]` can be set to equal `intra_bdpcm_luma_flag`. `intra_bdpcm_luma_dir_flag` equal to 0 can specify that the BDPCM prediction direction is horizontal.An intra_bdpcm_luma_dir_flag value of 1 specifies that the BDPCM prediction direction is vertical. For x = x0..x0 + cbwidth - 1, y = y0..y0 + cbheight - 1, and cIdx = 0, the variable BdpcmDir[x][y][cIdx] can be set to equal intra_bdpcm_luma_dir_flag. Subpicks and / or regions can be included by referencing the identifier of the subpick header corresponding to the third subpick and / or other elements in the current frame.

[0070] At step 320, and continuing to refer to Figure 3 The decoder detects the second region in the bitstream as an indication encoded based on the transmission skip residual coding; this can be, but is not limited to, the above reference. Figures 1 to 2Perform as described. Detection may include and / or, for example, before detecting that transport skip residual coding is enabled, such as as described above. In an embodiment, the bitstream may include a sub-picture header corresponding to a first region. Detection may include detecting an indication that at least a first region in the sub-picture header is encoded according to a transport skip residual coding protocol; this may include a transform skip enabled flag. For example, and not limitingly, a sh_ts_residual_coding_disabled_flag equal to 1 may specify that the residual_coding syntax structure can be used to parse residual samples of transform skip blocks in the current stripe and / or other fields. A sh_ts_residual_coding_disabled_flag equal to 0 may specify that the residual_ts_coding syntax structure can be used to parse residual samples of transform skip blocks in the current stripe. When sh_ts_residual_coding_disabled_flag does not exist, it can be inferred that it is equal to 0. transform_skip_flag[x0][y0][cIdx] may specify whether a transform can be applied to the associated transform block. The array indices x0, y0 specify the position (x0, y0) of the top-left luminance sample of the considered transform block relative to the top-left luminance sample of the image. The array index cIdx specifies an indicator for the color components; for example, it can be equal to 0 for Y, 1 for Cb, and 2 for Cr. A transform_skip_flag[x0][y0][cIdx] equal to 1 specifies that the transform cannot be applied to the associated transform block. A transform_skip_flag[x0][y0][cIdx] equal to 0 specifies that the decision to apply the transform to the associated transform block depends on other syntax elements. The transform skip mode can be signaled implicitly, either alternatively or additionally. For example, when `transform_skip_flag[x0][y0][cIdx]` does not exist, it can be inferred that: if `bdpcmFlag[x0][y0][cIdx]` equals 1, then `transform_skip_flag[x0][y0][cIdx]` equals 1; otherwise, if `bdpcmFlag[x0][y0][cIdx]` equals 0, then `transform_skip_flag[x0][y0][cIdx]` equals 0. Subpicture and / or region-specific headers can be explicitly included in the data corresponding to the current frame. Subpictures and / or regions can be included by referencing the identifier of the subpicture header corresponding to a third subpicture and / or other elements of the current frame.

[0071] At step 325, and continuing to refer to Figure 3The decoder detects that the third region is encoded according to a lossy encoding protocol and decodes the third region according to a lossy decoding protocol corresponding to the lossless encoding protocol; this can be performed according to any lossy decoding process described herein, including processes involving DCT and other processes described below. The bitstream may include sub-pictures and / or region-specific headers corresponding to the third region, and detection may include an indication in the sub-picture header that the third region is encoded according to a lossy encoding protocol. The sub-pictures and / or region-specific headers may be explicitly included in the data corresponding to the current frame. For example, as described above, the sub-pictures and / or region-specific headers may be included by referring to an identifier of the sub-pictures and / or region-specific headers corresponding to the third sub-picture. In an embodiment, the decoder may be configured to decode the first region using a first processor thread as defined above, and to decode the third region element using a second processor thread.

[0072] Continue to refer to Figure 3 The decoder can decode the current frame. Decoding the current frame may include decoding a first region using a BDPCM decoding protocol corresponding to the BDPCM encoding protocol. Decoding the current frame may include decoding a second region using a transport skip residual decoding protocol corresponding to a transport skip residual encoding protocol. Decoding the current frame may include decoding a third region using a lossy decoding protocol corresponding to a lossy encoding protocol.

[0073] Still referencing Figure 3 The decoder may include an entropy decoder processor configured to receive a bitstream and decode it into quantization coefficients, an inverse quantization and inverse transform processor configured to process the quantization coefficients (including performing inverse discrete cosine), a deblocking filter, a frame buffer, and an intra-frame prediction processor. At least one of the first, second, and third regions may form part of a quadtree plus a binary decision tree. At least one of the first, second, and third regions includes a coding tree unit. In some embodiments, at least one of the first, second, and third regions may include a coding tree unit (CTU), a coding unit (CU), or a prediction unit (PU).

[0074] Figure 4 This is a system block diagram illustrating an example decoder 400 capable of decoding bitstream 428 using a combination of lossy and lossless encoding protocols. Decoder 400 may include an entropy decoder processor 404, an inverse quantization and inverse transform processor 408, a deblocking filter 412, a frame buffer 416, a motion compensation processor 420, and / or an intra-frame prediction processor 424.

[0075] During operation, and still referencing Figure 4The bitstream 428 can be received by the decoder 400 and input to the entropy decoder processor 404, which can decode a portion of the bitstream's entropy into quantization coefficients. The quantization coefficients can be provided to the inverse quantization and inverse transform processor 408, which can perform inverse quantization and inverse transform to create a residual signal. This residual signal can be added to the output of the motion compensation processor 420 or the intra-prediction processor 424, depending on the processing mode. The outputs of the motion compensation processor 420 and the intra-prediction processor 424 can include block predictions based on previously decoded blocks. The sum of the predictions and residuals can be processed by the deblocking filter 412 and stored in the frame buffer 416.

[0076] Continue to refer to Figure 4 Decoder 400 may be designed and / or configured to perform any method, method step, or sequence of method steps in any order and with any degree of repetition as described in any embodiment of the present invention. For example, decoder 400 may be configured to repeatedly execute a single step or sequence until a desired or commanded result is achieved; may iteratively and / or recursively execute repetitions of steps or sequences of steps, using the output of previous repetitions as inputs to subsequent repetitions, aggregating repetitive inputs and / or outputs to produce an aggregated result, reducing or subtracting one or more variables (such as global variables), and / or dividing a large processing task into a set of smaller processing tasks to be solved iteratively. Decoder 400 may execute any step or sequence of steps as described in this disclosure in parallel, such as using two or more parallel threads, processor cores, etc., to execute steps two or more times simultaneously and / or substantially simultaneously; and may perform task partitioning between parallel threads and / or processes according to any protocol suitable for partitioning tasks between iterations. Those skilled in the art will recognize upon reading the full contents of this disclosure a variety of ways in which iterative, recursive, and / or parallel processing can be used to subdivide, share, or otherwise process steps, sequences of steps, processing tasks, and / or data.

[0077] Figure 5 This is a system block diagram illustrating an exemplary embodiment of a video encoder 500 capable of constructing a list of motion vector candidates, including adding a single global motion vector candidate to the list. The example video encoder 500 may receive input video 504, which may be initially segmented and / or partitioned according to a processing scheme such as a tree-structured macroblock partitioning scheme (e.g., quadtree plus binary tree). Examples of a tree-structured macroblock partitioning scheme may include partitioning picture frames into large blocks called coding tree units (CTUs). In some implementations, each CTU may be further partitioned one or more times into several sub-blocks called coding units (CUs). The final result of this partitioning may include a set of sub-blocks that may be called prediction units (PUs). Transform units (TUs) may also be utilized.

[0078] Still referencing Figure 5 The instance video encoder 500 may include an intra-frame prediction processor 508, a motion estimation / compensation processor 512 (also known as an inter-frame prediction processor) capable of constructing a list of motion vector candidates (including adding individual global motion vector candidates to the list of motion vector candidates), a transform / quantization processor 516, an inverse quantization / inverse transform processor 520, a loop filter 524, a decoded image buffer 528, and / or an entropy coding processor 532. Bitstream parameters may be input to the entropy coding processor 532 to be included in the output bitstream 536.

[0079] During operation, and continue to refer to Figure 5 For each block of the input video 504 frame, it can be determined whether the block is processed via intra-frame prediction or using motion estimation / compensation. The block can be provided to either the intra-frame prediction processor 508 or the motion estimation / compensation processor 512. If the block is to be processed via intra-frame prediction, the intra-frame prediction processor 508 can perform processing to output a predictor. If the block is to be processed via motion estimation / compensation, then the motion estimation / compensation processor 512 can perform processing including: constructing a list of motion vector candidates, including adding a single global motion vector candidate to the list of motion vector candidates (if applicable).

[0080] Still referencing Figure 5 The residual can be formed by subtracting the predictor from the input video. The residual can be received by a transform / quantization processor 516, which can perform transform processing (e.g., Discrete Cosine Transform (DCT)) to produce coefficients that can be quantized. The quantized coefficients and any associated signaling information can be provided to an entropy coding processor 532 for entropy coding and included in the output bitstream 536. The entropy coding processor 532 can support the encoding of signaling information related to encoding the current block. Additionally, the quantization coefficients can be provided to an inverse quantization / inverse transform processor 520, which can reproduce pixels that can be combined with the predictor and processed by a loop filter 524. The output of the loop filter can be stored in a decoded image buffer 528 for use by a motion estimation / compensation processor 512, which is capable of constructing a list of motion vector candidates, including adding a single global motion vector candidate to the list.

[0081] Further reference Figure 5 Although some variations have been described in detail above, other modifications or additions are possible. For example, in some implementations, the current block may include any symmetrical block (8×8, 16×16, 32×32, 64×64, 128×128, etc.) and any asymmetrical block (8×4, 16×8, etc.).

[0082] In some implementations, and still referencing Figure 5 This allows for the implementation of a quadtree plus binary decision tree (QTBT). In QTBT, at the encoding tree unit level, the partitioning parameters of the QTBT can be dynamically derived to adapt to local characteristics without transmitting any overhead. Subsequently, at the encoding unit level, the joint classifier decision tree structure can eliminate unnecessary iterations and control the risk of erroneous predictions. In some implementations, the LTR frame block update mode can be used as an additional option available at each leaf node of the QTBT.

[0083] In some implementations, and still referencing Figure 5 Additional syntax elements can be signaled at different levels of the bitstream. For example, an enable flag can be used for the entire sequence by including an enable flag encoded in the Sequence Parameter Set (SPS). Furthermore, CTU flags can be encoded at the Code Tree Unit (CTU) level.

[0084] Continue to refer to Figure 5 Non-transitory computer program products (i.e., physically embodied computer program products) may store instructions that, when executed by one or more data processors of one or more computing systems, cause at least one data processor to perform the operations and / or steps described herein, including but not limited to any operation that the above-described 400 and / or encoder 500 may be configured to perform. Similarly, computer systems may also be described that include one or more data processors and memory coupled to the one or more data processors. The memory may temporarily or permanently store instructions that cause at least one processor to perform one or more operations described herein. Additionally, the methods may be implemented by one or more data processors within a single computing system or distributed among two or more computing systems. Such computing systems may be connected via one or more connections (including connections via networks (e.g., the Internet, wireless wide area networks, local area networks, wide area networks, wired networks, etc.), via direct connections between one or more of the multiple computing systems, and may exchange data and / or commands or other instructions, etc.

[0085] Continue to refer to Figure 5The encoder 500, decoder 400, and / or their circuitry may be designed and / or configured to perform any method, method step, or sequence of method steps in any order and with any degree of repetition as described in any embodiment of the invention. For example, the encoder 500, decoder 400, and / or their circuitry may be configured to repeatedly execute a single step or sequence until a desired or commanded result is achieved; to iteratively and / or recursively execute repetitions of steps or sequences of steps, using the output of previous repetitions as inputs for subsequent repetitions, aggregating repetitive inputs and / or outputs to produce an aggregated result, reducing or decrementing one or more variables (such as global variables), and / or dividing a large processing task into a set of smaller processing tasks that are iteratively addressed. The encoder 500, decoder 400, and / or their circuitry may execute any step or sequence of steps as described in the invention in parallel, for example, by using two or more parallel threads, processor cores, or the like to execute steps two or more times simultaneously and / or substantially simultaneously; and to perform task partitioning between parallel threads and / or processes according to any protocol suitable for partitioning tasks between iterations. Those skilled in the art will recognize, upon reading the full contents of this disclosure, that various methods can be used to subdivide, share, or otherwise process steps, sequences of steps, processing tasks, and / or data using iteration, recursion, and / or parallel processing.

[0086] The embodiments disclosed herein include a decoder comprising circuitry configured to receive an encoded video bitstream, identify a current frame in the bitstream, wherein the current frame includes a first region, a second region, and a third region, detect that the first region in the bitstream is encoded using block differential pulse code modulation, detect that the second region in the bitstream is encoded using transform skip residual coding, and detect that the third region in the bitstream is encoded using lossy coding, wherein the lossy coding includes at least one of inter-frame prediction and intra-frame prediction.

[0087] In some embodiments, the bitstream further includes a sub-picture header corresponding to the first region, and detecting that the first region is encoded using block differential pulse code modulation further includes detecting an indication in the sub-picture header that at least the first region is encoded using block differential pulse code modulation. In some embodiments, the sub-picture header is explicitly included in the data corresponding to the current frame. In some embodiments, a sub-picture is included by referring to an identifier in a sub-picture header corresponding to a third sub-picture.

[0088] In some embodiments, the bitstream further includes a sub-picture header corresponding to the second region, and the decoder is further configured to detect in the sub-picture header an indication that the second region using transform-skip residual coding is encoded using transform-skip residual coding. In some embodiments, the sub-picture header is explicitly included in the data corresponding to the current frame. In some embodiments, the decoder is further configured to decode the first region using a first processor thread and to decode the second region elements using a second processor thread. The decoder may also be configured to decode the current frame, wherein decoding the current frame further includes decoding the first region using a decoding protocol corresponding to block differential pulse code modulation. The decoder may also be configured to decode the current frame, wherein decoding the current frame further includes decoding the second region using a decoding protocol corresponding to transform-skip residual coding. The decoder may also be configured to decode the current frame, wherein decoding the current frame further includes decoding the third region using a decoding protocol corresponding to a lossy coding protocol.

[0089] In some embodiments, a method of combined lossless and lossy encoding includes: receiving an encoded video bitstream by a decoder; identifying a current frame in the bitstream by the decoder, wherein the current frame includes a first region, a second region, and a third region; detecting in the bitstream by the decoder that the first region is encoded using block differential pulse code modulation; detecting in the bitstream by the decoder that the second region is encoded using transform skip residual coding; and detecting in the bitstream by the decoder that the third region is encoded using lossy coding, wherein the lossy coding includes at least one of inter-frame prediction and intra-frame prediction.

[0090] In some embodiments, the bitstream further includes a sub-picture header corresponding to a first region, and detecting that the first region is encoded using block differential pulse code modulation further includes detecting an indication in the sub-picture header that at least the first region is encoded using block differential pulse code modulation. In some embodiments, the sub-picture header is explicitly included in the data corresponding to the current frame. Subpictures can be included by referring to an identifier in a sub-picture header corresponding to a third subpicture. The bitstream may include a sub-picture header corresponding to a second region, and the decoder may also be configured to detect in the sub-picture header an indication that a second region encoded using transform skip residual coding is encoded using transform skip residual coding. The sub-picture header may be explicitly included in the data corresponding to the current frame.

[0091] The method may include decoding a first region using a first processor thread and decoding elements of a third region using a second processor thread. The method may include decoding a current frame, wherein decoding the current frame further includes decoding the first region using a decoding protocol corresponding to block differential pulse code modulation. The method may include decoding the current frame, wherein decoding the current frame further includes decoding a second region using a decoding protocol corresponding to transform-skip residual coding. The method may include decoding the current frame, wherein decoding the current frame further includes decoding the third region using a decoding protocol corresponding to a lossy coding protocol.

[0092] In some embodiments, the decoder includes circuitry configured to receive an encoded bitstream, identify a current frame in the bitstream, wherein the current frame includes a first sub-image and a second sub-image, detect an indication in the bitstream that the first sub-image is encoded according to a lossless encoding protocol, and decode the current frame, wherein decoding the current frame further includes decoding the first sub-image using a lossless decoding protocol corresponding to the lossless encoding protocol.

[0093] In some embodiments, the bitstream may include a sub-image header corresponding to a first sub-image, and detection may include detecting in the sub-image header an indication that at least the first sub-image is encoded according to a lossless encoding protocol. The sub-image header may be explicitly included in the data corresponding to the current frame. Sub-images may be included by referring to an identifier in the sub-image header corresponding to a third sub-image. The decoder may also be configured to detect that a second sub-image is encoded according to a lossy encoding protocol, and to decode the second sub-image according to a lossy decoding protocol corresponding to the lossless encoding protocol. The bitstream may include a sub-image header corresponding to a second sub-image, and the decoder may also be configured to detect in the sub-image header an indication that the second sub-image is encoded according to a lossy encoding protocol. The sub-image header may be explicitly included in the data corresponding to the current frame. Sub-image headers may be included by referring to an identifier in the sub-image header corresponding to a third sub-image. The decoder may also be configured to decode the first sub-image using a first processor thread, and to decode the second sub-image element using a second processor thread. The decoder may include an entropy decoder processor configured to receive a bitstream and decode it into quantization coefficients, an inverse quantization and inverse transform processor configured to process the quantization coefficients (including performing inverse discrete cosine), a deblocking filter, a frame buffer, and an intra-frame prediction processor. At least one of the first and second sub-images may form part of a quadtree plus a binary decision tree. At least one of the first and second sub-images may include a coding tree unit. At least one of the first and second sub-images may include a coding unit. At least one of the first and second sub-images may include a prediction unit.

[0094] In some embodiments, a method of combined lossless and lossy encoding includes: receiving a bitstream at a decoder; identifying a current frame in the bitstream by the decoder, wherein the current frame includes a first sub-image and a second sub-image; detecting an indication in the bitstream that the first sub-image is encoded according to a lossless encoding protocol by the decoder; and decoding the current frame by the decoder, wherein decoding the current frame further includes decoding the first sub-image using a lossless decoding protocol corresponding to the lossless encoding protocol.

[0095] In some embodiments, the bitstream may further include a sub-image header corresponding to a first sub-image, and detection may include detecting in the sub-image header an indication that at least the first sub-image is encoded according to a lossless encoding protocol. The sub-image header may be explicitly included in the data corresponding to the current frame. Sub-images may be included by referencing an identifier in a sub-image header corresponding to a third sub-image. The method may include detecting that a second sub-image is encoded according to a lossy encoding protocol, and decoding the second sub-image according to a lossy decoding protocol corresponding to the lossless encoding protocol. In some embodiments, the bitstream may include a sub-image header corresponding to a second sub-image, and detection may include detecting in the sub-image header an indication that the second sub-image is encoded according to a lossy encoding protocol. The sub-image header may be explicitly included in the data corresponding to the current frame. Sub-image headers may be included by referencing an identifier in a sub-image header corresponding to a third sub-image. The decoder may also be configured to decode the first sub-image using a first processor thread and decode the second sub-image element using a second processor thread.

[0096] In some embodiments, the decoder may include an entropy decoder processor configured to receive a bitstream and decode it into quantization coefficients, an inverse quantization and inverse transform processor configured to process the quantization coefficients (including performing inverse discrete cosine), a deblocking filter, a frame buffer, and an intra-frame prediction processor. At least one of the first and second sub-images may form part of a quadtree plus a binary decision tree. At least one of the first and second sub-images may include a coding tree unit. At least one of the first and second sub-images may include a coding unit. At least one of the first and second sub-images may include a prediction unit.

[0097] It should be noted that any one or more aspects and embodiments described herein can be readily implemented using one or more machines programmed according to the teachings of this specification (e.g., one or more computing devices used as user computing devices for electronic documents, one or more server devices such as document servers, etc.), as will be apparent to those skilled in the art of computers. As will be apparent to those skilled in the art of software, a skilled programmer can readily prepare appropriate software code based on the teachings of this disclosure. The aspects and implementations employing software and / or software modules discussed above may also include suitable hardware for assisting in the implementation of machine-executable instructions for the software and / or software modules.

[0098] Such software can be a computer program product employing a machine-readable storage medium. A machine-readable storage medium can be any medium capable of storing and / or encoding a sequence of instructions executable by a machine (e.g., a computing device) and causing the machine to perform any of the methods and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CDs, CD-Rs, DVDs, DVD-Rs, etc.), magneto-optical disks, read-only memory "ROM" devices, random access memory "RAM" devices, magnetic cards, optical cards, solid-state storage devices, EPROMs, EEPROMs, and any combinations thereof. As used herein, machine-readable media are intended to include single media as well as collections of physically separate media, such as, for example, an optical disk combined with computer memory or a collection of one or more hard disk drives. As used herein, machine-readable storage media do not include transient signal transmissions.

[0099] Such software may also include information (e.g., data) carried as data signals on a data carrier (such as a carrier wave). For example, machine-executable information may include data-bearing signals embodied in a data carrier, wherein the signals encode a sequence of instructions or portions thereof for execution by a machine (e.g., a computing device), and any related information (e.g., data structures and data) that causes the machine to perform any of the methods and / or embodiments described herein.

[0100] Examples of computing devices include, but are not limited to, e-book readers, computer workstations, terminal computers, server computers, handheld devices (e.g., tablets, smartphones, etc.), network devices, network routers, network switches, bridges, any machine capable of executing a sequence of instructions specifying an action to be taken by the machine, and any combination thereof. In one example, a computing device may include and / or be included in a self-service terminal.

[0101] Figure 6A graphical representation of an embodiment of a computing device, illustrating an exemplary form of computer system 600, is shown, wherein a set of instructions can be executed to cause a control system to perform any one or more aspects and / or methods of this disclosure. It is also contemplated that a set of instructions specifically configured to cause one or more devices to perform any one or more aspects and / or methods of this disclosure can be implemented using multiple computing devices. Computer system 600 includes a processor 604 and a memory 608 communicating with each other and with other components via a bus 612. Bus 612 may include any of several types of bus architectures, including but not limited to memory buses, memory controllers, peripheral buses, local buses, and any combinations thereof using any of various bus architectures.

[0102] Processor 604 may include any suitable processor, such as, but not limited to, a processor incorporated with logic circuitry for performing arithmetic and logical operations, such as an arithmetic and logic unit (ALU), which may be regulated by a state machine and guided by operational inputs from memory and / or sensors; as a non-limiting example, processor 604 may be organized according to von Neumann and / or Harvard architectures. Processor 604 may include, incorporate and / or incorporate, but is not limited to, microcontrollers, microprocessors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), graphics processing units (GPUs), general-purpose GPUs, tensor processing units (TPUs), analog or mixed-signal processors, trusted platform modules (TPMs), floating-point units (FPUs), and / or system-on-a-chip (SoCs).

[0103] Memory 608 may include various components (e.g., machine-readable media), including but not limited to random access memory components, read-only components, and any combination thereof. In one example, a basic input / output system 616 (BIOS) including basic routines such as those that facilitate the transfer of information between elements within computer system 600 during startup may be stored in memory 608. Memory 608 may also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 620 embodying any one or more aspects and / or methods of this disclosure. In another example, memory 608 may also include any number of program modules, including but not limited to an operating system, one or more application programs, other program modules, program data, and any combination thereof.

[0104] Computer system 600 may also include storage device 624. Examples of storage devices (e.g., storage device 624) include, but are not limited to, hard disk drives, disk drives, optical disc drives combined with optical media, solid-state storage devices, and any combination thereof. Storage device 624 may be connected to bus 612 via a suitable interface (not shown). Example interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FireWire), and any combination thereof. In one example, storage device 624 (or one or more components thereof) may be removably mated to computer system 600 (e.g., via an external port connector (not shown)). In particular, storage device 624 and associated machine-readable medium 628 may provide non-volatile and / or volatile storage of machine-readable instructions, data structures, program modules, and / or other data for computer system 600. In one example, software 620 may reside wholly or partially within machine-readable medium 628. In another example, software 620 may reside wholly or partially within processor 604.

[0105] Computer system 600 may also include input device 632. In one example, a user of computer system 600 may input commands and / or other information into computer system 600 via input device 632. Examples of input device 632 include, but are not limited to, alphanumeric input devices (e.g., keyboards), pointing devices, joysticks, game controllers, audio input devices (e.g., microphones, voice response systems, etc.), cursor control devices (e.g., mice), touchpads, optical scanners, video capture devices (e.g., still cameras, video cameras), touchscreens, and any combination thereof. Input device 632 may be connected to bus 612 via any of a variety of interfaces (not shown), including but not limited to serial interfaces, parallel interfaces, game ports, USB interfaces, firewire interfaces, direct interfaces to bus 612, and any combination thereof. Input device 632 may include a touchscreen interface, which may be part of or separate from display 636, as discussed further below. Input device 632 may be used as a user selection device for selecting one or more graphical representations in the graphical interface described above.

[0106] Users can also input commands and / or other information to computer system 600 via storage device 624 (e.g., removable disk drive, flash drive, etc.) and / or network interface device 640. Network interface devices (such as network interface device 640) can be used to connect computer system 600 to one or more of various networks (such as network 644) and one or more remote devices 648 connected thereto. Examples of network interface devices include, but are not limited to, network interface cards (e.g., mobile network interface cards, LAN cards), modems, and any combination thereof. Examples of networks include, but are not limited to, wide area networks (e.g., the Internet, corporate networks), local area networks (e.g., networks associated with offices, buildings, campuses, or other relatively small geographical areas), telephone networks, data networks associated with telephone / voice providers (e.g., mobile communication provider data and / or voice networks), direct connections between two computing devices, and any combination thereof. Networks such as network 644 can employ wired and / or wireless communication modes. Typically, any network topology can be used. Information (e.g., data, software 620, etc.) can be transmitted to and / or from computer system 600 via network interface device 640.

[0107] Computer system 600 may also include a video display adapter 652 for transmitting displayable images to a display device, such as monitor 636. Examples of display devices include (but are not limited to) liquid crystal displays (LCDs), cathode ray tube (CRTs), plasma displays, light-emitting diode (LED) displays, and any combination thereof. Display adapter 652 and monitor 636 may be used in conjunction with processor 604 to provide graphical representations of various aspects of this disclosure. In addition to display devices, computer system 600 may include one or more other peripheral output devices, including but not limited to audio speakers, printers, and any combination thereof. Such peripheral output devices may be connected to bus 612 via peripheral interface 656. Examples of peripheral interfaces include, but are not limited to, serial ports, USB connections, FireWire connections, parallel connections, and any combination thereof.

[0108] The foregoing is a detailed description of illustrative embodiments of the present invention. Various modifications and additions can be made without departing from the spirit and scope of the invention. Features of each of the various embodiments described above can be suitably combined with features of other described embodiments to provide multiple feature combinations in associated new embodiments. Furthermore, although several individual embodiments have been described above, what is described herein is merely an illustration of the application of the principles of the invention. Additionally, although specific methods herein may be shown and / or described as being performed in a particular order, the order is highly variable within the scope of ordinary art to implement the methods, systems, and software according to this disclosure. Therefore, this specification is intended to be illustrative only and not to otherwise limit the scope of the invention.

[0109] Exemplary embodiments have been disclosed above, and exemplary embodiments are illustrated in the accompanying drawings. Those skilled in the art will understand that various changes, omissions, and additions can be made to the specific disclosure herein without departing from the spirit and scope of the invention.

Claims

1. A decoder, the decoder comprising circuitry configured to: Receive encoded video bitstream; The current frame is identified in the bitstream, wherein the current frame includes a first region, a second region, and a third region, wherein the first region is a first independently encoded sub-image, the second region is a second independently encoded sub-image, and the third region is the remaining part of the image; The detection of the first region in the bitstream is performed using block differential pulse code modulation; The detection of the second region in the bitstream is performed using transform skip residual coding, but not block differential pulse code modulation; and The detection of the third region in the bitstream is performed using lossy coding, wherein the lossy coding includes at least one of inter-frame prediction and intra-frame prediction, discrete cosine transform of residual pixel values, and quantization of transform coefficients.

2. The decoder according to claim 1, wherein: The bitstream also includes a sub-image header corresponding to the first region; and Detecting that the first region is encoded using block differential pulse code modulation further includes: detecting in the sub-image header an indication that at least the first region is encoded using block differential pulse code modulation.

3. The decoder according to claim 2, wherein, The sub-image header is explicitly included in the data corresponding to the current frame.

4. The decoder according to claim 2, wherein, The sub-image is included by referring to the identifier in the sub-image header corresponding to the third sub-image.

5. The decoder according to claim 1, wherein: The bitstream also includes a sub-image header corresponding to the second region; and The decoder is also configured to detect in the sub-image header an indication that a second region using transform skip residual coding is encoded using transform skip residual coding.

6. The decoder according to claim 5, wherein, The sub-image header is explicitly included in the data corresponding to the current frame.

7. The decoder of claim 1, wherein the decoder is further configured to: Decode the first region using the first processor thread; and The second processor thread is used to decode the elements of the second region.

8. The decoder of claim 1 is further configured to decode the current frame, wherein, Decoding the current frame further includes: decoding the first region using a decoding protocol corresponding to block differential pulse code modulation.

9. The decoder of claim 1, further configured to decode the current frame, wherein decoding the current frame further includes decoding the second region using a decoding protocol corresponding to using transform skip residual coding.

10. The decoder of claim 1 is further configured to decode the current frame, wherein decoding the current frame further includes decoding the third region using a decoding protocol corresponding to a lossy encoding protocol.

11. A method for combining lossless and lossy decoding, the method comprising: The decoder receives the encoded video bitstream; The decoder identifies the current frame in the bitstream, wherein the current frame includes a first region, a second region, and a third region, wherein the first region is a first independently encoded sub-image, the second region is a second independently encoded sub-image, and the third region is the remaining part of the image; The decoder detects in the bitstream that the first region is encoded using block differential pulse code modulation; The decoder detects in the bitstream that the second region is encoded using transform skip residual coding but not block differential pulse code modulation; as well as The third region is detected by the decoder in the bitstream as being encoded using lossy coding, wherein the lossy coding includes at least one of inter-frame prediction and intra-frame prediction, discrete cosine transform of residual pixel values, and quantization of transform coefficients.

12. The method according to claim 11, wherein: The bitstream also includes a sub-image header corresponding to the first region; and Detecting that the first region is encoded using block differential pulse code modulation further includes: detecting in the sub-image header an indication that at least the first region is encoded using block differential pulse code modulation.

13. The method according to claim 12, wherein, The sub-image header is explicitly included in the data corresponding to the current frame.

14. The method according to claim 12, wherein, The sub-image is included by referring to the identifier in the sub-image header corresponding to the third sub-image.

15. The method according to claim 11, wherein: The bitstream also includes a sub-image header corresponding to the second region; and The decoder is also configured to detect in the sub-image header an indication that a second region using transform skip residual coding is encoded using transform skip residual coding.

16. The method according to claim 15, wherein, The sub-image header is explicitly included in the data corresponding to the current frame.

17. The method of claim 11, further comprising: The first region is decoded using the first processor thread; as well as The third region element is decoded using a second processor thread.

18. The method of claim 11, further comprising: Decoding the current frame further includes: decoding the first region using a decoding protocol corresponding to block differential pulse code modulation.

19. The method of claim 11, further comprising decoding the current frame, wherein decoding the current frame further comprises decoding the second region using a decoding protocol corresponding to the use of transform skip residual coding.

20. The method of claim 11, further comprising: Decoding the current frame further includes decoding the third region using a decoding protocol corresponding to a lossy encoding protocol.

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