Pixel circuit, driving method thereof, and display device

Abstract

A pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a storage sub-circuit, a light emitting control sub-circuit, a first initialization sub-circuit and a second initialization sub-circuit. The data writing sub-circuit is configured to transmit a data signal provided by a data line to a third node under the control of a scan line. The threshold compensation sub-circuit is configured to turn on the first node and the second node under the control of the scan line, so as to write a threshold voltage of the driving sub-circuit to the storage sub-circuit. The light emitting control sub-circuit is configured to turn on the first power supply line and the second node under the control of a light emitting control line, and turn on the third node and the fourth node. The first initialization sub-circuit is configured to turn on the first power supply line and the first node under the control of a reset line. The second initialization sub-circuit is configured to turn on a reference voltage line and the fourth node under the control of the reset line, and turn on the reference voltage line and the fourth node under the control of the scan line.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a pixel circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess advantages such as ultra-thinness, wide viewing angle, active emission, high brightness, continuously adjustable emission color, low cost, fast response speed, low power consumption, wide operating temperature range, and flexible display capabilities. They have gradually become a promising next-generation display technology and are receiving increasing attention. Based on different driving methods, OLEDs can be divided into two types: passive matrix (PM) and active matrix (AM). AMOLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0005] On one hand, this disclosure provides a pixel circuit for driving a light-emitting element to emit light, comprising: a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a storage sub-circuit, a light emission control sub-circuit, a first initialization sub-circuit, and a second initialization sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node, and is configured to provide a driving current to the third node under the control of the first node. The data writing sub-circuit is coupled to a data line, a scan line, and the third node, and is configured to transmit a data signal provided by the data line to the third node under the control of the scan line. The threshold compensation sub-circuit is coupled to the scan line, the first node, and the second node, and is configured to turn on the first node and the second node under the control of the scan line to write the threshold voltage of the driving sub-circuit into the storage sub-circuit. The storage sub-circuit is coupled to the first node and a fourth node. The light emission control sub-circuit is coupled to a light emission control line, a first power line, a second node, a third node, and a fourth node, and is configured to turn on the first power line and the second node, and turn on the third node and the fourth node, under the control of the light emission control line. The first initialization sub-circuit, coupled to a reset line, a first power line, and a first node, is configured to turn on the first power line and the first node under the control of the reset line. The second initialization sub-circuit, coupled to a scan line, a reset line, a reference voltage line, and a fourth node, is configured to turn on the reference voltage line and the fourth node under the control of the reset line, and also under the control of the scan line. The first electrode of the light-emitting element is coupled to the fourth node, and the second electrode of the light-emitting element is coupled to the second power line.

[0006] In some exemplary embodiments, the reset line of the pixel circuit located in the nth row is coupled to the scan line that drives the pixel circuit in the (n-1)th row, where n is a positive integer.

[0007] In some exemplary embodiments, the pixel circuit further includes a voltage regulator circuit coupled to the scan line and the fourth node.

[0008] In some exemplary embodiments, the voltage regulator sub-circuit includes: a voltage regulator capacitor; a first terminal of the voltage regulator capacitor is coupled to a fourth node, and a second terminal of the voltage regulator capacitor is coupled to a scan line.

[0009] In some exemplary embodiments, the driving sub-circuit includes: a driving transistor; the control electrode of the driving transistor is coupled to a first node, the first electrode of the driving transistor is coupled to a second node, and the second electrode of the driving transistor is coupled to a third node.

[0010] In some exemplary embodiments, the first initialization sub-circuit includes: a first initialization transistor; the control electrode of the first initialization transistor is coupled to a reset line, the first electrode of the first initialization transistor is coupled to a first power supply line, and the second electrode of the first initialization transistor is coupled to a first node.

[0011] In some exemplary embodiments, the second initialization sub-circuit includes a second initialization transistor and a third initialization transistor. The control electrode of the second initialization transistor is coupled to a reset line, the first electrode of the second initialization transistor is coupled to a reference voltage line, and the second electrode of the second initialization transistor is coupled to a fourth node. The control electrode of the third initialization transistor is coupled to a scan line, the first electrode of the third initialization transistor is coupled to a reference voltage line, and the second electrode of the third initialization transistor is coupled to a fourth node.

[0012] In some exemplary embodiments, the threshold compensation sub-circuit includes: a threshold compensation transistor; the control electrode of the threshold compensation transistor is coupled to a scan line, the first electrode of the threshold compensation transistor is coupled to a first node, and the second electrode of the threshold compensation transistor is coupled to a second node.

[0013] In some exemplary embodiments, the light-emitting control sub-circuit includes: a first light-emitting control transistor and a second light-emitting control transistor. The control electrode of the first light-emitting control transistor is coupled to a light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to a first power supply line, and the second electrode of the first light-emitting control transistor is coupled to a second node. The control electrode of the second light-emitting control transistor is coupled to a light-emitting control line, the first electrode of the second light-emitting control transistor is coupled to a third node, and the second electrode of the second light-emitting control transistor is coupled to a fourth node.

[0014] In some exemplary embodiments, the data writing sub-circuit includes: a data writing transistor; the control electrode of the data writing transistor is coupled to a scan line, the first electrode of the data writing transistor is coupled to a data line, and the second electrode of the data writing transistor is coupled to a third node.

[0015] In some exemplary embodiments, the storage sub-circuit includes: a storage capacitor; a first end of the storage capacitor is coupled to a first node, and a second end of the storage capacitor is coupled to a fourth node.

[0016] In some exemplary embodiments, the driving sub-circuit includes: a driving transistor; the first initialization sub-circuit includes: a first initialization transistor; the second initialization sub-circuit includes: a second initialization transistor and a third initialization transistor; the threshold compensation sub-circuit includes: a threshold compensation transistor; the light emission control sub-circuit includes: a first light emission control transistor and a second light emission control transistor; the data writing sub-circuit includes: a data writing transistor; and the storage sub-circuit includes: a storage capacitor. The control electrode of the driving transistor is coupled to a first node, the first electrode of the driving transistor is coupled to a second node, and the second electrode of the driving transistor is coupled to a third node. The control electrode of the first initialization transistor is coupled to a reset line, the first electrode of the first initialization transistor is coupled to a first power supply line, and the second electrode of the first initialization transistor is coupled to a first node. The control electrode of the second initialization transistor is coupled to a reset line, the first electrode of the second initialization transistor is coupled to a reference voltage line, and the second electrode of the second initialization transistor is coupled to a fourth node. The control electrode of the third initialization transistor is coupled to a scan line, the first electrode of the third initialization transistor is coupled to a reference voltage line, and the second electrode of the third initialization transistor is coupled to a fourth node. The control electrode of the threshold compensation transistor is coupled to the scan line, the first electrode of the threshold compensation transistor is coupled to the first node, and the second electrode of the threshold compensation transistor is coupled to the second node. The control electrode of the first light-emitting control transistor is coupled to the light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to the first power line, and the second electrode of the first light-emitting control transistor is coupled to the second node. The control electrode of the second light-emitting control transistor is coupled to the light-emitting control line, the first electrode of the second light-emitting control transistor is coupled to the third node, and the second electrode of the second light-emitting control transistor is coupled to the fourth node. The control electrode of the data writing transistor is coupled to the scan line, the first electrode of the data writing transistor is coupled to the data line, and the second electrode of the data writing transistor is coupled to the third node. The first terminal of the storage capacitor is coupled to the first node, and the second terminal of the storage capacitor is coupled to the fourth node.

[0017] In some exemplary embodiments, the driving transistor, the first initialization transistor, the second initialization transistor, the third initialization transistor, the threshold compensation transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the data writing transistor are all N-type transistors.

[0018] In some exemplary embodiments, the first initialization transistor and the threshold compensation transistor are dual-gate transistors.

[0019] On the other hand, embodiments of this disclosure provide a driving method for a pixel circuit, applied to the pixel circuit described above, comprising: in an initialization phase, under the control of a reset line, a first initialization sub-circuit turns on a first power supply line and a first node, and a second initialization sub-circuit turns on a reference voltage line and a fourth node; in a writing phase, under the control of a scan line, a data writing sub-circuit transmits the data signal provided by the data line to a third node, a threshold compensation sub-circuit turns on the first node and a second node to write the threshold voltage of the driving sub-circuit into the storage sub-circuit, and the second initialization sub-circuit turns on the reference voltage line and the fourth node; in an emission phase, under the control of an emission control line, an emission control sub-circuit turns on the first power supply line and the second node, and turns on the third node and the fourth node to transmit the driving current output by the driving sub-circuit to the emission element.

[0020] On the other hand, embodiments of this disclosure provide a display device including the pixel circuit described above.

[0021] In some exemplary embodiments, the display device further includes a gate driving circuit. The gate driving circuit includes a plurality of cascaded first shift register units and a plurality of cascaded second shift register units. The output of the nth-stage first shift register unit is coupled to a scan line driving the nth row of pixel circuits; the output of the (n-1)th-stage first shift register unit is coupled to a reset line driving the nth row of pixel circuits; and the output of the nth-stage second shift register unit is coupled to a light-emitting control line driving the nth row of pixel circuits; where n is a positive integer.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0024] Figure 1 This is a schematic diagram of the pixel circuit structure of at least one embodiment of the present disclosure;

[0025] Figure 2 This is another schematic diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0026] Figure 3 This is an equivalent circuit diagram of the driving sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure;

[0027] Figure 4This is an equivalent circuit diagram of the first initialization sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure;

[0028] Figure 5 This is an equivalent circuit diagram of the second initialization sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure;

[0029] Figure 6 This is an equivalent circuit diagram of the threshold compensation sub-circuit of the pixel circuit in at least one embodiment of the present disclosure;

[0030] Figure 7 This is an equivalent circuit diagram of the light emission control sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure;

[0031] Figure 8 An equivalent circuit diagram of the data writing sub-circuit of the pixel circuit for at least one embodiment of this disclosure;

[0032] Figure 9 This is an equivalent circuit diagram of the storage sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure;

[0033] Figure 10 This is an equivalent circuit diagram of the voltage regulator sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure;

[0034] Figure 11 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0035] Figure 12 for Figure 11 The provided timing diagram for the pixel circuit;

[0036] Figure 13 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0037] Figure 14 This is a flowchart of a pixel circuit driving method according to at least one embodiment of the present disclosure;

[0038] Figure 15 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure;

[0039] Figure 16 This is another schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0040] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0041] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0042] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements, not to limit the quantity. The term “multiple” in this disclosure refers to two or more quantities.

[0043] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0044] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0045] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0046] In this disclosure, to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other as the second electrode. The first electrode can be either the source electrode or the drain electrode, and the second electrode can be either the drain electrode or the source electrode. Furthermore, the gate electrode of the transistor is referred to as the control electrode. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0047] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0048] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0049] OLED light-emitting elements emit light using a current-driven method, thus requiring high current stability from both the driving transistor (DTFT, DrivingTFT) and the OLED light-emitting element. However, due to the limitations of the manufacturing process, the current stability of the driving transistor output is poor, and the threshold voltage Vth of the driving transistor can shift under the influence of factors such as temperature, thereby affecting the display effect and lifespan of the display device.

[0050] This disclosure provides a pixel circuit and its driving method, as well as a display device, which compensates for the threshold voltage of the driving sub-circuit, avoids the influence of the threshold voltage on the driving current of the light-emitting element, and thus improves the display effect.

[0051] Figure 1 This is a schematic diagram of the pixel circuit structure according to at least one embodiment of the present disclosure. Figure 1As shown, the pixel circuit provided in this exemplary embodiment is used to drive a light-emitting element to emit light. The pixel circuit of this embodiment includes: a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a storage sub-circuit, a light emission control sub-circuit, a first initialization sub-circuit, and a second initialization sub-circuit. The driving sub-circuit is coupled to a first node N1, a second node N2, and a third node N3, and is configured to provide a driving current to the third node N3 under the control of the first node N1. The data writing sub-circuit is coupled to a data line DL, a scan line GL, and the third node N3, and is configured to transmit the data signal provided by the data line DL to the third node N3 under the control of the scan line GL. The threshold compensation sub-circuit is coupled to the scan line GL, the first node N1, and the second node N2, and is configured to turn on the first node N1 and the second node N2 under the control of the scan line GL to write the threshold voltage of the driving sub-circuit into the storage sub-circuit. The storage sub-circuit is coupled to the first node N1 and a fourth node N4. A light-emitting control subcircuit, coupled to the light-emitting control line EML, the first power supply line PL1, the second node N2, the third node N3, and the fourth node N4, is configured to turn on the first power supply line PL1 and the second node N2, and to turn on the third node N3 and the fourth node N4, under the control of the light-emitting control line EML. A first initialization subcircuit, coupled to the reset line RST, the first power supply line PL1, and the first node N1, is configured to turn on the first power supply line PL1 and the first node N1, under the control of the reset line RST. A second initialization subcircuit, coupled to the scan line GL, the reset line RST, the reference voltage line REF, and the fourth node N4, is configured to turn on the reference voltage line REF and the fourth node N4, under the control of the reset line RST, and also under the control of the scan line GL. The first electrode of the light-emitting element is coupled to the fourth node N4, and the second electrode of the light-emitting element is coupled to the second power supply line PL2.

[0052] In some exemplary embodiments, the light-emitting element can be an organic light-emitting diode (OLED). The first electrode of the light-emitting element can be an anode, and the second electrode can be a cathode. However, this embodiment is not limited to this.

[0053] In some exemplary embodiments, the first power line PL1 can continuously provide a high-level signal, for example, the first power line PL1 provides a first power signal ELVDD. The second power line PL2 can continuously provide a low-level signal, for example, the second power line PL2 provides a second power signal ELVSS.

[0054] The pixel circuit provided in this embodiment can achieve real-time internal compensation of the threshold voltage of the driving sub-circuit, thereby avoiding display defects caused by threshold voltage drift of the driving sub-circuit.

[0055] In some exemplary embodiments, the reset line coupled to the pixel circuit in the nth row is coupled to the scan line driving the pixel circuit in the (n-1)th row, where n is a positive integer. In this exemplary embodiment, the scan line driving the pixel circuit in the (n-1)th row can be multiplexed as the reset line driving the pixel circuit in the nth row, providing a reset signal to the pixel circuit in the nth row. In this way, the gate driving circuit only needs to provide two different gate driving signals (i.e., scan signal and light emission control signal) to the pixel circuit, which simplifies the structure of the gate driving circuit, improves signal stability, and facilitates the realization of a narrow bezel in the display device.

[0056] Figure 2 This is another schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 2 As shown, the pixel circuit provided in this exemplary embodiment further includes a voltage regulator circuit. The voltage regulator circuit is coupled to the scan line GL and the fourth node N4. The voltage regulator circuit is configured to maintain the voltage of the fourth node N4 to prevent the leakage current of the transistor from affecting the compensation effect of the threshold voltage.

[0057] Figure 3 This is an equivalent circuit diagram of the driving sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 3 As shown, the driving sub-circuit in the pixel circuit includes a driving transistor M8. The control electrode of the driving transistor M8 is coupled to the first node N1, the first electrode of the driving transistor M8 is coupled to the second node N2, and the second electrode of the driving transistor M8 is coupled to the third node N3. The driving transistor M8 is configured to provide driving current to the third node N3 under the control of the first node N1.

[0058] Figure 3 An exemplary structure of the driver sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit is not limited to this, as long as its function can be achieved.

[0059] Figure 4 This is an equivalent circuit diagram of a first initialization sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 4 As shown, the first initialization sub-circuit in the pixel circuit includes a first initialization transistor M1. The control electrode of the first initialization transistor M1 is coupled to the reset line RST, the first electrode of the first initialization transistor M1 is coupled to the first power supply line PL1, and the second electrode of the first initialization transistor M1 is coupled to the first node N1.

[0060] Figure 4 An exemplary structure of the first initialization sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first initialization sub-circuit is not limited to this, as long as its function can be achieved.

[0061] Figure 5 This is an equivalent circuit diagram of the second initialization sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 5 As shown, the second initialization sub-circuit in the pixel circuit includes a second initialization transistor M3 and a third initialization transistor M4. The control electrode of the second initialization transistor M3 is coupled to the reset line RST, the first electrode of the second initialization transistor M3 is coupled to the reference voltage line REF, and the second electrode of the second initialization transistor M3 is coupled to the fourth node N4. The control electrode of the third initialization transistor M4 is coupled to the scan line GL, the first electrode of the third initialization transistor M4 is coupled to the reference voltage line REF, and the second electrode of the third initialization transistor M4 is coupled to the fourth node N4.

[0062] Figure 5 An exemplary structure of the second initialization sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second initialization sub-circuit is not limited to this, as long as its function can be achieved.

[0063] Figure 6 This is an equivalent circuit diagram of the threshold compensation sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 6 As shown, the threshold compensation sub-circuit in the pixel circuit includes a threshold compensation transistor M2. The control electrode of the threshold compensation transistor M2 is coupled to the scan line GL, the first electrode of the threshold compensation transistor M2 is coupled to the first node N1, and the second electrode of the threshold compensation transistor M2 is coupled to the second node N2.

[0064] Figure 6 An exemplary structure of the threshold compensation sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the threshold compensation sub-circuit is not limited to this, as long as its function can be achieved.

[0065] Figure 7 This is an equivalent circuit diagram of the light emission control sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 7 As shown, the light-emitting control sub-circuit in the pixel circuit includes: a first light-emitting control transistor M5 and a second light-emitting control transistor M6. The control electrode of the first light-emitting control transistor M5 is coupled to the light-emitting control line EML, the first electrode of the first light-emitting control transistor M5 is coupled to the first power supply line PL1, and the second electrode of the first light-emitting control transistor M5 is coupled to the second node N2. The control electrode of the second light-emitting control transistor M6 is coupled to the light-emitting control line EML, the first electrode of the second light-emitting control transistor M6 is coupled to the third node N3, and the second electrode of the second light-emitting control transistor M6 is coupled to the fourth node N4.

[0066] Figure 7 An exemplary structure of the light-emitting control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the light-emitting control sub-circuit is not limited to this, as long as its function can be achieved.

[0067] Figure 8 This is an equivalent circuit diagram of the data writing sub-circuit of the pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 8 As shown, the data writing sub-circuit in the pixel circuit includes a data writing transistor M7. The control electrode of the data writing transistor M7 is coupled to the scan line GL, the first electrode of the data writing transistor M7 is coupled to the data line DL, and the second electrode of the data writing transistor M7 is coupled to the third node N3.

[0068] Figure 8 An exemplary structure of the data writing sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the data writing sub-circuit is not limited to this, as long as its function can be achieved.

[0069] Figure 9 This is an equivalent circuit diagram of the storage sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 9 As shown, the storage sub-circuit in the pixel circuit includes a storage capacitor C1. The first end of the storage capacitor C1 is coupled to the first node N1, and the second end of the storage capacitor C1 is coupled to the fourth node N4.

[0070] Figure 9 An exemplary structure of the storage sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the storage sub-circuit is not limited to this, as long as its function can be achieved.

[0071] Figure 10 This is an equivalent circuit diagram of the voltage regulator sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 10 As shown, the voltage regulator sub-circuit in the pixel circuit includes a voltage regulator capacitor C2. The first terminal of the voltage regulator capacitor C2 is coupled to the fourth node N4, and the second terminal of the voltage regulator capacitor C2 is coupled to the scan line GL.

[0072] Figure 10 An exemplary structure of a voltage regulator circuit is shown. It will be readily understood by those skilled in the art that the implementation of the voltage regulator circuit is not limited to this, as long as its function can be achieved.

[0073] Figure 11 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 11As shown, the driving sub-circuit includes: driving transistor M8; the first initialization sub-circuit includes: first initialization transistor M1; the threshold compensation sub-circuit includes: threshold compensation transistor M2; the second initialization sub-circuit includes: second initialization transistor M3 and third initialization transistor M4; the light emission control sub-circuit includes: first light emission control transistor M5 and second light emission control transistor M6; the data writing sub-circuit includes: data writing transistor M7; the storage sub-circuit includes: storage capacitor C1; and the voltage regulation sub-circuit includes: voltage regulation capacitor C2.

[0074] In some exemplary implementations, such as Figure 11 As shown, the control electrode of driving transistor M8 is coupled to the first node N1, the first electrode of driving transistor M8 is coupled to the second node N2, and the second electrode of driving transistor M8 is coupled to the third node N3. The control electrode of the first initialization transistor M1 is coupled to the reset line RST, the first electrode of the first initialization transistor M1 is coupled to the first power supply line PL1, and the second electrode of the first initialization transistor M1 is coupled to the first node N1. The control electrode of the second initialization transistor M3 is coupled to the reset line RST, the first electrode of the second initialization transistor M3 is coupled to the reference voltage line REF, and the second electrode of the second initialization transistor M3 is coupled to the fourth node N4. The control electrode of the third initialization transistor M4 is coupled to the scan line GL, the first electrode of the third initialization transistor M4 is coupled to the reference voltage line REF, and the second electrode of the third initialization transistor M4 is coupled to the fourth node N4. The control electrode of the threshold compensation transistor M2 is coupled to the scan line GL, the first electrode of the threshold compensation transistor M2 is coupled to the first node N1, and the second electrode of the threshold compensation transistor M2 is coupled to the second node N2. The control electrode of the first light-emitting control transistor M5 is coupled to the light-emitting control line EML. The first electrode of the first light-emitting control transistor M5 is coupled to the first power supply line PL1, and the second electrode of the first light-emitting control transistor M5 is coupled to the second node N2. The control electrode of the second light-emitting control transistor M6 is coupled to the light-emitting control line EML. The first electrode of the second light-emitting control transistor M6 is coupled to the third node N3, and the second electrode of the second light-emitting control transistor M6 is coupled to the fourth node N4. The control electrode of the data writing transistor M7 is coupled to the scan line GL. The first electrode of the data writing transistor M7 is coupled to the data line DL, and the second electrode of the data writing transistor M7 is coupled to the third node N3. The first terminal of the storage capacitor C1 is coupled to the first node N1, and the second terminal of the storage capacitor C1 is coupled to the fourth node N4. The first terminal of the voltage regulator capacitor C2 is coupled to the fourth node N4, and the second terminal of the voltage regulator capacitor C2 is coupled to the scan line GL. The first electrode of the light-emitting element EL is coupled to the fourth node N4, and the second electrode of the light-emitting element EL is coupled to the second power supply line PL2.

[0075] In some exemplary embodiments, transistors M1 to M8 in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield. In some possible implementations, the multiple transistors in the pixel circuit may include both P-type and N-type transistors. This embodiment is not limited in this respect.

[0076] In some exemplary embodiments, transistors M1 to M8 in the pixel circuit can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs have advantages such as high mobility and fast charging, while OPT TFTs have advantages such as low leakage current. Integrating LTPS TFTs and OPTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0077] The following is through Figure 11 The working process of the provided pixel circuit further illustrates the solution of this embodiment.

[0078] by Figure 11 Taking the provided pixel circuits, which all use N-type thin-film transistors as an example, for... Figure 11 The operation of the pixel circuit shown is illustrated by way of example. Figure 12 for Figure 11 The timing diagram of the pixel circuit shown is as follows. Figure 11 As shown, the pixel circuit involved in this exemplary embodiment includes: 8 transistor units (i.e., transistors M1 to M8), 2 capacitor units (i.e., storage capacitor C1 and voltage regulator capacitor C2), 5 input terminals (i.e., data line DL, scan line GL, reset line RST, light emission control line EML, and reference voltage line REF), and 2 power supply terminals (i.e., first power supply line PL1 and second power supply line PL2). The first power supply line PL1 continuously provides a high-level signal, for example, a first power signal ELVDD, and the second power supply line PL2 continuously provides a low-level signal, for example, a second power signal ELVSS.

[0079] In this exemplary embodiment, the scan line GL(n) driving the nth row of pixel circuits is configured to provide a scan signal G(n). The scan line GL(n-1) driving the (n-1)th row of pixel circuits can be multiplexed as the reset line RST driving the nth row of pixel circuits, configured to provide a reset signal to the nth row of pixel circuits. That is, the reset signal provided by the reset line RST of the nth row of pixel circuits is the scan signal G(n-1). Here, n is a positive integer.

[0080] like Figure 12 As shown, the operation of the pixel circuit within one frame time period includes the following stages: initialization stage T1, writing stage T2, and light emission stage T3.

[0081] The first stage, T1, is the initialization stage, such as... Figure 12 As shown, the light emission control signal EM provided by the light emission control line EML is at a low level, and the first light emission control transistor M5 and the second light emission control transistor M6 are disconnected; the scan signal G(n) provided by the scan line GL is at a low level, and the threshold compensation transistor M2, the data writing transistor M7, and the third initialization transistor M4 are disconnected; the reset signal (i.e., the scan signal G(n-1)) provided by the reset line RST is at a high level, and the first initialization transistor M1 and the second initialization transistor M3 are turned on. The first initialization transistor M1 and the second initialization transistor M3 are turned on, initializing the two ends of the storage capacitor C1 (i.e., the first node N1 and the fourth node N4). The first initialization transistor M1 connects the first node N1 to the first power supply line PL1, so that the voltage V of the first node N1 is V N1 =ELVDD, where ELVDD is the first power signal provided by the first power line PL1; the second initialization transistor M3 turns on the fourth node N4 and the reference voltage line REF, making the voltage V of the fourth node N4... N4 =Vref, where Vref is the reference voltage provided by the reference voltage line REF.

[0082] The second stage, T2, is the write stage, such as... Figure 12As shown, the light emission control signal EM provided by the light emission control line EML is at a low level, and the first light emission control transistor M5 and the second light emission control transistor M6 are disconnected; the reset signal (i.e., the scan signal G(n-1)) provided by the reset line RST is at a low level, and the first initialization transistor M1 and the second initialization transistor M3 are disconnected; the scan signal G(n) provided by the scan line GL is at a high level, and the threshold compensation transistor M2, the third initialization transistor M4, and the data writing transistor M7 are turned on. The threshold compensation transistor M2 and the data writing transistor M7 are turned on, so that the data line DL establishes a path with the first node N1 through the data writing transistor M7, the driving transistor M5, and the threshold compensation transistor M2. The threshold compensation transistor M2 turns the first node N1 and the second node N2 on, and the driving transistor M8 forms a diode structure. The charge of the first node N1 flows to the data line DL through the threshold compensation transistor M2, the driving transistor M3, and the data writing transistor M7 until the voltage V of the first node N1 reaches a certain level. N1 = Vdata + Vth, where Vth is the threshold voltage of the driving transistor M8, and Vdata is the voltage of the data signal DA transmitted on the data line DL. The third initialization transistor M4 is turned on, connecting the reference voltage line REF to the fourth node N4, thus maintaining the voltage of the fourth node N4 at the reference voltage Vref, i.e., V... N4 =Vref.

[0083] During this stage, although the driving transistor M8 is turned on and generates a driving current, the driving current cannot flow into the light-emitting element EL because the second light-emitting control transistor M6 is turned off, and the light-emitting element EL does not emit light.

[0084] The third stage, T3, is the luminescence stage, such as... Figure 12 As shown, the reset signal (i.e., scan signal G(n-1)) provided by the reset line RST is low, and the first initialization transistor M1 and the second initialization transistor M3 are turned off; the scan signal G(n) provided by the scan line GL is low, and the threshold compensation transistor M2, the third initialization transistor M4, and the data write transistor M7 are turned off; the light emission control signal EM provided by the light emission control line EML is high, and the first light emission control transistor M5 and the second light emission control transistor M6 are turned on. Under the voltage holding effect of the storage capacitor C1, the gate-source voltage Vgs of the driving transistor M8 is V N1 -V N4 = Vdata + Vth - Vref. The drive current generated by the driving transistor M8 flows into the light-emitting element EL through the second light-emitting control transistor M6. The drive current Id output by the driving transistor M8 can be obtained by the following formula:

[0085]

[0086] in, μ is the channel mobility of the driving transistor, W and L are the channel width and channel length of the driving transistor, respectively, and C is the channel mobility of the driving transistor. ox Vth is the channel capacitance per unit area of ​​the driving transistor. Vdata is the gate-source voltage difference of the driving transistor. Vth is the threshold voltage of the driving transistor. Vdata is the voltage of the data signal DA transmitted via the data line DL. Vref is the reference voltage provided by the reference voltage line REF.

[0087] As can be seen from the above formula, the driving current is independent of the threshold voltage Vth of the driving transistor, and depends only on the voltage of the data signal DA provided by the data line DL and the reference voltage Vref provided by the reference voltage line REF. This eliminates the influence of the threshold voltage of the driving transistor on the driving current, thereby ensuring uniform display brightness of the display device and improving the display effect.

[0088] In this exemplary embodiment, a pixel circuit comprising eight transistors and two capacitors can be used to realize the storage and compensation function of the threshold voltage of the driving transistor, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current.

[0089] In this exemplary embodiment, the two ends of the voltage stabilizing capacitor C2 are connected to the fourth node N2 and the scan line GL, respectively, which can stabilize the potential of the fourth node N4 and prevent the leakage current of the transistor from affecting the compensation effect.

[0090] In some exemplary embodiments, the voltage of the data signal DA transmitted by the data line DL can be approximately 0V to 5V, and the threshold voltage Vth of the driving transistor can be approximately -1V to 1V. However, this embodiment is not limited to this.

[0091] The pixel circuit of this exemplary embodiment can achieve internal threshold voltage compensation, thereby improving the display effect. Furthermore, by multiplexing the scan signal as the reset signal, the structure of the gate drive circuit can be simplified, which is beneficial for achieving a narrow bezel design. In addition, the pixel circuit of this exemplary embodiment uses N-type thin-film transistors, which can improve problems such as short-term image retention caused by the hysteresis of P-type transistors.

[0092] Figure 13 This is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 13As shown, the first initialization transistor M1 and the threshold compensation transistor M2 can be dual-gate transistors. In this example, the first initialization transistor M1 includes two first sub-transistors M1_1 and M1_2. The control electrodes of the first sub-transistors M1_1 and M1_2 are coupled and connected to the reset line RST; the first electrode of the first sub-transistor M1_1 is coupled to the first node N1, the second electrode of the first sub-transistor M1_1 is coupled to the first electrode of the first sub-transistor M1_2, and the second electrode of the first sub-transistor M1_2 is coupled to the first power supply line PL1. The threshold compensation transistor M2 includes two second sub-transistors M2_1 and M2_2. The control electrodes of the second sub-transistors M2_1 and M2_2 are coupled and connected to the scan line GL; the first electrode of the second sub-transistor M2_1 is coupled to the first node N1, the second electrode of the second sub-transistor M2_1 is coupled to the first electrode of the second sub-transistor M2_2, and the second electrode of the second sub-transistor M2_2 is coupled to the second node N2.

[0093] This exemplary embodiment employs a dual-gate structure for the first initialization transistor and the threshold compensation transistor, which reduces leakage current from the threshold compensation transistor to the first node during the initialization and light-emitting phases, as well as leakage current from the first initialization transistor to the first node during the writing and light-emitting phases, thus preventing the leakage current of the transistor from affecting the compensation effect.

[0094] The remaining structure and timing of the pixel circuit in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0095] At least one embodiment of this disclosure also provides a method for driving a pixel circuit. Figure 14 This is a flowchart illustrating a pixel circuit driving method according to at least one embodiment of this disclosure. Figure 14 As shown, the driving method for the pixel circuit in this exemplary embodiment includes the following steps:

[0096] Step 100: During the initialization phase, under the control of the reset line, the first initialization sub-circuit connects the first power supply line and the first node, and the second initialization sub-circuit connects the reference voltage line and the fourth node.

[0097] Step 200: During the writing phase, under the control of the scan line, the data writing sub-circuit transmits the data signal provided by the data line to the third node, the threshold compensation sub-circuit turns on the first node and the second node to write the threshold voltage of the driving sub-circuit into the storage sub-circuit, and the second initialization sub-circuit turns on the reference voltage line and the fourth node.

[0098] Step 300: During the light-emitting stage, under the control of the light-emitting control line, the light-emitting control sub-circuit turns on the first power line and the second node, and turns on the third node and the fourth node, so as to transmit the driving current output by the driving sub-circuit to the light-emitting element.

[0099] The pixel circuit driving method provided in this exemplary embodiment is used in the pixel circuit provided in the foregoing embodiments. Its implementation principle and effect are similar, so it will not be described again here.

[0100] At least one embodiment of this disclosure also provides a display device, including a pixel circuit. The implementation principle and effect of the pixel circuit are similar to those of the foregoing embodiments, and therefore will not be repeated here.

[0101] In some exemplary embodiments, the display device may include a display substrate, and pixel circuitry may be disposed on the display substrate. The display substrate may be an OLED display substrate. The display device may be any product or component with display functionality, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0102] In some exemplary embodiments, the display device further includes a gate driving circuit. The gate driving circuit includes a plurality of cascaded first shift register units and a plurality of cascaded second shift register units. The output of the nth-stage first shift register unit is coupled to a scan line driving the nth row of pixel circuits; the output of the (n-1)th-stage first shift register unit is coupled to a reset line driving the nth row of pixel circuits; and the output of the nth-stage second shift register unit is coupled to a light-emitting control line driving the nth row of pixel circuits; where n is a positive integer.

[0103] Figure 15 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 15 As shown, the display device includes: multiple pixel circuits 10, multiple scan lines (e.g., scan lines GL(0) to GL(n)), multiple light emission control lines (e.g., light emission control lines EML(1) to EML(n)), multiple data lines (e.g., data lines DL(1) to DL(m)), gate drive circuits 12a and 12b, a data driver, and a timing controller. Wherein, n and m are both positive integers.

[0104] In some examples, multiple pixel circuits 10 are located in the display area of ​​the display device, and gate driving circuits 12a and 12b are located on opposite sides of the display area. For example, gate driving circuit 12a is located on the left side of the display area, and gate driving circuit 12b is located on the right side of the display area. Taking gate driving circuit 12a as an example, gate driving circuit 12a includes: multiple cascaded first shift register units G_GOA and multiple cascaded second shift register units EM_GOA. The output of the nth-stage first shift register unit G_GOA(n) is coupled to the scan line GL(n) driving the nth row of pixel circuits; the output of the (n-1)th-stage first shift register unit G_GOA(n-1) is coupled to the reset line driving the nth row of pixel circuits. The output of the nth-stage second shift register unit EM_GOA(n) is coupled to the light emission control line EML(n) driving the nth row of pixel circuits. The structure of gate driving circuit 12b can be referred to the structure of gate driving circuit 12a, and therefore will not be described further here.

[0105] In some exemplary embodiments, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and can provide clock signals, scan start signals, transmit stop signals, etc., of specifications suitable for the gate driver circuit to the gate driver circuit. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data lines DL(1) to DL(m). For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data lines DL(1) to DL(m) on a pixel-by-pixel basis. Multiple cascaded first shift register units of the gate driver circuit can generate scan signals to be provided to scan lines GL(0) to GL(n) by receiving clock signals, scan start signals, etc., from the timing controller. Multiple cascaded second shift register units of the gate driver circuit can generate light emission control signals to be provided to light emission control lines EML(1) to EML(n) by receiving clock signals, transmit stop signals, etc., from the timing controller.

[0106] In this exemplary embodiment, the gate driving circuit only needs to provide scanning signals and light emission control signals to the pixel circuit, which has a simple structure, good signal stability, and is conducive to realizing narrow bezel design.

[0107] Figure 16 This is another schematic diagram of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 16As shown, the gate driving circuit includes a first set of shift register units 121 and a second set of shift register units 122. The first set of shift register units 121 includes multiple cascaded first shift register units G_GOA, configured to generate a scan signal; the second set of shift register units 122 includes multiple cascaded second shift register units EM_GOA, configured to generate a light emission control signal. The first set of shift register units 121 and the second set of shift register units 122 can be located on opposite sides of the display area.

[0108] The remaining structure of the display device in this embodiment can be referred to... Figure 15 The description of the illustrated embodiment is omitted here.

[0109] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure and features thereof can be combined to obtain new embodiments.

[0110] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A pixel circuit for driving a light-emitting element to emit light, the pixel circuit comprising: The circuit includes a driver sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a storage sub-circuit, a light emission control sub-circuit, a first initialization sub-circuit, a second initialization sub-circuit, and a voltage regulator sub-circuit. The driving sub-circuit is coupled to the first node, the second node and the third node, and is configured to provide driving current to the third node under the control of the first node; The data writing sub-circuit is coupled to the data line, the scan line and the third node, and is configured to transmit the data signal provided by the data line to the third node under the control of the scan line; The threshold compensation sub-circuit is coupled to the scan line, the first node and the second node, and is configured to turn on the first node and the second node under the control of the scan line so as to write the threshold voltage of the driving sub-circuit into the storage sub-circuit. The storage sub-circuit is coupled to the first node and the fourth node; The light emission control sub-circuit is coupled to the light emission control line, the first power line, the second node, the third node, and the fourth node, and is configured to turn on the first power line and the second node, as well as the third node and the fourth node, under the control of the light emission control line. The first initialization sub-circuit is coupled to the reset line, the first power line and the first node, and is configured to turn on the first power line and the first node under the control of the reset line; The second initialization sub-circuit, coupled to the scan line, reset line, reference voltage line and fourth node, is configured to turn on the reference voltage line and the fourth node under the control of the reset line, and to turn on the reference voltage line and the fourth node under the control of the scan line. The first electrode of the light-emitting element is coupled to the fourth node, and the second electrode of the light-emitting element is coupled to the second power line; The voltage regulator sub-circuit includes a voltage regulator capacitor, the first end of which is coupled to the fourth node, and the second end of which is coupled to the scanning terminal. The reset line of the pixel circuit located in the nth row is coupled to the scan line that drives the pixel circuit in the (n-1)th row, where n is a positive integer; The scan line driving the (n-1)th row pixel circuit is multiplexed as the reset line driving the nth row pixel circuit, providing a reset signal to the nth row pixel circuit.

2. The pixel circuit according to claim 1, wherein, The driving sub-circuit includes: a driving transistor; the control electrode of the driving transistor is coupled to a first node, the first electrode of the driving transistor is coupled to a second node, and the second electrode of the driving transistor is coupled to a third node.

3. The pixel circuit according to claim 1, wherein, The first initialization sub-circuit includes: a first initialization transistor; the control electrode of the first initialization transistor is coupled to a reset line, the first electrode of the first initialization transistor is coupled to a first power supply line, and the second electrode of the first initialization transistor is coupled to a first node.

4. The pixel circuit according to claim 1, wherein, The second initialization sub-circuit includes: a second initialization transistor and a third initialization transistor; The control electrode of the second initialization transistor is coupled to the reset line, the first electrode of the second initialization transistor is coupled to the reference voltage line, and the second electrode of the second initialization transistor is coupled to the fourth node. The control electrode of the third initialization transistor is coupled to the scan line, the first electrode of the third initialization transistor is coupled to the reference voltage line, and the second electrode of the third initialization transistor is coupled to the fourth node.

5. The pixel circuit according to claim 1, wherein, The threshold compensation sub-circuit includes: a threshold compensation transistor; the control electrode of the threshold compensation transistor is coupled to the scan line, the first electrode of the threshold compensation transistor is coupled to a first node, and the second electrode of the threshold compensation transistor is coupled to a second node.

6. The pixel circuit according to claim 1, wherein, The light-emitting control sub-circuit includes: a first light-emitting control transistor and a second light-emitting control transistor; The control electrode of the first light-emitting control transistor is coupled to the light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to the first power supply line, and the second electrode of the first light-emitting control transistor is coupled to the second node. The control electrode of the second light-emitting control transistor is coupled to the light-emitting control line, the first electrode of the second light-emitting control transistor is coupled to the third node, and the second electrode of the second light-emitting control transistor is coupled to the fourth node.

7. The pixel circuit according to claim 1, wherein, The data writing sub-circuit includes: a data writing transistor; the control electrode of the data writing transistor is coupled to the scan line, the first electrode of the data writing transistor is coupled to the data line, and the second electrode of the data writing transistor is coupled to the third node.

8. The pixel circuit according to claim 1, wherein, The storage sub-circuit includes: a storage capacitor; the first end of the storage capacitor is coupled to a first node, and the second end of the storage capacitor is coupled to a fourth node.

9. The pixel circuit according to claim 1, wherein, The driving sub-circuit includes: a driving transistor; the first initialization sub-circuit includes: a first initialization transistor; the second initialization sub-circuit includes: a second initialization transistor and a third initialization transistor; the threshold compensation sub-circuit includes: a threshold compensation transistor; the light emission control sub-circuit includes: a first light emission control transistor and a second light emission control transistor; the data writing sub-circuit includes: a data writing transistor; the storage sub-circuit includes: a storage capacitor; The control electrode of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node. The control electrode of the first initialization transistor is coupled to the reset line, the first electrode of the first initialization transistor is coupled to the first power supply line, and the second electrode of the first initialization transistor is coupled to the first node. The control electrode of the second initialization transistor is coupled to the reset line, the first electrode of the second initialization transistor is coupled to the reference voltage line, and the second electrode of the second initialization transistor is coupled to the fourth node. The control electrode of the third initialization transistor is coupled to the scan line, the first electrode of the third initialization transistor is coupled to the reference voltage line, and the second electrode of the third initialization transistor is coupled to the fourth node. The control electrode of the threshold compensation transistor is coupled to the scan line, the first electrode of the threshold compensation transistor is coupled to the first node, and the second electrode of the threshold compensation transistor is coupled to the second node. The control electrode of the first light-emitting control transistor is coupled to the light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to the first power supply line, and the second electrode of the first light-emitting control transistor is coupled to the second node. The control electrode of the second light-emitting control transistor is coupled to the light-emitting control line, the first electrode of the second light-emitting control transistor is coupled to the third node, and the second electrode of the second light-emitting control transistor is coupled to the fourth node. The control electrode of the data writing transistor is coupled to the scan line, the first electrode of the data writing transistor is coupled to the data line, and the second electrode of the data writing transistor is coupled to the third node. The first end of the storage capacitor is coupled to the first node, and the second end of the storage capacitor is coupled to the fourth node.

10. The pixel circuit according to claim 9, wherein, The driving transistor, the first initialization transistor, the second initialization transistor, the third initialization transistor, the threshold compensation transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the data writing transistor are all N-type transistors.

11. The pixel circuit according to claim 9 or 10, wherein, The first initialization transistor and the threshold compensation transistor are dual-gate transistors.

12. A driving method for a pixel circuit, applied to a pixel circuit as described in any one of claims 1 to 11, the driving method comprising: During the initialization phase, under the control of the reset line, the first initialization sub-circuit connects the first power supply line and the first node, and the second initialization sub-circuit connects the reference voltage line and the fourth node. During the writing phase, under the control of the scan line, the data writing sub-circuit transmits the data signal provided by the data line to the third node, the threshold compensation sub-circuit turns on the first and second nodes to write the threshold voltage of the driving sub-circuit into the storage sub-circuit, and the second initialization sub-circuit turns on the reference voltage line and the fourth node. During the light-emitting stage, under the control of the light-emitting control line, the light-emitting control sub-circuit turns on the first power line and the second node, and turns on the third node and the fourth node, so as to transmit the driving current output by the driving sub-circuit to the light-emitting element.

13. A display device, comprising: The pixel circuit as described in any one of claims 1 to 11.

14. The display device according to claim 13, further comprising: Gate drive circuit; The gate drive circuit includes: multiple cascaded first shift register units and multiple cascaded second shift register units; The output of the first shift register unit of the nth stage is coupled to the scan line driving the nth row of pixel circuits; the output of the first shift register unit of the (n-1)th stage is coupled to the reset line driving the nth row of pixel circuits; the output of the second shift register unit of the nth stage is coupled to the light emission control line driving the nth row of pixel circuits; where n is a positive integer.

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