Pseudorandom number generator and pseudorandom number generation method

Abstract

The present disclosure provides a pseudo-random number generator and a pseudo-random number generation method. The pseudo-random number generator comprises: a signal mapping circuit configured to map a plurality of input signals using a chaotic model to obtain a plurality of chaotic signals having a four-wing chaotic state; a signal sampling circuit electrically connected to the signal mapping circuit and configured to sample the plurality of chaotic signals to obtain a plurality of state variables corresponding to each chaotic signal in the plurality of chaotic signals; and a signal operation circuit electrically connected to the signal sampling circuit and configured to perform an integer operation on the plurality of state variables corresponding to each chaotic signal to obtain a plurality of groups of random numbers corresponding to the plurality of chaotic signals respectively, each group of random numbers in the plurality of groups of random numbers comprising a plurality of random numbers.

Description

Technical Field

[0001] This disclosure relates to the field of information security technology, and more specifically, to a pseudo-random number generator and a pseudo-random number generation method. Background Technology

[0002] Random numbers are commonly used in the design of encryption systems. The randomness of the random numbers generated by a random number generator plays a crucial role in the security of an encryption system.

[0003] The randomness performance of pseudorandom number generators based on chaos theory depends on the dynamic behavior of the chaotic model, such as its dimensionality. Pseudorandom number generators typically use low-dimensional mappings to generate pseudorandom numbers with a two-winged chaotic effect. Examples include the tent map, the Enon map, and the Logistic map. However, pseudorandom numbers with a two-winged chaotic effect generated based on low-dimensional chaotic models have poor ergodicity and are easily cracked, thus posing a security vulnerability to encryption systems. Summary of the Invention

[0004] This disclosure provides a pseudo-random number generator and a method for generating pseudo-random numbers.

[0005] According to one aspect of this disclosure, a pseudo-random number generator is proposed, comprising: a signal mapping circuit for mapping multiple input signals using a chaotic model to obtain multiple chaotic signals with four-winged chaotic states; a signal sampling circuit electrically connected to the signal mapping circuit for sampling the multiple chaotic signals to obtain multiple state variables corresponding to each of the multiple chaotic signals; and a signal processing circuit electrically connected to the signal sampling circuit for performing floor operations on the multiple state variables corresponding to each chaotic signal to obtain multiple sets of random numbers corresponding to the multiple chaotic signals, wherein each set of random numbers includes multiple random numbers.

[0006] For example, the signal mapping circuit includes: a signal selection unit, used to select multiple input signals based on a chaotic model to obtain multiple sets of signals, each set of signals including at least one of the multiple input signals; and multiple processing channels, electrically connected to the signal selection unit, used to perform mapping operations on the multiple sets of signals based on the chaotic model to obtain multiple chaotic signals; wherein, the signal selection unit is further used to select multiple chaotic signals based on the chaotic model when it is determined that the number of mapping operations of the multiple processing channels is less than a preset number, to obtain multiple sets of signals, and to send the multiple sets of signals to the multiple processing channels respectively, each set of signals including at least one of the multiple chaotic signals.

[0007] For example, each of the multiple operation channels includes: a first inverter for performing an inverted summation operation on one of the multiple sets of signals to obtain a first operation result; an inverting integrator electrically connected to the first inverter for performing an inverted integration operation on the first operation to obtain a second operation result; and a second inverter electrically connected to the inverting integrator for performing an inverted scaling operation on the second operation result to obtain a chaotic signal.

[0008] For example, the signal mapping circuit further includes: a signal generation unit electrically connected to multiple operation channels for generating multiple initial signals; wherein, the multiple operation channels are also used to perform mapping operations on multiple sets of signals based on a chaotic model to obtain multiple chaotic signals, and each set of signals includes at least one initial signal among multiple initial signals.

[0009] For example, the signal generation unit includes multiple DC power supplies for generating multiple initial signals based on multiple initial voltage values.

[0010] For example, a chaotic model includes a four-dimensional chaotic model, multiple input signals including a first input signal, a second input signal, a third input signal, and a fourth input signal, multiple chaotic signals including a first chaotic signal, a second chaotic signal, a third chaotic signal, and a fourth chaotic signal, and the four-dimensional chaotic model includes: the mapping relationship between the first chaotic signal and the first, second, and third input signals; the mapping relationship between the second chaotic signal and the first, second, and third input signals; the mapping relationship between the third chaotic signal and the first, second, third, and fourth input signals; and the mapping relationship between the fourth chaotic signal and the second, third, and fourth input signals.

[0011] For example, multiple chaotic signals output after n mapping operations are related to multiple chaotic signals output after n-1 mapping operations, where n = 1, 2, ..., N, where N is a positive integer and N is the preset number of operations; when n = 1, the multiple chaotic signals output after n-1 mapping operations are multiple initial signals.

[0012] For example, the signal sampling circuit includes: a front-end conditioning unit for conditioning the waveforms and amplitudes of multiple chaotic signals respectively; and a sampling unit for converting the conditioned multiple chaotic signals from analog signals to digital signals, and sampling the digital signals at a preset frequency to obtain multiple state variables corresponding to each chaotic signal among the multiple chaotic signals.

[0013] For example, the sampling unit is also used to sample the digital signal 3f+D times at a preset frequency to obtain 3f+D state variables corresponding to each chaotic signal among multiple chaotic signals, where f is the preset frequency and D is the number of random numbers in each set of random numbers.

[0014] For example, a signal processing circuit includes a microcontroller unit, which uses a rounding model to perform rounding operations on multiple state variables corresponding to each chaotic signal to obtain multiple random number sequences corresponding to the multiple chaotic signals.

[0015] For example, the signal processing circuit also includes a test unit, which is electrically connected to the microcontroller unit, for converting the random number sequence into a bit stream and performing a randomness test on the bit stream; wherein, if the randomness test results are determined to meet the randomness requirements, the microcontroller unit is also used to output multiple random number sequences.

[0016] According to another aspect of the embodiments of this disclosure, a pseudo-random number generation method is provided, comprising: a signal mapping circuit mapping multiple input signals using a chaotic model to obtain multiple chaotic signals having a four-winged chaotic state; a signal sampling circuit sampling the multiple chaotic signals to obtain multiple state variables corresponding to each of the multiple chaotic signals; and a signal processing circuit performing a rounding operation on the multiple state variables corresponding to each chaotic signal to obtain multiple sets of random numbers corresponding to the multiple chaotic signals, wherein each set of random numbers includes multiple random numbers.

[0017] According to embodiments of this disclosure, generating random numbers using a chaotic signal with a four-winged chaotic state can increase the numerical range of random numbers and improve their ergodicity and randomness. Furthermore, the pseudo-random number generator of this disclosure utilizes the complex dynamic behavior of a chaotic signal with a four-winged chaotic state, avoiding the problem of periodic degradation of chaotic signals and improving the security of random numbers applied in encryption systems. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments in conjunction with the accompanying drawings. It should be noted that throughout the drawings, the same elements are indicated by the same or similar reference numerals.

[0019] Figure 1 A schematic diagram of the structure of a pseudo-random number generator according to an embodiment of the present disclosure is shown;

[0020] Figure 2 A schematic diagram of the structure of a signal mapping circuit according to an embodiment of the present disclosure is shown;

[0021] Figure 3 A schematic diagram of a signal mapping circuit according to another embodiment of the present disclosure is shown;

[0022] Figure 4 A schematic diagram of a signal mapping circuit according to another embodiment of the present disclosure is shown;

[0023] Figure 5A A schematic diagram of the structure of a signal generation unit according to an embodiment of the present disclosure is shown;

[0024] Figure 5B A schematic diagram of the structure of a first computing channel according to an embodiment of the present disclosure is shown;

[0025] Figure 5C A schematic diagram of the structure of the second computing channel according to an embodiment of the present disclosure is shown;

[0026] Figure 5D A schematic diagram of the structure of the third computing channel according to an embodiment of the present disclosure is shown;

[0027] Figure 5E A schematic diagram of the structure of the fourth computing channel according to an embodiment of the present disclosure is shown;

[0028] Figure 6 A schematic diagram of a pseudo-random number generator according to another embodiment of the present disclosure is shown; and

[0029] Figure 7 A flowchart of a pseudo-random number generation method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0031] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0032] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" may refer to two components being directly connected, or to two components being connected via one or more other components, wherein the connection method is electrical connection or electrical coupling.

[0033] This disclosure provides a method comprising: a signal mapping circuit for mapping multiple input signals using a chaotic model to obtain multiple chaotic signals with a four-winged chaotic state; a signal sampling circuit electrically connected to the signal mapping circuit for sampling the multiple chaotic signals to obtain multiple state variables corresponding to each of the multiple chaotic signals; and a signal processing circuit electrically connected to the signal sampling circuit for performing floor operations on the multiple state variables corresponding to each chaotic signal to obtain multiple sets of random numbers corresponding to the multiple chaotic signals, wherein each set of random numbers includes multiple random numbers.

[0034] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0035] Figure 1 A schematic diagram of a pseudo-random number generator according to an embodiment of the present disclosure is shown.

[0036] like Figure 1 As shown, the pseudo-random number generator 100 includes a signal mapping circuit 110, a signal sampling circuit 120, and a signal processing circuit 130. The signal mapping circuit 110, the signal sampling circuit 120, and the signal processing circuit 130 are electrically connected in sequence.

[0037] The signal mapping circuit 110 uses a chaotic model to map multiple input signals to obtain multiple chaotic signals with four-winged chaotic states.

[0038] Chaos models can include three-dimensional chaos models, four-dimensional chaos models, five-dimensional chaos models, or higher-dimensional chaos models.

[0039] For example, if the chaotic model is determined to be a four-dimensional chaotic model, there can be four input signals. By performing a chaotic mapping on the four input signals using the four-dimensional chaotic model, four chaotic signals are obtained. For instance, the phase plane diagram of the four chaotic signals can form a four-winged chaotic state.

[0040] The signal sampling circuit 120 samples multiple chaotic signals to obtain multiple state variables corresponding to each chaotic signal.

[0041] For example, multiple state variables can be discrete voltage values. When there are four chaotic signals, the signal sampling circuit 120 can sample each of the four chaotic signals D times to obtain 4D voltage values, where D is a positive integer. The 4D voltage values ​​can be transmitted to the signal processing circuit 130 via a data bus.

[0042] The signal processing circuit 130 performs floor operations on multiple state variables corresponding to each chaotic signal to obtain multiple sets of random numbers corresponding to each chaotic signal. Each set of random numbers contains multiple random numbers.

[0043] For example, the signal processing circuit 130 performs a floor operation on the D voltage values ​​of each of the four chaotic signals to obtain four sets of random numbers. Each set of random numbers includes D random numbers.

[0044] According to embodiments of this disclosure, the phase distribution of multiple chaotic signals with a four-winged chaotic state is wider, thereby generating a larger range of random numbers and improving the randomness of the random numbers.

[0045] Figure 2 A schematic diagram of a signal mapping circuit according to an embodiment of the present disclosure is shown.

[0046] like Figure 2 As shown, the signal mapping circuit 210 can perform chaotic mapping using an M-dimensional chaotic model, where M is a positive integer. The signal mapping circuit 210 includes a signal selection unit 211, a first operation channel 212, a second operation channel 213, ..., an Mth operation channel 214, and a signal generation unit 215.

[0047] The two ends of the first operation channel 212 are electrically connected to the signal selection unit 211, the two ends of the second operation channel 213 are electrically connected to the signal selection unit 211, and the two ends of the Mth operation channel 214 are electrically connected to the signal selection unit 211. The signal generation unit 215 is electrically connected to the first operation channel 212, the second operation channel 213, ..., the Mth operation channel 214.

[0048] Signal selection unit 211 selects from multiple input signals based on a chaotic model, resulting in multiple sets of signals. Each set of signals includes at least one of the multiple input signals. First operation channel 212, second operation channel 213, ..., Mth operation channel 214 perform mapping operations on the multiple sets of signals based on the chaotic model, resulting in multiple chaotic signals. For example, signal selection unit 211 selects from four input signals based on a chaotic model, resulting in four sets of signals, each including at least one of the four input signals. Signal mapping circuit 210 includes four operation channels, which perform chaotic mapping on the four sets of input signals respectively, outputting four chaotic signals.

[0049] For example, a chaotic model includes a four-dimensional chaotic model, where multiple input signals include a first input signal, a second input signal, a third input signal, and a fourth input signal, and multiple chaotic signals include a first chaotic signal, a second chaotic signal, a third chaotic signal, and a fourth chaotic signal. The four-dimensional chaotic model includes the mapping relationships between the first chaotic signal and the first, second, and third input signals; the mapping relationships between the second chaotic signal and the first, second, and third input signals; the mapping relationships between the third chaotic signal and the first, second, third, and fourth input signals; and the mapping relationships between the fourth chaotic signal and the second, third, and fourth input signals.

[0050] For example, the four input signals include signal x, signal y, signal z, and signal w. The chaotic model includes a four-dimensional chaotic model, which is represented by the dimensionless equation (1):

[0051]

[0052] and The output is a chaotic signal, x, y, z, and w are input signals, and a, b, c, d, e, and f are preset control parameters.

[0053] The four-dimensional chaotic model includes: performing a chaotic mapping on signal x using signals x, y, and z, and outputting a chaotic signal. Using signals x, y, and z, a chaotic mapping is performed on signal y to output a chaotic signal. Using signals x, y, z, and w, a chaotic mapping is performed on signal z to output a chaotic signal. And by using signals y, z, and w to perform a chaotic mapping on signal w, a chaotic signal is output.

[0054] The signal selection unit 211 selects from four input signals based on the chaotic model, resulting in four sets of signals. The first set of signals includes signals x, y, and z. The second set of signals includes signals x, y, and z. The third set of signals includes signals x, y, z, and w. The fourth set of signals includes signals y, z, and w.

[0055] The four processing channels perform mapping operations on the four sets of signals respectively, resulting in chaotic signals x, y, z, and w. Chaotic signals Chaotic signals and chaotic signals

[0056] When the number of mapping operations for multiple computation channels is determined to be less than a preset number, the chaotic signal... Chaotic signals Chaotic signals and chaotic signals The input signal, which serves as the input signal for the computational mapping channel, is selected by the signal selection unit 211 based on a chaotic model from multiple chaotic signals to obtain multiple sets of signals, which are then sent to multiple computational channels respectively. Each set of signals includes at least one chaotic signal from the multiple chaotic signals.

[0057] In this embodiment of the disclosure, the chaotic signal output after one mapping operation can be represented as x1, y1, z1, and w1. For example, if it is determined that the number of mapping operations of the four operation channels is less than a preset number, the signal selection unit 211 can select the four chaotic signals output after one mapping operation based on the chaotic model to obtain four sets of signals, and send the four sets of signals to the four operation channels respectively.

[0058] The first group of signals includes chaotic signals x1, y1, and z1. The second group of signals includes chaotic signals x1, y1, and z1. The third group of signals includes chaotic signals x1, y1, z1, and w1. The fourth group of signals includes chaotic signals y1, z1, and w1.

[0059] The four processing channels perform mapping operations on the four sets of signals respectively, resulting in chaotic signals x2, y2, z2 and w2 after two mapping operations.

[0060] The multiple chaotic signals output after n mapping operations are related to the multiple chaotic signals output after n-1 mapping operations, where n = 1, 2, ..., N, where N is a positive integer and N is the preset number of operations. When n = 1, the multiple chaotic signals output after n-1 mapping operations are multiple initial signals.

[0061] For example, the chaotic signal output after n mapping operations is represented by the dimensionless equation (2):

[0062]

[0063] x n y n z n and w n Let x be the chaotic signal output after n mapping operations. n-1 y n-1 z n-1 and w n-1 This is the chaotic signal output after n-1 mapping operations.

[0064] When n-1=0, x0, y0, z0 and w0 are the initial signals.

[0065] When the signal mapping circuit 210 is in its initial state, the input signal is the initial signal. The signal generation unit 215 generates multiple initial signals. The signal selection unit 211 selects from the multiple initial signals based on a chaotic model to obtain multiple sets of signals. Each set of signals includes at least one of the multiple initial signals.

[0066] For example, the four processing channels perform mapping operations on four sets of initial signals respectively. The first set of signals includes initial signals x0, y0, and z0. The second set of signals includes initial signals x0, y0, and z0. The third set of signals includes initial signals x0, y0, z0, and w0. The fourth set of signals includes initial signals y0, z0, and w0.

[0067] In this embodiment of the disclosure, the input signal is iteratively chaotically mapped using the signal selection unit 211, the first operation channel 212, the second operation channel 213, ... and the Mth operation channel 214 to obtain the output chaotic signal.

[0068] Figure 3 A schematic diagram of a signal mapping circuit according to another embodiment of the present disclosure is shown.

[0069] When the chaotic model is determined to include a four-dimensional chaotic model, the signal mapping circuit 310 includes four operation channels. For example... Figure 3 As shown, the signal mapping circuit 310 includes a signal selection unit 311, a first operation channel 312, a second operation channel 313, a third operation channel 314, a fourth operation channel 315, and a signal generation unit 316.

[0070] In this embodiment, the signal selection unit 311 is similar to the signal selection unit 211 in the previous embodiment. The signal generation unit 316 is similar to the signal generation unit 215 in the previous embodiment. For the sake of simplicity, this disclosure will not repeat the details.

[0071] The first operational channel 312 includes a first inverter 3121, an inverting integrator 3122, and a second inverter 3123. The second operational channel 313 includes a first inverter 3131, an inverting integrator 3132, and a second inverter 3133. The third operational channel 314 includes a first inverter 3141, an inverting integrator 3142, and a second inverter 3143. The fourth operational channel 315 includes a first inverter 3151, an inverting integrator 3152, and a second inverter 3153.

[0072] The first inverters 3121, 3131, 3141 and 3151 perform inversion and summation operations on one group of signals from multiple groups of signals to obtain the first operation result.

[0073] For example, the inverting integrator 3122 is electrically connected to the first inverter 3121. The inverting integrator 3122 performs an inverting integration operation on the first operation from the first inverter 3121 to obtain a second operation result. The second inverter 3123 is electrically connected to the inverting integrator 3122. The second inverter 3123 performs an inverting scaling operation on the second operation result from the inverting integrator 3122 to obtain a chaotic signal.

[0074] Inverting integrator 3132 is electrically connected to the first inverter 3131. Inverting integrator 3132 performs an inverting integration operation on the first operation from the first inverter 3131 to obtain a second operation result. Second inverter 3133 is electrically connected to the inverting integrator 3132. Second inverter 3133 performs an inverting scaling operation on the second operation result from the inverting integrator 3132 to obtain a chaotic signal.

[0075] Inverting integrator 3142 is electrically connected to the first inverter 3141. Inverting integrator 3142 performs an inverting integration operation on the first operation from the first inverter 3141 to obtain a second operation result. Second inverter 3143 is electrically connected to the inverting integrator 3142. Second inverter 3143 performs an inverting scaling operation on the second operation result from the inverting integrator 3142 to obtain a chaotic signal.

[0076] Inverting integrator 3152 is electrically connected to the first inverter 3151. Inverting integrator 3152 performs an inverting integration operation on the first operation from the first inverter 3151 to obtain a second operation result. Second inverter 3153 is electrically connected to the inverting integrator 3152. Second inverter 3153 performs an inverting scaling operation on the second operation result from the inverting integrator 3152 to obtain a chaotic signal.

[0077] First inverters 3121, 3131, 3141, and 3151 perform multiplication and inverted addition operations on multiple signals in a set of signals. Inverting integrators 3122, 3132, 3142, and 3152 perform integration operations on multiple signals in a set of signals. Second inverters 3123, 3133, 3143, and 3153 perform inversion operations on multiple signals in a set of signals.

[0078] For example, a four-dimensional chaotic model is:

[0079]

[0080] The first inverter 3121 multiplies signals y and z, and then adds the result of the multiplication to signal x in an inverted manner to obtain the first result. The inverting integrator 3122 integrates the first result to obtain the second result (signal -x). The second inverter 3123 inverts the second result to obtain the chaotic signal. (Signal x).

[0081] The first inverter 3131 multiplies signals x and z, and then adds the result of the multiplication of the two signals y in reverse phase to obtain the first result. The inverting integrator 3132 integrates the first result to obtain the second result (signal -y). The second inverter 3133 inverts the second result to obtain the chaotic signal. (signal y).

[0082] The first inverter 3141 multiplies signals x and y, and then adds the result of the multiplication to signals z and w in an inverted manner to obtain the first result. The inverting integrator 3142 integrates the first result to obtain the second result (signal -z). The second inverter 3143 inverts the second result to obtain the chaotic signal. (Signal z)

[0083] The first inverter 3151 multiplies signals y and w, and then adds the multiplication result to signal z in an inverted manner to obtain the first result. The inverting integrator 3152 integrates the first result to obtain the second result (signal -w). The second inverter 3153 inverts the second result to obtain the chaotic signal. (signal w).

[0084] Figure 4 A schematic diagram of a signal mapping circuit according to another embodiment of the present disclosure is shown. Figure 4 The circuit schematic of the signal mapping circuit 410 is shown. Figures 5A-5E To Figure 4 An exploded view of the signal mapping circuit 410 is shown.

[0085] Figure 4 An embodiment of a signal mapping circuit corresponding to the four-dimensional chaotic model shown by the dimensionless equation (1) is presented.

[0086] It should be noted that, Figure 4The signal selection unit is not shown. The signal input selection module may include a multiplier and a branch selection switch, etc. The branch selection switch is electrically connected to multiple operation channels, and controls at least one of the multiple input signals to be input to the operation channel, thereby realizing the coupling relationship between the multiple operation channels. Figure 4 In this diagram, the signal transmission process is represented by the electrical connection relationship of multiple operational channels, and the signal selection unit is omitted from the diagram.

[0087] Figure 5A A schematic diagram of the structure of a signal generation unit according to an embodiment of the present disclosure is shown. Figure 5B A schematic diagram of the structure of a first computing channel according to an embodiment of the present disclosure is shown. Figure 5C A schematic diagram of the structure of the second computing channel according to an embodiment of the present disclosure is shown. Figure 5D A schematic diagram of the structure of the third computing channel according to an embodiment of the present disclosure is shown. Figure 5E A schematic diagram of the structure of the fourth computing channel according to an embodiment of the present disclosure is shown.

[0088] like Figure 5A As shown, the signal generation unit includes multiple DC power supplies Vx, Vy, Vz, and Vw. The DC power supplies Vx, Vy, Vz, and Vw generate multiple initial signals based on multiple initial voltage values.

[0089] Initially, switch S is in the connected state. The DC power supply voltage is the initial voltage value. Based on the initial voltage value, the DC power supply generates an initial voltage signal. The initial voltage signal can be -x, -y, -z, or -w. After the initial voltage signal is input to the processing channel, switch S is in the open state. After switch S is open, the DC power supply does not participate in the subsequent signal iteration mapping process.

[0090] For example, the initial voltages of DC power supplies Vx, Vy, Vz, and Vw can all be 0.1V.

[0091] like Figure 5B As shown, the first processing channel is used to perform chaotic mapping on the signal x.

[0092] The first operational channel includes resistors R1, R2, R3, R4, R5, and R6, multiplier A1, operational amplifiers U1, U2, and U3, and capacitor C1.

[0093] For example, R1 = 2KΩ, R2 = 3KΩ, R3 = 12KΩ, R4 = 55KΩ, R5 = R6 = 10KΩ, C1 = 33nF, and the output gain of multiplier A1 is 1.

[0094] Resistors R1, R2, R3, R4, R5, and R6 are linear resistors. Operational amplifiers U1, U2, and U3 are analog operational amplifiers.

[0095] Operational amplifiers U1, U2, and U3 are connected to a first power supply VCC and a second power supply VEE, with the voltage of the second power supply VEE being lower than that of the first power supply VCC. All three operational amplifiers operate under the drive of the first power supply VCC and the second power supply VEE. The positive input terminals of operational amplifiers U1, U2, and U3 are grounded.

[0096] Resistors R1, R2, R3, multiplier A1, and operational amplifier U1 form the first inverter. Resistor R4, operational amplifier U2, and capacitor C1 form the inverting integrator. Resistors R5 and R6, and operational amplifier U3 form the second inverter.

[0097] Multiplier A1 receives signals -y and z at its input. Multiplier A1 performs a multiplication operation on -y and z, and sends the result -y*z through resistor R1 to the negative input of operational amplifier U1. Signal x is input to the negative input of operational amplifier U1 through resistor R2. Resistor R3 is electrically connected to the negative input and output of operational amplifier U1, respectively. Through resistor R3 and operational amplifier U1, the result -y*z and signal x are added in opposite phase, outputting the sum -a*x + b*y*z.

[0098] The sum of the outputs of operational amplifier U1, -a*x + b*y*z, is sent to the negative input terminal of operational amplifier U2 via resistor R4. The two ends of capacitor C1 are electrically connected to the negative input terminal and the output terminal of operational amplifier U2, respectively. Through capacitor C1 and operational amplifier U2, the sum of -a*x + b*y*z is integrated in reverse phase, resulting in the output signal -x.

[0099] The signal -x is sent to the negative input terminal of operational amplifier U3 via resistor R5. Resistor R6 is electrically connected to both the negative input and output terminals of operational amplifier U3. The signal -x is inverted via resistor R6 and operational amplifier U3, resulting in the output signal x.

[0100] like Figure 5C As shown, the second processing channel is used to perform chaotic mapping on the signal y.

[0101] The second operational channel includes resistors R7, R8, R9, R10, R11, and R12, multiplier A2, multiplier A3, multiplier A4, operational amplifier U4, operational amplifier U5, operational amplifier U6, and capacitor C2.

[0102] For example, R7 = 2KΩ, R8 = 25KΩ, R9 = 100KΩ, R10 = 55KΩ, R11 = R12 = 10KΩ, C2 = 33nF, and the output gain of multipliers A2, A3 and A4 is 1.

[0103] Resistors R7, R8, R9, R10, R11, and R12 are linear resistors. Operational amplifiers U4, U5, and U6 are analog operational amplifiers.

[0104] Operational amplifiers U4, U5, and U6 are connected to a first power supply VCC and a second power supply VEE, with the voltage of the second power supply VEE being lower than that of the first power supply VCC. All three operational amplifiers operate under the drive of the first power supply VCC and the second power supply VEE. The positive input terminals of operational amplifiers U4, U5, and U6 are grounded.

[0105] Resistors R7, R8, R9, multipliers A2, A3, A4, and operational amplifier U4 form the first inverter. Resistor R10, operational amplifier U5, and capacitor C2 form the inverting integrator. Resistors R11 and R12, and operational amplifier U6 form the second inverter.

[0106] Multiplier A2 receives signals -x and z at its input. Multiplier A2 performs a multiplication operation on -x and z to obtain the result -x*z. Multiplier A4 receives signals y and y' at its input. Multiplier A4 performs a multiplication operation on y and y' to obtain the result y'. 2 The input of multiplier A3 receives the signal y and the result y. 2 Multiplier A4 performs operations on the signal y and the result y. 2 Perform multiplication to obtain the result y. 3 The calculation result -x*z is sent to the negative input terminal of operational amplifier U4 via resistor R7. The calculation result y 3 The input is passed through resistor R8 to the negative input terminal of operational amplifier U4. Resistor R9 is electrically connected to the negative input and output terminals of operational amplifier U4, respectively. The operation results -x*z and y are processed through resistor R9 and operational amplifier U4. 3Perform inverse addition and output the sum c*x*zb*y 3 .

[0107] The sum of the outputs of operational amplifier U4 is c*x*zb*y 3 The signal is transmitted to the negative input terminal of operational amplifier U5 via resistor R10. The two ends of capacitor C2 are electrically connected to the negative input and output terminals of operational amplifier U5, respectively. The sum of the values ​​of capacitor C2 and operational amplifier U5 is c*x*zb*y. 3 Perform inverse integration and output signal -y.

[0108] The signal -y is sent to the negative input terminal of operational amplifier U6 via resistor R11. Resistor R12 is electrically connected to both the negative input and output terminals of operational amplifier U6. The signal -y is inverted via resistor R12 and operational amplifier U6, resulting in the output signal y.

[0109] like Figure 5D As shown, the third processing channel is used to perform chaotic mapping on the signal z.

[0110] The third operational channel includes resistors R13, R14, R15, R16, R17, R18, and R19, multiplier A5, operational amplifiers U7, U8, and U9, and capacitor C3.

[0111] For example, R13 = 2KΩ, R14 = 1KΩ, R15 = 16KΩ, R16 = 8KΩ, R17 = 55KΩ, R18 = R19 = 10KΩ, C3 = 33nF, and the output gain of multiplier A5 is 1.

[0112] Resistors R13, R14, R15, R16, R17, R18, and R19 are linear resistors. Operational amplifiers U7, U8, and U9 are analog operational amplifiers.

[0113] Operational amplifiers U7, U8, and U9 are connected to a first power supply VCC and a second power supply VEE, with the voltage of the second power supply VEE being lower than that of the first power supply VCC. All three operational amplifiers operate under the drive of the first power supply VCC and the second power supply VEE. The positive input terminals of operational amplifiers U7, U8, and U9 are grounded.

[0114] Resistors R13, R14, R15, R16, multiplier A5, and operational amplifier U7 form the first inverter. Resistor R17, operational amplifier U8, and capacitor C3 form the inverting integrator. Resistors R18 and R19, and operational amplifier U9 form the second inverter.

[0115] Multiplier A5 receives signals x and y at its input. Multiplier A5 performs a multiplication operation on signals x and y, obtaining the result x*y. The result x*y is then sent to the negative input of operational amplifier U7 via resistor R13. Signal -z is input to the negative input of operational amplifier U7 via resistor R14, and signal -w is input to the negative input of operational amplifier U7 via resistor R15. Resistor R16 is electrically connected to the negative input and output of operational amplifier U7, respectively. Through resistor R16 and operational amplifier U7, the result x*y, signal -w, and signal -z are added in opposite phases, outputting the sum -b*x*y + d*z + e*w.

[0116] The summation result -b*x*y+d*z+e*w output by operational amplifier U7 is sent to the negative input terminal of operational amplifier U8 via resistor R17. The two ends of capacitor C3 are electrically connected to the negative input terminal and the output terminal of operational amplifier U8, respectively. Through capacitor C3 and operational amplifier U8, the summation result -b*x*y+d*z+e*w is integrated in reverse phase, outputting the signal -z.

[0117] The signal -z is sent to the negative input terminal of operational amplifier U9 via resistor R18. Resistor R19 is electrically connected to both the negative input and output terminals of operational amplifier U9. The signal -z is inverted via resistor R19 and operational amplifier U9, resulting in the output signal z.

[0118] like Figure 5E As shown, the fourth operation channel is used to perform chaotic mapping on the signal w.

[0119] The fourth operational channel includes resistors R20, R21, R22, R23, R24, and R25, multiplier A6, operational amplifiers U10, U11, and U2, and capacitor C4.

[0120] For example, R20 = 20KΩ, R21 = 1KΩ, R22 = 4KΩ, R23 = 55KΩ, R24 = R25 = 10KΩ, C4 = 33nF, and the output gain of multiplier A6 is 1.

[0121] Resistors R20, R21, R22, R23, R24, and R25 are linear resistors. Operational amplifiers U10, U11, and U12 are analog operational amplifiers.

[0122] Operational amplifiers U10, U11, and U12 are connected to a first power supply VCC and a second power supply VEE, with the voltage of the second power supply VEE being lower than that of the first power supply VCC. All three operational amplifiers operate under the drive of the first power supply VCC and the second power supply VEE. The positive input terminals of operational amplifiers U10, U11, and U12 are grounded.

[0123] Resistors R20, R21, R22, multiplier A6, and operational amplifier U10 form the first inverter. Resistor R23, operational amplifier U11, and capacitor C4 form the inverting integrator. Resistors R24 and R25, and operational amplifier U12 form the second inverter.

[0124] The input of multiplier A6 receives signals y and -w. Multiplier A6 performs a multiplication operation on signals y and -w, and sends the result -y*w to the negative input of operational amplifier U10 via resistor R20. Signal z is input to the negative input of operational amplifier U10 via resistor R21. The two ends of resistor R22 are electrically connected to the negative input and output of operational amplifier U10, respectively. Through resistor R22 and operational amplifier U10, the result -y*w and signal z are added in opposite phase, and the sum is output as f*y*wb*z.

[0125] The summation result f*y*wb*z output from operational amplifier U10 is sent to the negative input terminal of operational amplifier U11 via resistor R23. The two ends of capacitor C4 are electrically connected to the negative input terminal and the output terminal of operational amplifier U11, respectively. Through capacitor C1 and operational amplifier U11, the summation result f*y*wb*z is integrated in reverse phase, outputting the signal -w.

[0126] The signal -w is sent to the negative input terminal of operational amplifier U12 via resistor R24. Resistor R25 is electrically connected to the negative input and output terminals of operational amplifier U12, respectively. The signal -w is inverted through resistor R25 and operational amplifier U12, resulting in the output signal w.

[0127] In the signal mapping circuit 400, signals x and -x output from the first operational channel are both sent to the signal selection unit; signals y and -y output from the second operational channel are both sent to the signal selection unit; signals z and -z output from the third operational channel are both sent to the signal selection unit; and signals w and -w output from the fourth operational channel are both sent to the signal selection unit. The signal selection unit selects from signals x, -x, y, -y, z, -z, w, and -w to obtain multiple sets of signals.

[0128] In this embodiment of the disclosure, signal x and signal y form a four-winged chaotic effect, signal x and signal z form a four-winged chaotic effect, signal z and signal y form a four-winged chaotic effect, and signal x and signal w form a four-winged chaotic effect.

[0129] Figure 6 A schematic diagram of a pseudo-random number generator according to another embodiment of the present disclosure is shown.

[0130] like Figure 6 As shown, the pseudo-random number generator 600 includes a signal mapping circuit 610, a signal sampling circuit 620, and a signal processing circuit 630.

[0131] In this embodiment, the signal mapping circuit 610, signal sampling circuit 620, and signal processing circuit 630 are similar to the signal mapping circuit 110, signal sampling circuit 120, and signal processing circuit 130 in the preceding embodiments. For the sake of brevity, this disclosure will not repeat them.

[0132] The signal sampling circuit 620 includes a front-end conditioning unit 621 and a sampling unit 622. The signal processing circuit 630 includes a microcontroller unit 631 and a testing unit 632.

[0133] For example, the front-end conditioning unit 621 is used to condition the waveforms and amplitudes of multiple chaotic signals respectively, thereby improving the quality of the chaotic signals. For example, the front-end conditioning unit 621 amplifies the chaotic signals to facilitate sampling by the sampling unit 622. For example, the front-end conditioning unit 621 filters the chaotic signals to remove impurity signals from the chaotic signals.

[0134] The sampling unit 622 converts the conditioned chaotic signals from analog signals to digital signals, and samples the digital signals at a preset frequency to obtain multiple state variables corresponding to each chaotic signal.

[0135] For example, multiple state variables of multiple chaotic signals are {x} i y i , z i w i}. i = 1, 2, ..., I. I is the number of samples.

[0136] Sampling unit 622 will sample multiple state variables {x} i y i , z i w i The data is sent to the microcontroller unit 631 via the data bus. The sampling unit 622 samples the digital signal 3f+D times at a preset frequency to obtain 3f+D state variables corresponding to each chaotic signal among the multiple chaotic signals. f is the preset frequency, and D is the number of random numbers in each set of random numbers.

[0137] To ensure the randomness of the obtained random number sequence, the microcontroller unit 631 discards the first 3f samples of 3f+D state variables, thus guaranteeing that the sampled data comes from signals that have already fully entered a chaotic state. For example, at f = 100 times / min, the microcontroller unit 631 acquires D+300 data points and discards the first 300 samples, obtaining multiple state variables {x}. i y i , z i w i}, i = 1, 2, ..., D, where D is the preset number of sampled data, and D sampled data can generate D random numbers.

[0138] The microcontroller unit 631 handles multiple state variables {x} i y i , z i w i Preprocessing is performed. The microcontroller unit 631 uses a rounding model to perform rounding operations on the multiple state variables corresponding to each chaotic signal, thereby obtaining multiple random number sequences corresponding to the multiple chaotic signals. For example, the microcontroller unit 631, in conjunction with the bit width of the analog-to-digital converter in the sampling unit 622, performs rounding processing on the state variables according to the following formula (3):

[0139]

[0140] mod(a, b) represents the operation of taking the remainder of a and b. This indicates that 'a' is rounded down to the nearest integer in the direction of negative infinity. |a| indicates that 'a' is taken as the absolute value.

[0141] After the test unit 632 converts the random number sequence obtained through rounding into a bitstream, it performs a randomness test on the bitstream. If the randomness test results of multiple random number sequences meet the randomness requirements, the microcontroller unit 631 outputs multiple random number sequences, forming multiple random number arrays. If the randomness test results of multiple random number sequences meet the randomness requirements, the microcontroller unit 631 can also store the multiple random number sequences in memory for later retrieval of random numbers from memory.

[0142] For example, multiple random number arrays that pass the randomness test can include random number arrays X{x0, x1, x2, ..., x... D}, Random number array Y{y0, y1, y2, ..., y D}, Random number array Z{z0, z1, z2, ..., z D} and a random number array W{w0, w1, w2, ..., w D}

[0143] Based on practical application requirements, the random number array X{x0, x1, x2, ..., x...} is defined as follows: D}, Random number array Y{y0, y1, y2, ..., y D}, Random number array Z{z0, z1, z2, ..., z D} and a random number array W{w0, w1, w2, ..., w D The data can be saved to the stack memory space of the microcontroller unit 631 or other storage media such as static random access memory (SRAM) for encryption or other system selection that requires random numbers.

[0144] Figure 7 A flowchart of a pseudo-random number generation method according to an embodiment of the present disclosure is shown.

[0145] like Figure 7 As shown, the pseudo-random number generation method of this embodiment can be applied to a pseudo-random number generator according to embodiments of this disclosure. The pseudo-random number generation method of this embodiment includes operations S710 to S730.

[0146] When operating the S710, the signal mapping circuit uses a chaotic model to map multiple input signals to obtain multiple chaotic signals with four-winged chaotic states.

[0147] In this embodiment of the disclosure, operation S710 corresponds to the operation performed by the signal mapping circuit 610 described above, and will not be described again here for the sake of simplicity.

[0148] When operating the S720, the signal sampling circuit samples multiple chaotic signals to obtain multiple state variables corresponding to each of the multiple chaotic signals.

[0149] In this embodiment of the disclosure, operation S720 corresponds to the operation performed by the signal sampling circuit 620 described above, and will not be described again here for the sake of simplicity.

[0150] During operation of S730, the signal processing circuit performs floor operations on multiple state variables corresponding to each chaotic signal, obtaining multiple sets of random numbers corresponding to each chaotic signal. Each set of random numbers contains multiple random numbers.

[0151] In this embodiment of the disclosure, operation S730 corresponds to the operation performed by the above-described signal processing circuit 630, and will not be described again here for the sake of simplicity.

[0152] It should be noted that the technical solutions of the embodiments of this disclosure are shown by way of example only in the above description, and do not mean that the embodiments of this disclosure are limited to the above steps and structures. Where possible, the steps and structures can be adjusted and omitted as needed. Therefore, some steps and units are not essential elements for implementing the overall inventive concept of the embodiments of this disclosure.

[0153] The present disclosure has now been described in conjunction with preferred embodiments. It should be understood that those skilled in the art can make various other changes, substitutions, and additions without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of the embodiments of the present disclosure is not limited to the specific embodiments described above, but should be defined by the appended claims.

Claims

1. A pseudo-random number generator, comprising: A signal mapping circuit is used to map multiple input signals using a chaotic model to obtain multiple chaotic signals with a four-winged chaotic state. A signal sampling circuit, electrically connected to the signal mapping circuit, is used to sample the plurality of chaotic signals to obtain a plurality of state variables corresponding to each of the plurality of chaotic signals; and A signal processing circuit, electrically connected to the signal sampling circuit, is used to perform floor operations on multiple state variables corresponding to each chaotic signal to obtain multiple sets of random numbers corresponding to the multiple chaotic signals, wherein each set of random numbers includes multiple random numbers. The signal mapping circuit includes: A signal selection unit is configured to select from the plurality of input signals based on the chaotic model to obtain multiple sets of signals, each set of signals including at least one of the plurality of input signals; and Multiple processing channels are electrically connected to the signal selection unit and are used to perform mapping operations on multiple sets of signals based on the chaotic model to obtain multiple chaotic signals. The signal selection unit is further configured to select multiple chaotic signals based on the chaotic model when the number of mapping operations of the multiple computing channels is less than a preset number, to obtain multiple sets of signals, and to send the multiple sets of signals to the multiple computing channels respectively, wherein each set of signals includes at least one chaotic signal among multiple chaotic signals. Each of the plurality of computation channels includes: The first inverter is used to perform an inverted summation operation on one of the multiple sets of signals to obtain a first operation result; An inverting integrator, electrically connected to the first inverter, is used to perform an inverting integration operation on the first operation to obtain a second operation result; and The second inverter, electrically connected to the inverting integrator, is used to perform an inverting proportional operation on the second calculation result to obtain a chaotic signal.

2. The pseudo-random number generator according to claim 1, wherein, The signal mapping circuit also includes: A signal generation unit, electrically connected to the plurality of computing channels, is used to generate a plurality of initial signals; The multiple processing channels are also used to perform mapping operations on multiple sets of signals based on the chaotic model to obtain multiple chaotic signals. Each set of signals includes at least one initial signal among the multiple initial signals.

3. The pseudo-random number generator according to claim 2, wherein, The signal generation unit includes: Multiple DC power supplies are used to generate multiple initial signals based on multiple initial voltage values, respectively.

4. The pseudo-random number generator according to any one of claims 1 to 3, wherein, The chaotic model includes a four-dimensional chaotic model. The multiple input signals include a first input signal, a second input signal, a third input signal, and a fourth input signal. The multiple chaotic signals include a first chaotic signal, a second chaotic signal, a third chaotic signal, and a fourth chaotic signal. The four-dimensional chaotic model includes: The mapping relationship between the first chaotic signal and the first input signal, the second input signal and the third input signal; The mapping relationship between the second chaotic signal and the first input signal, the second input signal and the third input signal; The mapping relationship between the third chaotic signal and the first input signal, the second input signal, the third input signal, and the fourth input signal; and The mapping relationship between the fourth chaotic signal and the second input signal, the third input signal, and the fourth input signal.

5. The pseudo-random number generator according to claim 2, wherein, The multiple chaotic signals output after n mapping operations are related to the multiple chaotic signals output after n-1 mapping operations, where n = 1, 2, ..., N, where N is a positive integer and N is a preset number of operations; when n = 1, the multiple chaotic signals output after n-1 mapping operations are the multiple initial signals.

6. The pseudo-random number generator according to claim 1, wherein, The signal sampling circuit includes: A front-end conditioning unit is used to condition the waveforms and amplitudes of the plurality of chaotic signals respectively; and The sampling unit is used to convert the multiple conditioned chaotic signals from analog signals into digital signals, and sample the digital signals at a preset frequency to obtain multiple state variables corresponding to each of the multiple chaotic signals.

7. The pseudo-random number generator according to claim 6, wherein, The sampling unit is further configured to sample the digital signal 3f+D times at the preset frequency to obtain 3f+D state variables corresponding to each of the plurality of chaotic signals, where f is the preset frequency and D is the number of random numbers in each set of random numbers.

8. The pseudo-random number generator according to claim 1, wherein, The signal processing circuit includes a microcontroller unit, which is used to perform floor operations on multiple state variables corresponding to each chaotic signal using a floor model to obtain multiple random number sequences corresponding to the multiple chaotic signals.

9. The pseudo-random number generator according to claim 8, wherein, The signal processing circuit further includes a test unit, which is electrically connected to the microcontroller unit, for converting the random number sequence into a bit stream and performing a randomness test on the bit stream; Wherein, if the randomness test results are all determined to meet the randomness requirements, the microcontroller unit is also used to output the plurality of random number sequences.

10. A method for generating pseudo-random numbers, comprising: The signal mapping circuit uses a chaotic model to map multiple input signals to obtain multiple chaotic signals with four-winged chaotic states; The signal sampling circuit samples the plurality of chaotic signals to obtain a plurality of state variables corresponding to each of the plurality of chaotic signals; as well as The signal processing circuit performs a rounding operation on multiple state variables corresponding to each chaotic signal to obtain multiple sets of random numbers corresponding to the multiple chaotic signals respectively. Each set of random numbers includes multiple random numbers. The signal mapping circuit includes: A signal selection unit is configured to select from the plurality of input signals based on the chaotic model to obtain multiple sets of signals, each set of signals including at least one of the plurality of input signals; and Multiple processing channels are electrically connected to the signal selection unit and are used to perform mapping operations on multiple sets of signals based on the chaotic model to obtain multiple chaotic signals. The signal selection unit is further configured to select multiple chaotic signals based on the chaotic model when the number of mapping operations of the multiple computing channels is less than a preset number, to obtain multiple sets of signals, and to send the multiple sets of signals to the multiple computing channels respectively, wherein each set of signals includes at least one chaotic signal among multiple chaotic signals. Each of the plurality of computation channels includes: The first inverter is used to perform an inverted summation operation on one of the multiple sets of signals to obtain a first operation result; An inverting integrator, electrically connected to the first inverter, is used to perform an inverting integration operation on the first operation to obtain a second operation result; and The second inverter, electrically connected to the inverting integrator, is used to perform an inverting proportional operation on the second calculation result to obtain a chaotic signal.

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