Timing circuit critical node positioning method and device based on time window graph model

Abstract

The application relates to a time window graph model-based timing circuit critical node positioning method and equipment, which comprises the following steps: 1) analyzing a circuit netlist, initializing a criticality calculation matrix according to a circuit node type, wherein the criticality calculation matrix comprises a single fault calculation matrix and a multiple fault calculation matrix; 2) based on a time window graph model, aggregating circuit node states through circuit simulation simulation to obtain circuit node slices; 3) calculating the criticality of all nodes in the slices to a target node based on probability and the criticality calculation matrix; and 4) obtaining critical nodes of the timing circuit according to node criticality sorting. Compared with the prior art, the application has the advantages of small time and space overhead, and the result obtained based on the method has greater reliability improvement for reinforcement of the timing circuit.

Description

Technical Field

[0001] This invention belongs to the field of reliability calculation of integrated circuits, and relates to a method for locating critical nodes in a circuit, and more particularly to a method and device for locating critical nodes in a timing circuit based on a time window graph model. Background Technology

[0002] As integrated circuit feature sizes continue to shrink, power supply voltages decrease, and operating frequencies increase, manufacturing processes become increasingly complex. This inevitably leads to a decrease in circuit reliability tolerance; for example, further reductions in device size increase the probability of uncertain circuit failures. Therefore, conducting reliability assessments for integrated circuits is crucial for high-reliability circuit design. It helps in selecting or designing the most suitable structure to optimize the relationship between circuit area, power consumption, latency, and reliability requirements.

[0003] To identify critical circuit units in a circuit structure, academia and industry have proposed various localization strategies. Currently, most methods focus on locating critical nodes in combinational circuits. Sequential circuits, due to their often larger scale and the presence of flip-flops leading to the continuous accumulation and propagation of faults, make evaluation even more difficult. Methods applicable to locating critical nodes in sequential circuits mainly include graph theory-based analysis methods and simulation-based analysis methods. There are methods based on graph neural networks to locate critical nodes in sequential circuits, such as using GraphSAGE networks to predict the impact of flip-flop nodes on the original output of the circuit to locate critical nodes. However, these methods do not consider the accumulation of faults in sequential circuits and are difficult to obtain effective training data. There are also methods based on Monte Carlo simulations of circuit behavior to identify critical circuit nodes. This method has high accuracy and is recognized by industry professionals, but it often has very high time overhead. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology, which is only applicable to small-scale combinational circuits and has high time overhead, and to provide a method and device for locating key nodes of timing circuits based on a time window diagram model with high positioning accuracy and fast calculation speed, which can be applied to the effective positioning of key units of large-scale and ultra-large-scale circuits.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A method for locating critical nodes in sequential circuits based on a time window graph model includes the following steps:

[0007] 1) Analyze the circuit netlist and initialize the critical calculation matrix according to the circuit node type. The critical calculation matrix includes a single fault calculation matrix and a multi-fault calculation matrix.

[0008] 2) Based on the time window graph model, the circuit node states are aggregated through circuit simulation to obtain circuit node slices;

[0009] 3) Calculate the criticality of all nodes in the slice to the target node based on the probability and the criticality calculation matrix;

[0010] 4) Based on the criticality of the nodes, obtain the critical nodes of the sequential circuit.

[0011] Furthermore, the analytical circuit netlist specifically includes:

[0012] Extract the basic gate information of the circuit, construct the circuit integrity linked list, and record the positions of the original input terminal, original output terminal, flip-flop, and circuit node input terminal in the integrity linked list. The target node is the union of the original output terminal node and the flip-flop.

[0013] Furthermore, the key computation matrix is ​​constructed using the truth table method.

[0014] Furthermore, the single-fault calculation matrix and the multi-fault calculation matrix are specifically represented as follows:

[0015]

[0016]

[0017] Wherein, equation (1) is the single-fault calculation matrix. The expression, equation (2), is the multi-single fault calculation matrix. The expression, The value of the node representing the number of TP type input terminals iptn is obtained by using the truth table method under the input signal combination ivn and the fault condition isv. In equation (1), ivn∈[0,2] iptn -1],isv∈[1,2 iptn-1 In equation (2), ivn∈[0,2] iptn -1],isv∈[0,2 iptn -1].

[0018] Furthermore, the circuit node states are aggregated by statistically analyzing the frequency of occurrence of the input vectors of each node.

[0019] Furthermore, in step 2), when performing circuit simulation, the simulation is stopped when the number of simulations reaches the set window size, and circuit node slices are obtained.

[0020] Furthermore, when calculating the criticality of all nodes in a slice to the target node, the probability of the influence of each node on the original output of each slice circuit is calculated based on the aggregated node information.

[0021] Furthermore, before executing step 4), steps 2) and 3) are executed multiple times to obtain the node criticality under different slices.

[0022] Furthermore, when considering the criticality of a computing node to a target node, a flip-flop is used as a medium to calculate the impact of faults in past clock signals on the original output of the circuit in the current clock signal by analyzing the influence patterns of the computing node on the flip-flop and the influence patterns of the flip-flop on the original output of the circuit.

[0023] Furthermore, the criticality of each node in the sequential circuit slice is calculated using the following formula:

[0024] Key calculation formulas for node input:

[0025]

[0026] Where cri represents the criticality of the node input, and ipv represents the probability distribution vector of the node's input combinations. The criticality of the node input is calculated by combining the node's input combination probability distribution with the single fault calculation matrix.

[0027] Formula for calculating node criticality transmission:

[0028] ipt j .pos(tn)=pos(tn)×cri j

[0029] Among them, ipt j Let pos(n) represent the node corresponding to the j-th input terminal, and cri represent the criticality of the node to the target node n. j This represents the criticality of the j-th input terminal of a node. The formula calculates the criticality of the corresponding node at the input terminal by combining the criticality of the node and the criticality of the input terminal.

[0030] Formula for calculating the probability vector of combined error signals received by a node:

[0031]

[0032] Where vpcif represents the probability vector of the combination of erroneous signals received by the node, and pof represents the probability that the node's output will change under a specific condition;

[0033] Formula for calculating the probability of a node output change:

[0034]

[0035] The present invention also provides an electronic device, including one or more processors, a memory, and one or more programs stored in the memory, said one or more programs including instructions for executing the timing circuit critical node localization method based on the time window graph model as described above.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. This invention, based on a time window graph model aggregating node states, combines a criticality calculation matrix and probabilistic calculation methods to achieve iterative calculation for circuit node criticality assessment. This enables effective quantification of the criticality level of circuit units, reducing computational complexity while maintaining assessment accuracy. It significantly reduces the computational overhead for locating critical nodes in sequential circuits, thus expanding the applicability of this method and facilitating its application in calculating the criticality of sequential circuit nodes. This invention not only boasts high positioning accuracy but also fast computation speed, making it suitable for the effective location of critical units in large-scale and ultra-large-scale circuits.

[0038] 2. This invention calculates the probability that nodes in past slices will affect the target node in the current slice by using the probability of different nodes affecting the trigger and the probability of the trigger affecting the target node. This allows the method to consider the accumulation of faults in sequential circuits at a lower cost during the calculation, which makes it difficult to extend the application of the existing critical node location method to sequential circuits and to balance the shortcomings of time overhead and accuracy.

[0039] 3. This invention locates critical nodes in timing circuits by considering the accumulation of timing circuit faults across different timing frames. Experiments on 50 ISCAS-89 and 6 ITC-99 reference circuits have verified that this method maintains high accuracy while having a much lower time and space overhead than the Monte Carlo method.

[0040] 4. The positioning results obtained by this invention help circuit designers to grasp the criticality of each node in the circuit of the designed product in a timely manner, so as to make reasonable selections and decisions. Attached Figure Description

[0041] Figure 1 This is a flowchart of a method for locating critical nodes in sequential circuits based on a time window diagram model;

[0042] Figure 2 This is an example of the aggregation of node states within a time window;

[0043] Figure 3 This is an example of a key computational matrix application;

[0044] Figure 4 These are the experimental results of this method on 50 ISCAS-89 reference circuits;

[0045] Figure 5 These are the experimental results of this method on six ITC-99 reference circuits. Detailed Implementation

[0046] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0047] Embodiments of the present invention provide a method for locating critical nodes in timing circuits based on a time window graph model, such as... Figure 1 As shown, it includes the following steps:

[0048] Step 1: Netlist resolution and initialization of related variables

[0049] 1.1) Read the netlist, extract the basic gate information of the circuit, construct the circuit integrity linked list LC, identify all the original input terminals PI, original output terminals PO, flip-flops FF, and the position ipt of the input terminals of the circuit nodes in LC, and initialize the node number variable m = length(LC), window size variable w, target node list variable tns (the union of PO and FF), loop variable simi = 0, simulation number simn, and critical calculation allowable error e; where the integrity linked list LC means that the input terminal information of any node in the linked list can be extracted from the output terminal information of the preceding node, and length represents the number of elements to be taken from the list;

[0050] 1.2) Based on the basic gate type tp and the number of input terminals iptn, and by utilizing the arrangement characteristics of the iptn input signals, a single-fault calculation matrix for the basic gate of type tp and number of input terminals iptn is constructed using the truth table method. With multi-fault calculation matrix Specifically as follows:

[0051]

[0052]

[0053] in The basic gate representing the number of TP-type inputs, iptn, is determined using a truth table method under the conditions of input signal combination ivn and fault condition isv. ivn∈[0,2] iptn -1], isv=2 i , i∈[0,iptn-1]; ivn∈[0,2 iptn -1],isv∈[0,2 iptn-1]. Furthermore, the vector forms of ivn and isv are as follows:

[0054] ivn = [s0…s iptn-1 ]

[0055] isv = [is0…is iptn-1 ]

[0056] Among them, s i s represents the input signal at the i-th input terminal of the basic gate. i = "0" or "1"; is i Indicates whether the i-th input terminal received an error signal, is i = "0" or "1", where "0" indicates that the i-th input terminal received a correct signal, and "1" indicates that the i-th input terminal received an incorrect signal. Decimal notation is used to represent vectors ivn and isv when constructing the critical computation matrix.

[0057] Step 2: Locate the critical nodes of the timing circuit

[0058] 2.1) For each node in LC, initialize node criticality CGR=0 and node failure mode list fmdl to be empty. Here, node criticality refers to the impact of the node on the overall reliability of the circuit.

[0059] 2.2) Jump to step 3 to calculate and obtain the slice slc simi All nodes in LC for slice slc simi The criticality of the target node's TNS;

[0060] 2.3) For each node ni in LC and each node PO in POs, determine whether ni.pos(PO) is not equal to 0. If so, update ni.CGR = ni.CGR + ni.pos(PO), where ni.CGR represents the criticality of node ni and ni.pos(PO) represents the criticality of ni to PO. If ni does not affect PO, then ni.pos(PO) is equal to 0.

[0061] 2.4) For each node failure mode in the fmdl, first extract the corresponding nodes ni and ft, and initialize the output change probability pof of all nodes in LC to 0. Then, for each trigger FF and its corresponding pos in ft, set FF.pof = pos, and jump to step 5 to calculate the previous slice node pair slc. simi Calculate the impact probability of the target node in the slice, and update ni.CGR = ni.CGR + ni.pos(PO);

[0062] 2.5) For each node ni in LC and each node FF in FFs, check if ni.pos(FF) is not equal to 0. If so, update ft(FF) = ni.pos(FF); combine<ni,ft> Add it to the fmdl, where ft stores the trigger nodes that can be affected by ni and their criticality, such as ft(FF) indicating that ni is critical to trigger node FF;

[0063] 2.6) Execute simi = simi + 1, and check if simi equals simn. If yes, jump to 2.7); otherwise, jump to 2.2).

[0064] 2.7) Critical nodes are those with larger CGRs. Nodes are sorted according to their CGR in the LC, and the critical nodes are returned.

[0065] Step 3: Circuit node state simulation and circuit node state aggregation

[0066] 3.1) For each node n in LC, initialize the input combination probability distribution vector n.ipv to 1×2 iptn An empty vector;

[0067] 3.2) For each original input node in LC, randomly generate an input vector and initialize the loop variables i = 0 and j = 0;

[0068] 3.3) Extract the i-th node ni in LC, determine whether ni is the original input terminal node of the circuit. If yes, go to 3.4); otherwise, calculate and update the output signal of ni, extract the output signal of the input terminal node of ni, construct the input signal combination ni.ivn, calculate the decimal representation divn of ni.ivn, and execute ni.ipv(divn) = ni.ipv(divn) + 1 / w, where ni.ipv(divn) represents the frequency of the input signal combination divn of node ni.

[0069] 3.4) Determine if the end of LC has been reached. If so, go to 3.5); otherwise, execute i = i + 1 and go to 3.3.

[0070] 3.5) Execute j = j + 1, and determine whether j equals w. If yes, go to step 4; otherwise, go to step 2.2.

[0071] Step 4: Calculate the criticality of all nodes in the slice to the target node.

[0072] 4.1) For each node n in LC, initialize the probability of n's influence on nodes in tns to be empty, initialize the loop variable i = m, and n.pos(nn) is used to represent the probability that the failure of node n will affect node nn, that is, the criticality of node n to node nn.

[0073] 4.2) Extract the i-th node ni from LC, determine whether ni belongs to tns, if so, execute ni.pos(ni) = 1 and jump to 4.3); otherwise, jump to 4.3);

[0074] 4.3) Calculate the critical transfer coefficient cri of each input terminal of ni according to the following formula, extract the input terminal node ipt of ni, and initialize the loop variable j = 0;

[0075]

[0076] 4.4) Extract the j-th input node ipt of ni j Initialize the loop variable k = 0;

[0077] 4.5) Extract the k-th target node tn, and check if n.pos(tn) is less than e. If yes, jump to 4.6); otherwise, check ipt. j Check if .pos(tn) equals 0. If so, execute ipt. j .pos(tn)=n.pos(tn)×n.cri j If yes, jump to 4.6); otherwise, jump to 4.7.

[0078] 4.6) Execute k = k + 1, and check if k equals length(tns). If yes, jump to 4.8); otherwise, jump to 4.5.

[0079] 4.7) Initialize ipt j Set .pof=1 and proceed to step 5 to update ipt. j .pos(tn) = tn.pof, jump to 4.6);

[0080] 4.8) Execute j = j + 1, and check if j is less than ni.iptn. If yes, jump to 4.4); otherwise, execute i = i - 1, and check if i equals -1. If yes, jump to 4.9); otherwise, jump to 4.2.

[0081] 4.9) Step 4 ends, return the result.

[0082] Step 5: Calculate the probability of the target node's TNS output changing based on the probability of the node's output changing (pof).

[0083] 5.1) Initialize the loop variable ii = 0;

[0084] 5.2) Extract the i-th node n from LC ii Determine n ii If it is the original input node, execute ii = ii + 1 and jump to 5.2); otherwise, initialize the loop variable jj = 0 and the node receives the error signal combination probability vector vpcif = 1.

[0085] 5.3) Extract n ii The jjth input node ipt jj Determine ipt jj Check if pof is less than e. If so, jump to 5.4; otherwise, calculate vpcif according to the following formula. Execute jj = jj + 1, and determine if jj equals n. ii If .iptn is true, then calculate and update n according to the following formula. ii If the value is .pof, then jump to 5.4); otherwise, jump to 5.3.

[0086]

[0087]

[0088] 5.4) Execute ii = ii + 1, and check if ii equals m. If yes, jump to 5.5); otherwise, jump to 5.2).

[0089] 5.5) Step 5 ends, return the result.

[0090] The above method aggregates node states through a time window graph model and calculates the criticality of nodes in different slices using a probability-based calculation method. This allows the method to maintain accuracy while still having a fast calculation speed. At the same time, considering the accumulation of faults in sequential circuits, it locates critical nodes in sequential circuits, thereby improving reliability.

[0091] If the above methods are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0092] This embodiment verifies the accuracy, time overhead, memory overhead, and result stability of the proposed method by comparing experimental results on 50 ISCAS-89 reference circuits with results obtained by the Monte Carlo method; and compares experimental results on 6 ITC-99 reference circuits with results obtained by the random method to illustrate the effectiveness and time overhead of the proposed method on large-scale sequential circuits.

[0093] The accuracy (acc) of the results is measured using vector distance, as shown in the following formula.

[0094]

[0095] rp i rpmc represents the sorting position of the i-th gate node in LC in the result of this method. i This represents the sorting position of the i-th gate node in LC within the Monte Carlo method results. Ng-1 represents the maximum difference between the nodes of this method and the Monte Carlo method, used to ensure the calculation result is between 0 and 1. Time overhead (tr) and memory overhead (mr) are represented by the ratio of the time and space overhead required by this method to that required by the Monte Carlo method, respectively. Result stability (stb) is calculated according to the following formula:

[0096]

[0097]

[0098] rp ij This represents the sorting position of the i-th gate node in LC within the results of this method in the j-th iteration. i This represents the average ranking position of the i-th gate node in LC across all j results using this method, where nres is the number of results involved in the calculation, 4 / (Ng-1). 2It's RP ij The maximum variance is used to ensure that the calculation result is between 0 and 1. Since the scale of the six ITC-99 reference circuits is large, the Monte Carlo method cannot effectively obtain results. Therefore, this method is compared with the stochastic method, and its effectiveness is demonstrated by implementing a selective hardening strategy.

[0099] Figure 4 The figure shows the performance of this method on 50 ISCAS-89 benchmark circuits. The average performance is obtained by averaging the performance across the 50 circuits. The figure also shows the performance of 20 circuits. Experimental results demonstrate that this method has higher accuracy and stability compared to the Monte Carlo method. The time and memory overhead of this method are significantly lower than those of the Monte Carlo method. Furthermore, as the circuit size increases, the growth rate of the time and space overhead of this method is slower than that of the Monte Carlo method, making it suitable for larger-scale circuits.

[0100] Figure 5 The results show a comparison between the experimental results of this method and the results obtained by the random method on six ITC-99 reference circuits. (5a) shows the relationship between the time overhead of this method and the random method and the number of nodes of each type in the circuit, where nff and npriipt represent the number of circuit flip-flops and original input terminals, respectively. The results show that the time overhead of this method is greatly affected by nff and Ng. In (5b), Scheme 1 and Scheme 2 harden the first 0.5% and 1% of nodes, respectively. The failure probability of the hardened nodes is set to 0.5%, and the failure probability of the remaining nodes is 1%. The results show that hardening the critical nodes calculated by this method can achieve better results. In summary, compared with the random method, this method has lower time overhead and higher accuracy.

[0101] In summary, this method addresses the shortcomings of existing critical node localization methods, which often neglect fault accumulation, making them difficult to extend to sequential circuits and struggle to balance time overhead and accuracy. Based on a time window graph model, by aggregating node states from different time frames and employing corresponding probability-based calculation methods, this method significantly reduces the computational overhead of locating critical nodes in sequential circuits, sacrificing some accuracy. By calculating the probability of different nodes influencing triggers and the probability of triggers influencing target nodes, the method calculates the probability of nodes in past slices affecting target nodes in the current slice. This allows the method to consider the problem of fault accumulation in sequential circuits at a relatively low computational cost.

[0102] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A method for locating critical nodes of a sequential circuit based on a time window graph model, characterized in that, The method comprises the following steps: 1) parsing a circuit netlist, initializing a criticality calculation matrix according to a circuit node type, the criticality calculation matrix comprising a single fault calculation matrix and a multiple fault calculation matrix; 2) aggregating circuit node states through circuit simulation modeling based on a time window graph model, to obtain circuit node slices; 3) calculating the criticality of all nodes in the slices to a target node based on probability and the criticality calculation matrix; 4) obtaining critical nodes of the sequential circuit according to node criticality ranking; The criticality calculation matrix is constructed by a truth table method; The single fault calculation matrix and the multiple fault calculation matrix are specifically represented as: （1） （2） Wherein, formula (1) is a single fault calculation matrix expression, formula (2) is a multi single fault calculation matrix expression, Indicates tp The number of input terminals of type iptn The node in input signal combination ivn And fault condition isv Condition, the value obtained by using truth table method, in formula (1), , In formula (2), , ; When calculating the criticality of a node to a target node, the influence of the node on a flip-flop and the influence of the flip-flop on a circuit original output end are calculated through a trigger as a medium, to calculate the influence of a fault in a past clock signal on a circuit original output end in a current clock signal.

2. The method of claim 1, wherein, The parsing of the circuit netlist specifically comprises: extracting basic gate information of the circuit, constructing an integrity linked list of the circuit, recording the positions of original input ends, original output ends, flip-flops and input ends of circuit nodes in the integrity linked list, and the target node is a set of original output end nodes and flip-flops.

3. The method of claim 1, wherein, The circuit node states are aggregated by counting the appearance frequency of each node input vector.

4. The method of claim 1, wherein, In step 2), when the simulation times reach a set window size, the circuit simulation modeling is stopped to obtain circuit node slices.

5. The method of claim 1, wherein, When calculating the criticality of all nodes in the slices to the target node, the influence probability of the nodes on each slice circuit original output end is calculated based on the aggregated node information.

6. The method of claim 1, wherein, Before step 4) is performed, steps 2) and 3) are repeatedly executed for a set number of times to obtain node criticality under different slices.

7. An electronic device, comprising: The device comprises one or more processors, a memory and one or more programs stored in the memory, the one or more programs comprising instructions for performing the sequential circuit critical node positioning method based on the time window graph model according to any one of claims 1-6.

Images