Low power voltage conversion circuit and conversion method

Abstract

The application discloses a low-power-consumption voltage conversion circuit and a conversion method, and belongs to the technical field of integrated circuits. When a voltage judgment circuit detects that the voltage difference between a first capacitor and a second capacitor is greater than a first threshold value, and a current detection circuit detects that the output current of the power output end of an operational amplifier is less than or equal to a second threshold value, or when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detection circuit detects that the output current of the power output end of the operational amplifier is greater than the second threshold value, the reference and bias circuit is turned on through a delay circuit. When the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detection circuit detects that the output current of the power output end of the operational amplifier is less than or equal to the second threshold value, the reference and bias circuit is turned off through the delay circuit, so that the static power consumption is reduced. The static working current of the application is very small and reaches the nA level.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a low-power voltage conversion circuit and conversion method. Background Technology

[0002] To meet various practical needs, integrated circuits typically require built-in voltage regulator circuits that do not change with the external environment. However, in applications such as portable electronic products, the circuit needs to operate at low voltage, which requires voltage conversion circuits. A typical voltage conversion circuit is an LDO (Low Dropout Regulator).

[0003] A traditional LDO circuit structure is as follows Figure 1 As shown, it includes a reference circuit, operational amplifier, regulating transistor, and resistors. The reference circuit provides the operational amplifier with a stable reference voltage that does not change with temperature and power supply voltage. The output (OUT) voltage value can be arbitrarily adjusted by the voltage division ratio of the resistors.

[0004] Many products, especially portable electronic devices, have stringent power consumption requirements. Without compromising functionality, the lower the rated power consumption of the voltage conversion circuit, the better. However, the main power consumption of traditional voltage conversion circuits is concentrated in the reference circuit, operational amplifier, and resistors, resulting in relatively high operating power consumption. Summary of the Invention

[0005] This application provides a low-power voltage conversion circuit and method to address the problem of high power consumption in traditional voltage conversion circuits caused by the high power consumption of the reference circuit, operational amplifier, and resistors. The technical solution is as follows:

[0006] On one hand, a low-power voltage conversion circuit is provided, the low-power voltage conversion circuit including a reference and bias circuit, a low-power bias circuit, a first switch, a second switch, a first capacitor, a second capacitor, an operational amplifier, a voltage judgment circuit, a current detection circuit, and a delay circuit; the difference between the first capacitor and the second capacitor is greater than a predetermined threshold.

[0007] The reference voltage output end of the reference and bias circuit is connected with one end of the first switch and one end of the second switch respectively, and the bias voltage output end is connected with the bias voltage input end of the operational amplifier; the other end of the first switch is connected with one end of the first capacitor, the non-inverting input end of the operational amplifier and the slow voltage input end of the voltage judgment circuit respectively; the other end of the second switch is connected with one end of the second capacitor and the fast voltage input end of the voltage judgment circuit respectively; the other end of the first capacitor and the other end of the second capacitor are grounded; the output end of the low-power bias circuit is connected with the bias input end of the voltage judgment circuit and the low-power bias input end of the operational amplifier respectively; the power output end of the operational amplifier is connected with the inverting input end of the operational amplifier and serves as the output end of the low-power voltage conversion circuit, and the detection output end of the operational amplifier is connected with the input end of the current detection circuit; the output end of the voltage judgment circuit is connected with the voltage detection input end of the delay circuit; the output end of the current detection circuit is connected with the current detection input end of the delay circuit; the output end of the delay circuit is connected with the control input end of the reference and bias circuit;

[0008] When the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is greater than the first threshold value, and the current detection circuit detects that the output current of the power output end of the operational amplifier is less than or equal to the second threshold value, or when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detection circuit detects that the output current of the power output end of the operational amplifier is greater than the second threshold value, the reference and bias circuit is turned on through the delay circuit; when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detection circuit detects that the output current of the power output end of the operational amplifier is less than or equal to the second threshold value, the reference and bias circuit is turned off through the delay circuit to reduce the static power consumption.

[0009] In a possible implementation, the voltage judgment circuit comprises: first to second NMOS tubes, a first comparator;

[0010] The drain end of the first NMOS tube is connected with a power supply signal, the gate end of the first NMOS tube serves as the slow voltage input end of the voltage judgment circuit, the source end of the first NMOS tube is connected with the drain end of the second NMOS tube and the non-inverting input end of the first comparator respectively, the gate end of the second NMOS tube is connected with the bias input end of the first comparator and serves as the bias input end of the voltage judgment circuit, the source end of the second NMOS tube is grounded, the inverting input end of the first comparator serves as the fast voltage input end of the voltage judgment circuit, and the output end of the first comparator serves as the output end of the voltage judgment circuit.

[0011] In a possible implementation, the voltage judging circuit comprises: a first PMOS tube, a second PMOS tube, a third NMOS tube, and a second comparator.

[0012] The source end of the first PMOS tube is connected with the source end of the second PMOS tube and is connected to a power supply signal, the gate end and the drain end of the first PMOS tube, the gate end of the second PMOS tube, and the drain end of the third NMOS tube are connected, the gate end of the third NMOS tube is connected with the bias input end of the second comparator and serves as the bias input end of the voltage judging circuit, the drain end of the second PMOS tube and the drain end of the third PMOS tube are connected with the inverting input end of the second comparator, the gate end of the third PMOS tube serves as the slow voltage input end of the voltage judging circuit, the source end of the third NMOS tube and the source end of the third PMOS tube are grounded, the non-inverting input end of the second comparator serves as the fast voltage input end of the voltage judging circuit, and the output end of the second comparator serves as the output end of the voltage judging circuit.

[0013] In a possible implementation, the voltage judging circuit comprises: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third comparator, a fourth comparator, and a first OR gate.

[0014] The source end of the fourth PMOS tube, the source end of the fifth PMOS tube, and the drain end of the fourth NMOS tube are connected and connected to a power supply signal, the gate end and the drain end of the fourth PMOS tube, the gate end of the fifth PMOS tube, and the drain end of the sixth NMOS tube are connected, the gate end of the sixth NMOS tube is connected with the bias input end of the third comparator, the gate end of the fifth NMOS tube, and the bias input end of the fourth comparator and serves as the bias input end of the voltage judging circuit, the drain end of the fifth PMOS tube and the drain end of the sixth PMOS tube are connected with the inverting input end of the third comparator, the gate end of the sixth PMOS tube is connected with the gate end of the fourth NMOS tube and serves as the slow voltage input end of the voltage judging circuit, the source end of the fourth NMOS tube is connected with the drain end of the fifth NMOS tube and the non-inverting input end of the fourth comparator, the non-inverting input end of the third comparator is connected with the inverting input end of the fourth comparator and serves as the fast voltage input end of the voltage judging circuit, the source end of the fifth NMOS tube, the drain end of the sixth NMOS tube, and the source end of the sixth PMOS tube are grounded, the output end of the third comparator is connected with one input end of the first OR gate, the output end of the fourth comparator is connected with the other input end of the first OR gate, and the output end of the first OR gate serves as the output end of the voltage judging circuit.

[0015] In a possible implementation, the operational amplifier comprises: a differential amplifier, a seventh PMOS tube, a seventh NMOS tube, an eighth NMOS tube, and a ninth NMOS tube.

[0016] The inverting input terminal of the differential amplifier is the non-inverting input terminal of the operational amplifier, the non-inverting input terminal of the differential amplifier is the inverting input terminal of the operational amplifier, the drain terminal of the seventh PMOS transistor and the drain terminal of the ninth NMOS transistor are connected and serve as the power output terminal of the operational amplifier, the bias input terminal of the differential amplifier is connected with the drain terminal of the seventh NMOS transistor and the drain terminal of the eighth NMOS transistor, the gate terminal of the seventh NMOS transistor serves as the bias voltage input terminal of the operational amplifier, the gate terminal of the eighth NMOS transistor is connected with the gate terminal of the ninth NMOS transistor and serves as the low-power consumption bias input terminal of the operational amplifier, the source terminal of the seventh PMOS transistor is connected with a power supply signal, the output terminal of the differential amplifier is connected with the gate terminal of the seventh PMOS transistor and serves as the detection output terminal of the operational amplifier, and the source terminal of the seventh NMOS transistor, the source terminal of the eighth NMOS transistor and the source terminal of the ninth NMOS transistor are grounded.

[0017] In a possible implementation, the current detection circuit comprises an eighth PMOS transistor, a first resistor, a first inverter and a second inverter.

[0018] The source terminal of the eighth PMOS transistor is connected with a power supply signal, the gate terminal of the eighth PMOS transistor serves as the input terminal of the current detection circuit, the drain terminal of the eighth PMOS transistor and one end of the first resistor are connected with the input terminal of the first inverter, the other end of the first resistor is grounded, the output terminal of the first inverter is connected with the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the current detection circuit.

[0019] In a possible implementation, the delay circuit comprises a second OR gate, a ninth PMOS transistor, a tenth NMOS transistor, a second resistor, a third capacitor and a third inverter.

[0020] One input terminal of the second OR gate serves as the voltage detection input terminal of the delay circuit, the other input terminal of the second OR gate serves as the current detection input terminal of the delay circuit, the output terminal of the second OR gate, the gate terminal of the ninth PMOS transistor and the gate terminal of the tenth NMOS transistor are connected, the source terminal of the ninth PMOS transistor is connected with a power supply signal, the drain terminal of the ninth PMOS transistor is connected with one end of the second resistor, the other end of the second resistor, the drain terminal of the tenth NMOS transistor and one end of the third capacitor are connected with the input terminal of the third inverter, the source terminal of the tenth NMOS transistor and the other end of the third capacitor are grounded, and the output terminal of the third inverter serves as the output terminal of the delay circuit.

[0021] In a possible implementation, the delay circuit comprises: a third OR gate, a tenth PMOS transistor, an eleventh NMOS transistor, a third resistor, a fourth capacitor, a fourth inverter and a fifth inverter.

[0022] The gate terminal of the tenth PMOS transistor is connected with the gate terminal of the eleventh NMOS transistor and serves as a voltage detection input terminal of the delay circuit, the gate terminal of the eleventh PMOS transistor is connected with the gate terminal of the twelfth NMOS transistor and serves as a current detection input terminal of the delay circuit, the source terminal of the tenth PMOS transistor and the source terminal of the eleventh PMOS transistor are connected with a power supply signal, the drain terminal of the tenth PMOS transistor is connected with one end of the third resistor, the other end of the third resistor, the drain terminal of the eleventh NMOS transistor and one end of the fourth capacitor are connected with the input terminal of the fourth inverter, the output terminal of the fourth inverter is connected with one input terminal of the third OR gate, the source terminal of the tenth PMOS transistor and the source terminal of the eleventh PMOS transistor are connected with a power supply signal, the drain terminal of the eleventh PMOS transistor is connected with one end of the fourth resistor, the other end of the fourth resistor, the drain terminal of the twelfth NMOS transistor and one end of the fifth capacitor are connected with the input terminal of the fifth inverter, the output terminal of the fifth inverter is connected with the other input terminal of the third OR gate, the output terminal of the third OR gate serves as an output terminal of the delay circuit, and the source terminal of the eleventh NMOS transistor, the other end of the fourth capacitor, the source terminal of the twelfth NMOS transistor and the other end of the fifth capacitor are grounded.

[0023] In a possible implementation, when the voltage difference between the first capacitor and the second capacitor is greater than a first threshold value, the voltage judgment circuit outputs a high level; when the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, the voltage judgment circuit outputs a low level.

[0024] When the output current of the power output terminal of the operational amplifier is greater than a second threshold value, the current detection circuit outputs a high level; when the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold value, the current detection circuit outputs a low level.

[0025] In one aspect, a low-power-consumption voltage conversion method is provided, which is used in the low-power-consumption voltage conversion circuit as described above, and the method comprises:

[0026] When the voltage judging circuit detects that the voltage difference between the first capacitor and the second capacitor is greater than the first threshold value, and the current detecting circuit detects that the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold value, or when the voltage judging circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detecting circuit detects that the output current of the power output terminal of the operational amplifier is greater than the second threshold value, the reference and bias circuit is turned on by the delay circuit;

[0027] When the voltage judging circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detecting circuit detects that the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold value, the reference and bias circuit is turned off by the delay circuit to reduce the static power consumption.

[0028] The technical scheme provided by the embodiment of the present application has at least the following beneficial effects:

[0029] 1. When the voltage judging circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detecting circuit detects that the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold value, the reference and bias circuit is turned off, so that the static working current of the low-power-consumption voltage conversion circuit is very small, which can reach the nA level, and is suitable for the low-power-consumption application field.

[0030] 2. The process portability of the low-power-consumption voltage conversion circuit is very strong, and can adapt to different processes. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical scheme in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0032] Figure 1 is a structural schematic diagram of a traditional low-dropout linear regulator;

[0033] Figure 2 is a structural schematic diagram of a low-power-consumption voltage conversion circuit;

[0034] Figure 3a is a structural schematic diagram of a first implementation mode of a voltage judging circuit;

[0035] Figure 3b is a working principle waveform diagram of the first implementation mode of the voltage judging circuit;

[0036] Figure 4ais a structure diagram of a second implementation of the voltage judging circuit;

[0037] Figure 4b is a working principle waveform diagram of the second implementation of the voltage judging circuit;

[0038] Figure 5 is a structure diagram of a third implementation of the voltage judging circuit;

[0039] Figure 6 is a structure diagram of the operational amplifier;

[0040] Figure 7 is a structure diagram of the current detecting circuit;

[0041] Figure 8a is a structure diagram of a first implementation of the delay circuit;

[0042] Figure 8b is a structure diagram of a second implementation of the delay circuit;

[0043] Figure 9a is a structure diagram of a first implementation of the reference and bias circuit;

[0044] Figure 9b is a structure diagram of a second implementation of the reference and bias circuit;

[0045] Figure 10 is a structure diagram of a specific circuit of the operational amplifier (OP1 / OP2);

[0046] Figure 11 is a structure diagram of a specific circuit of the bias circuit in FIG. 9;

[0047] Figure 12 is a structure diagram of a specific circuit of the low-power bias circuit;

[0048] Figure 13 is a working waveform diagram of the low-power voltage conversion circuit when there is no output current;

[0049] Figure 14 is a circuit working waveform diagram of the low-power voltage conversion circuit when there is output current;

[0050] Figure 15 is a working state diagram of the low-power voltage conversion circuit;

[0051] Figure 16 is a flow diagram of the low-power voltage conversion method. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0053] Please refer to Figure 2 which shows a structure diagram of a low-power-consumption voltage conversion circuit provided by an embodiment of the present application. The low-power-consumption voltage conversion circuit can include a reference and bias circuit, a low-power-consumption bias circuit, a first switch SW0, a second switch SW1, a first capacitor C0, a second capacitor C1, an operational amplifier, a voltage judgment circuit, a current detection circuit and a delay circuit. The difference between the first capacitor C0 and the second capacitor C1 is greater than a predetermined threshold. The predetermined threshold can be a large number, so as to ensure that the capacitance of the first capacitor C0 is much greater than the capacitance of the second capacitor C1.

[0054] The reference voltage output end of the reference and bias circuit is connected with one end of the first switch SW0 and one end of the second switch SW1 respectively, and the bias voltage output end is connected with the bias voltage input end of the operational amplifier; the other end of the first switch SW0 is connected with one end of the first capacitor C0, the non-inverting input end of the operational amplifier and the slow voltage input end of the voltage judgment circuit respectively; the other end of the second switch SW1 is connected with one end of the second capacitor C1 and the fast voltage input end of the voltage judgment circuit respectively; the other end of the first capacitor C0 and the other end of the second capacitor C1 are grounded; the output end of the low-power-consumption bias circuit is connected with the bias input end of the voltage judgment circuit and the low-power-consumption bias input end of the operational amplifier respectively; the power output end of the operational amplifier is connected with the inverting input end of the operational amplifier and serves as the output end of the low-power-consumption voltage conversion circuit, the detection output end of the operational amplifier is connected with the input end of the current detection circuit; the output end of the voltage judgment circuit is connected with the voltage detection input end of the delay circuit; the output end of the current detection circuit is connected with the current detection input end of the delay circuit; the output end of the delay circuit is connected with the control input end of the reference and bias circuit.

[0055] When the voltage judgment circuit detects that the voltage difference between the first capacitor C0 and the second capacitor C1 is greater than the first threshold, and the current detection circuit detects that the output current of the power output end of the operational amplifier is less than or equal to the second threshold, or when the voltage judgment circuit detects that the voltage difference between the first capacitor C0 and the second capacitor C1 is less than or equal to the first threshold, and the current detection circuit detects that the output current of the power output end of the operational amplifier is greater than the second threshold, the reference and bias circuit is turned on through the delay circuit; when the voltage judgment circuit detects that the voltage difference between the first capacitor C0 and the second capacitor C1 is less than or equal to the first threshold, and the current detection circuit detects that the output current of the power output end of the operational amplifier is less than or equal to the second threshold, the reference and bias circuit is turned off through the delay circuit, so as to reduce the static power consumption.

[0056] The three structures of the voltage judgment circuit will be described below.

[0057] (1) Figure 3a In it, the voltage judgment circuit includes: the first to second NMOS transistors, and the first comparator; the drain terminal of the first NMOS transistor N0 is connected to the power supply signal VDD, the gate terminal of the first NMOS transistor N0 serves as the slow voltage input terminal of the voltage judgment circuit, the source terminal of the first NMOS transistor N0 is respectively connected to the drain terminal of the second NMOS transistor N1 and the non-inverting input terminal of the first comparator, the gate terminal of the second NMOS transistor N1 is connected to the bias input terminal of the first comparator and serves as the bias input terminal of the voltage judgment circuit, the source terminal of the second NMOS transistor N1 is grounded, the inverting input terminal of the first comparator serves as the fast voltage input terminal of the voltage judgment circuit, and the output terminal of the first comparator serves as the output terminal of the voltage judgment circuit.

[0058] Figure 3b The working principle of the voltage judgment circuit is shown: when the circuit is in standby, due to the reverse bias current of the reverse bias PN junction (diode), there is leakage current in the capacitor nodes VC1 and VC2. When the leakage current between VC1 (VC2) and the ground is greater than the leakage current between the power supply and VC1 (VC2), the voltages on the first capacitor C0 and the second capacitor C1 will slowly decrease due to the leakage. Since the capacitance value of the first capacitor C0 is much larger than that of the second capacitor C1, the decreasing speed of VC0 is much slower than that of VC1. Let the gate-source voltage of the first NMOS transistor N0 be VGSN0, and the voltage at the non-inverting terminal of the first comparator be VC0 - VGSN0. When VC1 < VC0 - VGSN0, the output voltage of the first comparator flips, that is, when the difference between VC1 and VC2 is greater than the first threshold value Vx (VGSN0), the output signal A changes from a low level to a high level, and the overall circuit starts to work.

[0059] (2) Figure 4a In it, the voltage judgment circuit includes: the first to third PMOS transistors, the third NMOS transistor N2, and the second comparator; the source terminals of the first PMOS transistor P0 and the second PMOS transistor P1 are connected and connected to the power supply signal VDD, the gate terminal and the drain terminal of the first PMOS transistor P0, the gate terminal of the second PMOS transistor P1 and the drain terminal of the third NMOS transistor N2 are connected, the gate terminal of the third NMOS transistor N2 is connected to the bias input terminal of the second comparator and serves as the bias input terminal of the voltage judgment circuit, the drain terminals of the second PMOS transistor P1 and the third PMOS transistor P2 are connected to the inverting input terminal of the second comparator, the gate terminal of the third PMOS transistor P2 serves as the slow voltage input terminal of the voltage judgment circuit, the source terminals of the third NMOS transistor N2 and the third PMOS transistor P2 are grounded, the non-inverting input terminal of the second comparator serves as the fast voltage input terminal of the voltage judgment circuit, and the output terminal of the second comparator serves as the output terminal of the voltage judgment circuit.

[0060] Figure 4bThe working principle of the voltage judging circuit is shown: when the circuit is in standby, the voltage on the first capacitor C0 and the second capacitor C1 slowly rises when the leakage current between VC1 (VC2) and the ground is less than the leakage current between the power supply and VC1 (VC2); since the capacitance of the first capacitor C0 is much greater than the capacitance of the second capacitor C1, the rising speed of VC1 is less than that of VC2. Assuming that the source-gate voltage of the third PMOS tube P2 is VGSP2, and the voltage at the inverting terminal of the second comparator is VC1-VGSP2, when VC1>VC1-VGSP2, the output voltage of the second comparator flips, that is, when the difference between VC1 and VC2 is greater than the first threshold value Vx (VGSP2), the output signal A changes from low to high, and the overall circuit starts to work.

[0061] (3) Figure 5 In the voltage judging circuit, the fourth to sixth PMOS tubes, the fourth to sixth NMOS tubes, the third to fourth comparators, and the first OR gate OR0 are connected as follows: the source terminal of the fourth PMOS tube P3, the source terminal of the fifth PMOS tube P4, and the drain terminal of the fourth NMOS tube N3 are connected and connected to the power supply signal VDD; the gate terminal and the drain terminal of the fourth PMOS tube P3, the gate terminal of the fifth PMOS tube P4, and the drain terminal of the sixth NMOS tube N5 are connected; the gate terminal of the sixth NMOS tube N5 is connected with the bias input terminal of the third comparator, the gate terminal of the fifth NMOS tube N4, and the bias input terminal of the fourth comparator, and serves as the bias input terminal of the voltage judging circuit; the drain terminal of the fifth PMOS tube P4 is connected with the drain terminal of the sixth PMOS tube P5 and the inverting input terminal of the third comparator; the gate terminal of the sixth PMOS tube P5 is connected with the gate terminal of the fourth NMOS tube N3 and serves as the slow voltage input terminal of the voltage judging circuit; the source terminal of the fourth NMOS tube N3 is connected with the drain terminal of the fifth NMOS tube N4 and the non-inverting input terminal of the fourth comparator; the non-inverting input terminal of the third comparator is connected with the inverting input terminal of the fourth comparator and serves as the fast voltage input terminal of the voltage judging circuit; the source terminal of the fifth NMOS tube N4, the source terminal of the sixth NMOS tube N5, and the source terminal of the sixth PMOS tube P5 are grounded; the output terminal of the third comparator is connected with one input terminal of the first OR gate OR0; the output terminal of the fourth comparator is connected with the other input terminal of the first OR gate OR0; and the output terminal of the first OR gate OR0 serves as the output terminal of the voltage judging circuit.

[0062] Figure 5 The working principle of the voltage judging circuit is shown: when the circuit is in standby, the voltage on the first capacitor C0 and the second capacitor C1 slowly rises when the leakage current between VC1 (VC2) and the ground is less than the leakage current between the power supply and VC1 (VC2); since the capacitance of the first capacitor C0 is much greater than the capacitance of the second capacitor C1, the rising speed of VC1 is less than that of VC2. Assuming that the source-gate voltage of the third PMOS tube P2 is VGSP2, and the voltage at the inverting terminal of the second comparator is VC1-VGSP2, when VC1>VC1-VGSP2, the output voltage of the second comparator flips, that is, when the difference between VC1 and VC2 is greater than the first threshold value Vx (VGSP2), the output signal A changes from low to high, and the overall circuit starts to work. Figure 3a and Figure 4a When the leakage current between VC1 (VC2) and the ground is similar to the leakage current between the power supply and VC1 (VC2), the voltage on the first capacitor C0 (the second capacitor C1) may rise or fall, which is applicable to the circuit in Figure 5 .

[0063] The structure of the operational amplifier is described below.

[0064] Figure 6 In the amplifier, the differential amplifier, the seventh PMOS tube P6, the seventh to ninth NMOS tubes are included; the inverting input end of the differential amplifier is the non-inverting input end of the amplifier, the non-inverting input end of the differential amplifier is the inverting input end of the amplifier, the drain end of the seventh PMOS tube P6 and the drain end of the ninth NMOS tube N8 are connected and serve as the power output end of the amplifier, the bias input end of the differential amplifier is connected with the drain end of the seventh NMOS tube N6 and the drain end of the eighth NMOS tube N7, the gate end of the seventh NMOS tube N6 serves as the bias voltage input end of the amplifier, the gate end of the eighth NMOS tube N7 and the gate end of the ninth NMOS tube N8 are connected and serve as the low-power consumption bias input end of the amplifier, the source end of the seventh PMOS tube P6 is connected with the power supply signal, the output end of the differential amplifier and the gate end of the seventh PMOS tube P6 are connected and serve as the detection output end of the amplifier, the source end of the seventh NMOS tube N6, the source end of the eighth NMOS tube N7 and the source end of the ninth NMOS tube N8 are grounded.

[0065] The structure of the current detection circuit will be described below.

[0066] Figure 7 In the current detection circuit, the eighth PMOS tube P7, the first resistor R0, the first to second inverters are included; the source end of the eighth PMOS tube P7 is connected with the power supply signal VDD, the gate end of the eighth PMOS tube P7 serves as the input end of the current detection circuit, the drain end of the eighth PMOS tube P7 and one end of the first resistor R0 are connected with the input end of the first inverter INV0, the other end of the first resistor R0 is grounded, the output end of the first inverter INV0 is connected with the input end of the second inverter INV1, the output end of the second inverter INV1 serves as the output end of the current detection circuit.

[0067] The two structures of the delay circuit will be described below.

[0068] (1) Figure 8aIn the delay circuit, the second OR gate OR1, the ninth PMOS transistor P8, the tenth NMOS transistor N9, the second resistor R1, the third capacitor C2, and the third inverter INV2 are included. One input terminal of the second OR gate OR1 is used as a voltage detection input terminal of the delay circuit, another input terminal of the second OR gate OR1 is used as a current detection input terminal of the delay circuit, the output terminal of the second OR gate OR1 and the gate terminal of the ninth PMOS transistor P8 are connected to the gate terminal of the tenth NMOS transistor N9, the source terminal of the ninth PMOS transistor P8 is connected to the power supply signal VDD, the drain terminal of the ninth PMOS transistor P8 is connected to one terminal of the second resistor R1, the other terminal of the second resistor R1, the drain terminal of the tenth NMOS transistor N9, and one terminal of the third capacitor C2 are connected to the input terminal of the third inverter INV2, the source terminal of the tenth NMOS transistor N9 and the other terminal of the third capacitor C2 are grounded, and the output terminal of the third inverter INV2 is used as an output terminal of the delay circuit.

[0069] (2) Figure 8b In the delay circuit, the third OR gate OR2, the tenth and eleventh PMOS transistors, the eleventh and twelfth NMOS transistors, the third and fourth resistors, the fourth and fifth capacitors, and the fourth and fifth inverters are included. The gate terminal of the tenth PMOS transistor P9 is connected to the gate terminal of the eleventh NMOS transistor N10 and is used as a voltage detection input terminal of the delay circuit, the gate terminal of the eleventh PMOS transistor P10 is connected to the gate terminal of the twelfth NMOS transistor N11 and is used as a current detection input terminal of the delay circuit, the source terminal of the tenth PMOS transistor P9 and the source terminal of the eleventh PMOS transistor P10 are connected to the power supply signal, the drain terminal of the tenth PMOS transistor P9 is connected to one terminal of the third resistor R2, the other terminal of the third resistor R2, the drain terminal of the eleventh NMOS transistor N10, and one terminal of the fourth capacitor C3 are connected to the input terminal of the fourth inverter INV3, the output terminal of the fourth inverter INV3 is connected to one input terminal of the third OR gate OR2, the source terminal of the tenth PMOS transistor P9 and the source terminal of the eleventh PMOS transistor P10 are connected to the power supply signal, the drain terminal of the eleventh PMOS transistor P10 is connected to one terminal of the fourth resistor R3, the other terminal of the fourth resistor R3, the drain terminal of the twelfth NMOS transistor N11, and one terminal of the fifth capacitor C4 are connected to the input terminal of the fifth inverter INV4, the output terminal of the fifth inverter INV4 is connected to another input terminal of the third OR gate OR2, the output terminal of the third OR gate OR2 is used as an output terminal of the delay circuit, and the source terminal of the eleventh NMOS transistor N10, the other terminal of the fourth capacitor C3, the source terminal of the twelfth NMOS transistor N11, and the other terminal of the fifth capacitor C4 are grounded.

[0070] The structure of the reference and bias circuit will be described below.

[0071] (1) Figure 9aIn this circuit, the enable input terminal of the first operational amplifier OP0 is connected to the enable input terminal of the bias circuit and receives the enable signal EN. The non-inverting input terminal of the first operational amplifier OP0 and one end of the fifth resistor R4 are connected to the anode of the first diode D0. The inverting input terminal of the first operational amplifier OP0 and one end of the sixth resistor R5 are connected to one end of the seventh resistor R6. The output terminal of the first operational amplifier OP0, the other end of the fifth resistor R4 and the other end of the sixth resistor R5 are connected to one end of the eighth resistor R7. The other end of the eighth resistor R7 is connected to one end of the ninth resistor R8 and serves as the reference voltage output terminal of the reference and bias circuit. The other end of the ninth resistor R8, the cathode of the second diode D1 and the cathode of the first diode D0 are grounded. The anode of the second diode D1 is connected to the other end of the seventh resistor R6. The output terminal of the bias circuit serves as the bias voltage output terminal of the reference and bias circuit.

[0072] (2) Figure 9b In this circuit, the enable input of the second operational amplifier OP1, the enable input of the third operational amplifier OP2, and the enable input of the bias circuit are connected and connected to the enable signal EN. The non-inverting input of the second operational amplifier OP1, one end of the ninth resistor R8, and the anode of the third diode D2 are connected. The inverting input of the second operational amplifier OP1, one end of the tenth resistor R9, and one end of the eleventh resistor R10 are connected. The output of the second operational amplifier OP1, the other end of the ninth resistor R8, and the other end of the tenth resistor R9 are connected to the non-inverting input of the third operational amplifier OP2. The output of the third operational amplifier OP2 is connected to one end of the twelfth resistor R11 and serves as the reference voltage output of the reference and bias circuit. The inverting input of the third operational amplifier OP2, the other end of the twelfth resistor R11, and one end of the thirteenth resistor R12 are connected. The other end of the thirteenth resistor R12, the cathode of the fourth diode D3, and the cathode of the third diode D2 are grounded. The anode of the fourth diode D3 is connected to the other end of the eleventh resistor R10. The output of the bias circuit serves as the bias voltage output of the reference and bias circuit.

[0073] Figure 9a The first operational amplifier OP0 and Figure 9b The second operational amplifier OP1 in the series has the same structure. Figure 10The circuit structure of the operational amplifier is shown, wherein the source end of the twelfth PMOS tube P11, the source end of the thirteenth PMOS tube P12 and the drain end of the seventeenth NMOS tube N16 are connected and accessed to the VDD power signal, the gate end of the twelfth PMOS tube P11 and the gate end of the thirteenth PMOS tube P12 are connected, the drain end of the twelfth PMOS tube P11, the source end of the fourteenth PMOS tube P13 and the source end of the fifteenth PMOS tube P14 are connected, the gate end of the fourteenth PMOS tube P13 serves as the non-inverting input end of the operational amplifier, the gate end of the fifteenth PMOS tube P14 serves as the inverting input end of the operational amplifier, the drain end of the fourteenth PMOS tube P13, the drain end and the gate end of the thirteenth NMOS tube N12 and the gate end of the fourteenth NMOS tube N13 are connected, the drain end of the fifteenth PMOS tube P14, the drain end of the fourteenth NMOS tube N13, the gate end of the fifteenth NMOS tube N14 and one end of the sixth capacitor C5 are connected, the drain end of the thirteenth PMOS tube P12, the other end of the sixth capacitor C5, the drain end of the fifteenth NMOS tube N14, the drain end of the sixteenth NMOS tube N15 and the gate end of the seventeenth NMOS tube N16 are connected, the input end of the sixth inverter INV5 serves as the enable input end of the operational amplifier, the output end of the sixth inverter INV5 and the gate end of the sixteenth NMOS tube N15 are connected, the source end of the seventeenth NMOS tube N16 serves as the output end of the operational amplifier, and the source ends of the thirteenth to sixteenth NMOS tubes are grounded.

[0074] Figure 11 The circuit structure of the bias circuit in the reference and bias circuit is shown, wherein the gate end of the sixteenth PMOS tube P15 and the gate end of the eighteenth NMOS tube N17 are connected and serve as the enable input end of the bias circuit, the source end of the sixteenth PMOS tube P15, the source end of the seventeenth PMOS tube P16, the source end of the eighteenth PMOS tube P17 and the source end of the nineteenth PMOS tube P18 are connected and accessed to the power signal VDD, the drain end of the sixteenth PMOS tube P15, the gate end and the drain end of the seventeenth PMOS tube P16, the gate end and the drain end of the eighteenth PMOS tube P17 and the gate end of the nineteenth PMOS tube P18 are connected, the drain end of the seventeenth PMOS tube P16 and the drain end of the eighteenth NMOS tube N17 are connected, the source end of the eighteenth NMOS tube N17, the drain end and the gate end of the nineteenth NMOS tube N18 and the gate end of the twentieth NMOS tube N19 are connected, the source end of the twentieth NMOS tube N19 and one end of the fifth resistor R4 are connected, the drain end of the nineteenth PMOS tube P18 and the drain end and the gate end of the twenty-first NMOS tube N20 are connected and serve as the output end of the bias circuit, the source end of the nineteenth NMOS tube N18, the other end of the fifth resistor R4 and the source end of the twenty-first NMOS tube N20 are grounded.

[0075] The structure of the low-power-consumption bias circuit is described below.

[0076] Figure 12 The circuit structure of the low-power bias circuit is shown, wherein the source end of the twentieth PMOS tube P19, the source end of the twenty-first PMOS tube P20 and the source end of the twenty-second PMOS tube P21 are connected and accessed to the power signal VDD, the gate end of the twentieth PMOS tube P19, the gate end of the twenty-first PMOS tube P20 and the gate end of the twenty-second PMOS tube P21 are connected, the drain end of the twentieth PMOS tube P19, the drain end of the twenty-second NMOS tube N21 and the gate end are connected to the gate end of the twenty-third NMOS tube N22, the source end of the twenty-third NMOS tube N22 is connected to one end of the sixth resistor R5, the drain end of the twenty-second PMOS tube P21 is connected to the source end and the gate end of the twenty-fourth NMOS tube N23 and serves as the output end of the low-power bias circuit, and the source end of the twenty-second NMOS tube N21, the other end of the sixth resistor R5 and the source end of the twenty-fourth NMOS tube N23 are grounded.

[0077] Figure 13 The working principle of the delay circuit changing the low-power voltage conversion circuit state through voltage detection is that the voltage VC1 on the first capacitor C0 and the voltage VC2 on the second capacitor C1 change at the same time, and since the capacitance value of the first capacitor C0 is greater than that of the second capacitor C1, the voltage difference on the two capacitors gradually increases, and when the difference is greater than the first threshold value Vx, the voltage judgment circuit outputs a positive pulse, that is, when the voltage difference between the first capacitor C0 and the second capacitor C0 is greater than the first threshold value, the voltage judgment circuit outputs a high level, at this time, the voltage detection end of the delay circuit receives a high level signal A, and the output current IOUT of the driving output end of the operational amplifier is less than the second threshold value Ix, at this time, the current detection end of the delay circuit receives a low level signal B, that is, when the output current of the power output end of the operational amplifier is less than or equal to the second threshold value, the current detection circuit outputs a low level, at this time, the delay circuit outputs a high level pulse width and increases the delay t0 after processing the signals A and B.

[0078] Figure 14The working principle of the time delay circuit is to change the low-power voltage conversion circuit state through current detection. The voltage VC1 on the first capacitor C0 and the voltage VC2 on the second capacitor C1 change at the same time. Since the capacitance value of the first capacitor C0 is greater than the capacitance value of the second capacitor C1, the voltage difference between the two capacitors gradually increases, but the difference is still less than the first threshold value Vx. The voltage judgment circuit outputs a low level. That is, when the voltage difference between the first capacitor C0 and the second capacitor C0 is less than or equal to the first threshold value, the voltage judgment circuit outputs a low level. At this time, the voltage detection end of the time delay circuit receives a low level signal A. The output current IOUT of the driving output end of the operational amplifier is greater than the second threshold value Ix. A positive pulse is output. That is, when the output current of the power output end of the operational amplifier is greater than the second threshold value, the current detection circuit outputs a high level. At this time, the time delay circuit outputs a high level signal C after processing signals A and B with an increased time delay t1.

[0079] The first switch SW0 and the second switch SW1 are controlled by the output signal of the time delay circuit. When the output of the time delay circuit is a high level, the first switch SW0 and the second switch SW1 are closed at the same time. When the output is a low level, the first switch SW0 and the second switch SW1 are opened at the same time.

[0080] As shown in Figure 15 When the circuit works stably, the output current Iout of the driving output end of the operational amplifier is less than the second threshold value Ix. The circuit enters a low-power standby state. At this time, the first switch SW0 and the second switch SW1 are opened, the low-power bias circuit does not work, and the output current Iout is zero. The first capacitor C0 and the second capacitor C1 will change slowly due to leakage. The capacitance value of the second capacitor C1 is much smaller than the capacitance value of the first capacitor C0. Therefore, the change speed of the voltage VC2 on the second capacitor C1 is much greater than the change speed of the voltage VC1 on the first capacitor C0. When the difference between VC1 and VC2 reaches the first threshold value Vx, the circuit refreshes the state of the first capacitor C0 and the second capacitor C1, and the output current Iout increases. When Iout is greater than the second threshold value Ix, the first switch SW0 and the second switch SW1 are closed, and the circuit returns to normal work.

[0081] Please refer to Figure 16 , which shows a flowchart of a low-power voltage conversion method provided by an embodiment of the application. The low-power voltage conversion method can include:

[0082] Step 1601, when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is greater than the first threshold value, and the current detection circuit detects that the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold value, or when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detection circuit detects that the output current of the power output terminal of the operational amplifier is greater than the second threshold value, the reference and bias circuit is turned on by the delay circuit.

[0083] Step 1602, when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold value, and the current detection circuit detects that the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold value, the reference and bias circuit is turned off by the delay circuit to reduce the static power consumption.

[0084] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk.

[0085] The above description is not intended to limit the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A low-power voltage conversion circuit, characterized in that, The low-power voltage conversion circuit includes a reference and bias circuit, a low-power bias circuit, a first switch, a second switch, a first capacitor, a second capacitor, an operational amplifier, a voltage judgment circuit, a current detection circuit, and a delay circuit. The difference between the first capacitor and the second capacitor is greater than a predetermined threshold. The reference voltage output terminal of the reference and bias circuit is connected to one end of the first switch and one end of the second switch, respectively; the bias voltage output terminal is connected to the bias voltage input terminal of the operational amplifier; the other end of the first switch is connected to one end of the first capacitor, the non-inverting input terminal of the operational amplifier, and the slow voltage input terminal of the voltage judgment circuit, respectively; the other end of the second switch is connected to one end of the second capacitor and the fast voltage input terminal of the voltage judgment circuit, respectively; the other ends of the first capacitor and the other ends of the second capacitor are grounded; the output terminal of the low-power bias circuit is connected to the bias input terminal of the voltage judgment circuit and the low-power bias input terminal of the operational amplifier, respectively; the power output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier and serves as the output terminal of the low-power voltage conversion circuit; the detection output terminal of the operational amplifier is connected to the input terminal of the current detection circuit; the output terminal of the voltage judgment circuit is connected to the voltage detection input terminal of the delay circuit; the output terminal of the current detection circuit is connected to the current detection input terminal of the delay circuit. The output terminal of the delay circuit is connected to the control input terminal of the reference and bias circuit. When the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is greater than the first threshold, and the current detection circuit detects that the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold, or when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold, and the current detection circuit detects that the output current of the power output terminal of the operational amplifier is greater than the second threshold, the reference and bias circuit is turned on through the delay circuit. When the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to a first threshold, and the current detection circuit detects that the output current at the power output terminal of the operational amplifier is less than or equal to a second threshold, the reference and bias circuit is turned off by the delay circuit to reduce static power consumption.

2. The low-power voltage conversion circuit according to claim 1, characterized in that, The voltage determination circuit includes: a first and a second NMOS transistor, and a first comparator; The drain of the first NMOS transistor is connected to the power supply signal. The gate of the first NMOS transistor serves as the slow voltage input terminal of the voltage judgment circuit. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the non-inverting input terminal of the first comparator. The gate of the second NMOS transistor is connected to the bias input terminal of the first comparator and serves as the bias input terminal of the voltage judgment circuit. The source of the second NMOS transistor is grounded. The inverting input terminal of the first comparator serves as the fast voltage input terminal of the voltage judgment circuit. The output terminal of the first comparator serves as the output terminal of the voltage judgment circuit.

3. The low-power voltage conversion circuit according to claim 1, characterized in that, The voltage determination circuit includes: first to third PMOS transistors, a third NMOS transistor, and a second comparator; The source terminal of the first PMOS transistor is connected to the source terminal of the second PMOS transistor and is connected to a power supply signal. The gate and drain terminals of the first PMOS transistor, the gate terminal of the second PMOS transistor, and the drain terminal of the third NMOS transistor are connected. The gate terminal of the third NMOS transistor is connected to the bias input terminal of the second comparator and serves as the bias input terminal of the voltage judgment circuit. The drain terminals of the second PMOS transistor and the third PMOS transistor are connected to the inverting input terminal of the second comparator. The gate terminal of the third PMOS transistor serves as the slow voltage input terminal of the voltage judgment circuit. The source terminals of the third NMOS transistor and the third PMOS transistor are grounded. The non-inverting input terminal of the second comparator serves as the fast voltage input terminal of the voltage judgment circuit. The output terminal of the second comparator serves as the output terminal of the voltage judgment circuit.

4. The low-power voltage conversion circuit according to claim 1, characterized in that, The voltage determination circuit includes: fourth to sixth PMOS transistors, fourth to sixth NMOS transistors, third to fourth comparators, and a first OR gate; The source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the drain of the fourth NMOS transistor are connected and connected to a power supply signal. The gate and drain of the fourth PMOS transistor, the gate of the fifth PMOS transistor, and the drain of the sixth NMOS transistor are connected. The gate of the sixth NMOS transistor is connected to the bias input of the third comparator, the gate of the fifth NMOS transistor, and the bias input of the fourth comparator, and serves as the bias input of the voltage judgment circuit. The drain of the fifth PMOS transistor, the drain of the sixth PMOS transistor, and the inverting input of the third comparator are connected. The gate of the sixth PMOS transistor is connected to the gate of the fourth NMOS transistor and serves as the bias input of the voltage judgment circuit. The slow voltage input terminal of the voltage judgment circuit is connected to the source terminal of the fourth NMOS transistor, the drain terminal of the fifth NMOS transistor, and the non-inverting input terminal of the fourth comparator. The non-inverting input terminal of the third comparator is connected to the inverting input terminal of the fourth comparator and serves as the fast voltage input terminal of the voltage judgment circuit. The source terminals of the fifth NMOS transistor, the sixth NMOS transistor, and the sixth PMOS transistor are grounded. The output terminal of the third comparator is connected to one input terminal of the first OR gate, and the output terminal of the fourth comparator is connected to the other input terminal of the first OR gate. The output terminal of the first OR gate serves as the output terminal of the voltage judgment circuit.

5. The low-power voltage conversion circuit according to claim 1, characterized in that, The operational amplifier includes: a differential amplifier, a seventh PMOS transistor, and seventh to ninth NMOS transistors; The inverting input of the differential amplifier serves as the non-inverting input of the operational amplifier (op-amp), and the non-inverting input of the differential amplifier serves as the inverting input of the op-amp. The drain of the seventh PMOS transistor is connected to the drain of the ninth NMOS transistor and serves as the power output of the op-amp. The bias input of the differential amplifier is connected to the drains of the seventh and eighth NMOS transistors. The gate of the seventh NMOS transistor serves as the bias voltage input of the op-amp. The gate of the eighth and ninth NMOS transistors is connected to the gate of the op-amp and serves as the low-power bias input of the op-amp. The source of the seventh PMOS transistor is connected to a power signal. The output of the differential amplifier is connected to the gate of the seventh PMOS transistor and serves as the detection output of the op-amp. The sources of the seventh, eighth, and ninth NMOS transistors are grounded.

6. The low-power voltage conversion circuit according to claim 1, characterized in that, The current detection circuit includes: an eighth PMOS transistor, a first resistor, and first and second inverters; The source terminal of the eighth PMOS transistor is connected to a power supply signal, the gate terminal of the eighth PMOS transistor serves as the input terminal of the current detection circuit, the drain terminal of the eighth PMOS transistor and one end of the first resistor are connected to the input terminal of the first inverter, the other end of the first resistor is grounded, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the current detection circuit.

7. The low-power voltage conversion circuit according to claim 1, characterized in that, The delay circuit includes: a second OR gate, a ninth PMOS transistor, a tenth NMOS transistor, a second resistor, a third capacitor, and a third inverter; One input terminal of the second OR gate serves as the voltage detection input terminal of the delay circuit, and the other input terminal of the second OR gate serves as the current detection input terminal of the delay circuit. The output terminal of the second OR gate, the gate terminal of the ninth PMOS transistor, and the gate terminal of the tenth NMOS transistor are connected. The source terminal of the ninth PMOS transistor is connected to a power supply signal. The drain terminal of the ninth PMOS transistor is connected to one end of the second resistor. The other end of the second resistor, the drain terminal of the tenth NMOS transistor, and one end of the third capacitor are connected to the input terminal of the third inverter. The source terminal of the tenth NMOS transistor and the other end of the third capacitor are grounded. The output terminal of the third inverter serves as the output terminal of the delay circuit.

8. The low-power voltage conversion circuit according to claim 1, characterized in that, The delay circuit includes: a third OR gate, tenth to eleventh PMOS transistors, eleventh to twelfth NMOS transistors, third to fourth resistors, fourth to fifth capacitors, and fourth to fifth inverters; The gate of the tenth PMOS transistor is connected to the gate of the eleventh NMOS transistor and serves as the voltage detection input of the delay circuit. The gate of the eleventh PMOS transistor is connected to the gate of the twelfth NMOS transistor and serves as the current detection input of the delay circuit. Power signals are connected to the source terminals of the tenth and eleventh PMOS transistors. The drain of the tenth PMOS transistor is connected to one end of a third resistor. The other end of the third resistor, the drain of the eleventh NMOS transistor, and one end of a fourth capacitor are connected to the input of a fourth inverter. The output of the fourth inverter is connected to one input of the third OR gate. The source terminals of the tenth PMOS transistor and the eleventh PMOS transistor are connected to a power supply signal. The drain terminal of the eleventh PMOS transistor is connected to one end of the fourth resistor. The other end of the fourth resistor, the drain terminal of the twelfth NMOS transistor, and one end of the fifth capacitor are connected to the input terminal of the fifth inverter. The output terminal of the fifth inverter is connected to the other input terminal of the third OR gate. The output terminal of the third OR gate serves as the output terminal of the delay circuit. The source terminal of the eleventh NMOS transistor, the other end of the fourth capacitor, the source terminal of the twelfth NMOS transistor, and the other end of the fifth capacitor are grounded.

9. The low-power voltage conversion circuit according to any one of claims 1 to 8, characterized in that, When the voltage difference between the first capacitor and the second capacitor is greater than the first threshold, the voltage judgment circuit outputs a high level; when the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold, the voltage judgment circuit outputs a low level. When the output current of the power output terminal of the operational amplifier is greater than the second threshold, the current detection circuit outputs a high level; when the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold, the current detection circuit outputs a low level.

10. A low-power voltage conversion method, characterized in that, In a low-power voltage conversion circuit as described in any one of claims 1 to 9, the method comprises: When the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is greater than the first threshold, and the current detection circuit detects that the output current of the power output terminal of the operational amplifier is less than or equal to the second threshold, or when the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to the first threshold, and the current detection circuit detects that the output current of the power output terminal of the operational amplifier is greater than the second threshold, the reference and bias circuit is turned on through the delay circuit. When the voltage judgment circuit detects that the voltage difference between the first capacitor and the second capacitor is less than or equal to a first threshold, and the current detection circuit detects that the output current at the power output terminal of the operational amplifier is less than or equal to a second threshold, the reference and bias circuit is turned off by the delay circuit to reduce static power consumption.

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