A method for testing the tunneling oxide layer resistance of a TOPCon battery and calculating its backside series resistance

Abstract

The present invention discloses a method for testing the tunneling layer resistance of a TOPCon battery and a method for calculating the back-side series resistance of the battery. The method tests the resistance R between any grid lines of the synchronously prepared TOPCon battery. 01 The resistance R between the gate lines corresponding to the insulating mask monitoring sample 02 Data processing is performed to obtain the tunneling layer resistance R2, which is then multiplied by the local gate line area to obtain the tunneling layer resistivity. Full-surface testing is then performed to determine the tunneling oxide layer resistance distribution at different locations. This quantitative method effectively describes the tunneling resistance distribution across the entire cell surface. It is simple, low-cost, and requires minimal testing time, making it suitable for industrial monitoring. The test results are more objective and accurate, directly reflecting electrical performance, and can be quantitatively calculated to verify battery power loss. This foundation also allows for calculation of the series resistance on the back side of the cell.

Description

Technical Field

[0001] The present invention relates to the technical field of resistance testing methods, and in particular to a method for testing the tunneling oxide layer resistance of a TOPCon battery and a method for calculating the back-side series resistance of the battery. Background Art

[0002] In order to increase the proportion of photovoltaic power generation, cost reduction and efficiency improvement are the two main lines of photovoltaic manufacturing. The current mainstream photovoltaic cells are crystalline silicon solar cells. The IBC structure solves the problem of shading of the grid lines on the front of the cell, improves the area utilization, and greatly improves the appearance, efficiency and practical value of photovoltaic cells. TOPCon technology has become one of the most promising new high-efficiency cell technologies due to its process route and the extremely high compatibility with the traditional PERC cell production line and its obvious efficiency gain. In TOPCon cell technology, the preparation of the back POLO structure is the core to achieve high efficiency. The characteristic of the POLO structure is that it can meet the requirements of multi-carrier transmission while meeting the requirements of passivation. The application of this feature requires a suitable tunneling oxide layer to match the diffusion process. However, in the mass production process, due to the ultra-thin characteristics of the tunneling oxide layer, process monitoring of it is often missing. At present, the industry's monitoring of the tunneling oxide layer is mostly indirect monitoring, mainly characterizing the thickness and doping curve, and cannot directly describe its impact on the cell series resistance. That is, the common tunneling monitoring solutions in the industry currently include the following two:

[0003] 1. Direct observation and thickness monitoring. Common solutions: SEM (scanning electron microscope) and TEM (transmission electron microscope) are used to directly observe and test the thickness of the tunnel oxide layer to quantitatively describe the thickness of the tunnel oxide layer. Direct observation methods require expensive testing equipment and long testing times, which increases monitoring and labor costs and is not conducive to industrial monitoring. In addition, the results obtained are single-point results, which cannot fully describe the differences across the entire battery surface and make it difficult to analyze and guide the overall performance of the battery.

[0004] 2. Analyze the internal diffusion through the diffusion curve. Common testing methods include SIMS (secondary ion mass spectrometry), ECV (electrochemical capacitance voltage method), etc. Test the doping curve to observe the internal diffusion slope at the junction of Poly Si and c-Si, and qualitatively describe the tunneling oxide layer doping cutoff effect; the curve analysis method is a qualitative test and the analysis results are relatively subjective and prone to misjudgment. At the same time, its test requires sampling and destructive testing before preparing the battery product. It is impossible to obtain tunneling results directly based on the battery, that is, it is impossible to compare and analyze with the battery results. In addition, its test results are also subject to regional limitations and cannot describe the results of the entire battery sample.

[0005] However, generally speaking, the existing technology lacks a method that can be directly applied to the calculation of series resistance, and there is an urgent need to develop a test method that can directly obtain quantitative results of the resistance of the tunnel oxide layer. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention provides a method for testing the tunneling layer resistance of TOPCon cells and calculating the backside series resistance of the cells. This intuitive and quantifiable method can truly reflect the impact of the tunneling resistance on the overall series resistance in the TOPCon cell structure, thereby addressing the shortcomings of tunneling layer monitoring in existing TOPCon cell R&D and manufacturing.

[0007] A first aspect of the present invention provides a method for testing the tunneling layer resistance of a TOPCon battery, the method comprising the following steps:

[0008] (1) Preparing TOPCon battery samples, and simultaneously preparing P-type monitoring sheet samples and insulating mask monitoring samples; the insulating mask monitoring samples and TOPCon battery samples are prepared simultaneously, with the only difference being that an insulating mask layer is prepared on the back side of the insulating mask monitoring samples;

[0009] (2) By monitoring the resistivity and square resistance of the N-type single crystal silicon wafer sample used to prepare the TOPCon battery sample, the silicon wafer lateral transmission resistance R is calculated. sh-bulk ;

[0010] (3) Use the P-type monitoring chip sample to monitor the n+Poly square resistance, and calculate the Poly layer lateral transmission resistance R through the square resistance sh-poly , perform Poly lateral transmission resistance monitoring;

[0011] (4) Use the insulating mask monitoring sample to conduct comprehensive test monitoring of contact and Poly lateral transmission, test the resistance between the gate lines to obtain the comprehensive value R of the contact resistance and Poly lateral resistance 02 (ie: the resistance between the corresponding gate lines of the mask monitoring sample R 02 This comprehensive value is actually represented; it is also the resistance value between gate lines directly measured by a multimeter for the insulation mask monitoring sample);

[0012] (5) The R obtained in step (4) 02 The value is combined with the resistance R between the gate lines of TOPCon battery samples from the same batch 01 , the test results are compared, the tunnel layer resistivity is calculated by the following formula, and finally the R 01 Forming the tunnel resistance distribution of the entire battery surface:

[0013]

[0014] For the technical solution described above, it is further preferred that the R 01 and R 02 The algorithm is as follows:

[0015]

[0016] R 02 =2R1+R3

[0017]

[0018] Where R1 is the contact resistance,

[0019] R2 is the tunnel resistance,

[0020] R3 is the lateral transmission resistance of the Poly layer,

[0021] R4 is the lateral transmission resistance of the silicon substrate,

[0022] R 01 The resistance between the gate lines of the TOPCon battery sample is directly measured by a multimeter;

[0023] R 02 For the insulation mask monitoring sample, the resistance value between the gate lines is directly measured by a multimeter;

[0024] R sh-poly is the Poly lateral transmission resistance;

[0025] R sh-bulk is the lateral transfer resistance of the silicon substrate;

[0026] d is the grid line spacing;

[0027] Z is the length of the gate line segment.

[0028] For the technical solution described above, it is further preferred that the TOPCon cell sample is obtained by texturing an N-type single crystal silicon wafer, preparing an emitter and etching the back surface, preparing a back field, passivating an anti-reflection film, and metallizing.

[0029] For the technical solution described above, it is further preferred that the insulating mask monitoring sample is obtained from an N-type single crystal silicon wafer after texturing, emitter preparation and back surface etching, mask preparation, back field preparation, passivation anti-reflection film, and metallization.

[0030] For the technical solution described above, it is further preferred that the P-type monitoring film sample is obtained by texturing a P-type single crystal silicon wafer, etching the back surface morphology, and preparing the back field (the P-type film monitors the back Poly square resistor, and there is no need to prepare the front emitter).

[0031] For the technical solution described above, it is further preferred that the texturing step is to remove the damaged layer on the surface of the silicon wafer in a mixed solution of KOH and H2O2 with a mass ratio of 1:3 to 8, and then perform texturing in a 1 to 5 wt% KOH solution to form a pyramid velvet surface of 1 to 5 μm on the surface.

[0032] For the technical solution described above, it is further preferred that the steps of preparing the emitter and etching the back surface morphology include: preparing the emitter by B diffusion on the front side, with a square resistance of 110 to 150 ohm / □, a BSG thickness of 50 to 120 nm on the front side, and alkaline polishing after removing the BSG on the back side of the silicon wafer to make the reflectivity of the back side of the silicon wafer greater than 40%.

[0033] For the technical solution described above, it is further preferred that the mask preparation includes the steps of coating, plating, and thermal oxidation.

[0034] For the technical solution described above, it is further preferred that the method for preparing the back field includes the following steps: placing the sample into LPCVD, preparing a 1-2 nm tunneling layer and a 50-150 nm amorphous silicon intrinsic deposition on one side, and using a high-temperature phosphorus diffusion temperature of 700-900°C to complete high-temperature crystallization and diffusion.

[0035] For the technical solution described above, it is further preferred that ALD is used to deposit 3 to 10 nm thick aluminum oxide on the front side of the passivation anti-reflection film, and PECVD is used to prepare 75 to 80 nm thick silicon nitride; and 70 to 100 nm thick silicon nitride is deposited on the back side of the above-mentioned silicon wafer.

[0036] For the technical solution described above, it is further preferred that the metallization preparation step includes: printing a silver paste electrode on the back side of the silicon wafer and printing a silver-aluminum paste electrode on the front side in sequence by screen printing, and then sintering.

[0037] In the technical solution described above, the selection range of the N-type single crystal silicon wafer or the P-type single crystal silicon wafer is relatively wide. In the embodiment, only common silicon wafer types are used for experiments, among which the N-type single crystal silicon wafer has a resistivity range of 0.8 to 1.5 ohm.cm and a minority carrier lifetime > 2.5 ms; the P-type single crystal silicon wafer has a resistivity range of 0.5 to 1.5 ohm.cm, but the scope of protection of this application is not limited to this.

[0038] A second aspect of the present invention provides a method for calculating the back-side series resistance of a TOPCon battery. The method is based on the tunneling layer resistance test method of the TOPCon battery described above and comprises the following steps:

[0039] (1) The backside Poly tunneling resistance R2 is measured using the method of the present invention;

[0040] (2) The comprehensive value of back contact resistance and Poly lateral resistance R is measured using an insulating mask monitoring sample 02 ;

[0041] (3) The front contact resistance of the battery sample is measured using the TLM method and is recorded as R c ;

[0042] (4) Calculate the front lateral transmission resistance and substrate transmission resistance through the front square resistance and the original silicon wafer body resistance;

[0043] (5) Calculate the gate line resistance based on the paste properties and corresponding printing parameters;

[0044] (6) Based on the above resistances, linear addition is performed to obtain the battery series resistance result;

[0045] For the technical solution described above, it is further preferred that the step (4) described in the method is to use a four-probe device to test the front side of the sample after the front emitter is prepared, obtain the square resistance monitoring of the front emitter, and calculate the emitter layer lateral transfer resistance R through the square resistance sh-emitter ;

[0046] For the technical solution described above, it is further preferred that the step (5) described in the method uses a four-probe device to monitor the resistivity and square resistance of the N-type single crystal silicon wafer to calculate the silicon wafer lateral transmission resistance R sh-bulk .

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] This method is a quantitative test that effectively describes the tunneling resistance distribution across the entire battery surface. Compared to direct observation methods, it uses simpler equipment, is less expensive, and takes less time to test, making it suitable for industrial monitoring. Compared to diffusion curve analysis, the test results are more objective and accurate, directly reflecting the electrical performance, and enabling quantitative calculations to verify battery power loss.

[0049] At the same time, during the calculation process, there is no need to additionally measure the contact resistance Rc of the battery sample, and avoid the gate line width L and the carrier transmission length L T For interference in contact resistance test, R is directly obtained by monitoring the sample through the insulation mask. 02 =2R1+R3 value, which simplifies the calculation process and improves the test accuracy;

[0050] In addition, the test sample of the present invention is based on the normal finished product battery of TOPCon, and can be directly analyzed with the corresponding battery; it can be tested independently with simple equipment (multimeter) or synchronously with the contact resistance Rc. The test range is not limited and the whole surface distributed feedback can be realized, which effectively characterizes the tunneling resistance result of the whole surface battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a schematic diagram of a battery sample testing circuit according to the present invention;

[0052] Figure 2 2 is a schematic diagram of a test circuit for a mask sample according to the present invention. DETAILED DESCRIPTION

[0053] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0054] Example 1

[0055] Specific implementation cases of the present invention applied to N-type TOPCon batteries:

[0056] (1) Preparation of original sample

[0057] N-type single crystal silicon wafers with a resistivity range of 0.8 to 1.5 ohm.cm and a minority carrier lifetime of >2.5 ms, a thickness of 170 μm, and a size of 166 mm were selected as N-type feed samples. Before feeding, a four-probe device was used to monitor the resistivity and sheet resistance of the N-type single crystal silicon wafers to calculate the lateral transfer resistance R of the silicon wafer. sh-bulk , 50~120ohm / □;

[0058] The P-type single crystal silicon wafer with a resistivity range of 0.5 to 1.5 ohm.cm, a thickness of 170 μm and a size of 166 mm was selected as the P-type sample for R sh-poly Test samples.

[0059] (2) Velveting

[0060] The damaged layer on the surface of all silicon wafers in step (1) is removed in a mixed solution of KOH and H2O2 with a mass ratio of 1:3-8, and then texturing is performed in a 1-5wt% KOH solution to form a pyramid velvet surface with a size of 1-5μm.

[0061] (3) Preparation of emitter and back-side morphology etching

[0062] After the textured surface of the N-type sample is completed in step (2), the emitter is prepared by B diffusion on the front side, with a square resistance of 110-150 ohm / □ and a BSG thickness of 50-120 nm on the front side. After the BSG is removed from the back side of the silicon wafer, the back side of the silicon wafer is subjected to alkali polishing together with the P-type sample obtained in step (2) to make the reflectivity of the back side of the silicon wafer greater than 40%;

[0063] (4) Mask sample preparation

[0064] After the preparation of step (3), a portion of the N-type feed sample is randomly sampled (the preparation of the monitoring sheet is completed at the same time as the batch feeding, and the final monitoring result and the battery test result jointly describe the tunneling resistance of the batch), and an insulating mask layer is prepared on the back side by coating, plating, thermal oxidation and other methods as a mask monitoring sample. After metallization, it is used to test R 02 ;

[0065] (5) Back field preparation

[0066] The mask monitoring sample prepared in step (4) is placed together with the P-type sample in step (3) and the remaining N-type feed sample in step (4) in LPCVD, and a 1-2 nm tunneling layer and a 50-150 nm amorphous silicon intrinsic deposition are prepared on one side, and high-temperature phosphorus diffusion temperature of 700-900° C. is used to complete high-temperature crystallization and diffusion; respectively, a mask monitoring sample I, a P-type monitoring sample and the remaining N-type feed sample I are obtained;

[0067] (6)R sh-poly Square resistance test

[0068] The four-probe device is used to monitor the n+Poly square resistance of the P-type monitoring sample obtained in step (5), and the lateral transmission resistance R of the Poly layer is calculated by the square resistance. sh-poly , 40~200ohm / □;

[0069] (7) Preparation of passivation anti-reflection film

[0070] Take the mask monitoring sample I prepared in step (5) and the remaining N-type feed sample I prepared in step (5), and use ALD to deposit 3 to 10 nm thick aluminum oxide on the front side, and use PECVD to prepare 75 to 80 nm thick silicon nitride; deposit 70 to 100 nm thick silicon nitride on the back side of the above two different silicon wafers to complete the preparation of the two precursors. For the convenience of subsequent description, they are named mask precursor and battery precursor respectively.

[0071] (8) Metallization

[0072] Metallization is performed on the front and back sides of the mask precursor and battery precursor respectively. Silver paste electrodes are printed on the back side of the silicon wafer and silver-aluminum paste electrodes are printed on the front side in sequence by screen printing. Then, the insulating mask monitoring samples and TOPCon batteries are prepared by sintering (the insulating mask monitoring samples follow the battery flow. In order to monitor the true reflection of tunneling after the final battery process, the insulating mask monitoring samples and battery products with normal feeding are obtained).

[0073] (9) Tunneling layer resistance test

[0074] The TOPCon batteries (R 01 The resistance value of the battery sample is directly measured by a multimeter) Any resistance between the grid lines R 01 The gate line resistance R corresponding to the insulating mask monitoring sample obtained in step (8) (the insulating mask monitoring sample is also a battery structure, but is mainly used for parameter monitoring) 02, perform data processing (according to the following formula) to obtain the tunneling layer resistance R2, and multiply it by the local gate line area to obtain the tunneling layer resistivity 1E-3~1E-2ohm.cm, and perform full-surface testing to obtain the tunneling oxide layer resistance distribution at different locations;

[0075] More specifically:

[0076] TOPCon battery sample test circuit diagram, such as Figure 1 TOPCon battery samples were prepared using conventional processes (as described above) and the resistance between any gate lines was tested.

[0077]

[0078] Schematic diagram of the test circuit for the insulation mask monitoring sample, such as Figure 2 , prepare an insulating mask (i.e. R2'~∞) between the doped Poly-Si and the base c-Si

[0079] R 02 =2R1+R3

[0080]

[0081] All values can be directly tested and substituted into R 01 With R 02 R2, the tunnel resistance, can be calculated from:

[0082]

[0083] In the above formula:

[0084] R2' is the tunneling resistance of the insulating mask sample,

[0085] R1 is the contact resistance,

[0086] R2 is the tunnel resistance,

[0087] R3 is the lateral transmission resistance of the Poly layer,

[0088] R4 is the lateral transmission resistance of the silicon substrate,

[0089] R 01 The resistance between the gate lines of the TOPCon battery sample is directly measured by a multimeter;

[0090] R 02 For the insulation mask monitoring sample, the resistance value between the gate lines is directly measured by a multimeter;

[0091] R sh-poly is the Poly lateral transmission resistance;

[0092] R sh-bulk is the lateral transfer resistance of the silicon substrate;

[0093] d is the grid line spacing (printing parameter, measured under a microscope);

[0094] Z is the length of the gate line segment;

[0095] Then, data analysis was performed;

[0096] 1. The whole surface tunnel oxide layer resistance test can be performed to form the whole surface tunnel layer resistance distribution;

[0097] 2. Rapid measurement can be achieved;

[0098] 3. Quantifiable characterization results can improve the current photovoltaic cell monitoring system;

[0099] From the above analysis, it can be seen that: compared with the traditional SIMS (secondary ion mass spectrometry) and ECV (electrochemical capacitance voltage method), the method of the present invention uses a test doping curve to observe the inward expansion slope at the junction of Poly Si and c-Si, and qualitatively describes the tunneling oxide layer doping cutoff effect; and the judgment of qualitative results is prone to misjudgment; at the same time, the traditional test method requires sampling for destructive testing before preparing the finished battery product, and cannot directly obtain tunneling results based on the battery; in addition, its test results are also subject to regional limitations and cannot describe the results of the entire surface of the battery sample.

[0100] Example 2

[0101] A method for calculating the backside series resistance of a TOPCon battery; the method is based on the tunneling layer resistance test method of the TOPCon battery described above, and comprises the following steps:

[0102] (1) In step (9) of Example 1, the back Poly tunneling resistance R2 is measured;

[0103] (2) Example 1 Step (9) The insulation mask monitoring sample measures the comprehensive value R of the back contact resistance and the Poly lateral resistance 02 ;

[0104] (3) The front contact resistance R of the battery sample completed in step (8) of Example 1 was measured using the TLM method. c ;

[0105] (4) After the front emitter is prepared in step (3) of Example 1, a four-probe device is used to test the front of the sample to obtain the square resistance monitoring of the front emitter. The emitter layer lateral transfer resistance R is calculated based on the square resistance. sh-emitter ,

[0106] (5) In step (1) of Example 1, a four-probe device is used to monitor the resistivity and square resistance of the N-type single crystal silicon wafer to calculate the lateral transmission resistance R of the silicon wafer. sh-bulk ;

[0107] (6) Calculate the gate line resistance based on the paste properties and corresponding printing parameters;

[0108] (7) The battery series resistance is obtained by linearly adding the above resistances.

[0109] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for testing the tunneling layer resistance of a TOPCon battery, characterized in that: The method comprises the following steps: (1) Preparing TOPCon battery samples and simultaneously preparing P-type monitoring sheet samples and insulating mask monitoring samples; the insulating mask monitoring samples and TOPCon battery samples are prepared simultaneously, the only difference being that an insulating mask layer is prepared on the back of the insulating mask monitoring samples; (2) By monitoring the resistivity and square resistance of the N-type single crystal silicon wafer sample used to prepare the TOPCon battery sample, the silicon wafer lateral transfer resistance R sh-bulk ; (3) Use a P-type monitoring chip sample to monitor the n+Poly square resistance, and calculate the Poly layer lateral transmission resistance R through the square resistance sh-poly , perform Poly lateral transmission resistance monitoring; (4) Use the insulating mask monitoring sample to conduct comprehensive test monitoring of contact and Poly lateral transmission, and separate the resistance between the test gate lines to obtain the comprehensive value R of the contact resistance and Poly lateral resistance. 02 ; (5) The R obtained in step (4) 02 The value is combined with the resistance R between the gate lines of TOPCon battery samples from the same batch 01 , the test results are compared, the tunnel layer resistivity is calculated by the following formula, and finally the R 01 Forming the tunneling resistance distribution of the entire battery surface: ； The R 01 and R 02 The algorithm is as follows: ； ； ； Where R1 is the contact resistance, R2 is the tunnel resistance, R3 is the lateral transmission resistance of the Poly layer, R4 is the lateral transmission resistance of the silicon substrate, R 01 The resistance between the gate lines of the TOPCon battery sample is directly measured by a multimeter; R 02 For the insulation mask monitoring sample, the resistance value between the gate lines is directly measured by a multimeter; R sh-poly is the Poly lateral transmission resistance; R sh-bulk is the lateral transfer resistance of the silicon substrate; d is the grid line spacing; Z is the length of the gate line segment.

2. The method according to claim 1, characterized in that The TOPCon cell sample is obtained by texturing an N-type single crystal silicon wafer, preparing an emitter, etching the back surface, preparing a back field, passivating an anti-reflection film and metallizing the wafer.

3. The method according to claim 1, characterized in that The insulating mask monitoring sample is obtained by texturing an N-type single crystal silicon wafer, preparing an emitter and etching the back surface, preparing a mask, a back field, a passivation anti-reflection film, and metallization.

4. The method according to claim 1, wherein The P-type monitoring piece sample is obtained by texturing a P-type single crystal silicon piece, etching the back surface topography and preparing the back surface field.

5. The method according to any one of claims 2 to 4, characterized in that: The texturing step comprises removing the damaged layer on the surface of the silicon wafer in a mixed solution of KOH and H2O2 with a mass ratio of 1:3-8, and then texturing in a 1-5wt% KOH solution to form a pyramid velvet surface of 1-5µm on the surface.

6. The method according to claim 2 or 3, characterized in that The steps of preparing the emitter and etching the back surface include: preparing the emitter by B diffusion on the front surface, with a square resistance of 110-150 ohm / □, a front BSG thickness of 50-120nm, and alkaline polishing after removing the BSG on the back surface of the silicon wafer to make the reflectivity of the back surface of the silicon wafer greater than 40%.

7. The method according to claim 3, characterized in that The mask preparation includes the steps of coating, plating and thermal oxidation.

8. The method according to any one of claims 2 to 4, characterized in that: The method for preparing the back field includes the following steps: placing the sample in LPCVD, preparing a 1-2 nm tunneling layer and a 50-150 nm amorphous silicon intrinsic deposition on one side, and using a high-temperature phosphorus diffusion temperature of 700-900°C to complete high-temperature crystallization and diffusion.

9. The method according to claim 2 or 3, characterized in that The method for preparing the passivation anti-reflection film comprises the following steps: depositing aluminum oxide with a thickness of 3 to 10 nm on the front side by using ALD, and preparing silicon nitride with a thickness of 75 to 80 nm by using PECVD; and depositing silicon nitride with a thickness of 70 to 100 nm on the back side of the silicon wafer.

10. The method according to claim 2 or 3, characterized in that The metallization step includes: printing a silver paste electrode on the back of the silicon wafer and printing a silver-aluminum paste electrode on the front of the silicon wafer in sequence by screen printing, and then sintering.

11. A method for calculating the backside series resistance of a TOPCon battery, characterized by: The method is based on the tunneling layer resistance testing method of the TOPCon battery according to claim 1; It includes the following steps: Measure the backside Poly tunneling resistance; The comprehensive value of back contact resistance and Poly lateral resistance was measured using an insulating mask monitoring sample; The front contact resistance of the battery sample was measured using the TLM method; The front lateral transmission resistance and substrate transmission resistance are calculated by the front square resistance and the original silicon wafer body resistance; The gate line resistance is calculated based on the paste properties and corresponding printing parameters; The battery series resistance is obtained by linearly adding the above resistances.

Images