Data processor and electronic device

Abstract

The present disclosure provides a data processor and an electronic device, the processor comprising: a data preprocessing circuit configured to preprocess the to-be-processed data received via an input terminal to obtain a first operation result; a determination circuit electrically connected with the data preprocessing circuit, configured to determine whether the to-be-processed data of a current processing period and the to-be-processed data of a subsequent processing period are accumulated data according to an identifier of the to-be-processed data and an identifier of the to-be-processed data of the subsequent processing period, and obtain a determination result; a data normalization circuit electrically connected with the determination circuit, configured to normalize the first operation result; and output the normalized first operation result to the data preprocessing circuit according to the determination result; and a data operation circuit electrically connected with the data normalization circuit, configured to process the normalized first operation result to obtain a second operation result for the current processing period.

Description

Technical Field

[0001] This disclosure relates to the field of floating-point arithmetic technology, and more specifically, to a data processor and electronic device. Background Technology

[0002] With the rapid development of artificial intelligence and big data technologies, the demands on computing power are increasing. Various machine learning algorithms, such as Mixed Precision Training (MPT), improve computational accuracy by increasing the size of the neural network, but also increase the memory and computational requirements of the training model. MPT uses half-precision floating-point numbers (FP16) to store weights and gradients, which reduces memory usage while accelerating training.

[0003] In related technologies, to minimize precision loss while facilitating floating-point operations, non-standard FP48 (Float Point 48) cells are typically used to store the accumulated (Psum) result. Furthermore, to support Psum operations on various data types (such as Int8, Uint8, Int16, and FP16), the computation unit uses multiplexed adders to save area. Since a single floating-point addition operation requires five steps—alignment, mantissa summation, normalization, rounding, and overflow detection—these steps typically require 2-3 clock cycles to complete the operation. High-frequency network processors (NPUs) require even more clock cycles for processing.

[0004] However, when consecutive data at the same address need to be added, the floating-point adder cannot produce a result in a single clock cycle like integer addition, resulting in data wait time. This reduces the adder's utilization and affects the speed of floating-point calculations. Summary of the Invention

[0005] This disclosure presents a data processor and an electronic device.

[0006] According to a first aspect of this disclosure, a data processor is proposed, comprising: a data preprocessing circuit, including an input terminal and an output terminal; the data preprocessing circuit is configured to preprocess data to be processed received via the input terminal to obtain a first operation result, wherein the data to be processed includes an identifier, and to output the first operation result via the output terminal; a determination circuit, electrically connected to the data preprocessing circuit, configured to determine whether the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are accumulated data based on the identifier of the data to be processed and the identifier of the data to be processed in a subsequent processing cycle, and to obtain a determination result; wherein the subsequent processing cycle is the next processing cycle of the current processing cycle; a data normalization circuit, electrically connected to the determination circuit, configured to normalize the first operation result; and to output the normalized first operation result to the data preprocessing circuit based on the determination result; and a data operation circuit, electrically connected to the data normalization circuit, configured to process the normalized first operation result to obtain a second operation result for the current processing cycle.

[0007] For example, the data normalization circuit includes: a data normalization sub-circuit electrically connected to the determining circuit, configured to normalize the first operation result to obtain a normalized first operation result; a first register electrically connected to the data normalization sub-circuit, configured to delay the normalized first operation result to obtain a delayed first operation result; and outputting the delayed first operation result to the data preprocessing circuit according to the determining result; wherein the delayed first operation result is used to preprocess the data to be processed in the post-processing cycle to complete the processing of the data to be processed in the post-processing cycle.

[0008] For example, the data processing circuit includes: a rounding sub-circuit configured to round the normalized first operation result to obtain a rounded first operation result; an overflow check sub-circuit configured to perform an overflow check on the rounded first operation result to obtain an overflow check result; and a post-rounding sub-circuit configured to perform a post-rounding process on the rounded first operation result based on the overflow check result to obtain a second operation result for the current processing cycle.

[0009] For example, the data preprocessing circuit includes: a shift-alignment sub-circuit configured to perform shift-alignment processing on the data to be processed to obtain first intermediate data; and a first operation sub-circuit configured to perform operation processing on the first intermediate data to obtain a first operation result.

[0010] For example, the data to be processed includes first processed data and second processed data, both of which include an exponent and a mantissa; wherein, the shift pair circuit is further configured to: obtain an exponent difference based on the exponent of the first processed data and the exponent of the second processed data; and logically shift the first processed data and the second processed data based on the exponent difference to align the exponent of the first processed data and the exponent of the second processed data to obtain first intermediate data.

[0011] For example, the first operation sub-circuit is further configured to: perform operations and carry correction on the mantissa of the first processed data and the mantissa of the second processed data to obtain a first operation result; wherein, the first operation result includes the mantissa sum, the larger exponent bit, the leading 1, and the truncation bit; the mantissa sum is the sum of the mantissa of the first processed data and the mantissa of the second processed data; the larger exponent bit is the larger exponent bit among the exponent bits of the first processed data and the exponent bits of the second processed data; the leading 1 is obtained based on the mantissa sum and is used to indicate redundant sign bits; the truncation bit is the mantissa bit truncated after shifting and aligning the smaller exponent bit among the exponent bits of the first processed data and the exponent bits of the second processed data.

[0012] For example, the data normalization sub-circuit is configured as follows: based on the leading 1, the mantissa and truncation are spliced ​​and shifted to obtain the first normalized operation result.

[0013] For example, it also includes: a second register, electrically connected to the data processing circuit, for storing the second operation result from the data processing circuit.

[0014] For example, accumulated data indicates that the data to be processed in adjacent processing cycles comes from the same address.

[0015] According to a second aspect of the present disclosure, an electronic device is provided, including at least one data processor provided in the present disclosure.

[0016] According to the technical solution of the disclosed embodiments, a data processor is provided. In multiple processing cycles, the processor determines the data type of the data to be processed in the current processing cycle and the next processing cycle. If the data to be processed is cumulative data, the intermediate data of the current processing cycle is input into the next processing cycle for data preprocessing, thereby improving the data processing speed and avoiding excessively long data waiting time in the next processing cycle. Attached Figure Description

[0017] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments in conjunction with the accompanying drawings. It should be noted that throughout the drawings, the same elements are indicated by the same or similar reference numerals. In the figures:

[0018] Figure 1A schematic diagram of the encoding of a floating-point number according to an embodiment of the present disclosure is shown;

[0019] Figure 2 A structural block diagram of a data processor according to an embodiment of the present disclosure is shown;

[0020] Figures 3A-3B A schematic diagram of inputting data to be processed in a series of processing cycles according to an embodiment of the present disclosure is shown;

[0021] Figure 4 A structural block diagram of a data processor according to another embodiment of the present disclosure is shown;

[0022] Figure 5 This is a block diagram of an electronic device with a data processor applicable according to an embodiment of the present disclosure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0024] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by those skilled in the art. It should be noted that the terms used herein should be interpreted in a manner consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0025] The figures illustrate several block diagrams and / or flowcharts. It should be understood that some blocks, or combinations thereof, in the block diagrams and / or flowcharts can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that, when executed by the processor, these instructions can create means for implementing the functions / operations described in these block diagrams and / or flowcharts. The technology disclosed herein can be implemented in hardware and / or software (including firmware, microcode, etc.). Alternatively, the technology disclosed herein can take the form of a computer program product stored on a computer-readable storage medium, which is available for use by or in conjunction with an instruction execution system.

[0026] This disclosure provides a data processor, including a data preprocessing circuit with an input terminal and an output terminal. The data preprocessing circuit is configured to preprocess data to be processed received via the input terminal to obtain a first calculation result, wherein the data to be processed includes an identifier, and to output the first calculation result via the output terminal. A determination circuit, electrically connected to the data preprocessing circuit, is configured to determine whether the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are accumulated data based on the identifier of the data to be processed and the identifier of the data to be processed in the subsequent processing cycle, and to obtain a determination result. The subsequent processing cycle is the next processing cycle of the current processing cycle. A data normalization circuit, electrically connected to the determination circuit, is configured to normalize the first calculation result and output the normalized first calculation result to the data preprocessing circuit based on the determination result. A data calculation circuit, electrically connected to the data normalization circuit, is configured to process the normalized first calculation result to obtain a second calculation result for the current processing cycle.

[0027] Floating-point numbers include single-precision floating-point numbers (Float) and double-precision floating-point numbers (Double). Floating-point numbers use the IEEE (Institute of Electrical and Electronics Engineers) format. For example, a single-precision value of a floating-point type has 4 bytes, including a sign bit, an 8-bit binary exponent, and a 23-bit mantissa. This representation provides a value in -3.4 for single-precision floating-point types. 10 -38 ~3.4 10 -38 The numerical range between them.

[0028] Figure 1 A schematic diagram of the encoding of a floating-point number according to an embodiment of the present disclosure is shown.

[0029] like Figure 1As shown, floating-point numbers can be represented in computers using encoding methods. Floating-point number encodings include Exponent 110 and Mantissa 120.

[0030] Exponent 110 can represent the range of values ​​for a floating-point number. For example, the more Exponent bits there are, the wider the range that can be represented.

[0031] The precision of a floating-point number can be determined by the mantissa and the exponent; the more mantissas, the higher the precision of the floating-point number.

[0032] The decimal number corresponding to the floating-point number It can be represented as:

[0033]

[0034] Here, Bias is a fixed value, and the value of Bias is set according to the floating-point precision.

[0035] Taking the high-precision floating-point type (Float Point 48, FP48) as an example. An FP48 includes...

[0036] An 8-bit unsigned binary exponent 110 and a 40-bit signed binary mantissa 120. Mantissa 120 is stored in two's complement form.

[0037] For example, in FP48, Mantissa 120 includes a 1-bit sign, a 1-bit int, and 38 fractional bits. The 1-bit sign is located in the most significant bit of Mantissa 120, and the 1-bit int is located in the second most significant bit. In this encoding format, Mantissa 120 requires that the most significant bit and the second most significant bit be different. Therefore, the 1-bit sign and the 1-bit int are distinct.

[0038] For example, 1 bit sign is the sign bit. When 1 bit sign is "0", it represents a positive number. When 1 bit sign is "1", it represents a negative number. The combination of 1 bit sign and 1 bit int is "10" or "01".

[0039] For example, when Exponent 110 is all "1" and Mantissa 120 is not "0" except for 1 bit sign, F represents Not a Number (NAN).

[0040] For example, when Exponent 110 is all "1" and Mantissa 120 has 1 bit sign as "1" and the rest as "0", F represents negative infinity.

[0041] For example, when Exponent 110 is all "1" and Mantissa 120 has 1 bit sign as "0" and all others as "0", F represents positive infinity.

[0042] It should be noted that Nan and Infinity can be defined according to actual needs.

[0043] For example, when Exponent 110 is not "0" and Mantissa 120 is "0", F represents "false zero", and this encoding form is not allowed by default.

[0044] In some embodiments, improvements can be made to the floating-point arithmetic process, such as alignment, mantissa summation, normalization, rounding, and overflow detection, to increase the arithmetic speed and reduce the data waiting period.

[0045] Figure 2 A structural block diagram of a data processor according to an embodiment of the present disclosure is shown.

[0046] like Figure 2 As shown, the processor 200 may include a data preprocessing circuit 210, a determination circuit 220, a data normalization circuit 230, and a data processing circuit 240.

[0047] The data preprocessing circuit 210 includes an input terminal and an output terminal. The data preprocessing circuit 210 is configured to preprocess the data to be processed received via the input terminal to obtain a first calculation result. The data to be processed includes an identifier, and the first calculation result is output via the output terminal.

[0048] In this embodiment of the disclosure, the data to be processed may include first processed data and second processed data.

[0049] For example, the first processing data and the second processing data can be two input data acquired by the data preprocessing circuit 210 in the same processing cycle.

[0050] For example, the first processing data can be intermediate data from the previous processing cycle. The second processing data can be the input data acquired by the data preprocessing circuit 210 in the current processing cycle. At this time, by preprocessing the first and second processing data, the calculation process of the input data acquired in the adjacent processing cycle is completed.

[0051] In this embodiment of the disclosure, preprocessing the first processed data and the second processed data can be performed by shifting and adding the first processed data and the second processed data to obtain the mantissa sum, the larger exponent (max exp), the leading one, and the cut.

[0052] The determination circuit 220 is electrically connected to the data preprocessing circuit. The determination circuit 220 is configured to determine, based on the identifier of the data to be processed and the identifier of the data to be processed in a subsequent processing cycle, whether the data to be processed in the current processing cycle and the data to be processed in a subsequent processing cycle are cumulative data, thus obtaining a determination result. The subsequent processing cycle is the next processing cycle after the current processing cycle.

[0053] In this embodiment of the disclosure, the identifier of the data to be processed can be obtained from a data control signal. This control signal indicates whether the data to be processed in adjacent processing cycles originates from the same address. It should be noted that only data originating from the same address can be accumulated.

[0054] For example, identifiers can be represented in binary, such as "001", "010", "011", etc.

[0055] For example, if both the first and second processed data are identified by "001", it means that the first and second processed data come from the same address, and an accumulation operation can be performed on them. Otherwise, it means that the first and second processed data come from different addresses, and no accumulation operation is performed on them.

[0056] In this embodiment of the disclosure, the determination result indicates whether the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle come from the same address, that is, whether the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are accumulated data.

[0057] For example, if the identifier of the data to be processed in the current processing cycle is the same as the identifier of the data to be processed in the subsequent processing cycle, the determination result indicates that the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are data from the same address.

[0058] For example, if the identifier of the data to be processed in the current processing cycle is different from the identifier of the data to be processed in the subsequent processing cycle, the determination result indicates that the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are data from different addresses.

[0059] It should be noted that the identifiers such as "001", "010", and "011" in the above embodiments are merely illustrative examples and do not constitute a limitation of the embodiments disclosed herein.

[0060] The data normalization circuit 230 is electrically connected to the determination circuit 220. The data normalization circuit 230 is configured to normalize the first operation result and, based on the determination result, output the normalized first operation result to the data preprocessing circuit 210.

[0061] In this embodiment of the disclosure, the first operation result is normalized by normalizing the mantissa sum, the larger exponent max exp, the leading one, and the cut, to obtain the normalized first operation result.

[0062] For example, if the result indicates that the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are data from the same address, the data normalization circuit 230 is configured to output the normalized first operation result to the data preprocessing circuit 210 to realize the operation processing of the data to be processed in the subsequent processing cycle.

[0063] For example, if the result indicates that the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are data from different addresses, since the data from different addresses do not need to be accumulated, the data normalization circuit 230 does not need to output the normalized first operation result to the data preprocessing circuit 210.

[0064] The data processing circuit 240 is electrically connected to the data normalization circuit 230. The data processing circuit 240 is configured to process the normalized first processing result to obtain a second processing result for the current processing cycle.

[0065] In this embodiment of the disclosure, the data processing circuit 240 performs processing on the received normalized first processing result to obtain a second processing result for the current processing cycle. This second processing result is the accumulated result of the data to be processed for the current processing cycle.

[0066] According to embodiments of this disclosure, in multiple processing cycles, the processor determines the data type of the data to be processed in the current processing cycle and the next processing cycle. This allows, in cases where the data to be processed is cumulative data, intermediate data from the current processing cycle to be input into the next processing cycle for data preprocessing, thereby improving data processing speed and avoiding excessively long data waiting times in the next processing cycle.

[0067] It is understood that the determining circuit 220 in this embodiment can be a process of remapping data based on the determining result, including the selection process of mantissa sum, exponent exp, cut, and leading one. The remapping shown is related to the addition mode (single addition or cumulative addition) of the floating-point number, the data type (integer or floating-point), and the data bit width. The determining process can use control signals to adjust the output result.

[0068] Figures 3A-3B A schematic diagram of data to be processed in a series of processing cycles according to an embodiment of the present disclosure is shown.

[0069] like Figure 3A As shown, the data preprocessing circuit includes at least two input terminals, namely Input1 and Input2. Input1 and Input2 are used to receive the data to be processed.

[0070] In this embodiment of the disclosure, in each processing cycle, Input1 and Input2 receive only one piece of data to be processed or no input data. It should be noted that the interval between the rising edges of adjacent processing cycles represents one clock cycle T.

[0071] For example, after the circuit is reset, Input1 sequentially receives the data to be processed: Data1, Data3, Data4, Data5, Data7, ... . Input2 sequentially receives the data to be processed: Data2, 0, 0, Data6, Data8, ... . "0" indicates that no input data exists.

[0072] It should be noted that in the first processing cycle after the circuit reset, before the data to be processed is input to the data preprocessing circuit, the data to be processed is processed by register staking (i.e., delayed by one clock cycle). At this time, the data to be processed acquired in the post-processing cycle is input to the data preprocessing circuit so that the data type of the data to be processed in the current processing cycle and the data to be processed in the post-processing cycle can be determined during the data determination process.

[0073] For example, in the first processing cycle T1 after the circuit reset, one piece of data to be processed can be received simultaneously through Input1 and Input2. For example, Input1 receives Data1, and Input2 receives Data2. Data1 and Data2 are data from the same address.

[0074] For example, after Input1 and Input2 receive Data1 and Data2, but before performing preprocessing on Data1 and Data2, Data1 and Data2 are delayed (i.e., delayed by one clock cycle, entering the second processing cycle T2 after circuit reset). At this time, Input1 receives Data3, and Input2 has no input data.

[0075] For example, preprocessing Data1 and Data2 can be performed in the second processing cycle T2 after circuit reset, preprocessing the delayed Data1 and Data2, and using Data3 to determine whether the delayed Data1 and Data2 are data from the same address. Based on the determination result, the accumulation operation of Data3 with Data1 and Data2 is completed.

[0076] For example, if Data3 comes from the same address as Data1 and Data2, the intermediate data generated by Data1 and Data2 during the operation is normalized, and the normalized operation result and Data3 are delayed (i.e., entering the third processing cycle T3) to realize the summation of Data1 and Data2 and the summation of Data3.

[0077] For example, in the third processing cycle T3 after the circuit reset, Data4 is received through Input1, while no data is input to Input2. At this time, the sum of Data1 and Data2, along with Data3, is preprocessed, and it is determined whether Data4 and Data3 originate from the same address.

[0078] For example, if Data4 and Data3 are data from the same address, the sum of Data1, Data2 and Data3 and Data4 are normalized, and the normalized result is delayed before entering the fourth processing cycle T4.

[0079] For example, such as Figure 3A As shown, in the fourth processing cycle T4 after the circuit reset, Data5 is received through Input1 and Data6 is received through Input2.

[0080] The identifiers for Data4, Data5, and Data6 are determined by the circuit, and the determination result is obtained.

[0081] For example, if the result indicates that Data5 and Data4 are data from different addresses, and Data5 and Data6 are data from the same address, then in the fourth processing cycle T4, Data5 and Data6 are preprocessed, normalized, and processed to obtain the calculation result for Data5 and Data6.

[0082] This process continues sequentially, completing the calculations for Data7, Data8, and so on.

[0083] like Figure 3B As shown, after the circuit is reset, it sequentially receives the data to be processed, Data1, 0, Data3, Data4, Data6, ..., through Input1. It sequentially receives the data to be processed, Data2, 0, 0, Data5, Data7, ..., through Input2.

[0084] For example, in the first processing cycle T1 after the circuit reset, Input1 receives Data1 and Input2 receives Data2. Preprocessing the delayed Data1 and Data2 yields a first calculation result for Data1 and Data2. Then, normalizing and performing calculations on the first calculation result yields a second calculation result for Data1 and Data2.

[0085] For example, in the second processing cycle T2 after the circuit reset, neither Input1 nor Input2 has any input data. The flag bit of Data2 is used to determine whether Data2 is the last input data.

[0086] For example, if Data2 is not the last input data, then in the second processing cycle T2, the preprocessed and normalized results of Data1 and Data2 can be delayed (i.e., entering the third processing cycle T3 after the circuit reset).

[0087] For example, if Data2 is the last input data, then Data1 and Data2 will be processed to obtain the result of the operation, and the accumulation process will end.

[0088] For example, in the third processing cycle T3 after the circuit is reset, Input1 receives Data3, while Input2 has no input data.

[0089] For example, if Data2 is not the last input data, determine whether Data3 comes from the same address as Data1 and Data2. If Data3 comes from the same address as Data1 and Data2, then perform the summation operation of Data3 with Data1 and Data2 based on the result of the second processing cycle T2 and Data3.

[0090] For example, in the fourth processing cycle T4 after the circuit is reset, Data4 is received through Input1 and Data5 is received through Input2.

[0091] The identifiers for Data3, Data4, and Data5 are determined by the circuit, and the determination result is obtained.

[0092] For example, if the result indicates that Data3 and Data4 are data from different addresses, and Data4 and Data5 are data from the same address, then in the fourth processing cycle T4, Data4 and Data5 are preprocessed, normalized, and processed to obtain the calculation result for Data4 and Data5.

[0093] This process continues sequentially, completing the calculations for Data6, Data7, and so on.

[0094] It should be noted that, Figures 3A-3B The data to be processed received in each processing cycle is merely illustrative and does not constitute a limitation of the embodiments disclosed herein. For example, Figures 3A-3B The data to be processed in the table only indicates the order in which the data was acquired, not the order in which the data was compared. Furthermore, in each processing cycle, Input1 and Input2 may or may not contain input data. The data type and whether the data is the last piece of data to be processed are determined by the data's identifier and flag bits to complete the data computation process.

[0095] Figure 4 A structural block diagram of a data processor according to another embodiment of the present disclosure is shown.

[0096] like Figure 4 As shown, the processor 400 includes a data preprocessing circuit 410, a determination circuit 420, a data normalization circuit 430, a data processing circuit 440, and a second register 450.

[0097] The data preprocessing circuit 410 includes an input terminal and an output terminal. The data preprocessing circuit 410 is configured to preprocess the data to be processed received via the input terminal to obtain a first calculation result. The data to be processed includes an identifier, and the first calculation result is output via the output terminal.

[0098] In this embodiment of the disclosure, the data preprocessing circuit 410 includes a shift-order sub-circuit 411 and a first operation sub-circuit 412.

[0099] The shift alignment sub-circuit 411 includes at least two input terminals and an output terminal. The shift alignment sub-circuit 411 is configured to perform shift alignment processing on the data to be processed received via the input terminals to obtain first intermediate data.

[0100] The first operational sub-circuit 412 is configured to perform operations on the first intermediate data to obtain the first operational result.

[0101] According to embodiments of this disclosure, shifting and aligning the data to be processed includes obtaining an exponent difference based on the exponent bits of the first processed data and the second processed data. Based on the exponent difference, the first processed data and the second processed data are logically shifted to align the exponent bits of the first processed data and the second processed data, resulting in first intermediate data.

[0102] For example, in the first processing cycle T1 after circuit reset, processor 400 receives first processed data 0x4580_1000_0000 and second processed data 0x43af_09dc_0000. After delaying 0x4580_1000_0000 and 0x43af_09dc_0000, they are input to shift alignment circuit 411. Here, 0x4580_1000_0000 and 0x43af_09dc_0000 are data from the same address.

[0103] In the second processing cycle T2, the third processed data received via the input of the shift pair circuit 411 is 5ebf_f000_0000. It should be noted that, for ease of understanding of the floating-point FP48 representation, the hexadecimal FP48 representation will be used as an example.

[0104] It is understandable that in the first processing cycle T1 after the circuit reset, the data to be processed received by the processor needs to be delayed so that the data to be processed received in the first processing cycle T1 and the data to be processed received in the second processing cycle T2 are processed in the same cycle to confirm the data type and complete the data accumulation operation. It should be noted that in subsequent processing cycles after the first processing cycle T1 after the circuit reset, there is no need to delay the data to be processed received at the input terminal.

[0105] For example, the exponent exp1 of 0x4580_1000_0000 is 45, and the mantissa1 is 80_1000_0000. The exponent exp2 of 0x43af_09dc_0000 is 43, and the mantissa2 is af_09dc_0000. Therefore, the larger exponent of 0x4580_1000_0000 and 0x43af_09dc_0000 is max_exp1 = 45. The difference in exponents between 0x4580_1000_0000 and 0x43af_09dc_0000 is exp_sft1 = 2.

[0106] Shifting the mantissa a_f_09dc_0000 two bits to the right according to exp_sft1, we get the Mantissa2' of 0x43af_09dc_0000 as eb_c277_0000. Then, based on the shifted eb_c277_0000, we obtain the truncation cut1 = 3'b0. It should be noted that 3'b0 represents 3 bits of binary 0, i.e., "000".

[0107] For example, the first intermediate data may include Mantissa2', the larger exponent max_exp1, the exponent difference exp_sft1, and the truncation cut1.

[0108] According to embodiments of this disclosure, the first arithmetic sub-circuit 412 is configured to perform arithmetic and carry correction on the mantissa of the first processed data and the mantissa of the second processed data to obtain a first arithmetic result. The first arithmetic result includes the mantissa and mantissa_sum, the larger exponent bit max_exp, the leading one, and the cut bit.

[0109] For example, based on the mantissa and mantissa_sum in the first operation result, the larger exponent bit max_exp is adjusted. If a "1" is carried over to the highest bit of both the mantissa and mantissa_sum, the larger exponent bit needs to be incremented by "1". Otherwise, no adjustment is needed for the larger exponent bit.

[0110] In this embodiment, the mantissa and mantissa_sum are the sum of the mantissas of the first processed data and the mantissas of the second processed data after shifting and alignment (i.e., the sum of the mantissas of mantissa1 and mantissa2'). The larger exponent, max_exp, is the larger exponent between the exponents of the first and second processed data. The leading one is obtained based on the mantissa and mantissa_sum, and is used to indicate redundant sign bits. The truncation is the mantissa bits truncated after shifting and alignment of the processed data with the smaller exponent between the exponents of the first and second processed data.

[0111] For example, following the above embodiment, the mantissa1 80_1000_0000 and mantissa2 eb_c277_0000 are summed and carry corrected to obtain mantissa_sum1 = eb_c277_0000 + 80_1000_0000 + 0 (carry correction) = 16b_d277_0000. mantissa_sum1 is the mantissa of a 41-bit signed number.

[0112] It should be noted that in the first processing cycle after the circuit is reset, the carry correction is set to "0" by default.

[0113] It is understood that the carry correction value in this embodiment is either "0" or "1". The carry correction value is obtained based on the cumulative sum of the current processing cycle, the data size of the next processing cycle, and the value corresponding to the three cut bits.

[0114] For example, if the data in the next processing cycle is greater than the cumulative sum of the current processing cycle, the carry correction value is "0".

[0115] For example, if the data in the next processing cycle is less than or equal to the cumulative sum of the current processing cycle, the carry correction is determined by whether the value corresponding to the three-digit cut is greater than 0.5. For example, if cut=001, then the value corresponding to cut is 0.125. If the value corresponding to cut is greater than 0.5, the carry correction value is "1". Otherwise, the carry correction value is "0".

[0116] According to mantissa_sum1(16b_d277_0000), the value corresponding to leading one is lead_num1=0.

[0117] In this embodiment of the disclosure, the leading one is obtained based on the number of identical digits in the mantissa_sum and the number of identical digits in the first few digits. For example, in mantissa_sum1 (16b_d277_0000), the hexadecimal "6" can be represented as "0110" in binary, and the number of identical digits in the first two digits is 0, so lead_num1 = 0.

[0118] It should be noted that the mantissa addition part includes, but is not limited to, addition circuits (such as half adders, full adders, carry-lookahead adders, etc.), and can also be selected from the technology library based on timing, area, and power consumption. In addition, the calculation method of leading one is not limited to the "from high bit to low bit" method shown in the above embodiments, but can also be from "low bit to high bit", "binary search", or other methods.

[0119] It is understandable that the first calculation result obtained by processing the first and second data includes mantissa_sum1, max_exp1, lead_num1, and cut1.

[0120] The determination circuit 420 is electrically connected to the output terminal of the first operational sub-circuit 412. The determination circuit 420 is configured to determine whether the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are accumulated data based on the identifier of the data to be processed and the identifier of the data to be processed in the subsequent processing cycle, and obtain a determination result.

[0121] For example, following the above embodiment, the determining circuit 420 determines whether 5ebf_f000_0000 is data from the same address as 0x4580_1000_000 and 0x43af_09dc_0000 based on the identifiers 0x4580_1000_000 and 0x43af_09dc_0000.

[0122] If the identifiers 0x4580_1000_000, 0x43af_09dc_0000, and 5ebf_f000_0000 are the same, it means that 5ebf_f000_0000, 0x4580_1000_000, and 0x43af_09dc_0000 are data from the same address. In this case, the accumulated result of 0x4580_1000_000 and 0x43af_09dc_0000 is then processed with 5ebf_f000_0000 to obtain the accumulated result for consecutive processing cycles.

[0123] If the identifiers 0x4580_1000_000, 0x43af_09dc_0000, and 5ebf_f000_0000 are different, it means that 5ebf_f000_0000 comes from a different address than 0x4580_1000_000 and 0x43af_09dc_0000, and therefore no operation is performed on 5ebf_f000_0000. Alternatively, if data with the same address as 5ebf_f000_0000 exists in the same processing cycle as the input 5ebf_f000_0000, then operation is performed between 5ebf_f000_0000 and that data.

[0124] The data normalization circuit 430 is electrically connected to the output of the determination circuit 420. The data normalization circuit 430 is configured to normalize the first operation result and, based on the determination result, output the normalized first operation result to the shift alignment sub-circuit 411.

[0125] According to embodiments of the present disclosure, the data normalization circuit 430 includes a data normalization sub-circuit 431 and a first register 432.

[0126] The data normalization sub-circuit 431 is electrically connected to the determination circuit 420. The data normalization sub-circuit 431 is configured to normalize the first operation result to obtain a normalized first operation result.

[0127] The first register 432 is electrically connected to the data normalization sub-circuit 431. The first register 432 is configured to delay the normalized first operation result to obtain a delayed first operation result. Based on the determined result, the delayed first operation result is output to the data preprocessing circuit. The delayed first operation result is used to preprocess the data to be processed in the subsequent processing cycle, thereby completing the processing of the data to be processed in the subsequent processing cycle.

[0128] In this embodiment of the disclosure, normalizing the first operation result can be achieved by concatenating and shifting the mantissa, mantissa_sum, and cut in the first operation result based on the leading one in the first operation result, thereby obtaining the normalized first operation result.

[0129] For example, following the above embodiment, based on lead_num1=0, mantissa_sum1 16b_d277_0000 and cut1 3'b0 are concatenated to obtain 16b_d277_0000_3'b0. Then, 16b_d277_0000_3'b0 is shifted left by 0 bits to obtain b5e_93b8_0000.

[0130] For example, the normalized first operation result, such as b5e_93b8_0000 (i.e., the data concatenated from mantissa_sum1 and cut1), max_exp1, lead_num1, mantissa_sum1, and 5ebf_f000_0000, undergoes a delay processing through the first register 432 and is then input to the shift pair circuit 411. That is, the operation process of the data to be processed, 5ebf_f000_000, is completed in the third processing cycle T3 after the circuit reset.

[0131] It should be noted that in the first processing cycle after the circuit is reset, the acquired data to be processed is delayed. This delay can also be performed using the first register 432. In other words, the data delay process can be completed using the first register 432, which simplifies the circuit structure and improves the circuit integration.

[0132] The data processing circuit 440 is electrically connected to the first register 432. The data processing circuit 440 is configured to process the normalized first operation result to obtain a second operation result for the current processing cycle.

[0133] According to embodiments of the present disclosure, the data processing circuit 440 includes a rounding sub-circuit 441, an overflow check sub-circuit 442, and a post-rounding sub-circuit 443.

[0134] The rounding sub-circuit 441 is configured to round the normalized first operation result to obtain the rounded first operation result.

[0135] The overflow check sub-circuit 442 is configured to perform an overflow check on the first operation result after rounding, and obtain the overflow check result.

[0136] The rounding sub-circuit configuration 443 is used to perform rounding on the first operation result after rounding based on the overflow check result, so as to obtain the second operation result for the current processing cycle.

[0137] For example, following the above embodiment, the sum b5e_93b8_0000 in the normalized first operation result is rounded to obtain the rounded result b5_e93b_8000, and the new cut1'=4'b0. After rounding, the exponent is carried over by "1".

[0138] It is understandable that rounding is required for the cut to avoid the accumulation of additive errors, typically using the "round to the nearest whole number" method. When higher precision is required, round to even (even-number rounding) or other methods can also be used. Furthermore, in some embodiments, the rounding operation can be selected based on the scenario and the area and power consumption.

[0139] For example, an overflow check confirms that the result after rounding has not overflowed. Furthermore, a post-rounding operation is performed on the rounded result, yielding 46b5_e93b_8000. Therefore, the cumulative result of the operation on 0x4580_1000_0000 and 43af_09dc_0000 obtained in the first processing cycle T1 is 46b5_e93b_8000.

[0140] In the embodiments of this disclosure, regardless of the determination result output by the determination circuit 420, the data processing circuit 440 can output a second calculation result for the current processing cycle for the data to be processed obtained in the current processing cycle. This second calculation result is the calculation result for the data to be processed obtained in the current processing cycle.

[0141] For example, if the determination result output by the determination circuit 420 indicates that 5ebf_f000_0000, 0x4580_1000_000, and 0x43af_09dc_0000 are data from the same address, the first register 432 outputs the delayed first operation result to the shift pair sub-circuit 411 to complete the operation processing of the data to be processed 5ebf_f000_0000 in the second processing cycle T2.

[0142] For example, in the first operation result, max_exp1 is 45, and the mantissa_sum1 is b5e_93b8_0000. In the third processed data 5ebf_f000_0000, the exponent exp3 is 5e, and the mantissa3 is bf_f000_0000.

[0143] For example, by comparing the exponent bits max_exp1 and exp3, the larger exponent bit max_exp2 is found to be 5e. The difference in exponent bits exp_exp2 = 0x5e - 0x46 = 0x18 = 24.

[0144] For example, based on the exponent difference exp_sft2=24, concatenating mantissa_sum1 (b5e_93b8_0000) and cut1 (3'b0) and shifting them 24 bits to the right yields ff_ffff_b5e9. At this point, cut2=3b_8000_0000. Retaining three bits from cut2 gives cut2' as "0b001".

[0145] The mantissas ff_ffff_b5e9 and bf_f000_0000 are summed and corrected to obtain mantissa_sum2 = ff_ffff_b5e9 + bf_f000_0000 + 0 (carry correction) = 1bf_efff_b5e. Based on 1bf_efff_b5e, lead_num2 = 1.

[0146] In the third processing cycle T3, the first normalized operation result is bef_fffb_5e92 (i.e., the data concatenated from the new mantissa_sum2 and cut2), max_exp2, lead_num2, and the new data to be processed. Processing the first normalized operation result yields the accumulated result for the second processing cycle. The first normalized operation result is then delayed and output to the shift pair circuit 411. This process continues in a loop to complete the data processing in subsequent cycles.

[0147] In some embodiments, such as Figure 4 As shown, the memory provided in this disclosure may further include a second register 450, electrically connected to the data processing circuit 400. The second register 450 is configured to store the second operation result from the data processing circuit.

[0148] In this embodiment of the disclosure, the second register 450 may be a built-in cache unit.

[0149] For example, the second register 450 may include multiple cache sub-units. The first cache sub-unit is used to store the result of the second operation.

[0150] For example, the second register 450 may also include different cache partitions, one of which is used to store computation data.

[0151] In some embodiments, the processor provided in this disclosure can also be used to implement integer accumulation operations, and to support accumulation operations of a pair of large-width integers or multiple pairs of small-width integers.

[0152] For example, for the accumulation operation of integer data, multiple segments of integer data can be accumulated.

[0153] For example, in FP48 computation, the mantissa is 40 bits. Therefore, a 40-bit adder can be used to implement the accumulation operation. An unsigned adder can be used for the computation.

[0154] For example, two 20-bit adders (e.g., 20-bit + 20-bit) can be used to perform addition operations on two integers. Note that carry or borrow should be corrected.

[0155] For example, two 15-bit adders (such as 15-bit + 15-bit) can be used to perform addition operations on two integers.

[0156] Furthermore, it can be extended to 60-bit integer accumulation. Since the longest path width is 40 bits, a 60-bit adder can also be used to calculate the addition of two pairs of 30-bit integers, provided the timing is met. Similarly, by combining these, a 48-bit adder can also be used to calculate the addition of two pairs of 34-bit integers and 19-bit integers.

[0157] It's understandable that no leading one is generated during integer operations. Integer operations further optimize computation speed compared to floating-point operations.

[0158] According to embodiments of this disclosure, by comparing the identifier of the data to be processed in the current processing cycle with the identifier of the data to be processed in the subsequent processing cycle, it is determined whether the data in adjacent processing cycles is accumulated data. If the data in adjacent processing cycles is accumulated data, the intermediate data generated in the current processing cycle is input to the subsequent processing cycle to perform the accumulation operation on the data to be processed in the subsequent processing cycle. This process eliminates the need to wait until the data processing cycle in the current processing cycle is completed before proceeding to the next processing cycle, effectively improving data processing efficiency, reducing data waiting time, and thus improving processor performance.

[0159] Furthermore, the embodiments provided in this disclosure only require a delay in processing the data to be processed acquired in the first processing cycle after the circuit reset, so that the data to be processed acquired in the first processing cycle and the data to be processed acquired in the second processing cycle are in the same processing cycle for data type confirmation. Based on the confirmation result, the intermediate calculation result of the preprocessing cycle is output to the postprocessing cycle. The data to be processed acquired in the postprocessing cycle does not need to wait for the data processing in the preprocessing cycle to be completed before it is calculated, effectively improving the data processing efficiency.

[0160] It should be noted that the data to be processed in the above embodiments are merely illustrative examples to help those skilled in the art understand the solutions provided in this disclosure, and do not constitute a limitation on the embodiments of this disclosure.

[0161] Figure 5 This is a block diagram of an electronic device with a data processor applicable according to an embodiment of the present disclosure. Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0162] like Figure 5As shown, the electronic device 500 described in this embodiment includes a processor 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage portion 508 into a random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the processor according to embodiments of this disclosure.

[0163] RAM 503 stores various programs and data required for the operation of system 500. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 performs various operations of the processor according to embodiments of the present disclosure by executing programs in ROM 502 and / or RAM 503. It should be noted that the programs may also be stored in one or more memories other than ROM 502 and RAM 503. Processor 501 may also perform various operations of the processor according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0164] According to embodiments of this disclosure, the electronic device 500 may further include an input / output (I / O) interface 505, which is also connected to the bus 504. The system 500 may also include one or more of the following components connected to the I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A driver 510 is also connected to the I / O interface 505 as needed.

[0165] It should be noted that the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0166] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of processors, circuits, and electronic devices according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0167] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0168] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A data processor, comprising: Data preprocessing circuit, including input and output terminals; The data preprocessing circuit is configured to preprocess the data to be processed received via the input terminal to obtain a first operation result, wherein the data to be processed includes an identifier, and the first operation result is output via the output terminal; the data to be processed includes first processed data and second processed data, the first processed data is the intermediate data of the previous processing cycle of the current processing cycle, and the second processed data is the input data acquired by the data preprocessing circuit in the current processing cycle; the preprocessing includes shifting and alignment processing and addition processing on the first processed data and the second processed data to obtain the mantissa sum of the first processed data and the second processed data, the larger exponent bit, the leading 1, and the truncation bit; A determination circuit, electrically connected to the data preprocessing circuit, is configured to determine whether the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are accumulated data based on the identifier of the data to be processed and the identifier of the data to be processed in the subsequent processing cycle, and obtain a determination result; wherein, the subsequent processing cycle is the next processing cycle after the current processing cycle; if the identifier of the data to be processed in the current processing cycle is the same as the identifier of the data to be processed in the subsequent processing cycle, the determination result indicates that the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are data from the same address, and an accumulation operation is performed on the first processed data and the second processed data; if the identifier of the data to be processed in the current processing cycle is different from the identifier of the data to be processed in the subsequent processing cycle, the determination result indicates that the data to be processed in the current processing cycle and the data to be processed in the subsequent processing cycle are data from different addresses, and no accumulation operation is performed on the first processed data and the second processed data; A data normalization circuit, electrically connected to the determining circuit, is configured to normalize the first calculation result; and output the normalized first calculation result to the data preprocessing circuit based on the determining result. A data processing circuit, electrically connected to the data normalization circuit, is configured to process the normalized first processing result to obtain a second processing result for the current processing cycle. The data normalization circuit includes a first register configured to delay the normalized first operation result to obtain a delayed first operation result; and to output the delayed first operation result to the data preprocessing circuit according to the determined result; wherein the delayed first operation result is used to preprocess the data to be processed in the post-processing cycle to complete the processing of the data to be processed in the post-processing cycle.

2. The processor according to claim 1, wherein, The data normalization circuit includes: A data normalization sub-circuit, electrically connected to the determining circuit, is configured to normalize the first calculation result to obtain a normalized first calculation result; The first register is electrically connected to the data normalization sub-circuit.

3. The processor according to claim 1, wherein, The data processing circuit includes: The rounding sub-circuit is configured to round the normalized first calculation result to obtain the rounded first calculation result; An overflow check sub-circuit is configured to perform an overflow check on the rounded first operation result to obtain an overflow check result. The rounding sub-circuit is configured to perform a rounding process on the first rounded operation result based on the overflow check result, so as to obtain a second operation result for the current processing cycle.

4. The processor according to claim 1, wherein, The data preprocessing circuit includes: The shift alignment sub-circuit is configured to perform shift alignment processing on the data to be processed to obtain the first intermediate data; The first operational sub-circuit is configured to perform operations on the first intermediate data to obtain the first operational result.

5. The processor according to claim 4, wherein, The data to be processed includes first processed data and second processed data, both of which include an exponent and a mantissa; wherein, the shift pair circuit is further configured as follows: The difference in exponents is obtained based on the exponents of the first processed data and the exponents of the second processed data; Based on the exponent difference, the first processed data and the second processed data are logically shifted to align the exponent bits of the first processed data and the exponent bits of the second processed data, thereby obtaining the first intermediate data.

6. The processor according to claim 5, wherein, The first operational sub-circuit is further configured as follows: The mantissa of the first processed data and the mantissa of the second processed data are calculated and carried over to obtain the first calculation result; wherein, the first calculation result includes the sum of the mantissas, the larger exponent, the leading 1, and the truncation. The sum of the last digits is the sum of the last digits of the first processed data and the last digits of the second processed data; The larger exponent is the larger exponent between the exponent of the first processed data and the exponent of the second processed data. The leading 1 is obtained based on the sum of the mantissas, and the leading 1 is used to indicate redundant sign bits; The truncation is the mantissa removed after shifting and aligning the exponents of the first and second processed data, where the exponent is smaller.

7. The processor according to claim 6, wherein, The data normalization sub-circuit is configured as follows: Based on the preceding 1, the mantissa and the truncation are concatenated and shifted to obtain the normalized first operation result.

8. The processor according to claim 1, wherein, Also includes: The second register is electrically connected to the data processing circuit and is configured to store the second processing result from the data processing circuit.

9. The processor according to claim 1, wherein, The accumulated data consists of data to be processed in adjacent processing cycles, and the accumulated data comes from the same address.

10. An electronic device, comprising: At least one data processor according to any one of claims 1 to 9.

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