Graphics processor, operating method, and machine-readable storage medium

Abstract

A graphics processor (GPU), an operating method, and a machine-readable storage medium are provided. The GPU includes a command processor circuit and a geometry pipeline circuit. The command processor circuit sends a current primitive block to the geometry pipeline circuit for geometry processing. The geometry pipeline circuit decides to enable coarse-grained depth testing or fine-grained depth testing according to a hardware descriptor. When the geometry pipeline circuit enables the fine-grained depth testing, the geometry pipeline circuit performs fine-grained depth testing culling on a plurality of primitives of the current primitive block sent by the command processor circuit to the geometry pipeline circuit, stores fine-grained depth testing results in a fine-grained depth buffer, and discards drawing of the current primitive block.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a graphics processor, a method of operation, and a machine-readable storage medium. Background Technology

[0002] A Graphics Processing Unit (GPU), also known as a display core, video processor, display chip, or graphics chip, is a microprocessor specifically designed to perform graphics calculations (such as rendering) on ​​personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones). To enhance the realism of rendered scenes, shadow rendering is a crucial technique.

[0003] A typical method for shadow rendering is shadow mapping. Shadow mapping consists of two passes. The first pass renders the scene from the perspective of the light sources, generating depth information of scene objects in a depth buffer. Typically, a scene contains multiple light sources, so the first pass needs to generate a depth buffer for each light source. More complex algorithms generate depth buffers of different resolutions for each light source to improve the memory access efficiency of the second pass, shading. The second pass renders the entire scene again from the perspective of the actual scene camera, and then determines whether the object portion corresponding to each pixel is in shadow based on the depth information generated in the first pass.

[0004] According to the standard GPU application programming interface (API), a rendering pass must include at least a vertex shading stage, a rasterization stage, and a pixel shading stage. Mapping to GPU hardware architecture, the mainstream architectures include Immediate Mode Rendering (IMR) and Tiled-Based Deferred Rendering (TBDR). These two architectures are fundamental concepts in the industry and will not be discussed in detail here. The TBDR architecture typically consists of two hardware pipelines: a binning pipeline and a rendering pipeline. The binning pipeline mainly handles vertex shading and some preliminary primitive culling techniques, such as back-face culling and coarse / fine depth culling. Surviving primitives are stored in memory at a tile granularity as input to the rendering pipeline. In this context, a tile refers to the smallest unit of the rendering screen divided at a certain granularity. For example, dividing a 512x512 screen into 64x64 granular units, each 64x64 is called a tile. When rendered geometry falls into this tile, the post-vertex information is stored in the tile's memory. The rendering pipeline performs rasterization and pixel shading at the tile granularity. The rendering pipeline takes the vertex shading results from memory as input, using the tile as the granular unit, and performs rasterization and pixel shading. Using tiles as the granular unit significantly reduces the number of read / write operations to external Double Data Rate (DDR) memory, resulting in a significant reduction in external bandwidth requirements and power consumption. Despite these advantages, the TBDR architecture, due to the two operations involved, increases the rendering time of one effective primitive.

[0005] The first pass in shadow mapping is typically a depth-only pass. This means that in most scenarios, the corresponding pixel shading is pass-through, meaning the pixel shading doesn't operate during shadow mapping. However, in the TBDR architecture, the depth-only pass still needs to go through the binning and rendering pipelines completely, which is a significant drawback compared to the IMR architecture. The depth-only pass consumes a very heavy workload in scene rendering. Although in many cases, the pixel shader for the depth pass is pass-through, for mainstream tile-based GPU architectures, the depth pass currently always needs to go through the binning pipeline to execute the vertex shader, and then to the rendering pipeline to execute triangle setup, rasterization, Z-testing, and pixel shader. The entire path time for the depth-only pass is greatly lengthened, significantly impacting the performance of the rendering algorithm. Summary of the Invention

[0006] This invention provides a graphics processing unit (GPU) and its operation method, as well as a machine-readable storage medium, to shorten the time of depth-only passes.

[0007] In an embodiment of the invention, the graphics processor includes a command processor (CP) circuit and a geometry pipeline (GP) circuit. The command processor circuit divides a job chain into rendering tasks for multiple primitive blocks (PBs), where each primitive block includes multiple primitives. The geometry pipeline circuit is coupled to the command processor circuit. The command processor circuit sends one of the multiple primitive blocks to the geometry pipeline circuit for geometry processing. The geometry pipeline circuit determines whether to enable a coarse-grained depth test (coarse Z test) or a fine-grained depth test (fine Z test) based on the hardware descriptor. When the geometry pipeline circuit enables fine-grained depth testing, it performs fine-grained depth test culling on multiple primitives of the current primitive block sent to it by the command processor circuit, stores the fine-grained depth test results in the fine-grained depth buffer, and discards the current primitive block.

[0008] In an embodiment of the present invention, the operation method includes: dividing a task chain into rendering tasks for multiple primitive blocks, wherein each primitive block includes multiple primitives; sending one of the multiple primitive blocks to the geometry pipeline circuit of the graphics processor for geometry processing; the geometry pipeline circuit determining whether to enable coarse-grained depth testing or fine-grained depth testing based on a hardware descriptor; and when the geometry pipeline circuit enables the fine-grained depth testing, the geometry pipeline circuit performs fine-grained depth testing on multiple primitives of the current primitive block sent to the geometry pipeline circuit to eliminate them, storing the fine-grained depth test results in a fine-grained depth buffer, and discarding the drawing of the current primitive block.

[0009] In an embodiment of the invention, the machine-readable storage medium is used to store non-transitory machine-readable instructions. When the non-transitory machine-readable instructions are executed by a computer, the operation method of the graphics processor can be implemented.

[0010] Based on the above, after receiving a task, the geometry pipeline circuit completes the shading task operation according to normal procedures. The geometry pipeline circuit can dynamically determine whether to enable coarse-grained depth testing or fine-grained depth testing based on the hardware descriptor. If fine-grained depth testing is enabled, the geometry pipeline circuit performs fine-grained depth test culling on the primitives and stores / updates the fine-grained depth test results in the fine-grained depth buffer, then discards the drawing (does not send pixel tasks to the stream processor cluster circuit), and returns a job done signal to inform the command processor circuit that the task has been completed. Depth-only passes do not require pass-through to the stream processor cluster circuit (saving pixel task processing time). Therefore, the graphics processor can shorten the time for depth-only passes. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a circuit block of a graphics processing unit (GPU) according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram illustrating, according to an embodiment of the present invention, that a rendered screen is divided into multiple tiles.

[0013] Figure 3 This is a circuit block diagram illustrating a geometric pipeline circuit and a stream processor cluster circuit in a GPU, according to an embodiment of the present invention.

[0014] Figure 4 This is a flowchart illustrating a GPU operation method according to an embodiment of the present invention.

[0015] Explanation of reference numerals in the attached figures

[0016] 100: Graphics Processing Unit (GPU)

[0017] 2DP0: Two-dimensional pipeline

[0018] CDB0: Coarse-grained depth buffer

[0019] CMP0: Calculate Pipeline

[0020] CP1: Command Processor Circuit

[0021] CU0: Computational Unit

[0022] EZ0: Enhanced Depth Testing Module

[0023] FDB0: Fine-grained depth buffer

[0024] GP1_0, GP1_1, GP1_N: Geometric Pipeline Circuit

[0025] GPBE0: Geometric Pipeline Rear End

[0026] GPFE0: Geometric Pipeline Front End

[0027] MEM1: Memory

[0028] PP0: Pixel pipeline

[0029] RTC0: Ray Tracing Core

[0030] SPC1_0, SPC1_4, SPC1_N*4: Stream processor cluster circuit

[0031] S410, S420, S430, S441, S442, S443, S451, S452, S453, S454: Steps

[0032] T0, T1, T2, T3: Primitives

[0033] TC0: Tensor Core

[0034] TIL0: Tiling Module

[0035] TILE0, TILE1, TILE2, TILE3, TILE4, TILE5, TILE6, TILE7, TILE8, TILE9, TILE10, TILE11, TILE12, TILE13, TILE14, TILE15: Tiles

[0036] VPT0: Viewport Transformation Module

[0037] VTG0: Shading Module Detailed Implementation

[0038] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0039] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0040] Figure 1 This is a schematic diagram of a circuit block of a graphics processing unit (GPU) 100 according to an embodiment of the present invention. Figure 1 The GPU 100 shown includes a command processor (CP) circuit CP1 and multiple geometry pipeline circuits (e.g., Figure 1 The circuits shown are GP1_0, GP1_1, and GP1_N, and multiple streaming processor clusters (SPCs) (e.g., Figure 1The diagram shows SPC1_0, SPC1_4, and SPC1_N*4, as well as memory MEM1. Memory MEM1 is a broad concept that can include various levels of on-chip memory, such as cache, high-bandwidth memory (HBM), and double-data-rate (DDR) memory. The number of geometry pipeline circuits and the number of stream processor cluster circuits can be determined according to the actual design. The command processor circuit, geometry pipeline circuit, stream processor cluster circuit, memory, and other subsystems can be connected in any interconnection manner to transmit information. For example, one implementation of interconnection between the subsystems is a network on chip (NOC). Depending on different design requirements, in some embodiments, the above-mentioned command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as hardware circuits. In other embodiments, the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as firmware, software, or a combination of the two. In some other embodiments, the command processor circuitry, geometry pipeline circuitry, and / or stream processor cluster circuitry may be implemented as a combination of hardware, firmware, and software.

[0041] In hardware terms, the aforementioned command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as logic circuits on integrated circuits. For example, the functions of the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented in various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The functions of the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as hardware circuits, such as various logic blocks, modules, and circuits within integrated circuits, using hardware description languages ​​(e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0042] In software and / or firmware form, the functions of the aforementioned command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as programming codes. For example, the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. The semiconductor memory includes memory cards, read-only memory (ROM), flash memory, programmable logic circuits, or other semiconductor memory. The storage device includes tape, disk, hard disk drive (HDD), solid-state drive (SSD), or other storage devices. Electronic devices (e.g., CPUs, controllers, microcontrollers, or microprocessors) can read and execute the programming code from the machine-readable storage medium to implement the functions of command processor circuits, geometry pipeline circuits, and / or stream processor cluster circuits. Alternatively, the programming code can be provided to the electronic device via any transmission medium (e.g., communication networks or broadcast radio waves). The communication network is, for example, the Internet, wired communication networks, wireless communication networks, or other communication media.

[0043] The primary function of the command processor circuit CP1 is to issue task commands to other subsystems within the GPU 100 for execution. Depending on the specific design, CP1 may also include global synchronization, task scheduling, and / or other functions. Geometry pipeline circuits GP1_0 to GP1_N are coupled to CP1. CP1 can divide a job chain into rendering tasks for multiple primitive blocks (PBs), where each primitive block includes multiple primitives. CP1 sends these primitive blocks to GP1_0 to GP1_N for geometry processing according to their order in the job chain. The number of primitives in each primitive block can be determined based on the specific design. In some embodiments, each primitive block includes a draw call. CP1 sends tasks to GP1_0 to GP1_N in parallel, with the draw call as the granularity. For example, the first drawing call is sent to geometry pipeline circuit GP1_0, and the second drawing call is sent to geometry pipeline circuit GP1_1. This continues until the (N+1)th drawing call is sent to geometry pipeline circuit GP1_N. In other embodiments, each primitive block has the same number of primitives. The command processor circuit CP1 divides the task into primitive blocks at a granularity based on the number of primitives, sending tasks in parallel to geometry pipeline circuits GP1_0 through GP1_N. For example, a task chain or drawing call can be divided into multiple primitive blocks at a granularity of 512 primitives (or another number of primitives, determined by the actual design). The first primitive block is sent to geometry pipeline circuit GP1_0, and the second primitive block is sent to geometry pipeline circuit GP1_1. This continues until the (N+1)th primitive block is sent to geometry pipeline circuit GP1_N.

[0044] The geometry pipeline circuits GP1_0 to GP1_N are responsible for geometry-related tasks, such as the task constructors for vertex shading, geometry shading, and tessellation shading. GP1_0 to GP1_N also generate geometry processing results for the pixel pipeline (not shown in the diagram) in the stream processor cluster circuit. Each stream processor cluster circuit mainly includes an arithmetic logic unit (ALU), special function units, load-store units, and tensor cores (not shown in the diagram). Typically, a draw call includes both geometry processing and pixel processing tasks. Command processor circuit CP1 sends geometry processing tasks to geometry pipeline circuits GP1_0 to GP1_N for execution. Then, geometry pipeline circuits GP1_0 to GP1_N generate pixel processing tasks according to tile partitioning and send them to the stream processor cluster circuit (e.g., ...). Figure 1 (SPC1_0, SPC1_4, and SPC1_N*4 are shown). The stream processor cluster circuit performs pixel processing at the granularity of one or more tiles.

[0045] Figure 2 This diagram illustrates, according to an embodiment of the present invention, a rendered screen divided into multiple tiles. Depending on the actual design, each tile can be 32x32 pixels, 64x64 pixels, or other numbers of pixels. Typically, the size of the tiles can be set according to the architecture; larger or smaller tiles are both feasible implementations. Figure 2 In the illustrated embodiment, a screen is divided into 4x4 tiles TILE0, TILE1, TILE2, TILE3, TILE4, TILE5, TILE6, TILE7, TILE8, TILE9, TILE10, TILE11, TILE12, TILE13, TILE14, and TILE15. Primitives are ultimately rendered onto the screen. Primitives can fall within a single tile or span multiple tiles. Figure 2The diagram shows primitives T0, T1, T2, and T3. Primitive T0 covers blocks TILE2, TILE3, TILE8, and TILE9; primitive T1 covers blocks TILE3 and TILE9; primitive T2 covers block TILE0; and primitive T3 covers block TILE1.

[0046] Figure 3 This is a block diagram illustrating a geometric pipeline circuit (e.g., GP1_0) and a stream processor cluster circuit (e.g., SPC1_0) in a GPU 100 according to an embodiment of the present invention. Figure 3 The geometric pipeline circuit GP1_0 and the stream processor cluster circuit SPC1_0 shown can be used as Figure 1 This is one of many embodiments of the geometric pipeline circuit GP1_0 and the stream processor cluster circuit SPC1_0 shown. Figure 1 The other geometric pipeline circuits GP1_1 to GP1_N shown can be deduced by referring to the relevant description of geometric pipeline circuit GP1_0. Figure 1Other stream processor cluster circuits shown can be deduced from the relevant descriptions of the SPC1_0 stream processor cluster circuit, and will not be elaborated further. The command processor circuit CP1 sends a draw call or a primitive block (PB) to a geometry pipeline circuit GP1_0 for geometry processing. The geometry pipeline circuit GP1_0 includes a geometry pipeline front end (GPFE0) and a geometry pipeline back end (GPBE0). The front end and back end are clearer conceptually from a functional perspective, but other names can also be used in practice. The geometry processing performed by the geometry pipeline front end GPFE0 includes constructing shading tasks to send to the GPU 100 stream processor cluster circuits (such as SPC1_0 or other stream processor cluster circuits) for execution. Based on the actual design, the shading tasks include vertex shading tasks, geometry shading tasks, and tessellation shading tasks. The geometry pipeline front-end GPFE0 retrieves post-vertex information for further viewport transformation. Post-vertex information refers to the vertex information after processing by the shaders (such as vertex shaders or other shaders) in the stream processor cluster circuitry, typically including position information and other vertex attributes (such as normals, texture coordinates, etc.). Based on the actual design, the viewport transformation includes one or more primitive culling circuits, such as back-face culling, small triangle culling, etc. Primitives that meet multiple culling conditions will not be sent to the geometry processor back-end.

[0047] As an example, the geometry pipeline front-end GPFE0 includes the shading module VTG0 and the viewport transformation module VPT0. The shading module VTG0 takes the vertices corresponding to the primitives in the received drawing calls (or primitive blocks) and constructs task constructors for the vertex shaders, tessellation shaders, and geometry shaders, then sends them to the stream processor cluster circuitry (e.g., SPC1_0 or other stream processor cluster circuitry) for execution. The viewport transformation module VPT0 sequentially reads the post-vertex information corresponding to the drawing calls (or primitive blocks) from memory MEM1 for further standard graphics operations such as occlusion culling and perspective transformation.

[0048] As an example, the geometry pipeline backend GPBE0 includes an Enhanced Z-test module EZ0 and a tiling module TIL0. In the geometry pipeline backend GPBE0, the Enhanced Z-test module EZ0 can determine whether to enable coarse-grained depth testing or fine-grained depth testing based on the hardware descriptor. For example, when the hardware descriptor indicates that the task for the current primitive includes a depth-only pass (or depth-only task), the Enhanced Z-test module EZ0 chooses to enable the fine-grained depth test; otherwise, it chooses to enable the coarse-grained depth test. As an example, the fine-grained depth test performs depth testing on a pixel-by-pixel basis. The GPU 100 maintains one (or more) depth values ​​for each pixel in the fine-grained depth buffer FDB0. In contrast to the fine-grained depth test, the coarse-grained depth test performs depth testing on a pixel-by-pixel block basis. For example (but not limited to), a pixel block contains 4*4 pixels. The GPU 100 maintains a maximum depth value for each pixel block in the coarse-grained depth buffer CDB0.

[0049] When the Enhanced Depth Test module EZ0 decides to enable fine-grained depth testing, it selectively performs fine-grained depth test culling on the current primitives (the processing results of the geometry pipeline front-end GPFE0), stores the fine-grained depth test results in the fine-grained depth buffer FDB0, and decides to discard the current primitive block. When the geometry pipeline circuit GP1_0 decides to discard the current primitive block, it does not send pixel processing tasks to any stream processor cluster circuits and returns a job done signal to the command processor circuit CP1, indicating that the current primitive block has been completed. After receiving the job done signal from the geometry pipeline circuit GP1_0, the command processor circuit CP1 issues tasks that depend on the fine-grained depth buffer FDB0.

[0050] When the Enhanced Depth Test Module EZ0 decides to enable coarse-grained depth testing, it selectively performs coarse-grained depth test culling on primitives (the processing results of geometry processing at the front end of the geometry pipeline GPFE0) and stores the coarse-grained depth test results in the coarse-grained depth buffer CDB0. When the Enhanced Depth Test Module EZ0 enables coarse-grained depth testing, the pixel pipeline PP0 in the GPU100's stream processor cluster circuit (e.g., SPC1_0 or other stream processor cluster circuits) retrieves the coarse-grained depth test results from the coarse-grained depth buffer CDB0 for fine-grained depth test culling and stores the fine-grained depth test results in the fine-grained depth buffer FDB0. The Tile Module TIL0 places the primitives passed through the coarse-grained depth test module CZ0 into the corresponding tile list for subsequent pixel processing by the stream processor cluster circuit. As an example, Figure 3 A schematic diagram of the block list for blocks TILE0, TILE1, ..., TILE15 is shown.

[0051] The stream processor cluster circuit SPC1_0 includes multiple pixel pipelines PP0 to process the geometric processing results of the geometry pipeline circuits (such as GP1_0 or other geometry pipeline circuits). For example, the pixel pipeline PP0 can further perform triangle setup, rasterization, fine Z test, and pixel shadertask construction on primitives on tiles. The pixel pipeline PP0 performs the fine Z test to output the pixel depth value to the fine depth buffer FDB0. The fine depth buffer FDB0 is read and used in subsequent algorithms of shadow mapping. The stream processor cluster circuit SPC1_0 may also include a compute pipeline CMP0 to handle computational tasks. The stream processor cluster circuit SPC1_0 may also include a 2D pipeline 2DP0 to handle operations such as 2D blit functions and memory copy. The stream processor cluster circuit SPC1_0 contains multiple Compute Units (CU0). Each CU0 includes the GPU100's main numerical computation units, arithmetic logic units (ALUs), special function units, and load-store units (not shown in the diagram). Each pixel task, 2D task, and / or computation task is assigned to a CU0 for execution. The SPC1_0 may also include a ray tracing core (RTC0) to accelerate ray tracing task processing. Furthermore, the SPC1_0 may include a tensor core (TC0) to accelerate matrix and convolution operations.

[0052] Figure 4 This is a flowchart illustrating an operation method of a graphics processing unit (GPU) according to an embodiment of the present invention. In some embodiments, Figure 4 The operating method shown can be implemented in firmware or software (i.e., a program). For example, Figure 4 The operations described can be implemented as non-transitory machine-readable instructions (programming code or program), which can be stored in a machine-readable storage medium. When these non-transitory machine-readable instructions are executed by a computer, they can be implemented... Figure 4The operation method is shown. In other embodiments, Figure 4 The operation method shown can be implemented in hardware, for example, implemented in... Figure 1 The GPU shown is 100.

[0053] Please refer to Figure 3 and Figure 4 In step S410, the command processor circuit CP1 divides a job chain into rendering tasks for multiple primitive blocks (PB), where each primitive block includes multiple primitives. In step S420, the command processor circuit CP1 sends one of the multiple primitive blocks (hereinafter referred to as the current primitive block) to the geometry pipeline circuit GP1_0 for geometry processing. In step S430, the geometry pipeline circuit GP1_0 determines whether to enable coarse-grained depth testing (coarse Z test) or fine-grained depth testing (fine Z test) based on the hardware descriptor. For example, when the hardware descriptor indicates that the task for the current primitive includes a depth-only pass (or depth-only task), the geometry pipeline circuit GP1_0 selects to enable the fine-grained depth test; otherwise, the geometry pipeline circuit GP1_0 selects to enable the coarse-grained depth test.

[0054] For depth-only passes (or depth-only tasks), the corresponding pixel shader is passthrough, meaning it doesn't perform any actual operations during shadow mapping. Therefore, the compiler can identify passthrough pixel shaders during compilation. In typical depth passes, the compiler can identify passthrough characteristics from the pixel shader's syntax. For example, if the main function of a pixel shader is empty, it indicates that the pixel shader performs no functionality, making it a passthrough shader. In this case, the compiler can pass this information to the driver, which then uses the hardware descriptor to instruct the GPU 100 to enable the fine-grained depth test (fine Z test) function of the geometry pipeline circuit GP1_0. Alternatively, the driver can identify that the corresponding rendering pass is not bound to a pixel shader. Therefore, the driver notifies the GPU 100 via the hardware descriptor to enable the fine-grained depth test function of the geometry pipeline circuit GP1_0. After receiving the draw call task, the geometry pipeline circuit GP1_0 completes the vertex shading, geometry shading, and tessellation shading tasks as normal. The strong depth test module EZ0 of the geometry pipeline backend GPBE0 determines whether to enable the coarse-grained depth test (coarse Z test) or the fine-grained depth test (fine Z test) based on the hardware descriptor.

[0055] When the enhanced depth testing module EZ0 of the geometry pipeline circuit GP1_0 enables fine-grained depth testing according to the hardware descriptor, the geometry pipeline circuit GP1_0 performs fine-grained depth testing and culling on the multiple primitives of the current primitive block (step S441), stores the fine-grained depth test results in the fine-grained depth buffer FDB0 (step S442), and discards the drawing of the current primitive block (step S443). When the geometry pipeline circuit GP1_0 discards the drawing of the current primitive block, the geometry pipeline circuit GP1_0 does not send pixel processing tasks to any stream processor cluster circuit, and the geometry pipeline circuit GP1_0 returns a job done signal to the command processor circuit CP1 to indicate that the task of the current primitive block has been completed. After the command processor circuit CP1 receives the job done signal returned by the geometry pipeline circuit GP1_0, the command processor circuit CP1 issues tasks that depend on the fine-grained depth buffer FDB0 to the corresponding subsystems in the GPU 100 for execution. The geometry pipeline circuit GP1_0 can perform depth-only passes, avoiding unnecessary workload in the stream processor cluster circuit and significantly shortening the execution time of depth-only passes. Compared to steps S451 to S454, steps S441 to S443 advance the fine-grained depth testing from the pixel pipeline of the stream processor cluster circuit (e.g., the pixel pipeline PP0 of the stream processor cluster circuit SPC1_0) to the geometry processing stage.

[0056] When the enhanced depth testing module EZ0 of the geometry pipeline circuit GP1_0 enables coarse-grained depth testing according to the hardware descriptor, the geometry pipeline circuit GP1_0 performs coarse-grained depth test rejection on the geometry processing results (step S451) and stores the coarse-grained depth test results in the coarse-grained depth buffer CDB0 (step S452) so that the pixel pipeline PP0 in the stream processor cluster circuit (e.g., SPC1_0 or other stream processor cluster circuits) can perform fine-grained depth test rejection. When the geometry pipeline circuit GP1_0 enables coarse-grained depth testing, the pixel pipeline PP0 retrieves the coarse-grained depth test results from the coarse-grained depth buffer CDB0 for fine-grained depth test rejection (step S453) and stores the fine-grained depth test results in the fine-grained depth buffer FDB0 (step S454).

[0057] In summary, after receiving a task, the geometry pipeline circuit GP1_0 completes the shading task operation according to normal procedures. GP1_0 can dynamically determine whether to enable coarse-grained depth testing or fine-grained depth testing based on the hardware descriptor. If GP1_0 enables fine-grained depth testing, it performs fine-grained depth test culling on the primitives and stores / updates the fine-grained depth test results in the fine-grained depth buffer FDB0, then discards the drawing (does not send pixel tasks to the stream processor cluster circuit), and returns a job done signal to the command processor circuit CP1 to inform it that the primitive block task is complete. Depth-only passes do not require pass-through to the stream processor cluster circuit (saving pixel task processing time). Therefore, GPU 100 can shorten the time for depth-only passes.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A graphics processor, characterized in that, The graphics processor includes: Command processor circuitry for dividing a task chain into rendering tasks for multiple primitive blocks, where each primitive block comprises multiple primitives; and A geometry pipeline circuit, coupled to the command processor circuit, wherein the command processor circuit sends one of the plurality of primitive blocks to the geometry pipeline circuit for geometry processing, and the geometry pipeline circuit determines whether to enable coarse-grained depth testing or fine-grained depth testing based on a hardware descriptor. When the geometry pipeline circuit enables the fine-grained depth test, the geometry pipeline circuit performs fine-grained depth test culling on the plurality of primitives of the current primitive block sent to the geometry pipeline circuit by the command processor circuit, stores the fine-grained depth test results in a fine-grained depth buffer, and discards the drawing of the current primitive block. Specifically, when the hardware descriptor indicates that the task for the current primitive block includes a depth-only task, the geometry pipeline circuit selects to enable the fine-grained depth test; otherwise, the geometry pipeline circuit selects to enable the coarse-grained depth test. The pixel shader corresponding to the depth-only task is pass-through.

2. The graphics processor according to claim 1, characterized in that, When the geometry pipeline circuit discards the drawing of the current primitive block, the geometry pipeline circuit does not send pixel processing tasks to the stream processor cluster circuit of the graphics processor, and the geometry pipeline circuit returns a task completion signal to the command processor circuit to indicate that the current primitive block has been completed.

3. The graphics processor according to claim 1, characterized in that, The geometric processing includes: Construct a shading task and send the shading task to the streaming processor cluster circuitry of the graphics processor for execution; and Retrieve the vertex information processed by the stream processor cluster circuit for further viewport transformation.

4. The graphics processor according to claim 3, characterized in that, The shading tasks include vertex shading tasks, geometry shading tasks, and surface tessellation shading tasks.

5. The graphics processor according to claim 3, characterized in that, The viewport transformation includes backface culling or small primitive culling.

6. The graphics processor according to claim 1, characterized in that, When the geometry pipeline circuit enables the coarse-grained depth test, the geometry pipeline circuit performs coarse-grained depth test rejection on the processing results of the geometry processing, and stores the coarse-grained depth test results in a coarse-grained depth buffer so that fine-grained depth test rejection can be performed on the pixel pipeline in the stream processor cluster circuit of the graphics processor.

7. The graphics processor according to claim 6, characterized in that, When the geometric pipeline circuit enables the coarse-grained depth test, the pixel pipeline retrieves the coarse-grained depth test result from the coarse-grained depth buffer to perform the fine-grained depth test rejection, and stores the fine-grained depth test result in the fine-grained depth buffer.

8. The graphics processor according to claim 2, characterized in that, After receiving the task completion signal, the command processor circuit issues a task that depends on the fine-grained depth buffer.

9. A method for operating a graphics processor, characterized in that, The operation method includes: A task chain is divided into rendering tasks for multiple primitive blocks, where each primitive block includes multiple primitives. One of the plurality of primitive blocks is sent to the geometry pipeline circuitry of the graphics processor for geometry processing; The geometry pipeline circuitry determines whether to enable coarse-grained depth testing or fine-grained depth testing based on the hardware descriptor; and When the geometry pipeline circuit enables the fine-grained depth test, the geometry pipeline circuit performs fine-grained depth test rejection on the plurality of primitives of the current primitive block sent to the geometry pipeline circuit, stores the fine-grained depth test results in the fine-grained depth buffer, and discards the drawing of the current primitive block. The operation method further includes: When the hardware descriptor indicates that the task for the current primitive block includes a depth-only task, the geometry pipeline circuit selects to enable the fine-grained depth test; otherwise, the geometry pipeline circuit selects to enable the coarse-grained depth test. The pixel shader corresponding to the depth-only task is pass-through.

10. The operating method according to claim 9, characterized in that, The operation method further includes: When the geometry pipeline circuit discards the drawing of the current primitive block, the geometry pipeline circuit does not send pixel processing tasks to the stream processor cluster circuit of the graphics processor, and the geometry pipeline circuit returns a task completion signal to the command processor circuit to indicate that the current primitive block has been completed.

11. The operating method according to claim 9, characterized in that, The geometric processing includes: Construct a shading task and send the shading task to the streaming processor cluster circuitry of the graphics processor for execution; and Retrieve the vertex information processed by the stream processor cluster circuit for further viewport transformation.

12. The operating method according to claim 11, characterized in that, The shading tasks include vertex shading tasks, geometry shading tasks, and surface tessellation shading tasks.

13. The operating method according to claim 11, characterized in that, The viewport transformation includes backface culling or small primitive culling.

14. The operating method according to claim 9, characterized in that, The operation method further includes: When the geometry pipeline circuit enables the coarse-grained depth test, the geometry pipeline circuit performs coarse-grained depth test rejection on the processing results of the geometry processing, and stores the coarse-grained depth test results in a coarse-grained depth buffer so that fine-grained depth test rejection can be performed on the pixel pipeline in the stream processor cluster circuit of the graphics processor.

15. The operating method according to claim 14, characterized in that, The operation method further includes: When the geometric pipeline circuit enables the coarse-grained depth test, the pixel pipeline retrieves the coarse-grained depth test result from the coarse-grained depth buffer to perform the fine-grained depth test rejection, and stores the fine-grained depth test result in the fine-grained depth buffer.

16. The operating method according to claim 10, characterized in that, The operation method further includes: After receiving the task completion signal, the command processor circuit issues a task that depends on the fine-grained depth buffer.

17. A machine-readable storage medium for storing non-transitory machine-readable instructions that, when executed by a computer, can implement the operation method of the graphics processor according to any one of claims 9-16.

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