A display panel and a display device

Abstract

The present disclosure provides a display panel and a display device, belonging to the technical field of display driving. The display panel includes a plurality of pixel units arranged in an array. The pixel units in the same row are electrically connected to the same power supply signal line, and each power supply signal line is electrically connected to a power supply voltage supply module through at least one power supply voltage supply line. The display panel is divided into a plurality of display areas arranged side by side in the column direction. The display panel has a first side and a second side arranged opposite to each other. The power supply voltage supply line introduces the power supply voltage provided by the power supply voltage supply module into the power supply signal line from the first side. The power supply signal line in at least the display area closest to the first side is electrically connected to the power supply voltage supply line through an adjustment unit to adjust the power supply voltage output by the power supply voltage supply module.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a display panel and a display device. Background Art

[0002] The driving of a display panel is mainly completed by a Display Driver Integrated Circuit (DDIC) and a Power Management Integrated Circuit (PMIC). Among them, the DDIC provides digital and analog signals, is responsible for driving the Thin Film Transistors (TFTs) in the display panel, and writing data voltages; the PMIC provides a power supply voltage signal ELVDD to drive the light-emitting materials in the display substrate to emit light.

[0003] In a display panel, as one of the very critical voltages in the pixel circuit, ELVDD can directly affect the light-emitting current. In an ideal situation where the impedance of the power supply voltage signal line transmitting ELVDD is negligible, the current flowing through each pixel driving circuit is the same. However, in actual situations, due to the inevitable presence of a certain trace impedance in the power supply voltage signal line, and as the size of the display panel is larger and the resolution is higher, the power supply voltage signal line is longer and the impedance is greater. ELVDD will generate a voltage drop (IR Drop) on the power supply voltage signal line. The power supply voltage near the PMIC in the display panel is higher than that far from the PMIC, resulting in different currents flowing through the pixel driving circuits at different positions, and ultimately causing a deviation in the display brightness of the display panel, thereby affecting the display effect of the display screen. Summary of the Invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a display panel and a display device.

[0005] In a first aspect, the technical solution adopted to solve the technical problems of the present disclosure is a display panel, which includes a plurality of pixel units arranged in an array. The pixel units in the same row are electrically connected to the same power supply signal line, and each of the power supply signal lines is electrically connected to a power supply voltage supply module through at least one power supply voltage supply line; wherein, the display panel is divided into a plurality of display areas arranged side by side in the column direction;

[0006] The display panel has a first side and a second side arranged opposite to each other, and the power supply voltage supply line introduces the power supply voltage provided by the power supply voltage supply module into the power supply signal line from the first side;

[0007] At least the power signal lines in the display area closest to the first side are electrically connected to the power voltage supply line through an adjustment unit to adjust the power voltage output by the power voltage supply module.

[0008] In some embodiments, the display panel further includes a control module, which is electrically connected to the control signal lines and is configured to provide a control voltage signal to the control signal lines to control the adjustment unit.

[0009] In some embodiments, except for the display area farthest from the first side, the power signal lines in the remaining display areas are all electrically connected to the power voltage supply line through the adjustment unit.

[0010] In some embodiments, the power signal lines each include a first end and a second end disposed opposite to each other, and the first end and the second end are respectively electrically connected to two different power voltage supply lines.

[0011] In some embodiments, the two different power voltage supply lines are respectively a first power voltage supply line and a second power voltage supply line; one of the first power voltage supply line and the second power voltage supply line is electrically connected to the adjustment unit.

[0012] In some embodiments, the two different power voltage supply lines are respectively a first power voltage supply line and a second power voltage supply line, and both the first power voltage supply line and the second power voltage supply line are electrically connected to independent adjustment units.

[0013] In some embodiments, the adjustment unit includes a thin film transistor; a first pole of the thin film transistor is electrically connected to the power voltage supply line, a second pole of the thin film transistor is electrically connected to the corresponding power signal line, and a control pole of the thin film transistor is electrically connected to the control signal line.

[0014] In some embodiments, the pixel unit includes a driving circuit and a light emitting device electrically connected to the driving circuit; the power signal line is electrically connected to the driving circuit to provide a power voltage for the driving circuit.

[0015] In some embodiments, the light emitting device is an organic light emitting diode.

[0016] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes the display panel according to any one of the above embodiments. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the power voltage routing of a display panel in the prior art;

[0018] Figure 2aIt is a schematic structural diagram of an exemplary pixel driving circuit;

[0019] Figure 2b is Figure 2a a driving timing diagram of the pixel driving circuit shown;

[0020] Figure 3 It is a schematic diagram of the power supply voltage partition of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 4 It is another schematic diagram of the power supply voltage partition of a display panel provided by an embodiment of the present disclosure;

[0022] Figure 5 It is another schematic diagram of the power supply voltage partition of a display panel provided by an embodiment of the present disclosure.

[0023] Wherein the reference numerals are: 10, pixel unit; 1, power supply signal line; 2, power supply voltage supply line; 21, first power supply voltage supply line; 22, second power supply voltage supply line; 20, power supply voltage supply module; 30, control module; AA1, first display area; AA2, second display area; AA3, third display area; 40, adjustment unit; 3, control signal line. Detailed implementation manners

[0024] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. The components of the embodiments of the present disclosure usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present disclosure provided in the accompanying drawings below is not intended to limit the scope of the present disclosure required to be protected, but only represents the selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. Words such as "including" or "comprising" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0026] As used in this disclosure, "a plurality or several" means two or more. "And / or" describes the relationship between associated objects and indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0027] The inventors found that in the prior art, as one of the very critical voltages in the pixel circuit, the power supply voltage of the display panel can directly affect the light-emitting current. Figure 1 FIG. [FIGURE NUMBER] is a schematic diagram of the power supply voltage routing of a display panel in the prior art, as Figure 1 shown. It includes a plurality of pixel units 10 arranged in an array. The pixel units 10 in the same row are electrically connected to the same power supply signal line 1, and each power supply signal line 1 is electrically connected to a power supply voltage supply module 20 through two power supply voltage supply lines 2. In an ideal situation where the impedance of the power supply voltage signal line for transmitting the power supply voltage is negligible, the current flowing through each pixel driving circuit is the same. However, in actual situations, due to the inevitable presence of a certain routing impedance in the power supply voltage signal line, and as the size of the display panel increases and the resolution becomes higher, the power supply voltage signal line becomes longer and the impedance becomes larger. The power supply voltage will generate a voltage drop on the power supply voltage signal line. The power supply voltage near the power management chip in the display panel is higher than that far from the power management chip, resulting in different currents flowing through the pixel driving circuits at different positions, and ultimately causing a deviation in the display brightness of the display panel, thereby affecting the display effect of the display screen.

[0028] It should be noted that the pixel unit includes a driving circuit and a light-emitting device electrically connected to the driving circuit. Here, a 7T1C (i.e., a structure of seven transistors and one capacitor) pixel driving circuit will be taken as an example for illustration. Figure 2a It is a schematic structural diagram of an exemplary pixel driving circuit; Figure 2b is Figure 2a a driving timing diagram of the pixel driving circuit shown in, as Figure 2a and 2b shown, the pixel driving circuit includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a storage capacitor Cst, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a light-emitting device D.

[0029] Specifically, the drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3. The source of the data writing transistor T4 is configured to be electrically connected to the data line Data to receive a data signal, and the gate of the data writing transistor T4 is configured to be electrically connected to the scan signal terminal Gate to receive a scan signal; the second electrode plate of the storage capacitor Cst is electrically connected to the first power supply voltage terminal ELVDD, and the first electrode plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3; the source of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3, and the gate of the threshold compensation transistor T2 is configured to be electrically connected to the scan signal terminal Gate to receive a compensation control signal; the source of the first reset transistor T1 is configured to be electrically connected to the reset power signal terminal Vinit to receive a reset signal, the drain of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the first reset transistor T1 is configured to be electrically connected to the reset control signal terminal Reset to receive a reset control signal; the drain of the second reset transistor T7 is configured to be electrically connected to the reset power signal terminal Vinit to receive a reset signal, the source of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting device D, and the gate of the second reset transistor T7 is configured to be electrically connected to the reset control signal terminal Reset to receive a reset control signal; the source of the first light-emitting control transistor T5 is electrically connected to the first power supply voltage terminal ELVDD, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control terminal EM to receive a light-emitting control signal; the source of the second light-emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting device D, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the light-emitting control terminal EM to receive a light-emitting control signal; the second electrode of the light-emitting device D is electrically connected to the second power supply voltage terminal ELVSS.

[0030] It should be noted that one of the first power supply voltage terminal ELVDD and the second power supply voltage terminal ELVSS is the high-voltage terminal and the other is the low-voltage terminal. For example, the first power supply voltage terminal ELVDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; while the second power supply voltage terminal ELVSS can be a voltage source to output a constant second voltage, and the second voltage is a negative voltage. For example, in some embodiments, the second power supply voltage terminal ELVSS can be grounded.

[0031] The scan signal and the compensation control signal can be the same, that is, the gates of the data writing transistor T4 and the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal (for example, the scan signal), thereby reducing the number of signal lines. Of course, it can be understood that the gates of the data writing transistor T4 and the threshold compensation transistor T2 can also be electrically connected to different signal lines respectively.

[0032] The scan signal and the compensation control signal can also be different, so that the gates of the data writing transistor T4 and the threshold compensation transistor T2 can be separately controlled, increasing the flexibility of controlling the pixel circuit. In the embodiments of the present disclosure, it is described by taking the gates of the data writing transistor T4 and the threshold compensation transistor T2 being electrically connected to the scan signal terminal Gate as an example.

[0033] The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be electrically connected to the same signal line, such as the light-emitting control terminal EM, to receive the same signal, thereby reducing the number of signal lines. Of course, it can be understood that the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can also be electrically connected to different signal lines respectively. In the embodiments of the present disclosure, it is described by taking the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 being electrically connected to the light-emitting control terminal EM as an example.

[0034] The gates of the first reset transistor T1 and the second reset transistor T7 can be electrically connected to the same signal line, such as the reset control signal terminal Reset, to receive the same signal, thereby reducing the number of signal lines. Of course, it can be understood that the gates of the first reset transistor T1 and the second reset transistor T7 can also be electrically connected to different signal lines respectively. In the embodiments of the present disclosure, it is described by taking the gates of the first reset transistor T1 and the second reset transistor T7 being electrically connected to the reset control signal terminal Reset as an example.

[0035] The source of the first reset transistor T1 and the drain of the second reset transistor T7 can be electrically connected to the same signal line, such as the reset power signal terminal Vinit. The reset power signal terminal Vinit can be a DC reference voltage terminal to output a constant DC reference voltage. The reset power signal terminal Vinit can be a high voltage terminal or a low voltage terminal, as long as it can provide a reset signal to reset the gate of the driving transistor T3 and the first electrode of the light-emitting element, and the present disclosure does not limit this. In the embodiment of the present disclosure, the source of the first reset transistor T1 and the drain of the second reset transistor T7 are both electrically connected to the reset power signal terminal Vinit as an example for illustration. Additionally, in the embodiment of the present disclosure, such as Figure 2a The specific structure in the pixel driving circuit shown can be set according to actual application requirements, and the embodiments of the present disclosure do not make specific limitations on this.

[0036] Such as Figure 2b As shown, the working process of this pixel driving circuit is divided into: a reset stage t1, a data writing and threshold compensation stage t2, and a light-emitting stage t3.

[0037] Reset stage (t1): A low-level signal is written to the reset control signal terminal Reset, and high-level signals are written to the scan signal terminal Gate and the light-emitting control terminal EM; the first reset transistor T1 and the second reset transistor T7 are turned on, and the gate of the driving transistor T3 is written with an initial voltage by the reset power signal terminal Vinit to prepare for writing the data voltage in the next frame. The anode of the light-emitting device D is written with an initialization voltage through the second reset transistor T7, so that the light-emitting device D is no longer in the forward conduction state, and the internal electric field formed by the directional movement of impurity ions in the light-emitting device D gradually disappears, thereby restoring the characteristics of the light-emitting device D.

[0038] Data writing and threshold compensation stage (t2): A low-level signal is written to the scan signal terminal Gate, and high-level signals are written to the reset control signal terminal Reset and the first light-emitting control terminal EM; the data writing transistor T4 and the threshold compensation transistor T2 are turned on. The driving transistor T3 is connected into a diode structure by the threshold compensation transistor T2, and the data voltage written on the data line Data is written to the gate of the driving transistor T3 through the data writing transistor T4 and the threshold compensation transistor T2 until the driving transistor T3 is turned off, and the gate voltage of the driving transistor T3 is stored in the storage capacitor Cst.

[0039] Emission stage (t3): A low-level signal is written to the emission control terminal EM, high-level signals are written to the scan signal terminal Gate and the reset control signal terminal Reset. Both the first emission control transistor T5 and the second emission control transistor T6 are turned on. The source of the driving transistor T3 is connected to the first power supply voltage terminal ELVDD, and the source voltage of the driving transistor T3 instantaneously changes from the data voltage of the previous stage to the first power supply voltage. The light-emitting device D emits light under the drive of the driving transistor T3. At this time, the driving transistor T3 operates in the saturation region until the reset stage of the next frame.

[0040] Among them, the expression of the emission current is as follows:

[0041]

[0042] Among them, I ds represents the driving current of the light-emitting device; V Data represents the data voltage; represents the channel width-to-length ratio of the thin-film transistor; C ox represents the dielectric constant; μ represents the equivalent mobility, that is, the average drift velocity of carriers under the action of a unit electric field.

[0043] According to the above expression of the emission current, in the pixel driving circuit of the display panel, when the given data voltage is the same, due to the non-uniformity of the display panel process, the power supply voltage loaded on the pixel driving circuit near the PMIC in the display panel is higher than the power supply voltage loaded on the pixel driving circuit far from the PMIC, resulting in different driving currents at different positions of the display panel. This requires different power supply voltages for different positions to make the brightness of different positions of the display panel the same, that is, to maintain the uniformity of brightness. For example, the power supply voltage loaded on the pixel driving circuit near the PMIC in the display panel can be adjusted to make the brightness of the entire display panel uniform.

[0044] In view of this, the embodiments of the present disclosure provide a display panel. By setting an adjustment unit to adjust the power supply voltage loaded on the pixel driving circuits in different regions of the display panel, the power supply voltage of the display panel can be partitioned without additionally increasing the number of power supply voltage channels, so that the display panel maintains brightness uniformity and ensures the display image quality.

[0045] In a first aspect, the technical solution adopted to solve the technical problems of the present disclosure is a display panel, Figure 3 which is a schematic diagram of power supply voltage partitioning of a display panel provided by an embodiment of the present disclosure, as Figure 3As shown in the figure, it includes a plurality of pixel units 10 arranged in an array. The pixel units 10 in the same row are electrically connected to the same power supply signal line 1, and each power supply signal line 1 is electrically connected to a power supply voltage supply module 20 through at least one power supply voltage supply line 2. Among them, the display panel is divided into a plurality of display areas arranged side by side in the column direction. The display panel has a first side and a second side arranged opposite to each other. The power supply voltage supply line 2 introduces the power supply voltage provided by the power supply voltage supply module 20 into the power supply signal line 1 from the first side. The power supply signal line 1 in at least the display area closest to the first side is electrically connected to the power supply voltage supply line 2 through an adjustment unit 40 to adjust the power supply voltage output by the power supply voltage supply module 20.

[0046] It should be noted that the "power supply signal line 1 in the display area" mentioned in the embodiments of the present disclosure refers to the power supply signal line 1 electrically connected to the pixel unit 10 in the display area, and this power supply signal line 1 is not necessarily strictly located in the display area.

[0047] For the convenience of description and understanding, in the embodiments of the present disclosure, the display panel is taken as an example of being divided into three display areas arranged side by side in the column direction, and the three display areas are the first display area AA1, the second display area AA2, and the third display area AA3 respectively. It should be noted that when the size of the display panel in the embodiments of the present disclosure is small, for example, when applied to a mobile phone, the number of display areas is usually within three. The same is true when the size of the display panel in the embodiments of the present disclosure is large. Of course, when dividing the display area of the display panel in the embodiments of the present disclosure, the number of display areas can be determined according to the size of the display panel, and the present disclosure does not make special restrictions on this.

[0048] As Figure 3 shown in the figure, in the embodiments of the present disclosure, each power supply signal line 1 is electrically connected to the power supply voltage supply module 20 through two power supply voltage supply lines 2, and the power supply voltage is provided for the pixel driving circuit of the pixel unit 10 through the power supply signal line 1. Such a setting can make the driving ability stronger, and at the same time reduce the voltage drop at different positions of the display panel caused by the wiring impedance, so as to improve the brightness uniformity of the display panel. In the embodiments of the present disclosure, the power supply voltage supply line 2 introduces the power supply voltage provided by the power supply voltage supply module 20 into the power supply signal line 1 from the first side. Compared with the display area close to the first side, the wiring impedance of the display area far from the first side will be greater, that is, a greater voltage drop will be generated. For example, after the power supply voltage output by the power supply voltage supply module 20 passes through the power supply voltage supply line 2 and the power supply signal line 1, the power supply voltage reaching the first display area AA1 will be less than that of the second display area AA2, and the power supply voltage reaching the second display area AA2 will be less than that of the third display area AA3; As Figure 3As shown, to ensure the uniformity of the display panel brightness, the power signal line 1 in the display area closest to the first side is electrically connected to the power voltage supply line 2 through the adjustment unit 40, that is, the power signal line 1 in the third display area AA3 is electrically connected to the power voltage supply line 2 through the adjustment unit 40, so as to adjust the power voltage output by the power voltage supply module 20, thereby ensuring the uniformity of the display panel brightness. Of course, in the embodiments of the present disclosure, the power signal lines 1 in the second display area AA2 and the third display area AA3 can both be electrically connected to the power voltage supply line 2 through the adjustment unit 40 to adjust the power voltage output by the power voltage supply module 20, and the present disclosure does not make special limitations on this.

[0049] In some embodiments, as Figure 3 shown, the display panel not only includes the above structure but also includes a control module 30, and the control module 30 is electrically connected to the control signal line 3. The control module 30 is configured to provide a control voltage signal for the control signal line 3 to control the adjustment unit 40.

[0050] In the embodiments of the present disclosure, the control module 30 can be a display driving chip, which is configured to provide a control voltage signal for the control signal line 3 to control the adjustment unit 40 to adjust the power voltage of its corresponding display area, thereby ensuring the brightness uniformity of the display panel. The control module 30 can be integrated on a flexible printed circuit board (Flexible Printed Circuit, FPC) or a COF flexible circuit board, and the control signal line 3 is bound to the flexible circuit board, and then the flexible circuit board can be folded to the back of the display panel. The power voltage supply module 20 in the embodiments of the present disclosure can be a power management chip, which is configured to provide a power voltage signal for the power voltage supply line 2, and then input the power voltage signal into the pixel driving circuit of the pixel unit 10 through the power signal line 1 electrically connected to the power voltage supply line 2.

[0051] In some embodiments, the control module 30 provides a control voltage signal, and the control voltage signal is loaded onto the adjustment unit 40. When the adjustment units 40 corresponding to different display areas are the same, by loading different control voltage signals onto the adjustment units 40 corresponding to different display areas of the display panel, the currents on the power signal lines 1 of each display area are made the same. At this time, the power voltages of the power signal lines 1 of each display area tend to be the same to ensure the brightness uniformity of the display panel. Of course, it can be understood that in the embodiments of the present disclosure, the adjustment units 40 corresponding to different display areas can be different. By loading the same control voltage signal onto the adjustment units 40 corresponding to different display areas of the display panel, the currents on the power signal lines 1 of each display area can also be made the same. At this time, the power voltages of the power signal lines 1 of each display area tend to be the same to ensure the brightness uniformity of the display panel.

[0052] In some embodiments, except for the display area farthest from the first side, the power signal lines 1 in the remaining display areas are all electrically connected to the power voltage supply line 2 through the adjustment unit 40.

[0053] Figure 4 Another schematic diagram of the power voltage partition of the display panel provided by the embodiments of the present disclosure is shown in Figure 4 As shown, in the embodiments of the present disclosure, except for the first display area AA1, the power signal lines 1 in the second display area AA2 and the third display area AA3 are all electrically connected to the power voltage supply line 2 through the adjustment unit 40, so as to realize the adjustment of the power voltage in the second display area AA2 and the third display area AA3, and to ensure the uniformity of the brightness of the display panel.

[0054] In some embodiments, the power signal lines 1 all include a first end and a second end arranged opposite to each other, and the first end and the second end are respectively electrically connected to two different power voltage supply lines 2.

[0055] As Figure 3 and Figure 4 shown, in the embodiments of the present disclosure, the power signal lines 1 all include a first end and a second end arranged opposite to each other, and the first end and the second end are respectively electrically connected to two different power voltage supply lines 2, that is, the bilateral driving method is adopted, and the power voltage is provided for the pixel driving circuit of the pixel unit 10 through the power signal lines 1. Specifically, as Figure 3 shown, two power voltages with the same value are input to the power signal lines 1 through two different power voltage supply lines 2. The first end and the second end of the power signal lines 1 in the first display area AA1 and the second display area AA2 are respectively electrically connected to two different power voltage supply lines 2, and the first end and the second end of the power signal lines 1 in the third display area AA3 are respectively electrically connected to two different power voltage supply lines 2 through independent adjustment units. Such a setting can make the driving ability stronger, and at the same time reduce the voltage drop at different positions of the display panel caused by the trace impedance, so as to improve the brightness uniformity of the display panel.

[0056] In some embodiments, the two different power voltage supply lines 2 are respectively a first power voltage supply line 21 and a second power voltage supply line 22; one of the first power voltage supply line 21 and the second power voltage supply line 22 is electrically connected to the adjustment unit 40.

[0057] Specifically, Figure 5 Another schematic diagram of the power voltage partition of the display panel provided by the embodiments of the present disclosure is shown in Figure 5As shown, in the embodiments of the present disclosure, the two different power supply voltage lines 2 are respectively a first power supply voltage line 21 and a second power supply voltage line 22. One of the first power supply voltage line 21 and the second power supply voltage line 22 is electrically connected to the adjustment unit 40. For example, the first power supply voltage line 21 is electrically connected to the adjustment unit 40. The power signal lines 1 in the second display area AA2 and the third display area AA3 are all electrically connected to the first power supply voltage line 21 through the adjustment unit 40, so as to realize the adjustment of the power supply voltage in the second display area AA2 and the third display area AA3, and ensure the uniformity of the display panel brightness.

[0058] In some embodiments, the two different power supply voltage lines 2 are respectively a first power supply voltage line 21 and a second power supply voltage line 22, and both the first power supply voltage line 21 and the second power supply voltage line 22 are electrically connected to independent adjustment units 40.

[0059] Specifically, as Figure 4 As shown, in the embodiments of the present disclosure, the two different power supply voltage lines 2 are respectively a first power supply voltage line 21 and a second power supply voltage line 22, and both the first power supply voltage line 21 and the second power supply voltage line 22 are electrically connected to independent adjustment units 40. For example, the first ends of the power signal lines 1 in the second display area AA2 and the third display area AA3 are electrically connected to the first power supply voltage line 21 through the adjustment unit 40, and the second ends of the power signal lines 1 in the second display area AA2 and the third display area AA3 are electrically connected to the second power supply voltage line 22 through the adjustment unit 40, so as to realize the adjustment of the power supply voltage in the second display area AA2 and the third display area AA3, and ensure the uniformity of the display panel brightness.

[0060] Furthermore, in some embodiments, taking the second display area AA2 as an example, for the power signal line 1 in the second display area AA2, its first end is electrically connected to the first power supply voltage line 21 through the adjustment unit 40, and its second end is electrically connected to the second power supply voltage line 22 through the adjustment unit 40; wherein, due to the different actual lengths of the traces, the trace impedances may not be the same, which may cause the power supply voltages near the first end of the power signal line 1 and near the second end of the power signal line 1 to have different actual effects. Therefore, the adjustment unit 40 near the first end of the power signal line 1 and the adjustment unit 40 near the second end of the power signal line 1 can be adjusted respectively, so that the power supply voltages at both ends of the power signal line 1 in the second display area AA2 are kept as close as possible to the same value, and the uniformity of the display panel brightness is ensured.

[0061] In some embodiments, the adjustment unit 40 includes a thin film transistor; a first pole of the thin film transistor is electrically connected to the power supply voltage supply line 2, a second pole of the thin film transistor is electrically connected to the corresponding power signal line 1, and a control pole of the thin film transistor is electrically connected to the control signal line 3.

[0062] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetric, there is no difference between the source and drain. In the embodiments of the present disclosure and subsequent descriptions, to distinguish the source and drain of the transistor, one pole is referred to as the first pole, the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first pole is the source of the P-type transistor, the second pole is the drain of the P-type transistor, and when a low-level signal is input to the gate, the source and drain are turned on; when an N-type transistor is used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and when a high-level signal is input to the gate, the source and drain are turned on.

[0063] Specifically, as Figure 3 、 Figure 4 and Figure 5 shown, the adjustment unit 40 in the embodiments of the present disclosure includes a thin film transistor, and by adjusting the current of the thin film transistor, the power supply voltage of different display areas is adjusted to achieve zonal control of the power supply voltage; wherein, a first pole of the thin film transistor is electrically connected to the power supply voltage supply line 2, a second pole of the thin film transistor is electrically connected to the corresponding power signal line 1, and a control pole of the thin film transistor is electrically connected to the control signal line 3. The control module 30 provides a control voltage signal for the control signal line 3. By changing the voltage signal input to the control pole of the thin film transistor, the current of the thin film transistor can be changed, thereby realizing the adjustment of the power supply voltage of the display area where it is located, and further ensuring the brightness uniformity of the display panel.

[0064] It should be noted that in the embodiments of the present disclosure, when a thin film transistor is used as the adjustment unit 40, it can be fabricated in one process with the thin film transistor in the pixel driving circuit. Therefore, adding the adjustment unit 40 does not increase the process cost. In addition, with Figure 4Taking the power voltage partition of the display panel shown as an example, the aspect ratios of the channels of the thin film transistors corresponding in the second display area AA2 and the third display area AA3 can be the same, so that they can respond to different control voltage signals, thereby realizing the adjustment of the power voltage in their respective areas, and further ensuring the uniformity of the brightness of the display panel. For example, when the control module 30 provides different control voltage signals to the thin film transistors corresponding to the second display area AA2 and the third display area AA3 respectively, the currents of the thin film transistors corresponding to the second display area AA2 and the third display area AA3 will change differently, that is, the current values are not the same, and the resistance value can be considered unchanged. At this time, the voltage loss changes differently, so that the power voltages of the second display area AA2 and the third display area AA3 change differently, thereby ensuring the uniformity of the brightness of the display panel. Of course, it can be understood that the aspect ratios of the channels of the thin film transistors corresponding in the second display area AA2 and the third display area AA3 can be different, so that they can respond to the same control voltage signal, thereby realizing the adjustment of the power voltage in their respective areas, and further ensuring the uniformity of the brightness of the display panel. For example, when the control module 30 provides the same control voltage signal to the thin film transistors corresponding to the second display area AA2 and the third display area AA3, the currents of the thin film transistors corresponding to the second display area AA2 and the third display area AA3 will change differently, that is, the current values are not the same, and the resistance value can be considered unchanged. At this time, the voltage loss changes differently, so that the power voltages of the second display area AA2 and the third display area AA3 change differently, thereby ensuring the uniformity of the brightness of the display panel.

[0065] In some embodiments, the aspect ratios of the channels of the thin film transistors used in the same display area can be the same, while the aspect ratios of the channels of the thin film transistors used in different display areas can be different, and the aspect ratio of the channel of the thin film transistor closer to the first side of the display panel is smaller.

[0066] In some embodiments, the pixel unit 10 includes a driving circuit and a light emitting device electrically connected to the driving circuit; the power signal line 1 is electrically connected to the driving circuit to provide a power voltage for the driving circuit. In the embodiments of the present disclosure, the pixel driving circuit can be a 5T2C driving circuit or a 7T1C driving circuit as shown in Figure 2a and so on, and the present disclosure does not make special restrictions on this.

[0067] In a second aspect, the embodiments of the present disclosure further provide a display device, which includes the display panel in any one of the above embodiments.

[0068] The display devices of the embodiments of the present disclosure include, but are not limited to, devices such as mobile phones, tablet computers, personal digital assistants, smart watches, in-vehicle displays, digital cameras, laptop computers, head-up displays, wearable devices, virtual reality, and augmented reality, so as to achieve the design effect of unified full-screen and interaction or other effects.

[0069] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A display panel, which includes a plurality of pixel units arranged in an array, the pixel units in the same row are electrically connected to the same power supply signal line, and each of the power supply signal lines is electrically connected to a power supply voltage supply module through at least one power supply voltage supply line; wherein, The display panel is divided into a plurality of display areas arranged side by side in the column direction; The display panel has a first side and a second side arranged opposite to each other, and the power supply voltage line introduces the power supply voltage provided by the power supply voltage module from the first side into the power supply signal line; The power supply signal line in at least the display area closest to the first side is electrically connected to the power supply voltage line through an adjustment unit to adjust the power supply voltage output by the power supply voltage module; The display panel further includes a control module, and the control module is electrically connected to the control signal line and is configured to provide a control voltage signal for the control signal line to control the adjustment unit; Wherein, the adjustment unit includes a thin film transistor; a first pole of the thin film transistor is electrically connected to the power supply voltage line, a second pole of the thin film transistor is electrically connected to the corresponding power supply signal line, and a control pole of the thin film transistor is electrically connected to the control signal line; the aspect ratio of the channel of the thin film transistor closer to the first side of the display panel is smaller.

2. The display panel according to claim 1, wherein, Except for the display area farthest from the first side, the power supply signal lines in the remaining display areas are all electrically connected to the power supply voltage line through the adjustment unit.

3. The display panel according to claim 1, wherein, The power supply signal lines all include a first end and a second end arranged opposite to each other, and the first end and the second end are respectively electrically connected to two different power supply voltage lines.

4. The display panel according to claim 3, wherein, The two different power supply voltage lines are respectively a first power supply voltage line and a second power supply voltage line; one of the first power supply voltage line and the second power supply voltage line is electrically connected to the adjustment unit.

5. The display panel according to claim 3, wherein, The two different power supply voltage lines are respectively a first power supply voltage line and a second power supply voltage line, and the first power supply voltage line and the second power supply voltage line are both electrically connected to independent adjustment units.

6. The display panel according to claim 1, wherein, The pixel unit includes a driving circuit and a light emitting device electrically connected to the driving circuit; the power supply signal line is electrically connected to the driving circuit to provide a power supply voltage for the driving circuit.

7. The display panel according to claim 6, wherein, The light emitting device is an organic light emitting diode.

8. A display device, wherein, Including the display panel according to any one of claims 1-7 above.

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