A redundant clock automatic detection and switching system

Abstract

The present invention discloses a redundant clock automatic detection and switching system, which is effectively applicable to application scenarios requiring redundant clock automatic switching. The provided automatic detection circuit can automatically generate a clock selection control signal based on the input of an external clock, and can adjust the decision threshold voltage value according to different application requirements. The provided low-noise amplifier circuit can restore the power of the external clock signal even with minimal noise. The provided two-input clock buffer circuit not only improves the clock output drive capability even with minimal noise, but also can simultaneously output multiple clocks for system use.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to a redundant clock automatic detection and switching system capable of detecting the health of a clock signal and performing automatic switching. Background Art

[0002] The clock source is used to provide a frequency-stable and level-matched square wave clock signal for the ring pulse generator. It usually consists of a quartz crystal oscillator and a positive feedback oscillation circuit composed of a NAND gate, whose output is sent to the ring pulse generator.

[0003] System clock signals are typically derived from two sources: an internal clock source and an external, high-precision clock source. The internal clock source is typically generated by a high-precision, low-temperature drift crystal oscillator, while the external clock source is typically generated by a high-precision signal source or a time-frequency converter. Generally, when a system operates independently, the internal clock source alone is sufficient for stable operation. However, if multiple identical systems need to operate synchronously, an external, high-precision, synchronized clock signal is required.

[0004] In the prior art, selecting the desired clock source typically involves program-controlled or switch-controlled multiplexers. This approach has numerous drawbacks, including the inability to automatically detect the health of the clock source. Furthermore, it cannot automatically select the desired clock source based on the health of the clock. Furthermore, noise is introduced when the clock signal passes through the multiplexer.

[0005] Therefore, how to provide a system that can detect the health status of clock signals and perform automatic switching is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the above problems, the present invention provides a redundant clock automatic detection and switching system for overcoming the above problems or at least partially solving the above problems.

[0007] The present invention provides the following solutions:

[0008] A redundant clock automatic detection and switching system, comprising:

[0009] A connector, configured to receive a first clock signal input by a first clock source;

[0010] a power divider connected to the connector, and configured to divide the first clock signal into two;

[0011] a detection circuit connected to the power divider, the detection circuit being configured to generate a clock selection control signal based on a comparison result of an identification voltage and a target decision threshold voltage; the identification voltage being a voltage signal with different amplitudes generated based on the strength of the first clock signal;

[0012] a low-noise amplifier, the low-noise amplifier being connected to the power divider, and configured to restore the power of the first clock signal, whose power has been halved, to the power of the first clock signal at the input end of the power divider;

[0013] A clock buffer, the detection circuit, the low-noise amplifier and the second clock source are respectively connected to the clock buffer; the clock buffer includes multiple clock output terminals; the clock buffer is used to determine the first clock source or the second clock source as the system clock according to the clock selection control signal.

[0014] Preferably, the first clock source is an external clock source, and the second clock source is an internal clock source.

[0015] Preferably: the detection circuit includes a detector; the detector is connected to the power divider; the detector is used to generate the identification voltage with different amplitudes according to the strength of the first clock signal.

[0016] Preferably, the detection circuit further comprises a voltage comparator, which is connected to the clock buffer and the detector respectively; the voltage comparator is used to compare the identification voltage with the target decision threshold voltage to generate the clock selection control signal.

[0017] Preferably, the detection circuit further includes a reference voltage source, the reference voltage source is connected to the voltage comparator, and the reference voltage source is used to provide a target decision threshold voltage for the voltage comparator.

[0018] Preferably, the target decision threshold voltage is determined according to application scenario requirements.

[0019] Preferably, the buffer includes two input clock buffers, and the two input clock buffers include a clock source selection port.

[0020] Preferably, a DC blocking capacitor is provided between the connector and the power divider.

[0021] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0022] The embodiments of the present application provide a redundant clock automatic detection and switching system that can be effectively applied to application scenarios where redundant clock automatic switching is required. The provided automatic detection circuit can automatically generate a clock selection control signal based on the input of the external clock, and can change the judgment threshold voltage value according to different application requirements. The provided low-noise amplifier circuit can restore the power of the external clock signal when minimal noise is introduced. The provided two-input clock buffer circuit can not only improve the clock output drive capability when relatively low noise is introduced, but can also simultaneously output multiple clocks for system use.

[0023] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0025] Figure 1 This is a connection block diagram of a redundant clock automatic detection and switching system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.

[0027] See also Figure 1 , is a redundant clock automatic detection and switching system provided by an embodiment of the present invention, such as Figure 1 As shown, the system may include:

[0028] Connector J1, the connector J1 is used to receive a first clock signal input by a first clock source;

[0029] A power divider U1, connected to the connector J1, and configured to divide the first clock signal into two;

[0030] A detection circuit, connected to the power divider U1, for generating a clock selection control signal based on a comparison result between an identification voltage and a target decision threshold voltage; the identification voltage is a voltage signal with different amplitudes generated according to the strength of the first clock signal;

[0031] A low-noise amplifier U5, connected to the power divider U1, configured to restore the power of the first clock signal, whose power has been halved, to the power of the first clock signal at the input end of the power divider U1;

[0032] The clock buffer U7, the detection circuit, the low-noise amplifier U5 and the second clock source U6 are respectively connected to the clock buffer U7; the clock buffer U7 includes multiple clock output terminals; the clock buffer U7 is used to determine the first clock source or the second clock source as the system clock according to the clock selection control signal.

[0033] The redundant clock automatic detection and switching system provided by the embodiment of the present application can detect the health of the clock source through the provided clock detection circuit and generate a control signal. The clock selection circuit formed can automatically switch the selected clock source according to the control signal generated by the detection circuit.

[0034] Furthermore, embodiments of the present application can provide that the first clock source is an external clock source, and the second clock source is an internal clock source. The redundant clock automatic detection and switching circuit provided in embodiments of the present application uses an external clock as the primary clock. If an external clock is connected via the J1 connector, the circuit automatically switches the external clock to the system clock. Otherwise, the internal clock is used as the system clock. The use of the external clock ensures the basis for clock synchronization between different devices.

[0035] The detection circuit provided in the embodiment of the present application can monitor the health status of the first clock source connected by the connector. Specifically, the embodiment of the present application can provide that the detection circuit includes a detector U3; the detector U3 is connected to the power divider U1; the detector U3 is used to generate the identification voltage of different amplitudes according to the strength of the first clock signal.

[0036] Furthermore, the detection circuit further includes a voltage comparator U4, which is connected to the clock buffer U7 and the detector U3 respectively; the voltage comparator U4 is used to compare the identification voltage with the target decision threshold voltage to generate the clock selection control signal.

[0037] Furthermore, the detection circuit also includes a reference voltage source U2, which is connected to the voltage comparator U4 and is used to provide a target decision threshold voltage for the voltage comparator U4. The target decision threshold voltage is determined based on the application scenario requirements. The threshold voltage can be customized by the user as needed.

[0038] The buffer provided in the embodiment of the present application may take various forms. For example, in one implementation, the embodiment of the present application may provide that the buffer includes a two-input clock buffer, and the two-input clock buffer includes a clock source selection port.

[0039] In order to further prevent the large DC component of the first clock signal from damaging the subsequent internal circuit, the embodiment of the present application may provide a DC blocking capacitor C1 between the connector J1 and the power divider U1.

[0040] The following is combined with Figure 1 , the system provided in this embodiment is described in detail.

[0041] The redundant clock automatic detection and switching system provided in the embodiment of the present application may include J1, C1, U1~U7, which complete the division of the external clock into two, external clock detection, clock signal amplification, and automatic clock switching; with the external clock as the main clock, if the external clock is connected through the J1 connector, the external clock is automatically switched to the system clock through the circuit, otherwise the internal clock is used as the system clock; the application of the external clock ensures the synchronous clock basis between different devices.

[0042] The J1 connector is the external clock input connector. The first clock source (external clock source) inputs the external clock signal through this connector. C1 is a DC blocking capacitor that prevents the large DC component in the external clock signal from damaging the internal circuitry behind it.

[0043] The U1 power divider splits the input external clock signal into two, one entering the automatic detection circuit and the other entering the low-noise amplifier.

[0044] U2, U3, and U4 form an automatic detection circuit. U3 is a detector that generates identification voltage signals of different amplitudes according to the strength of the input external clock signal; U2 is a reference voltage source that provides a decision threshold voltage for the U4 voltage comparator. The decision threshold voltage can be set to different voltage values ​​according to different application scenarios; U4 is a voltage comparator that compares the identification voltage generated by the U3 detector with the decision threshold voltage to generate a clock selection control signal.

[0045] U5 is a low-noise amplifier. After the external clock is divided into two by the U1 power divider, the power of the external clock signal entering the U5 low-noise amplifier is halved. The function of the U5 low-noise amplifier is to restore the signal power to the external clock signal power at the input end of the U1 power divider while introducing extremely small noise.

[0046] U6 is the second clock source (internal clock source), which is used as the system clock when there is no external clock input, ensuring that the device does not rely on the external clock source and can work independently.

[0047] U7 is a two-input clock buffer with two clock input sources and a clock source selection port. The clock selection control signal generated in step 3 can be used to select the first clock input source or the second clock input source as the system clock. The clock buffer has excellent noise suppression function. It can not only improve the output driving capability of the clock while introducing less noise, but also output multiple clocks for system use at the same time.

[0048] In summary, the redundant clock automatic detection and switching system provided in this application is effectively applicable to application scenarios requiring automatic redundant clock switching. The provided automatic detection circuit can automatically generate a clock selection control signal based on the input of an external clock, and can change the decision threshold voltage value according to different application requirements. The provided low-noise amplifier circuit can restore the power of an external clock signal even with minimal noise. The provided two-input clock buffer circuit not only improves the clock output drive capability even with minimal noise, but can also simultaneously output multiple clocks for system use.

[0049] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0050] Through the description of the above embodiments, it can be seen that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present application.

[0051] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without expending creative work.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A redundant clock automatic detection and switching system, characterized in that: include: A connector, configured to receive a first clock signal input by a first clock source; a power divider connected to the connector, and configured to divide the first clock signal into two; a detection circuit connected to the power divider, the detection circuit being configured to generate a clock selection control signal based on a comparison result of an identification voltage and a target decision threshold voltage; the identification voltage being a voltage signal with different amplitudes generated based on the strength of the first clock signal; a low-noise amplifier, the low-noise amplifier being connected to the power divider, and configured to restore the power of the first clock signal, whose power has been halved, to the power of the first clock signal at the input end of the power divider; A clock buffer, the detection circuit, the low-noise amplifier and the second clock source are respectively connected to the clock buffer; the clock buffer includes multiple clock output terminals; The clock buffer is used to determine the first clock source or the second clock source as a system clock according to the clock selection control signal.

2. The redundant clock automatic detection and switching system according to claim 1, characterized in that: The first clock source is an external clock source, and the second clock source is an internal clock source.

3. The redundant clock automatic detection and switching system according to claim 1, characterized in that: The detection circuit includes a detector; the detector is connected to the power divider; the detector is used to generate the identification voltage with different amplitudes according to the strength of the first clock signal.

4. The redundant clock automatic detection and switching system according to claim 3, characterized in that: The detection circuit further includes a voltage comparator, which is connected to the clock buffer and the detector respectively; the voltage comparator is used to compare the identification voltage with the target decision threshold voltage to generate the clock selection control signal.

5. The redundant clock automatic detection and switching system according to claim 4, characterized in that: The detection circuit further includes a reference voltage source, which is connected to the voltage comparator and is used to provide a target decision threshold voltage for the voltage comparator.

6. The redundant clock automatic detection and switching system according to claim 5, characterized in that: The target decision threshold voltage is determined according to application scenario requirements.

7. The redundant clock automatic detection and switching system according to claim 1, wherein: The buffer includes two input clock buffers, and the two input clock buffers include a clock source selection port.

8. The redundant clock automatic detection and switching system according to claim 1, wherein: A DC blocking capacitor is provided between the connector and the power divider.

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