A method, system, device and storage medium for timing generation of an analog-to-digital converter

Abstract

The application discloses a timing generation method, system, device and storage medium of an analog-to-digital converter, wherein the method comprises the following steps: acquiring a sampling data timing of an ADC; configuring a first comparison register value of a timer according to the sampling data timing of the ADC, and outputting a corresponding CNV signal in the sampling data timing of the ADC; and a conversion completion signal of the CNV signal triggers a DMA to adjust a second comparison register value of the timer, and output a corresponding sampling clock pulse in the sampling data timing of the ADC. The timing generation method, system, device and storage medium of the analog-to-digital converter provided by the application utilize the DMA and the timer of an MCU, realize automatic interaction between the DMA and the timer through parameter configuration, and automatically realize output of any clock pulse number by hardware without deep participation of the MCU, so that the application is simple, efficient, low in cost and high in operation efficiency.

Description

Technical Field

[0001] This invention belongs to the field of analog signal processing technology, and specifically relates to a timing generation method, system, device and storage medium for an analog-to-digital converter. Background Technology

[0002] With the rapid development of technologies such as integrated circuits, computer technology, medical technology, and wireless sensor networks, people are constantly pursuing portable and intelligent electronic products, such as smart home and health and medical home electronic devices. Among these, the ADC (Analog-to-Digital Converter) plays a crucial role as the link between the analog signal world and the digital signal world.

[0003] In high-speed data sampling system applications, 18-bit or 20-bit ADCs are frequently encountered; or, due to limited MCU (Microcontroller Unit) interface resources, the MCU may need to output 50 or more sampling pulses. Many ADCs currently available use SPI (Serial Peripheral Interface) interfaces, which are simple and convenient to use. However, the MCU's SPI interface is generally only configured to automatically output 8 or 16 clock pulses, which is inconvenient for ADCs requiring other pulse counts. In such cases, the MCU often needs to be deeply involved in the timing control of the ADC, leading to system complexity and high device and labor costs. Therefore, how to achieve arbitrary clock pulse output while reducing device costs is a pressing problem to be solved. Summary of the Invention

[0004] This invention provides a timing generation method, system, device, and storage medium for an analog-to-digital converter, which addresses the problems of how to achieve arbitrary clock pulse output and reduce device costs.

[0005] To address the aforementioned technical problems, this invention provides a timing generation method for an analog-to-digital converter, comprising: Acquire the timing sequence of the sampled data from the analog-to-digital converter (ADC); Configure the first comparison register value of the timer according to the sampling data timing of the ADC, and output the start conversion input (CNV) signal corresponding to the sampling data timing of the ADC; The CNV signal conversion completion signal triggers direct memory access (DMA) to adjust the value of the second comparator register of the timer and outputs the sampling clock pulse corresponding to the ADC sampling data timing.

[0006] Furthermore, the acquisition of the sampling data timing of the analog-to-digital converter (ADC) includes: Obtain the count value of N-bit sampled data from the ADC, wherein the count value includes the high and low level signals of the sampling clock pulse corresponding to the N-bit sampled data.

[0007] Furthermore, after obtaining the count value of the N-bit sampled data, the process further includes: Set the count value of the (N+1)th bit, which is used to control the level state of the (N+1)th pulse of the sampling clock pulse; After the sampling clock pulse corresponding to the N-bit sampled data is output, the (N+1)th pulse is continuously output for a certain period of time.

[0008] Further, configuring the first compare register value of the timer according to the timing of the sampled data from the ADC includes: Based on the pulse width modulation (PWM) output mode, the first comparison register value of the timer is configured according to the ADC sampling rate of the sampled data timing.

[0009] Further, the step of triggering direct memory access to adjust the second compare register value of the timer includes: After the CNV signal output conversion is complete, the direct memory access is triggered to adjust the value of the second compare register of the timer.

[0010] Furthermore, the timer synchronously outputs the sampling clock pulse and the start conversion input signal of the ADC's sampling data.

[0011] Furthermore, when the level signal of the start conversion input signal output by the timer changes, the timer outputs the sampling clock pulse corresponding to the sampling data timing.

[0012] The present invention also provides a timing generation system for an analog-to-digital converter, the system comprising a data acquisition module, a data configuration module, and a data output module; The data acquisition module is used to acquire the timing data of the analog-to-digital converter (ADC); The data configuration module is used to configure the first comparison register value of the timer according to the sampling data timing of the ADC, and output the start conversion input (CNV) signal corresponding to the sampling data timing of the ADC. The data output module is used to output the sampling clock pulse corresponding to the ADC sampling data timing when the CNV signal conversion completion signal triggers direct memory access (DMA) to adjust the value of the second comparison register of the timer.

[0013] The present invention also provides a timing generation device for an analog-to-digital converter, comprising a processor and a memory, wherein: The memory is used to store computer programs; The processor is used to read the computer program in the memory and execute the steps of any of the above-described timing generation methods for analog-to-digital converters.

[0014] The present invention also provides a computer-readable storage medium having a readable computer program stored thereon, which, when executed by a processor, implements the steps of any of the above-described methods for timing generation of an analog-to-digital converter.

[0015] This invention provides a timing generation method, system, device, and storage medium for an analog-to-digital converter. By utilizing the DMA and timer of an MCU and configuring parameters, automatic interaction between the DMA and timer is achieved. The output of any number of clock pulses can be automatically achieved by hardware without the need for deep involvement of the MCU. This method is simple, efficient, and low-cost, further improving operating efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and not all embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of this application.

[0017] Figure 1 This is a flowchart of a timing generation method for an analog-to-digital converter provided in an embodiment of the present invention; Figure 2 This is a specific embodiment diagram of a timing generation method for an analog-to-digital converter provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of a CNV signal transition triggering a DMA output to read sampled data pulses in a timing generation method for an analog-to-digital converter provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of outputting arbitrary reading sampling data pulses in the prior art provided by the embodiments of the present invention; Figure 5 This is a schematic diagram of the measured clock pulse waveform in a timing generation method for an analog-to-digital converter provided in an embodiment of the present invention; Figure 6 This is a functional block diagram of a timing generation system for an analog-to-digital converter provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the timing generation device for an analog-to-digital converter provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] To make the description of this disclosure more detailed and complete, illustrative descriptions of embodiments and specific examples of the present invention are provided below; however, these are not the only forms of implementing or utilizing the specific embodiments of the present invention. The embodiments cover features of multiple specific embodiments and the methods, steps, and their order for constructing and operating these specific embodiments. However, other specific embodiments may also be used to achieve the same or equivalent functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0021] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0022] This invention provides a timing generation method for an analog-to-digital converter (ADC), applicable to communication between an MCU (Microcontroller Unit) and an ADC. In high-speed data sampling systems, due to limited MCU interface resources, and considering the ADC's crucial role as a peripheral device for sensor data acquisition, 18-bit or 20-bit ADCs, or multiple ADCs daisy-chained together, are frequently encountered. In such cases, the MCU needs to output 50 or more sampling pulses. However, existing MCU SPI (Serial Peripheral Interface) interfaces typically only allow automatic output of 8 or 16 clock pulses, which is inconvenient for ADCs requiring higher pulse counts. This often necessitates deep MCU involvement in ADC timing control, significantly limiting application scenarios. It is understood that the above application scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in this application. The technical solutions of this application can also be applied to other scenarios.

[0023] Please refer to Figures 1-5 This is used to solve the problem of how to achieve arbitrary clock pulse output and reduce device cost. For example... Figure 1 The diagram shows a flowchart of a timing generation method for an analog-to-digital converter provided by an embodiment of the present invention. The method includes the following steps: Step S1: Obtain the sampling data timing of the analog-to-digital converter (ADC); In this embodiment of the invention, the acquired sampling data can be any number of bits, such as 18-bit or 20-bit ADC, or any number of bits of daisy-chain ADC. The invention does not impose any restrictions on the specific form of the sampling data.

[0024] As an optional implementation, the above-mentioned timing for acquiring sampling data includes acquiring a count value of N-bit sampling data of the ADC, wherein the count value includes the high and low level signals of the sampling clock pulse corresponding to the N-bit sampling data and the corresponding time information.

[0025] As an optional implementation, after obtaining the count value of N-bit sampled data, the method further includes setting the count value of the (N+1)th bit, which is used to control the level state of the (N+1)th pulse of the sampling clock pulse; after the sampling clock pulse corresponding to the N-bit sampled data is output, the (N+1)th pulse is continuously output for a certain period of time.

[0026] In the embodiments of the present invention, please refer to Figure 2This diagram illustrates a specific embodiment of a timing generation method for an analog-to-digital converter (ADC) provided by the present invention. Specifically, it shows a partial timing diagram of an SPI interface configured with an 18-bit ADC and a sampling rate of 1.8 Mbps. Assuming the number of SCK clock cycles to be output is N, corresponding to... Figure 2 The middle part needs to output 18 SCK (CMOS clock) signals.

[0027] Specifically, SCK represents the SPI communication rate. It's important to note that the master on the SPI bus must generate a corresponding clock signal at the start of communication. Within each SPI clock cycle, full-duplex data transmission occurs. The master sends one bit of data on the MOSI (Master Input Slave Output) line, which the slave reads; conversely, the slave sends one bit of data on the MISO line, which the master reads. The clock rate depends on the system clock frequency and the maximum SPI transmission rate that each system can provide.

[0028] Assuming the number of SCK clock cycles to be output is N, the count values ​​of N sampled data are obtained. These count values ​​include the high and low level times of the N clock pulses. The count values ​​of the obtained N sampled data are then compiled into a table and stored in the address addr. It should be noted that the storage of the count values ​​as a table and the specific storage address mentioned in this embodiment are optional specific embodiments. This embodiment does not further limit the storage format of the count values ​​or the specific storage address, as should be known by those skilled in the art.

[0029] After obtaining the count value of N sampled data, it is also necessary to set the count value of the (N+1)th sampled data. The count value of the (N+1)th sampled data is also made into a table with the first N sampled data and stored in the address addr. Of course, as an optional implementation, the count values ​​of the (N+1)th sampled data can also be made into a table and stored in the corresponding address. Unlike the count values ​​of the first N sampled data, the count value of the (N+1)th bit is used to control the level state of the (N+1)th pulse of the sampling clock pulse. After the sampling clock pulse corresponding to the N sampled data is output, the (N+1)th pulse is continuously output for a certain period of time.

[0030] Corresponding to Figure 2As can be clearly observed in the figure, after SCK outputs 18 clock pulses, SCK eventually becomes low and remains low for a certain period of time. If the count value of the N+1th sampled data, i.e., the high / low level state and the duration, is not set, the receiving device cannot distinguish how many clock pulses were previously output. At the same time, those skilled in the art can set the level state of the N+1th pulse to high or low and its duration as needed to distinguish them. This embodiment of the invention does not impose specific limitations on this.

[0031] Step S2: Configure the first comparison register value of the timer according to the sampling data timing of the ADC, and output the start conversion input CNV (Convert input signal) signal corresponding to the sampling data timing of the ADC; As an optional implementation, configuring the first comparison register value of the timer according to the sampling data timing of the ADC includes: configuring the first comparison register value of the timer according to the ADC sampling rate of the sampling data timing based on the pulse width modulation (PWM) output mode.

[0032] In this embodiment of the invention, the timer's OC1 (Output comparison) is first configured to PWM (Pulse Width Modulation) output mode. Then, the first CCR (Comparison register) value of the timer is set according to the ADC sampling rate of the sampled data. The specific value depends on the timing requirements of each ADC chip for the CNV signal. The value c of the first comparison register corresponds to... Figure 2 The middle part determines the width of the CNV signal high level.

[0033] Configure the CC event (compare complete event) of OC1 to automatically trigger DMA (Direct Memory Access). The timer CC event mainly includes IC event (input capture) and OC event (output compare). Specifically, in this embodiment of the invention, it is set to automatically trigger DMA to adjust the value of the second compare register of the timer after the timer counts out.

[0034] Furthermore, the data source address of the DMA is configured as addr, which is the count value of the N+1 sampled data mentioned above. The destination address of the DMA is configured as the address of OC2 of the timer that outputs an arbitrary clock. It should be noted that the purpose of this step is to set the placement position of the N+1 sampled data so that the MCU can read and process it. This invention does not impose any further restrictions on the actual placement position of the sampled data, as should be known by those skilled in the art.

[0035] Step S3: The CNV signal conversion completion signal triggers direct memory access (DMA) to adjust the value of the second comparator register of the timer and outputs the sampling clock pulse corresponding to the ADC sampling data timing.

[0036] As an optional implementation, the above-mentioned triggering of direct memory access to adjust the second comparison register value of the timer includes: triggering direct memory access to adjust the second comparison register value of the timer after the timer count time expires, that is, after the CNV signal output conversion completion signal.

[0037] As an optional implementation, the timer synchronously outputs the sampling clock pulse of the ADC's sampling data and the start conversion input signal.

[0038] As an optional implementation, when the level signal of the start conversion input signal output by the timer changes, the timer outputs the sampling clock pulse corresponding to the sampling data timing.

[0039] In this embodiment of the invention, in step S2, the CC event of OC1 is configured to automatically trigger DMA operation. The specific DMA operation is to trigger the second comparison register value of the DMA timer, that is, to automatically modify the value of the CCR register of OC2, thereby outputting the sampling clock pulse corresponding to the sampling data.

[0040] Specifically, with Figure 2 For example, since 18 clock pulses need to be output, it is necessary to obtain the count values ​​of 18 sampled data and set the count value of the 19th sampled data to low level. The count values ​​of these 19 sampled data are stored in addr. The data source address of DMA is configured as the above addr, and the destination address of DMA is configured as the address of OC2 of the timer that outputs arbitrary clocks. At the same time, it is set to trigger DMA operation whenever OC1 generates a CC event. Since the 18 clock pulses and the high and low level times of the 19th clock pulse have been obtained in advance, the timer counts according to the recorded order. When the counting time of a clock pulse reaches its preset high and low level time, the DMA is triggered to automatically modify the value of the CCR register of OC2 and start the counting and output of the next clock pulse until all 19 clock pulses are output. We can clearly observe that after SCK outputs 18 clock pulses in the figure, SCK finally becomes low level and lasts for a certain period of time.

[0041] For details, please refer to Figure 3This is a schematic diagram of the CNV signal transition triggering DMA output to read sampled data pulse in a timing generation method for an analog-to-digital converter provided in an embodiment of the present invention. Simultaneously with the output clock pulse (i.e., the sampling clock pulse), a CNV signal is also output. Depending on the specific communication format of the ADC chip, such as the SPI protocol, the CNV signal is the master control signal. When the CNV signal transitions from high to low, it triggers the DMA output clock pulse to read sampled data, indicating that the chip's SDO pin is valid at this time. The SDO signal is synchronized with the SCK signal, and one CLK corresponds to one bit of data. Therefore, it is only necessary to pay attention to the SCK signal when the CNV signal is low.

[0042] Further reference Figure 4 This is a schematic diagram of the prior art for outputting arbitrary reading sampled data pulses provided in the embodiments of the present invention. The traditional approach is to add an FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device) to realize a fast channel between the peripheral device and the MCU. The FPGA is programmed to control the SPI device with an arbitrary number of pulses. Although this approach frees up the MCU, the system is relatively complex, the device cost and labor cost are high, and it further increases the difficulty of maintenance and improvement. Therefore, it has shortcomings in actual operation and is not advisable.

[0043] Please refer to further details. Figure 5 This is a schematic diagram of the measured clock pulse waveform in a timing generation method for an analog-to-digital converter provided in an embodiment of the present invention. The rectangle in the figure controls the clock interval between two data points, which can be adjusted by programming to meet the requirements of different chips. The specific programming method is known to those skilled in the art, and the present invention will not elaborate further.

[0044] Based on the timing generation method of the above analog-to-digital converter, such as Figure 6 As shown, this embodiment of the invention also provides a timing generation system for an analog-to-digital converter, which includes a data acquisition module 601, a data configuration module 602, and a data output module 603. The aforementioned data acquisition module 601 is used to acquire the timing of the sampled data from the analog-to-digital converter (ADC); The data configuration module 602 described above is used to configure the first comparison register value of the timer according to the sampling data timing of the ADC, and output the start conversion input (CNV) signal corresponding to the sampling data timing of the ADC; The aforementioned data output module 603 is used to output the sampling clock pulse corresponding to the ADC sampling data timing sequence when the CNV signal conversion completion signal triggers direct memory access (DMA) to adjust the value of the second comparison register of the timer.

[0045] For further details regarding the implementation of the above technical solution by each module in the timing generation system of the analog-to-digital converter, please refer to the description in the timing generation method of the analog-to-digital converter provided in the above embodiments of the invention, which will not be repeated here.

[0046] Based on the timing generation method of the above analog-to-digital converter, such as Figure 7 As shown in the diagram, this embodiment of the invention also provides a schematic diagram of a timing generation device for an analog-to-digital converter. The device includes a processor 701 and a memory 702 coupled to the processor 701. The memory 702 stores a computer program, which, when executed by the processor 701, causes the processor 701 to perform the steps of the timing generation method for the analog-to-digital converter described in the above embodiment.

[0047] For further details regarding the implementation of the above technical solution by the processor 701 in the timing generation device of the analog-to-digital converter, please refer to the description in the timing generation method of the analog-to-digital converter provided in the above embodiments of the invention, which will not be repeated here.

[0048] The processor 701 can also be called a CPU (Central Processing Unit). The processor 701 may be an integrated circuit chip with signal processing capabilities. The processor 701 can also be a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware modules. The general-purpose processor can be a microprocessor, or the processor 701 can be any conventional processor.

[0049] like Figure 8As shown in the diagram, this embodiment of the invention also provides a schematic diagram of a computer-readable storage medium, on which a readable computer program 801 is stored. The computer program 801 can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in various embodiments of the invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks or optical disks, ROM (Read-Only Memory), RAM (Random Access Memory), or terminal devices such as computers, servers, mobile phones, and tablets.

[0050] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0051] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0052] This invention provides a timing generation method, system, device, and storage medium for an analog-to-digital converter. By utilizing the DMA and timer of an MCU and configuring parameters, automatic interaction between the DMA and timer is achieved. The output of any number of clock pulses can be automatically achieved by hardware without the need for deep involvement of the MCU. This method is simple, efficient, and low-cost, further improving operating efficiency.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A timing generation method for an analog-to-digital converter, characterized in that, include: Acquire the timing sequence of the sampled data from the analog-to-digital converter (ADC); Configure the first comparison register value of the timer according to the sampling data timing of the ADC, and output the start conversion input (CNV) signal corresponding to the sampling data timing of the ADC; The CNV signal conversion completion signal triggers direct memory access (DMA) to adjust the value of the second comparator register of the timer and outputs the sampling clock pulse corresponding to the ADC sampling data timing.

2. The timing generation method for an analog-to-digital converter as described in claim 1, characterized in that, The timing sequence for acquiring the sampled data of the analog-to-digital converter (ADC) includes: Obtain the count value of N-bit sampled data from the ADC, wherein the count value includes the high and low level signals of the sampling clock pulse corresponding to the N-bit sampled data.

3. The timing generation method for an analog-to-digital converter as described in claim 2, characterized in that, After obtaining the count value of N-bit sampled data, the process further includes: Set the count value of the (N+1)th bit, which is used to control the level state of the (N+1)th pulse of the sampling clock pulse; After the sampling clock pulse corresponding to the N-bit sampled data is output, the (N+1)th pulse is continuously output for a certain period of time.

4. The timing generation method for an analog-to-digital converter as described in claim 1, characterized in that, The step of configuring the first compare register value of the timer according to the timing of the sampled data from the ADC includes: Based on the pulse width modulation (PWM) output mode, the first comparison register value of the timer is configured according to the ADC sampling rate of the sampled data timing.

5. The timing generation method for an analog-to-digital converter as described in claim 1, characterized in that, The triggering of direct memory access to adjust the second compare register value of the timer includes: After the CNV signal output conversion is complete, the direct memory access is triggered to adjust the value of the second compare register of the timer.

6. The timing generation method for an analog-to-digital converter as described in claim 1, characterized in that, The timer synchronously outputs the sampling clock pulse and the start conversion input signal of the ADC's sampling data.

7. The timing generation method for an analog-to-digital converter as described in claim 5, characterized in that, When the level signal of the start conversion input signal output by the timer changes, the timer outputs the sampling clock pulse corresponding to the sampling data timing.

8. A timing generation system for an analog-to-digital converter, characterized in that, It includes a data acquisition module, a data configuration module, and a data output module; The data acquisition module is used to acquire the timing data of the analog-to-digital converter (ADC); The data configuration module is used to configure the first comparison register value of the timer according to the sampling data timing of the ADC, and output the start conversion input (CNV) signal corresponding to the sampling data timing of the ADC. The data output module is used to output the sampling clock pulse corresponding to the ADC sampling data timing when the CNV signal conversion completion signal triggers direct memory access (DMA) to adjust the value of the second comparison register of the timer.

9. A timing generation device for an analog-to-digital converter, comprising a processor and a memory, wherein: The memory is used to store computer programs; The processor is used to read the computer program in the memory and execute the steps of the timing generation method for the analog-to-digital converter as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a readable computer program stored thereon, the program being executed by a processor to implement the steps of the timing generation method for an analog-to-digital converter as described in any one of claims 1 to 7.

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