A method, apparatus, device and medium for improving NVMe accelerator availability

Abstract

The application provides a method, device, equipment and readable medium for improving the availability of an NVMe accelerator, the method comprising: reserving unused IO queues for a CPU in an NVMe disk; in response to receiving an instruction to modify the configuration of the NVMe accelerator, opening up memory space for the IO queues reserved for the CPU; sending unprocessed IO commands in the NVMe accelerator to the CPU through a data channel, and issuing the IO commands to the disk through the IO queues reserved for the CPU for processing; in response to the completion of the modification of the configuration of the NVMe accelerator, opening the NVMe accelerator and sending the IO commands to the NVMe accelerator or the CPU for processing based on the verification code stored in the configuration register of the NVMe accelerator. Through the use of the scheme of the application, the dynamic closing, opening and dynamic resource adjustment of the NVMe accelerator can be realized, the dynamic changes of the server hardware environment and the user can be adapted, the sending of the disk IO commands can be realized without interruption, and the high availability of the server can be ensured.

Description

Technical Field

[0001] This invention relates to the field of computers, and more particularly to a method, apparatus, device, and readable medium for improving the availability of NVMe accelerators. Background Technology

[0002] NVMe hard drives are increasingly being used in storage systems such as storage servers due to their superior performance. Compared to traditional HDDs with interfaces such as SATA / SAS, NVMe hard drives offer numerous advantages. Using NVMe hard drives can help storage systems overcome traditional performance bottlenecks and achieve significant performance improvements. However, these leaps in performance also bring new challenges to system design.

[0003] Servers typically require high availability, meaning service interruptions are not permitted. However, in some scenarios, such as disk or accelerator errors, or when the number of users or disks dynamically changes, requiring dynamic adjustments to accelerator resource allocation, it becomes unavoidable to shut down the hardware accelerator, modify its configuration, and then restart it. Since I / O commands are processed by the hardware accelerator, service interruptions are inevitable.

[0004] Furthermore, a more serious problem is that hardware systems using NVMe accelerators are often quite complex, with very deep pipelines. This means that after receiving an I / O command from the server, the command needs to be broken down into many steps and then executed sequentially. Therefore, when a hardware accelerator undergoes dynamic adjustments, it not only affects new server I / O processing during the adjustment period, but also, because the already broken-down server I / O may not be compatible with the adjusted hardware accelerator, shutting down the accelerator requires waiting for all the broken-down server I / O to complete, which often takes a considerable amount of time. This further increases the service interruption time. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a method, apparatus, device and readable medium for improving the availability of NVMe accelerators. By using the technical solution of this invention, it is possible to dynamically shut down, open and dynamically adjust the resources of NVMe accelerators, adapt to the dynamic changes of server hardware environment and users, and achieve uninterrupted sending of disk I / O commands, thus ensuring high availability of the server.

[0006] To achieve the above objectives, one aspect of the present invention provides a method for improving the availability of NVMe accelerators, comprising the following steps:

[0007] Reserve unused I / O queues for the CPU in NVMe disks;

[0008] In response to receiving an instruction to modify the NVMe accelerator configuration, memory space is allocated for the IO queue reserved for the CPU;

[0009] Unprocessed IO commands in the NVMe accelerator are sent to the CPU through the data channel, and the IO commands are sent to the disk for processing through the IO queue reserved for the CPU;

[0010] In response to the completion of NVMe accelerator configuration modification, the NVMe accelerator is opened and IO commands are sent to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register.

[0011] According to one embodiment of the present invention, reserving unused I / O queues for the CPU in an NVMe disk includes:

[0012] In response to the maximum number of queues for NVMe disks exceeding a first preset value, one unused IO queue is reserved for each CPU core;

[0013] In response to the maximum number of queues for the NVMe disk being less than the second preset value, all IO queues are assigned to the NVMe accelerator and one IO queue is deleted when the NVMe accelerator configuration is modified. After deletion, an unused IO queue is recreated for the CPU.

[0014] In response to the maximum number of queues for NVMe disks being less than a first preset value but greater than a second preset value, an unused IO queue is reserved for the CPU.

[0015] According to one embodiment of the present invention, it further includes:

[0016] The operating states of the NVMe accelerator are divided into normal operating state, off transition state, off state, and on transition state.

[0017] According to one embodiment of the present invention, sending unprocessed IO commands from the NVMe accelerator to the CPU via a data channel, and then issuing the IO commands to the disk for processing via an IO queue reserved for the CPU includes:

[0018] Switch the NVMe accelerator's running status to a transitional off state;

[0019] The NVMe accelerator internally records the execution status of each IO command issued to the disk and determines whether all IO commands have received IO responses.

[0020] Once all I / O responses have been received, a message is sent to the CPU indicating that the I / O command processing is complete.

[0021] Pause any unprocessed I / O commands in the NVMe accelerator, transfer them to the CPU via the data channel, record the transfer reason as NVMe accelerator shutdown, and switch the running state of the NVMe accelerator to shutdown;

[0022] The CPU sends I / O commands to the disk for processing by reserving an I / O queue for the CPU.

[0023] According to one embodiment of the present invention, it further includes:

[0024] In response to the NVMe accelerator being in a powered-off state, all IO commands received by the NVMe accelerator are forwarded to the CPU, and the reason is recorded as the NVMe accelerator being powered off.

[0025] According to one embodiment of the present invention, in response to the completion of NVMe accelerator configuration modification, opening the NVMe accelerator and sending IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register includes:

[0026] In response to the completion of NVMe accelerator configuration modifications, the running state of the NVMe accelerator will be switched to an open transitional state.

[0027] In response to the NVMe accelerator's running state being in the open transition state, the verification code is stored in the NVMe accelerator configuration register, and IO commands issued by the system are received, while unprocessed IO commands in the CPU are sent to the NVMe accelerator.

[0028] In response to the NVMe accelerator receiving an IO command, the IO command is decomposed to obtain the IO command verification code;

[0029] Compare the verification code of the IO command with the verification code in the NVMe accelerator configuration register;

[0030] The verification code in response to the IO command is the same as the verification code in the NVMe accelerator configuration register, and the received IO command is executed.

[0031] The verification code in response to the IO command is different from the verification code in the NVMe accelerator configuration register, and the IO command is handed over to the CPU for processing through the data channel.

[0032] According to one embodiment of the present invention, it further includes:

[0033] In response to the NVMe accelerator's running status being in an open transition state, determine whether the configuration modification has caused a change in the operating environment;

[0034] In response to changes in the operating environment caused by configuration modifications, the original verification code value is read out, incremented by 1 to form a new verification code, and the new verification code is written into the NVMe accelerator configuration register.

[0035] Inform the chip system of the new verification code value;

[0036] Since the configuration changes did not cause any changes in the operating environment, the verification code will not be updated.

[0037] Another aspect of the present invention provides an apparatus for improving the availability of NVMe accelerators, the apparatus comprising:

[0038] The reservation module is configured to reserve unused IO queues for the CPU in the NVMe disk;

[0039] The configuration module is configured to allocate memory space for the IO queue reserved for the CPU in response to a command to modify the NVMe accelerator configuration.

[0040] The sending module is configured to send unprocessed IO commands from the NVMe accelerator to the CPU through the data channel, and to send the IO commands to the disk for processing through the IO queue reserved for the CPU;

[0041] The processing module is configured to, in response to the completion of NVMe accelerator configuration modification, open the NVMe accelerator and send IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register.

[0042] Another aspect of the embodiments of the present invention also provides a computer device, the computer device comprising:

[0043] At least one processor; and

[0044] The memory stores computer instructions that can be executed by a processor, which, when executed by the processor, implement the steps of any of the methods described above.

[0045] In another aspect, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above methods.

[0046] The present invention has the following beneficial technical effects: The method for improving the availability of NVMe accelerators provided in the embodiments of the present invention, by reserving unused IO queues for the CPU in the NVMe disk; in response to receiving an instruction to modify the NVMe accelerator configuration, allocating memory space for the IO queues reserved for the CPU; sending unprocessed IO commands in the NVMe accelerator to the CPU through the data channel, and sending the IO commands to the disk for processing through the IO queues reserved for the CPU; and in response to the completion of the NVMe accelerator configuration modification, opening the NVMe accelerator and sending the IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register, can realize the dynamic shutdown, opening, and dynamic resource adjustment of the NVMe accelerator, can adapt to the dynamic changes of server hardware environment and users, can achieve uninterrupted transmission of disk IO commands, and ensure the high availability of the server. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic flowchart illustrating a method for improving the availability of NVMe accelerators according to an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of the IO queue distribution according to an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram illustrating the operating state of an NVMe accelerator according to an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the data path related to the verification code mechanism according to an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram illustrating that, according to an embodiment of the present invention, the verification code only sends new I / O to the hardware;

[0053] Figure 6 This is a schematic diagram of the overall framework according to an embodiment of the present invention;

[0054] Figure 7 A schematic diagram of an apparatus for improving the availability of NVMe accelerators according to an embodiment of the present invention;

[0055] Figure 8This is a schematic diagram of a computer device according to an embodiment of the present invention;

[0056] Figure 9 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0058] Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a method for improving the availability of NVMe accelerators. Figure 1 The diagram shown is a schematic flowchart of the method.

[0059] like Figure 1 As shown, the method may include the following steps:

[0060] S1 reserves unused I / O queues for the CPU within the NVMe disk. If the maximum number of queues on the NVMe disk is greater than a first preset value, one unused I / O queue is reserved for each CPU core. For a single-core CPU, multiple unused I / O queues can be reserved. If the maximum number of queues on the NVMe disk is less than a second preset value, all I / O queues are allocated to the NVMe accelerator. When modifying the NVMe accelerator configuration, one I / O queue is deleted, and a new unused I / O queue is created for the CPU after deletion. If the maximum number of queues on the NVMe disk is less than the first preset value but greater than the second preset value, then for both single-core and multi-core CPUs, only one unused I / O queue is reserved for the CPU. The reserved I / O queue does not allocate memory space to save memory usage; memory space is only allocated for the reserved queue when needed.

[0061] In response to a command to modify the NVMe accelerator configuration, S2 allocates memory space for the I / O queues reserved for the CPU. Under normal operating conditions, the CPU may not allocate memory space for the reserved I / O queues to conserve memory. The CPU only allocates memory space for the I / O command queues managed by the hardware accelerator (the I / O response queue is typically located in the hardware accelerator; if it were in memory, the CPU would also need to allocate this space. This is an implementation detail of the accelerator and does not affect the implementation of this invention, nor is it within the scope of this discussion). S2 then sends an I / O queue creation command to the disk through the management command queue and completes the binding with the aforementioned memory space.

[0062] S3 sends unprocessed IO commands from the NVMe accelerator to the CPU via the data channel, and then distributes the IO commands to the disk for processing via the IO queue reserved for the CPU.

[0063] In response to the completion of NVMe accelerator configuration modifications, S4 activates the NVMe accelerator and sends I / O commands to either the NVMe accelerator or the CPU for processing based on the verification code stored in the NVMe accelerator configuration register. The verification code is a binary code of several bits (minimum 1 bit). The bit width is related to the on / off frequency and system termination time; higher frequencies or longer termination times require a wider bit width. The verification code is stored in two locations: the NVMe accelerator's configuration register and the I / O command sent to the NVMe accelerator after the system has deconstructed the I / O command from the server. Whenever the NVMe accelerator receives an I / O command, it compares the two verification codes. If they match, the NVMe accelerator processes the command; otherwise, the CPU handles it.

[0064] In this invention, NVMe disk I / O commands are processed not only by the NVMe accelerator but also by the CPU, and the I / O commands processed by the CPU and NVMe accelerator belong to the same NVMe disk. During normal operation, all disk I / O commands are processed by the NVMe accelerator to achieve maximum disk read / write performance. At other times, such as during processes involving turning the NVMe accelerator on / off (e.g., modifying / enabling the accelerator hardware configuration), there may be stages where the CPU and NVMe accelerator jointly process disk I / O commands, or the CPU processes disk I / O commands independently. Operations such as turning the NVMe accelerator on / off or dynamically adjusting NVMe accelerator resources can ensure uninterrupted distribution of disk I / O commands.

[0065] Using a CAPTCHA mechanism enables rapid execution of the above process without waiting for the already disassembled server I / O to complete. Compared to traditional implementations, the main advantages of this invention are:

[0066] 1. A hardware and software collaboration mechanism was designed to enable dynamic shutdown / opening and dynamic resource adjustment of the NVMe accelerator to adapt to dynamic changes in server hardware environment / users, etc.

[0067] 2. During the dynamic adjustment process, disk I / O commands can be sent without interruption, ensuring high availability of the server.

[0068] By using the technical solution of this invention, it is possible to dynamically shut down, open, and dynamically adjust the resources of the NVMe accelerator, adapt to dynamic changes in server hardware environment and users, and ensure high availability of the server by sending disk I / O commands without interruption.

[0069] In a preferred embodiment of the present invention, reserving unused IO queues for the CPU in an NVMe disk includes:

[0070] In response to the maximum number of queues for NVMe disks exceeding a first preset value, one unused IO queue is reserved for each CPU core;

[0071] In response to the maximum number of queues for the NVMe disk being less than the second preset value, all IO queues are assigned to the NVMe accelerator and one IO queue is deleted when the NVMe accelerator configuration is modified. After deletion, an unused IO queue is recreated for the CPU.

[0072] In response to the maximum number of queues on the NVMe disk being less than a first preset value but greater than a second preset value, one unused IO queue is reserved for the CPU. This means that if an NVMe disk supports a maximum of n IO queues, only n-1 queues will be available to the NVMe accelerator, while one queue will remain unused. To achieve this, when the CPU performs the IO command queue creation operation (using the management command queue), it can create only n-1 IO command queues and IO response queues for the NVMe disk and only inform the NVMe accelerator of the doorbell registers (hereinafter collectively referred to as the IO doorbell registers) of these n-1 IO command queues and IO response queues. Since the NVMe accelerator relies on configuration information issued by the CPU in a hardware-software co-operation accelerator, under the above operation, the NVMe accelerator can only obtain the doorbell register addresses of n-1 IO queues, and therefore can only operate on these n-1 queues. Figure 2 As shown.

[0073] Considering performance during the transition phase, the above method can be generalized. When the maximum number of queues on the NVMe disk is relatively abundant (i.e., the number exceeds the first preset value), more IO command queues and IO response queues can be reserved for the CPU. In multi-core CPU scenarios, one queue can generally be reserved for each CPU core.

[0074] If the maximum number of queues for the NVMe disk is small, i.e., less than the second preset value, then to ensure normal IO performance, all IO queues can be allocated to the NVMe accelerator. During the transition phase, the CPU performs a handshake with the NVMe accelerator, suspends one of the IO queues, issues an IO queue deletion command through the management command queue, and then issues a recreate command to recreate the IO queue, pointing the queue to the memory space managed by the CPU.

[0075] In a preferred embodiment of the present invention, it further includes:

[0076] The operating states of NVMe accelerators are divided into normal operating state, shutdown transition state, shutdown state, and startup transition state. For example... Figure 3As shown, the NVMe accelerator's operating state is divided into four states: normal operation, shutdown transition state, shutdown state, and open transition state. To enable dynamic changes to the NVMe accelerator configuration, upon receiving a request, the CPU switches to the shutdown transition state. In this state, it performs cleanup work on the NVMe accelerator and the entire chip system using the accelerator. After cleanup, it switches back to the shutdown state, where hardware configuration can be modified. After modification, it switches back to the open transition state. In the open transition state, new server I / O commands are handed over to the NVMe accelerator for processing, and the CPU also hands over any received but unprocessed I / O commands to the NVMe accelerator. After the handover is complete, it returns to the normal operation state.

[0077] In a preferred embodiment of the present invention, sending unprocessed IO commands from the NVMe accelerator to the CPU via a data channel, and then issuing the IO commands to the disk for processing via an IO queue reserved for the CPU includes:

[0078] Switch the NVMe accelerator's running status to a transitional off state;

[0079] The NVMe accelerator internally records the execution status of each IO command issued to the disk and determines whether all IO commands have received IO responses.

[0080] Once all I / O responses have been received, a message is sent to the CPU indicating that the I / O command processing is complete.

[0081] Pause any unprocessed I / O commands in the NVMe accelerator, transfer them to the CPU via the data channel, record the transfer reason as NVMe accelerator shutdown, and switch the running state of the NVMe accelerator to shutdown;

[0082] The CPU sends I / O commands to the disk for processing by reserving an I / O queue for the CPU.

[0083] The above steps are the cleanup tasks that the NVMe accelerator needs to perform. Shutting down an NVMe accelerator usually takes a relatively long time, so the NVMe accelerator needs to handle cleanup tasks internally, mainly in the following three categories:

[0084] 1. The NVMe accelerator has been sent to the disk and is waiting for the disk to return the result.

[0085] 2. Commands that have been issued to the NVMe accelerator, are being processed or have not yet started processing, and that the NVMe accelerator has not yet issued to the disk;

[0086] 3. The chip system has completed command parsing, but no commands have yet been sent to the NVMe accelerator in the pipeline.

[0087] Regarding the first issue, the NVMe accelerator needs to add a handshake signal with the CPU. When the NVMe accelerator needs to be shut down, the CPU first sends a shutdown request to the NVMe accelerator. Internally, the NVMe accelerator needs to record the execution status of every I / O operation sent to the disk. Upon receiving the request, it determines whether all I / O commands have received an I / O response. If all have, it sends a notification to the CPU that the shutdown is complete.

[0088] Regarding the second issue, a data channel needs to be added between the NVMe accelerator and the CPU for the NVMe accelerator to send I / O commands to the CPU. When the NVMe accelerator receives a shutdown request, it can stop executing commands that have not yet been sent to the disk, and then hand over the command to the CPU through the data channel, recording the reason for the handover as the NVMe accelerator being shut down. After receiving the command, the CPU sends it to the disk through the I / O command queue managed by the CPU.

[0089] Regarding the third question, after receiving a shutdown request, the NVMe accelerator does not execute newly received IO commands. Instead, it transfers the command to the CPU through the data channel, recording the transfer reason as "NVMe accelerator shutdown." Upon receiving the command, the CPU issues it to the disk through the IO command queue managed by the CPU.

[0090] After implementing the above method, the chip system can still receive new IO commands from the server. These new IO commands will be processed by the CPU, and the IO commands previously received from the server will not be affected. They will be diverted from the NVMe accelerator to the CPU for execution. Therefore, from the server's perspective, the process is not even perceptible.

[0091] In a preferred embodiment of the present invention, it further includes:

[0092] In response to the NVMe accelerator being in the shutdown state, all I / O commands received by the NVMe accelerator are forwarded to the CPU, and the reason is recorded as NVMe accelerator shutdown. After a period of time, once the NVMe accelerator has received all I / O responses from the disk, it notifies the CPU that shutdown is complete, and then the running state enters the shutdown state. In the shutdown state, the NVMe accelerator may continue to receive I / O commands from the chip system. This is because entering the shutdown state does not require waiting for the chip system to complete dispatching all parsed but undispatched tasks. Since the pipeline depth of chip tasks is generally very deep, waiting for this process would greatly prolong the shutdown transition time and often require more complex detection and judgment logic. Therefore, in the NVMe accelerator shutdown state, the data path from the command input channel to the CPU remains open, and all received I / O commands are forwarded to the CPU, with the reason marked as hardware engine shutdown.

[0093] In a preferred embodiment of the present invention, in response to the completion of NVMe accelerator configuration modification, opening the NVMe accelerator and sending IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register includes:

[0094] In response to the completion of NVMe accelerator configuration modifications, the running state of the NVMe accelerator will be switched to an open transitional state.

[0095] In response to the NVMe accelerator's running state being in the open transition state, the verification code is stored in the NVMe accelerator configuration register, and IO commands issued by the system are received, while unprocessed IO commands in the CPU are sent to the NVMe accelerator.

[0096] In response to the NVMe accelerator receiving an IO command, the IO command is decomposed to obtain the IO command verification code;

[0097] Compare the verification code of the IO command with the verification code in the NVMe accelerator configuration register;

[0098] The verification code in response to the IO command is the same as the verification code in the NVMe accelerator configuration register, and the received IO command is executed.

[0099] The verification code in response to the IO command is different from the verification code in the NVMe accelerator configuration register, and the IO command is handed over to the CPU for processing through the data channel.

[0100] In the disabled state, the CPU modifies the configuration parameters of the hardware acceleration engine. After the modification, the CPU reopens the hardware acceleration engine, notifies the chip system NVMe accelerator that it can handle new I / O commands, and switches the running state to an open transitional state. It should be noted that some modifications to the hardware acceleration engine configuration parameters do not change the operating environment; that is, the modified hardware acceleration engine can still execute I / O commands received from the server before the modification. However, some modifications will change the operating environment, such as changing the binding relationship between the hardware acceleration engine and the disk. This will cause the reopened hardware acceleration engine to be unable to execute these "original" I / O commands. To address the issue of operational changes, this invention introduces a "verification code" mechanism. The verification code is a binary code of several bits (minimum 1 bit). The bit width is related to the shutdown / open frequency and the system termination time; the higher the frequency or the longer the system termination time, the wider the required bit width. The verification code is stored in two places: one is in the NVMe accelerator's configuration register, and the other is in the I / O commands sent to the NVMe accelerator after the system deconstructs the I / O commands from the server. Whenever an NVMe accelerator receives an I / O command, it needs to compare the verification code of the I / O command with the verification code in its own configuration register. If they match, the I / O command can be executed; otherwise, it is handed over to the CPU for processing via the data channel with the CPU. Figure 4 As shown, it should be noted that Figure 4 This only describes the data pathways related to the CAPTCHA mechanism, and does not describe all pathways in the system.

[0101] In a preferred embodiment of the present invention, it further includes:

[0102] In response to the NVMe accelerator's running status being in an open transition state, determine whether the configuration modification has caused a change in the operating environment;

[0103] In response to changes in the operating environment caused by configuration modifications, the original verification code value is read out, incremented by 1 to form a new verification code, and the new verification code is written into the NVMe accelerator configuration register.

[0104] Inform the chip system of the new verification code value;

[0105] Since the configuration changes did not cause any changes in the operating environment, the verification code will not be updated.

[0106] When the CPU switches its operating state from the off state to the on transition state, it will make a judgment. If the configuration change will cause a change in the operating environment, the CPU will first change the NVMe accelerator's verification code. The simplest rule is to read the value of the original verification code register, add 1, and then write it back to the verification code register. Figure 5As shown. Then, before the CPU notifies the chip system that the NVMe accelerator can process new IO commands, it needs to synchronize the chip system's environment parameters and inform the chip system of the aforementioned new verification code value. Upon receiving the new server IO command, the chip system will decompose the IO command according to the new environment parameters and configure the verification code of the decomposed IO command to be sent to the NVMe accelerator as the new verification code. If this configuration modification does not cause a change in the operating environment, both the NVMe accelerator and the chip system can retain the original verification code.

[0107] Considering that NVMe accelerators generally offer better performance, this invention proposes that after an NVMe accelerator is re-enabled, the CPU should, as far as possible, offload I / O commands to the NVMe accelerator for processing. To achieve this handover from the CPU to the NVMe accelerator, an additional data channel from the CPU to the NVMe accelerator is needed, such as... Figure 6 As shown.

[0108] When the hardware engine is reopened, there will be various IO commands in the system, such as IO commands for the "old" environment that have been disassembled and are to be dispatched to the hardware, IO commands for the "new" environment that have been dispatched to the hardware, IO commands for the "old" environment that have been dispatched to the CPU, IO commands for the "old" environment that the CPU receives from the chip system and is to be executed, IO commands that have been transferred to the CPU from the NVMe accelerator, and IO commands that have been transferred to the hardware but have not yet reached the CPU. Opening the transition state requires proper handling of the above IO commands, which is therefore a very complex and error-prone process.

[0109] This invention proposes to perform I / O processing according to the following principles:

[0110] 1. The CPU compares the verification code in the IO command received from the chip system with the new verification code from the NVMe accelerator. If they match, the code is handed over to the NVMe accelerator; otherwise, it is executed by the CPU.

[0111] 2. The CPU receives commands from the NVMe accelerator and determines the reason for the handover. If the accelerator is entering a shutdown transition or shutting down, it checks whether the verification code of the IO command is the same as the new verification code. If they are the same, the command is handed over to the NVMe accelerator again; otherwise, the CPU executes the command. If the handover reason is due to a mismatch in verification codes, the CPU executes the command.

[0112] 3. The NVMe accelerator compares the verification codes of the IO commands received from the system. If they are the same, the command is executed; otherwise, it is handed over to the CPU, and the reason for the handover is marked as a different verification code.

[0113] 4. The NVMe accelerator still needs to compare the verification codes for the IO commands received from the CPU. If they are the same, the command is executed; otherwise, it is handed over to the CPU, and the reason for the handover is marked as a different verification code.

[0114] The end marker for the open transition state is unclear because the aforementioned system contains a wide variety of IO commands. Tracking and counting each type of IO command is feasible, but resource-intensive. Therefore, this invention adopts a simpler approach: while in the open transition state, a request to enter the closed transition state can be received. After entering the closed transition state and being reopened, the CPU will assign a verification code different from both the first and second times. Therefore, in the new open transition state, the CPU may transfer IO commands to the NVMe accelerator, but these commands, which are not processed by the NVMe accelerator, are the second IO commands, i.e., not the same as the current verification code. This is why the NVMe accelerator still needs to compare the IO commands transferred by the CPU. From receiving the request to switch to the closed transition state to the system stabilizing in normal operation, as mentioned above, there is no clear time boundary. This invention proposes setting a very conservative time that guarantees the system will re-stabilize. This time is called the minimum switching time. The CPU then needs to maintain a table where each entry corresponds to a verification code, recording the time when the verification code was submitted with the closed request. After receiving a shutdown request, the CPU first calculates the target CAPTCHA, then extracts the time value based on the CAPTCHA, adds the minimum switching time to this time value to obtain the earliest switching time, and compares the current time with the earliest switching time. If the current time is less than the earliest switching time, the CPU needs to wait until it is greater than or equal to the earliest switching time. After implementing the above method, for systems with a large minimum switching time that cannot directly meet the on / off frequency requirements, this can be addressed by increasing the CAPTCHA bit width.

[0115] By using the technical solution of this invention, it is possible to dynamically shut down, open, and dynamically adjust the resources of the NVMe accelerator, adapt to dynamic changes in server hardware environment and users, and ensure high availability of the server by sending disk I / O commands without interruption.

[0116] It should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The embodiments of the computer program described above can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0117] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0118] Based on the above objectives, a second aspect of the embodiments of the present invention provides an apparatus for improving the availability of NVMe accelerators, such as... Figure 7 As shown, the device 200 includes:

[0119] The reservation module is configured to reserve unused IO queues for the CPU in the NVMe disk;

[0120] The configuration module is configured to allocate memory space for the IO queue reserved for the CPU in response to a command to modify the NVMe accelerator configuration.

[0121] The sending module is configured to send unprocessed IO commands from the NVMe accelerator to the CPU through the data channel, and to send the IO commands to the disk for processing through the IO queue reserved for the CPU;

[0122] The processing module is configured to, in response to the completion of NVMe accelerator configuration modification, open the NVMe accelerator and send IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register.

[0123] In view of the above objectives, a third aspect of the present invention provides a computer device. Figure 8 The diagram shown is a schematic representation of an embodiment of the computer device provided by the present invention. Figure 8 As shown, embodiments of the present invention include the following apparatus: at least one processor 21; and a memory 22 storing computer instructions 23 executable on the processor, which, when executed by the processor, implement the following method:

[0124] Reserve unused I / O queues for the CPU in NVMe disks;

[0125] In response to receiving an instruction to modify the NVMe accelerator configuration, memory space is allocated for the IO queue reserved for the CPU;

[0126] Unprocessed IO commands in the NVMe accelerator are sent to the CPU through the data channel, and the IO commands are sent to the disk for processing through the IO queue reserved for the CPU;

[0127] In response to the completion of NVMe accelerator configuration modification, the NVMe accelerator is opened and IO commands are sent to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register.

[0128] In a preferred embodiment of the present invention, reserving unused IO queues for the CPU in an NVMe disk includes:

[0129] In response to the maximum number of queues for NVMe disks exceeding a first preset value, one unused IO queue is reserved for each CPU core;

[0130] In response to the maximum number of queues for the NVMe disk being less than the second preset value, all IO queues are assigned to the NVMe accelerator and one IO queue is deleted when the NVMe accelerator configuration is modified. After deletion, an unused IO queue is recreated for the CPU.

[0131] In response to the maximum number of queues for NVMe disks being less than a first preset value but greater than a second preset value, an unused IO queue is reserved for the CPU.

[0132] In a preferred embodiment of the present invention, it further includes:

[0133] The operating states of the NVMe accelerator are divided into normal operating state, off transition state, off state, and on transition state.

[0134] In a preferred embodiment of the present invention, sending unprocessed IO commands from the NVMe accelerator to the CPU via a data channel, and then issuing the IO commands to the disk for processing via an IO queue reserved for the CPU includes:

[0135] Switch the NVMe accelerator's running status to a transitional off state;

[0136] The NVMe accelerator internally records the execution status of each IO command issued to the disk and determines whether all IO commands have received IO responses.

[0137] Once all I / O responses have been received, a message is sent to the CPU indicating that the I / O command processing is complete.

[0138] Pause any unprocessed I / O commands in the NVMe accelerator, transfer them to the CPU via the data channel, record the transfer reason as NVMe accelerator shutdown, and switch the running state of the NVMe accelerator to shutdown;

[0139] The CPU sends I / O commands to the disk for processing by reserving an I / O queue for the CPU.

[0140] In a preferred embodiment of the present invention, it further includes:

[0141] In response to the NVMe accelerator being in a powered-off state, all IO commands received by the NVMe accelerator are forwarded to the CPU, and the reason is recorded as the NVMe accelerator being powered off.

[0142] In a preferred embodiment of the present invention, in response to the completion of NVMe accelerator configuration modification, opening the NVMe accelerator and sending IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register includes:

[0143] In response to the completion of NVMe accelerator configuration modifications, the running state of the NVMe accelerator will be switched to an open transitional state.

[0144] In response to the NVMe accelerator's running state being in the open transition state, the verification code is stored in the NVMe accelerator configuration register, and IO commands issued by the system are received, while unprocessed IO commands in the CPU are sent to the NVMe accelerator.

[0145] In response to the NVMe accelerator receiving an IO command, the IO command is decomposed to obtain the IO command verification code;

[0146] Compare the verification code of the IO command with the verification code in the NVMe accelerator configuration register;

[0147] The verification code in response to the IO command is the same as the verification code in the NVMe accelerator configuration register, and the received IO command is executed.

[0148] The verification code in response to the IO command is different from the verification code in the NVMe accelerator configuration register, and the IO command is handed over to the CPU for processing through the data channel.

[0149] In a preferred embodiment of the present invention, it further includes:

[0150] In response to the NVMe accelerator's running status being in an open transition state, determine whether the configuration modification has caused a change in the operating environment;

[0151] In response to changes in the operating environment caused by configuration modifications, the original verification code value is read out, incremented by 1 to form a new verification code, and the new verification code is written into the NVMe accelerator configuration register.

[0152] Inform the chip system of the new verification code value;

[0153] Since the configuration changes did not cause any changes in the operating environment, the verification code will not be updated.

[0154] In view of the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium. Figure 9 The diagram shown is a schematic representation of an embodiment of the computer-readable storage medium provided by the present invention. Figure 9 As shown, computer-readable storage medium 31 stores a computer program 32 that, when executed by a processor, performs the following methods:

[0155] Reserve unused I / O queues for the CPU in NVMe disks;

[0156] In response to receiving an instruction to modify the NVMe accelerator configuration, memory space is allocated for the IO queue reserved for the CPU;

[0157] Unprocessed IO commands in the NVMe accelerator are sent to the CPU through the data channel, and the IO commands are sent to the disk for processing through the IO queue reserved for the CPU;

[0158] In response to the completion of NVMe accelerator configuration modification, the NVMe accelerator is opened and IO commands are sent to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register.

[0159] In a preferred embodiment of the present invention, reserving unused IO queues for the CPU in an NVMe disk includes:

[0160] In response to the maximum number of queues for NVMe disks exceeding a first preset value, one unused IO queue is reserved for each CPU core;

[0161] In response to the maximum number of queues for the NVMe disk being less than the second preset value, all IO queues are assigned to the NVMe accelerator and one IO queue is deleted when the NVMe accelerator configuration is modified. After deletion, an unused IO queue is recreated for the CPU.

[0162] In response to the maximum number of queues for NVMe disks being less than a first preset value but greater than a second preset value, an unused IO queue is reserved for the CPU.

[0163] In a preferred embodiment of the present invention, it further includes:

[0164] The operating states of the NVMe accelerator are divided into normal operating state, off transition state, off state, and on transition state.

[0165] In a preferred embodiment of the present invention, sending unprocessed IO commands from the NVMe accelerator to the CPU via a data channel, and then issuing the IO commands to the disk for processing via an IO queue reserved for the CPU includes:

[0166] Switch the NVMe accelerator's running status to a transitional off state;

[0167] The NVMe accelerator internally records the execution status of each IO command issued to the disk and determines whether all IO commands have received IO responses.

[0168] Once all I / O responses have been received, a message is sent to the CPU indicating that the I / O command processing is complete.

[0169] Pause any unprocessed I / O commands in the NVMe accelerator, transfer them to the CPU via the data channel, record the transfer reason as NVMe accelerator shutdown, and switch the running state of the NVMe accelerator to shutdown;

[0170] The CPU sends I / O commands to the disk for processing by reserving an I / O queue for the CPU.

[0171] In a preferred embodiment of the present invention, it further includes:

[0172] In response to the NVMe accelerator being in a powered-off state, all IO commands received by the NVMe accelerator are forwarded to the CPU, and the reason is recorded as the NVMe accelerator being powered off.

[0173] In a preferred embodiment of the present invention, in response to the completion of NVMe accelerator configuration modification, opening the NVMe accelerator and sending IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register includes:

[0174] In response to the completion of NVMe accelerator configuration modifications, the running state of the NVMe accelerator will be switched to an open transitional state.

[0175] In response to the NVMe accelerator's running state being in the open transition state, the verification code is stored in the NVMe accelerator configuration register, and IO commands issued by the system are received, while unprocessed IO commands in the CPU are sent to the NVMe accelerator.

[0176] In response to the NVMe accelerator receiving an IO command, the IO command is decomposed to obtain the IO command verification code;

[0177] Compare the verification code of the IO command with the verification code in the NVMe accelerator configuration register;

[0178] The verification code in response to the IO command is the same as the verification code in the NVMe accelerator configuration register, and the received IO command is executed.

[0179] The verification code in response to the IO command is different from the verification code in the NVMe accelerator configuration register, and the IO command is handed over to the CPU for processing through the data channel.

[0180] In a preferred embodiment of the present invention, it further includes:

[0181] In response to the NVMe accelerator's running status being in an open transition state, determine whether the configuration modification has caused a change in the operating environment;

[0182] In response to changes in the operating environment caused by configuration modifications, the original verification code value is read out, incremented by 1 to form a new verification code, and the new verification code is written into the NVMe accelerator configuration register.

[0183] Inform the chip system of the new verification code value;

[0184] Since the configuration changes did not cause any changes in the operating environment, the verification code will not be updated.

[0185] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0186] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0187] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0188] In one or more exemplary designs, functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. Storage media may be any available medium accessible to a general-purpose or special-purpose computer. By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store the required program code in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the aforementioned coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, disks and optical discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0189] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0190] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0191] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0192] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0193] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for improving the availability of NVMe accelerators, characterized in that, Includes the following steps: Reserve unused I / O queues for the CPU in NVMe disks; In response to receiving an instruction to modify the NVMe accelerator configuration, memory space is allocated for the IO queue reserved for the CPU; Unprocessed IO commands in the NVMe accelerator are sent to the CPU through the data channel, and the IO commands are sent to the disk for processing through the IO queue reserved for the CPU; In response to the completion of NVMe accelerator configuration modification, the NVMe accelerator is opened and IO commands are sent to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register. Specifically, reserving unused I / O queues for the CPU in NVMe disks includes: In response to the maximum number of queues for NVMe disks exceeding a first preset value, one unused IO queue is reserved for each CPU core; In response to the maximum number of queues for the NVMe disk being less than the second preset value, all IO queues are assigned to the NVMe accelerator and one IO queue is deleted when the NVMe accelerator configuration is modified. After deletion, an unused IO queue is recreated for the CPU. In response to the maximum number of queues for NVMe disks being less than a first preset value but greater than a second preset value, an unused IO queue is reserved for the CPU.

2. The method according to claim 1, characterized in that, Also includes: The operating states of the NVMe accelerator are divided into normal operating state, off transition state, off state, and on transition state.

3. The method according to claim 2, characterized in that, Unprocessed I / O commands in the NVMe accelerator are sent to the CPU via the data channel, and then the I / O commands are distributed to the disk for processing via the I / O queue reserved for the CPU. Switch the NVMe accelerator's running status to a transitional off state; The NVMe accelerator internally records the execution status of each IO command issued to the disk and determines whether all IO commands have received IO responses. Once all I / O responses have been received, a message is sent to the CPU indicating that the I / O command processing is complete. Pause any unprocessed I / O commands in the NVMe accelerator, transfer them to the CPU via the data channel, record the transfer reason as NVMe accelerator shutdown, and switch the running state of the NVMe accelerator to shutdown; The CPU sends I / O commands to the disk for processing by reserving an I / O queue for the CPU.

4. The method according to claim 3, characterized in that, Also includes: In response to the NVMe accelerator being in a powered-off state, all IO commands received by the NVMe accelerator are forwarded to the CPU, and the reason is recorded as the NVMe accelerator being powered off.

5. The method according to claim 1, characterized in that, In response to the completion of NVMe accelerator configuration modifications, the NVMe accelerator is opened and I / O commands are sent to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register, including: In response to the completion of NVMe accelerator configuration modifications, the running state of the NVMe accelerator will be switched to an open transitional state. In response to the NVMe accelerator's running state being in the open transition state, the verification code is stored in the NVMe accelerator configuration register, and IO commands issued by the system are received, while unprocessed IO commands in the CPU are sent to the NVMe accelerator. In response to the NVMe accelerator receiving an IO command, the IO command is decomposed to obtain the IO command verification code; Compare the verification code of the IO command with the verification code in the NVMe accelerator configuration register; The verification code in response to the IO command is the same as the verification code in the NVMe accelerator configuration register, and the received IO command is executed. The verification code in response to the IO command is different from the verification code in the NVMe accelerator configuration register, and the IO command is handed over to the CPU for processing through the data channel.

6. The method according to claim 5, characterized in that, Also includes: In response to the NVMe accelerator's running status being in an open transition state, determine whether the configuration modification has caused a change in the operating environment; In response to changes in the operating environment caused by configuration modifications, the original verification code value is read out, incremented by 1 to form a new verification code, and the new verification code is written into the NVMe accelerator configuration register. Inform the chip system of the new verification code value; Since the configuration changes did not cause any changes in the operating environment, the verification code will not be updated.

7. An apparatus for improving the availability of NVMe accelerators, characterized in that, The device includes: A reservation module, configured to reserve unused IO queues for the CPU in the NVMe disk; The configuration module is configured to allocate memory space for the IO queue reserved for the CPU in response to receiving an instruction to modify the NVMe accelerator configuration; The sending module is configured to send unprocessed IO commands in the NVMe accelerator to the CPU through the data channel, and to send the IO commands to the disk for processing through the IO queue reserved for the CPU; The processing module is configured to, in response to the completion of NVMe accelerator configuration modification, open the NVMe accelerator and send IO commands to the NVMe accelerator or CPU for processing based on the verification code stored in the NVMe accelerator configuration register. The reserved module is also used for: In response to the maximum number of queues for NVMe disks exceeding a first preset value, one unused IO queue is reserved for each CPU core; In response to the maximum number of queues for the NVMe disk being less than the second preset value, all IO queues are assigned to the NVMe accelerator and one IO queue is deleted when the NVMe accelerator configuration is modified. After deletion, an unused IO queue is recreated for the CPU. In response to the maximum number of queues for NVMe disks being less than a first preset value but greater than a second preset value, an unused IO queue is reserved for the CPU.

8. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-6.

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