Coding method, decoding method, device, equipment and readable storage medium

Abstract

The present application discloses an encoding method, a decoding method, an apparatus, a device, and a readable storage medium. First, at least one information bit group is obtained, the information bit group includes multiple information bits, and for any information bit group, a check coding process is performed on any information bit group to obtain a check bit group corresponding to any information bit group, and the check bit group corresponding to any information bit group includes multiple check bits. Then, at least one target bit group is modulated to obtain multiple target sparse signals, and a target bit group includes an information bit group and a check bit group corresponding to the information bit group. After that, the multiple target sparse signals are compressed into target codewords. The present application can reduce errors in transmission frames, reduce frame error rates, and improve the performance of communication systems.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to encoding methods, decoding methods, devices, equipment, and readable storage media. Background Art

[0002] The channel coding theorem is a crucial principle in the field of communications technology. It states that when a signal is transmitted over an error-prone channel, if the transmission rate is less than the channel capacity, a coding scheme exists that allows error-free transmission. Since the advent of this principle, developing coding schemes has been a major goal in the field of communications technology.

[0003] Sparse regression codes (SPARCs) are a coding scheme that encodes multiple information bits into a target codeword. The encoding process involves first obtaining multiple information bits to be transmitted, then modulating these information bits to generate multiple target sparse signals, and then compressing these target sparse signals into the target codeword. The target codeword may change during transmission. When the target codeword changes, decoding the changed target codeword can result in erroneous information bits. These erroneous information bits can cause transmission frame errors, impacting the performance of the communication system. Summary of the Invention

[0004] This application proposes an encoding method, a decoding method, an apparatus, a device and a readable storage medium for improving the efficiency of network management and enhancing user experience.

[0005] In a first aspect, a coding method is provided, comprising: obtaining at least one information bit group, wherein the information bit group includes multiple information bits; for any information bit group, performing check coding processing on the any information bit group to obtain a check bit group corresponding to the any information bit group, wherein the check bit group corresponding to the any information bit group includes multiple check bits; performing modulation processing on at least one target bit group to obtain multiple target sparse signals, wherein one target bit group includes one information bit group and a check bit group corresponding to the one information bit group; and compressing the multiple target sparse signals into target codewords.

[0006] The encoding method provided by this technical solution can carry verification information in the target codeword. Even if the target codeword changes, the correct information bits can still be obtained based on the verification information in the changed target codeword, thereby reducing errors in transmission frames, lowering the frame error rate, and improving the performance of the communication system.

[0007] In one possible implementation, the information bit group includes multiple rows and columns of information bits, with one row of information bits being one information bit unit; performing parity coding on any one of the information bit groups to obtain a parity bit group corresponding to the information bit group includes: performing parity coding on any one of the information bit units in the information bit group to obtain a parity bit unit corresponding to the information bit unit, wherein the parity bit unit includes multiple parity bits; and determining the parity bit group corresponding to the information bit group based on the parity bit units corresponding to each of the information bit units in the information bit group, wherein the parity bit group corresponding to the information bit group includes multiple rows and columns of parity bits, with one row of parity bits being one parity bit unit. By performing parity coding on each of the information bit units in the information bit group to obtain a parity bit group, parity information carried in a target codeword is obtained, thereby achieving the purpose of reducing the frame error rate and improving the performance of the communication system.

[0008] In one possible implementation, compressing the multiple target sparse signals into target codewords includes: determining a compression matrix based on a transmission rate; and compressing the multiple target sparse signals based on the compression matrix to obtain the target codewords. Determining the compression matrix based on the transmission rate and determining the target codewords based on the compression matrix ensures efficient transmission of the target codewords over the channel.

[0009] In one possible implementation, after compressing the multiple target sparse signals into target codewords, the method further includes: performing a clipping process on the target codewords to obtain the clipped target codewords; and transmitting the clipped target codewords over a target channel. Because the target codewords have a near-Gaussian distribution, clipping the target codewords reduces their peak-to-average power ratio, lowering requirements on a power amplifier at the transmitter and facilitating practical deployment.

[0010] In one possible implementation, the information bit group includes multiple rows and columns of information bits, with one column of information bits forming an information bit block; the parity bit group includes multiple rows and columns of parity bits, with one column of parity bits forming a parity bit block; and the modulating process of at least one target bit group to obtain multiple target sparse signals includes: for any target bit group, modulating each information bit block in the target bit group to obtain a target sparse signal corresponding to each information bit block in the target bit group; and modulating each parity bit block in the target bit group to obtain a target sparse signal corresponding to each parity bit block in the target bit group. By modulating each information bit block and each parity bit block to obtain a target sparse signal, a target codeword is further obtained based on the target sparse signal, so that the target codeword carries parity information, thereby achieving the purpose of reducing the frame error rate and improving the performance of the communication system.

[0011] In one possible implementation, modulating at least one target bit group to obtain multiple target sparse signals includes: performing bit interleaving on the at least one target bit group to obtain at least one target bit group after bit interleaving; and modulating the at least one target bit group after bit interleaving to obtain multiple target sparse signals. By performing bit interleaving on the M target bit groups, the order of information bits and check bits is disrupted, thereby distributing errors across the entire codeword space for channels with burst errors, thereby improving the decoding success rate.

[0012] In one possible implementation, obtaining at least one information bit group includes: obtaining multiple information bits to be transmitted; performing block processing on the multiple information bits to obtain multiple information bit blocks, each of which includes multiple information bits; and performing group processing on the multiple information bit blocks to obtain the at least one information bit group, each of which includes multiple rows and columns of information bits, with each column of information bits forming an information bit block. The information bits are first blocked into information bit blocks, and then the information bit blocks are grouped into information bit groups, thereby obtaining a parity bit group based on the information bit group, and then obtaining a target codeword based on the information bit group and the parity bit group. This allows the target codeword to carry parity information, which is beneficial for reducing a frame error rate.

[0013] In a second aspect, a decoding method is provided, the method comprising: obtaining a first codeword; decompressing the first codeword into multiple first sparse signals; demodulating the multiple first sparse signals to obtain at least one first demodulation bit group, wherein a first demodulation bit group includes a first group and a second group, the first group includes multiple information bits, and the second group includes multiple check bits; for any first demodulation bit group, performing check decoding processing on the first group in any first demodulation bit group based on the second group in any first demodulation bit group to obtain an information bit group, wherein the information bit group includes multiple information bits.

[0014] The decoding method provided by this technical solution can obtain a first demodulated bit group based on a first codeword, perform check decoding processing on the first group of the first demodulated bit group based on the second group obtained in the first demodulated bit group, and obtain an information bit group, thereby obtaining correct information bits based on the check information in the changed target codeword, reducing errors in transmission frames, lowering the frame error rate, and improving the performance of the communication system.

[0015] In one possible implementation, the demodulation processing of the multiple first sparse signals to obtain at least one first demodulation bit group includes: for any first sparse signal, demodulating the any first sparse signal to obtain at least one demodulation bit block corresponding to the any first sparse signal, the demodulation bit block including multiple information bits or multiple check bits; based on the at least one demodulation bit block corresponding to each of the multiple first sparse signals, determining the at least one first demodulation bit group, the first demodulation bit group including multiple rows and columns of information bits and multiple rows and columns of check bits, one column of information bits being a demodulation bit block, and one column of check bits being a demodulation bit block. By demodulating each first sparse signal to obtain at least one first demodulation bit group, the performance of the communication system is improved by performing check decoding processing on the first group of the first demodulation bit groups based on the second group of the first demodulation bit groups.

[0016] In one possible implementation, demodulating any one of the first sparse signals to obtain at least one demodulated bit block corresponding to the first sparse signal includes: converting the first one of the sparse signals into at least one sparse estimation signal, where the sparse estimation signal is an estimated value of the first sparse signal; and demodulating the sparse estimation signal to obtain a demodulated bit block. Converting each first sparse signal into at least one sparse estimation signal, and demodulating each sparse estimation signal, thereby integrating multiple scenarios for decoding and improving decoding accuracy.

[0017] In a possible implementation, performing checksum decoding processing on the first group of any one of the first demodulated bit groups based on the second group of any one of the first demodulated bit groups to obtain an information bit group includes: determining an information log-likelihood ratio LLR group based on the first group of any one of the first demodulated bit groups, where the information LLR group includes multiple LLRs; determining a check LLR group based on the second group of any one of the first demodulated bit groups, where the check LLR group includes multiple LLRs; and performing checksum decoding processing on the information LLR group based on the check LLR group to obtain an information bit group.

[0018] In a possible implementation, the information LLR group includes a plurality of information LLR units, the check LLR group includes a plurality of check LLR units; performing check decoding processing on the information LLR group based on the check LLR group to obtain an information bit group includes: decoding each target LLR unit in the first LLR group to obtain at least one candidate bit unit corresponding to each target LLR unit, a target LLR unit includes an information LLR unit and a check LLR unit, and a candidate bit unit includes an information bit unit and a check bit unit; for any candidate bit unit, based on any A check bit unit in a candidate bit unit checks the information bit unit in any candidate bit unit to obtain a check result for the candidate bit unit. In response to each target LLR unit in the first LLR group meeting a condition, an information bit group is obtained based on the target bit units corresponding to each target LLR unit in the first LLR group. A target LLR unit meets the condition that the check result for the target bit unit exists in at least one candidate bit unit corresponding to the target LLR unit, and the information bit unit in the target bit unit is a row of information bits in the information bit group. By decoding a target LLR unit into at least one candidate bit unit and checking the information bit unit in any candidate bit unit based on the check bit unit in any candidate bit unit, the target bit unit is determined from the at least one candidate bit unit, thereby determining the correct information bit, reducing errors in transmission frames, lowering the frame error rate, and improving the performance of the communication system.

[0019] In one possible implementation, verifying the information bit unit in any candidate bit unit based on the check bit unit in any candidate bit unit to obtain a verification result for the any candidate bit unit includes: performing check encoding processing on the information bit unit in any candidate bit unit to obtain a check bit unit to be compared; comparing the check bit unit to be compared with the check bit unit in any candidate bit unit, and obtaining a verification result for the any candidate bit unit based on the comparison result. The check bit unit in the candidate bit unit is verified using the information bit unit in the candidate bit unit to reduce errors in transmitted frames.

[0020] In a possible implementation, after verifying the information bit unit in any candidate bit unit based on the check bit unit in any candidate bit unit and obtaining the verification result of the any candidate bit unit, the method further includes: in response to the presence of at least one target LLR unit that does not meet the conditions in the first LLR group, obtaining a first bit group corresponding to any first demodulated bit group, the first bit group corresponding to any first demodulated bit group including the target bit units corresponding to each target LLR unit that meets the conditions in the first LLR group; determining a second codeword based on the first bit group corresponding to each first demodulated bit group; determining a second bit group corresponding to any first demodulated bit group based on the second codeword, the second bit group corresponding to any first demodulated bit group including the information bit units in the target bit units corresponding to each target LLR unit that does not meet the conditions in the first LLR group; and determining the one information bit group based on the first bit group corresponding to any first demodulated bit group and the second bit group corresponding to any first demodulated bit group. When there are target LLR units that have not been successfully verified, re-decoding is performed using the target bit units corresponding to the successfully verified target LLR units, thereby improving the decoding success rate while ensuring a low frame error rate.

[0021] In one possible implementation, determining the second codeword based on the first bit group corresponding to each first demodulated bit group includes: modulating the first bit group corresponding to each first demodulated bit group to obtain multiple second sparse signals; compressing the multiple second sparse signals into a third codeword; and determining the second codeword based on the first codeword and the third codeword. By determining the third codeword, the second codeword is further obtained by using the third codeword and the first codeword, and the second codeword is decoded, thereby reducing computational complexity and improving decoding speed.

[0022] In one possible implementation, any one of the first demodulation bit groups includes at least one demodulation bit block corresponding to each of the multiple first sparse signals; determining the information LLR group based on the first group in any one of the first demodulation bit groups and determining the check LLR group based on the second group in any one of the first demodulation bit groups include: for any one of the first sparse signals, determining the one LLR block based on at least one demodulation bit block corresponding to the any one of the first sparse signals, the LLR block including multiple LLRs; determining the information LLR group based on each LLR block corresponding to the first group in any one of the first demodulation bit groups; and determining the check LLR group based on each LLR block corresponding to the second group in any one of the first demodulation bit groups.

[0023] In one possible implementation, demodulating the multiple first sparse signals to obtain at least one first demodulated bit group includes: demodulating the multiple first sparse signals to determine at least one second demodulated bit group; and performing bit deinterleaving on the at least one second demodulated bit group to obtain the at least one first demodulated bit group. Bit interleaving can disrupt the order of information bits and parity bits. For channels with burst errors, the errors are dispersed throughout the codeword space. Deinterleaving the M second LLR groups restores the order of the LLRs, thereby restoring the order of the information bits and parity bits and improving the decoding success rate.

[0024] In one possible implementation, decompressing the first codeword into multiple first sparse signals includes: performing clipping compensation processing on the first codeword to obtain a clipping-compensated first codeword; and decompressing the clipping-compensated first codeword into multiple first sparse signals. Clipping compensation processing on the first codeword facilitates actual deployment while improving a decoding success rate.

[0025] In a third aspect, a coding device is provided, which includes: an acquisition module for acquiring at least one information bit group, wherein the information bit group includes multiple information bits; a check coding module for performing check coding processing on any information bit group to obtain a check bit group corresponding to the any information bit group, wherein the check bit group corresponding to the any information bit group includes multiple check bits; a modulation module for performing modulation processing on at least one target bit group to obtain multiple target sparse signals, wherein one target bit group includes one information bit group and a check bit group corresponding to the one information bit group; and a compression module for compressing the multiple target sparse signals into target codewords.

[0026] In one possible implementation, the information bit group includes multiple rows and columns of information bits, and one row of information bits constitutes one information bit unit; the check coding module is used to perform check coding processing on any information bit unit in any of the information bit groups to obtain a check bit unit corresponding to any of the information bit units, and the check bit unit includes multiple check bits; based on the check bit units corresponding to each of the information bit units in any of the information bit groups, the check bit group corresponding to any of the information bit groups is determined, and the check bit group corresponding to any of the information bit groups includes multiple rows and columns of check bits, and one row of check bits constitutes one check bit unit.

[0027] In a possible implementation, the compression module is configured to determine a compression matrix according to a transmission rate; and perform compression processing on the multiple target sparse signals based on the compression matrix to obtain target codewords.

[0028] In a possible implementation, the apparatus further includes: a limiting module configured to perform limiting processing on the target codeword to obtain a target codeword after the limiting processing; and a transmission module configured to transmit the target codeword after the limiting processing based on a target channel.

[0029] In one possible implementation, the information bit group includes multiple rows and columns of information bits, and one column of information bits constitutes an information bit block; the check bit group includes multiple rows and columns of check bits, and one column of check bits constitutes a check bit block; the modulation module is used to, for any target bit group, modulate each information bit block in the any target bit group to obtain a target sparse signal corresponding to each information bit block in the any target bit group; and modulate each check bit block in the any target bit group to obtain a target sparse signal corresponding to each check bit block in the any target bit group.

[0030] In one possible implementation, the modulation module is used to perform bit interleaving processing on the at least one target bit group to obtain at least one target bit group after bit interleaving processing; and to perform modulation processing on the at least one target bit group after bit interleaving processing to obtain multiple target sparse signals.

[0031] In one possible implementation, the acquisition module is used to obtain multiple information bits to be transmitted; block-process the multiple information bits to obtain multiple information bit blocks, and the information bit blocks include multiple information bits; group-process the multiple information bit blocks to obtain at least one information bit group, and the information bit group includes multiple rows and columns of information bits, and one column of information bits constitutes one information bit block.

[0032] In a fourth aspect, a decoding device is provided, which includes: an acquisition module for acquiring a first codeword; a decompression module for decompressing the first codeword into multiple first sparse signals; a demodulation module for demodulating the multiple first sparse signals to obtain at least one first demodulation bit group, wherein a first demodulation bit group includes a first group and a second group, the first group includes multiple information bits, and the second group includes multiple check bits; a check decoding module for performing check decoding processing on the first group of any first demodulation bit group based on the second group of any first demodulation bit group to obtain an information bit group, wherein the information bit group includes multiple information bits.

[0033] In one possible implementation, the demodulation module is used to perform demodulation processing on any first sparse signal to obtain at least one demodulation bit block corresponding to any first sparse signal, where the demodulation bit block includes multiple information bits or multiple check bits; based on the at least one demodulation bit block corresponding to each of the multiple first sparse signals, determine the at least one first demodulation bit group, where the first demodulation bit group includes multiple rows and columns of information bits and multiple rows and columns of check bits, where one column of information bits constitutes a demodulation bit block, and one column of check bits constitutes a demodulation bit block.

[0034] In one possible implementation, the demodulation module is used to convert any one of the first sparse signals into at least one sparse estimation signal, where the sparse estimation signal is an estimated value of any one of the first sparse signals; for any one of the sparse estimation signals, the demodulation processing is performed on the any one of the sparse estimation signals to obtain a demodulated bit block.

[0035] In one possible implementation, the check decoding module is configured to determine an information log-likelihood ratio (LLR) group based on a first group in any one of the first demodulated bit groups, where the information LLR group includes a plurality of LLRs; determine a check LLR group based on a second group in any one of the first demodulated bit groups, where the check LLR group includes a plurality of LLRs; and perform check decoding processing on the information LLR group based on the check LLR group to obtain an information bit group.

[0036] In a possible implementation, the information LLR group includes a plurality of information LLR units, and the check LLR group includes a plurality of check LLR units; the check decoding module is configured to perform decoding processing on each target LLR unit in the first LLR group to obtain at least one candidate bit unit corresponding to each target LLR unit, where a target LLR unit includes an information LLR unit and a check LLR unit, and a candidate bit unit includes an information bit unit and a check bit unit; for any candidate bit unit, based on the check bit unit in the any candidate bit unit, the information bit unit in the any candidate bit unit is checked to obtain a check result for the any candidate bit unit; in response to each target LLR unit in the first LLR group satisfying a condition, an information bit group is obtained based on the target bit unit corresponding to each target LLR unit in the first LLR group, where a target LLR unit satisfies the condition that a check result of a target bit unit exists in at least one candidate bit unit corresponding to the target LLR unit, and the information bit unit in the target bit unit is a row of information bits in the information bit group.

[0037] In one possible implementation, the check decoding module is used to perform check coding processing on the information bit unit in any candidate bit unit to obtain a check bit unit to be compared; the check bit unit to be compared is compared with the check bit unit in any candidate bit unit, and a check result of any candidate bit unit is obtained based on the comparison result.

[0038] In one possible implementation, the apparatus further includes: the acquisition module, further configured to, in response to the presence of at least one target LLR unit that does not meet the conditions in the first LLR group, acquire a first bit group corresponding to any one of the first demodulation bit groups, the first bit group corresponding to any one of the first demodulation bit groups including target bit units corresponding to respective target LLR units that meet the conditions in the first LLR group; a determination module, configured to determine a second codeword based on the first bit groups corresponding to respective first demodulation bit groups; determine a second bit group corresponding to any one of the first demodulation bit groups based on the second codeword, the second bit group corresponding to any one of the first demodulation bit groups including information bit units in target bit units corresponding to respective target LLR units that do not meet the conditions in the first LLR group; and determine the one information bit group based on the first bit group corresponding to any one of the first demodulation bit groups and the second bit group corresponding to any one of the first demodulation bit groups.

[0039] In one possible implementation, the determination module is configured to perform modulation processing on the first bit group corresponding to each of the first demodulated bit groups to obtain multiple second sparse signals; compress the multiple second sparse signals into a third codeword; and determine the second codeword based on the first codeword and the third codeword.

[0040] In one possible implementation, any one of the first demodulation bit groups includes at least one demodulation bit block corresponding to each of the multiple first sparse signals; the demodulation module is configured to determine, for any one of the first sparse signals, based on the at least one demodulation bit block corresponding to the any one of the first sparse signals, the one LLR block, where the LLR block includes multiple LLRs; determine the information LLR group based on the respective LLR blocks corresponding to the first group in any one of the first demodulation bit groups; and determine the check LLR group based on the respective LLR blocks corresponding to the second group in any one of the first demodulation bit groups.

[0041] In one possible implementation, the demodulation module is configured to perform demodulation processing on the multiple first sparse signals to determine at least one second demodulation bit group; and perform debit interleaving processing on the at least one second demodulation bit group to obtain the at least one first demodulation bit group.

[0042] In a possible implementation, the decompression module is configured to perform clipping compensation processing on the first codeword to obtain a first codeword after clipping compensation processing; and decompress the first codeword after clipping compensation processing into multiple first sparse signals.

[0043] In a fifth aspect, a data processing system is provided, the system comprising a network controller, the network controller being configured to execute any encoding method as described in the first aspect above, or to execute any decoding method as described in the second aspect above.

[0044] In a sixth aspect, a network device is provided, comprising a processor and a computer program. When the processor executes the computer program, the network device implements any encoding method as described in the first aspect above, or executes any decoding method as described in the second aspect above.

[0045] In the seventh aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a computer, it implements any encoding method as described in the first aspect above, or executes any decoding method as described in the second aspect above.

[0046] In an eighth aspect, a computer program product is provided, comprising a computer program. When the computer program is executed by a computer, it implements any encoding method as described in the first aspect above, or executes any decoding method as described in the second aspect above.

[0047] In a ninth aspect, a communication device is provided, comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other via an internal connection path; the memory is configured to store instructions; and the processor is configured to execute the instructions stored in the memory to control the transceiver to receive signals and to control the transceiver to transmit signals. When the processor executes the instructions stored in the memory, the processor executes any encoding method according to the first aspect or any decoding method according to the second aspect.

[0048] As an exemplary embodiment, there are one or more processors and one or more memories.

[0049] As an exemplary embodiment, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0050] In the specific implementation process, the memory can be a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. The embodiments of the present application do not limit the type of memory and the setting method of the memory and the processor.

[0051] In the tenth aspect, a chip is provided, comprising a processor for calling and executing instructions stored in a memory from a memory, so that a communication device equipped with the chip executes any encoding method as described in the first aspect above, or executes any decoding method as described in the second aspect above.

[0052] In the eleventh aspect, another chip is provided, comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute any encoding method as described in the first aspect above, or to execute any decoding method as described in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a schematic diagram of an implementation environment of an encoding method and a decoding method provided in an embodiment of the present application;

[0054] Figure 2 This is a flowchart of an encoding method provided in an embodiment of the present application;

[0055] Figure 3 This is a schematic diagram of a checksum coding process provided by an embodiment of the present application;

[0056] Figure 4 This is a flowchart of a decoding method provided by an embodiment of the present application;

[0057] Figure 5 is a schematic diagram of a first log-likelihood ratio (LLR) group provided in an embodiment of the present application;

[0058] Figure 6 This is a schematic diagram of information bit transmission provided by an embodiment of the present application;

[0059] Figure 7 This is a processing diagram of a generalized message transmission algorithm provided in an embodiment of the present application;

[0060] Figure 8 is a schematic diagram of a list decoder provided in an embodiment of the present application;

[0061] Figure 9 is a schematic diagram of another list decoder provided in an embodiment of the present application;

[0062] Figure 10 This is a schematic diagram of a bit error rate and frame error rate provided in an embodiment of the present application;

[0063] Figure 11 is another schematic diagram of bit error rate and frame error rate provided in an embodiment of the present application;

[0064] Figure 12 This is a schematic structural diagram of an encoding device provided in an embodiment of the present application;

[0065] Figure 13 This is a schematic structural diagram of a decoding device provided in an embodiment of the present application;

[0066] Figure 14 This is a schematic diagram of the structure of a network device provided in an embodiment of the present application;

[0067] Figure 15 This is a structural diagram of a network device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0069] SPARCs is a coding scheme used to modulate information bits to be transmitted into a sparse signal, and then compress the sparse signal into a codeword for transmission over a channel. Based on the principles of SPARCs, the present embodiment first performs parity coding on the information bits to be transmitted to obtain parity bits. The information bits and parity bits are then modulated to obtain a sparse signal. The sparse signal is then compressed into a codeword, so that the codeword carries parity information. The receiving end can then perform parity decoding on the codeword based on the parity information, improving the accuracy of the decoding result.

[0070] The encoding method and decoding method provided in the embodiments of the present application can be applied to Figure 1 In the implementation environment shown. Figure 1 As shown, the implementation environment includes device 101 and device 102. Optionally, device 101 includes, but is not limited to, a server and a user device. Similarly, device 102 includes, but is not limited to, a server and a user device. Device 101 and device 102 are communicatively connected. User devices include, but are not limited to, at least one of a smartphone, a game console, a desktop computer, a tablet computer, a vehicle-mounted terminal, and a laptop computer. The server can be a single server or a server cluster consisting of at least two servers. The server has functions such as data reception, data transmission, and data processing.

[0071] based on Figure 1 The implementation environment shown in the figure, this application embodiment provides a coding method. Please refer to Figure 2 , which shows a flow chart of an encoding method provided by an embodiment of the present application, wherein the encoding method provided by an embodiment of the present application is Figure 1 The encoding method is performed by the device 101 in the embodiment, and includes steps 201 to 204.

[0072] Step 201: Acquire at least one information bit group, where the information bit group includes multiple information bits.

[0073] The number of information bit groups is denoted as M. Multiple information bits included in an information bit group can be arranged into X rows and Y columns of information bits, and M, X, and Y are all positive integers.

[0074] A bit (binary digit, BIT) is a unit of information, which is one digit of a binary number. In the embodiments of the present application, for information to be transmitted, the information contained in one digit of a binary number is called an information bit. For example, for the information to be transmitted 100101, the information to be transmitted contains 6 information bits, and these 6 information bits are 1, 0, 0, 1, 0, and 1 respectively.

[0075] In this embodiment of the present application, M information bit groups are obtained, where M is a positive integer. Each information bit group includes X rows and Y columns of information bits, where X is a positive integer and Y is also a positive integer. In other words, X*Y information bits are arranged in X rows and Y columns to obtain an information bit group.

[0076] Optionally, obtaining at least one information bit group includes: obtaining multiple information bits to be transmitted; performing block processing on the multiple information bits to obtain multiple information bit blocks, wherein the information bit blocks include multiple information bits; performing group processing on the multiple information bit blocks to obtain at least one information bit group, wherein the information bit group includes multiple rows and columns of information bits, and one column of information bits constitutes one information bit block.

[0077] In the embodiment of the present application, since a column of information bits in an information bit group constitutes an information bit block, and the information bit group includes X rows and Y columns of information bits, the information bit group includes Y information bit blocks, one information bit block includes X information bits, and any two information bit blocks include the same number of information bits.

[0078] For example, there are 6000 information bits to be transmitted. These 6000 information bits are divided into blocks to obtain 1000 information bit blocks, each containing 6 information bits. These 1000 information bit blocks are then grouped to obtain 10 information bit groups, each containing 100 information bit blocks. In this case, an information bit group contains 6 x 100 information bits, i.e., 6 rows and 100 columns of information bits.

[0079] Step 202: For any information bit group, perform check coding processing on the information bit group to obtain a check bit group corresponding to the information bit group. The check bit group corresponding to the information bit group includes multiple check bits.

[0080] In an embodiment of the present application, for any one of the M information bit groups, a check coding process is performed on the any one of the information bit groups to obtain a check bit group corresponding to the any one of the information bit groups. The check bit group corresponding to the any one of the information bit groups includes multiple check bits arranged as check bits in X rows and Z columns, where Z is a positive integer.

[0081] In the embodiment of the present application, parity encoding is performed on each information bit group to obtain a parity bit group corresponding to each information bit group. The parity bit group corresponding to each information bit group includes parity bits in rows X and columns Z, where Z is a positive integer. For parity information, the information contained in one bit of a binary number is referred to as a parity bit. For example, for the parity information 011100, the parity information includes six parity bits, which are 0, 1, 1, 1, 0, and 0, respectively.

[0082] The check code processing method is not limited in the embodiment of the present application. For example, the check code processing method includes but is not limited to a cyclic redundancy check (CRC) check code method.

[0083] In one possible implementation, an information bit group includes multiple rows and columns of information bits, where one row of information bits constitutes one information bit unit; performing check coding processing on any information bit group to obtain a check bit group corresponding to any information bit group, including: performing check coding processing on any information bit unit in any information bit group to obtain a check bit unit corresponding to any information bit unit, where the check bit unit includes multiple check bits; determining the check bit group corresponding to any information bit group based on the check bit units corresponding to each information bit unit in any information bit group, where the check bit group corresponding to any information bit group includes multiple rows and columns of check bits, where one row of check bits constitutes one check bit unit.

[0084] In the embodiment of the present application, each row of information bits in an information bit group corresponds to an information bit unit. Since an information bit group includes information bits in X rows and Y columns, an information bit group includes X information bit units. Similarly, each row of parity bits in a parity bit group corresponds to a parity bit unit. Since a parity bit group includes parity bits in X rows and Z columns, a parity bit group includes X parity bit units.

[0085] When performing parity coding on any information bit group, parity coding is performed on any information bit unit in the information bit group to obtain a parity bit unit corresponding to the information bit unit. In other words, parity coding is performed on one information bit unit to obtain one parity bit unit. In this manner, parity coding is performed on each information bit unit in the information bit group to obtain a parity bit unit corresponding to each information bit unit, thereby obtaining a parity bit group corresponding to the information bit group.

[0086] For example, Figure 3 As shown, Figure 3 This is a schematic diagram of a checksum coding process provided by an embodiment of the present application. Figure 3 In the table on the left, an information bit group is formed, which includes X rows and Y columns (in Figure 3 Only 6 rows and 10 columns of information bits are shown in the table. A row of information bits is an information bit unit. The table on the right is the check bit group corresponding to the information bit group. The check bit group includes X rows and Z columns (in Figure 3 Only 6 rows and 3 columns of parity bits are shown in FIG. , and a row of parity bits is a parity bit unit. Figure 3It can be clearly seen that a check bit unit is obtained by performing check coding processing on an information bit unit in the information bit group. In this way, each information bit unit in the information bit group is checked and coded to obtain a check bit unit corresponding to each information bit unit, that is, a check bit group corresponding to the information bit group is obtained.

[0087] It can be understood that the embodiment of the present application performs check coding processing on any information bit group to obtain the check bit group corresponding to this information bit group. In this way, check coding processing can be performed on each information bit group in the M information bit groups to obtain the check bit group corresponding to each information bit group.

[0088] Step 203: Modulate at least one target bit group to obtain multiple target sparse signals. One target bit group includes an information bit group and a check bit group corresponding to the information bit group.

[0089] In this embodiment of the present application, a target bit group includes an information bit group and a parity bit group corresponding to the information bit group. Since the information bit group includes information bits in rows X and columns Y, and the parity bit group includes parity bits in rows X and columns Z, the target bit group includes target bits in rows X and columns (Y+Z). One information bit is a target bit, and one parity bit is also a target bit. Furthermore, since there are M information bit groups, and each information bit group corresponds to a parity bit group, there are also M target bit groups.

[0090] For any target bit group, there are no restrictions on the method of modulating that target bit group. For example, the target bit group is position-modulated using a target power to obtain multiple target sparse signals, with the target power being of any magnitude. In this way, the same target power is used for position modulation of each target bit group to obtain multiple target sparse signals. By allocating equal power, the encoding process is simplified and deployment is reduced.

[0091] In one possible implementation, the information bit group includes multiple rows and columns of information bits, one column of information bits constitutes an information bit block, and the check bit group includes multiple rows and columns of check bits, one column of check bits constitutes a check bit block; at least one target bit group is modulated to obtain multiple target sparse signals, including: for any target bit group, modulating each information bit block in any target bit group to obtain a target sparse signal corresponding to each information bit block in any target bit group; modulating each check bit block in any target bit group to obtain a target sparse signal corresponding to each check bit block in any target bit group.

[0092] In the embodiment of the present application, each column of information bits in an information bit group corresponds to an information bit block. Since an information bit group includes information bits in X rows and Y columns, an information bit group includes Y information bit blocks. Similarly, each column of parity bits in a parity bit group corresponds to a parity bit block. Since a parity bit group includes parity bits in X rows and Z columns, a parity bit group includes Z parity bit blocks.

[0093] When modulating any target bit group, any information bit block in the target bit group is modulated to obtain the target sparse signal corresponding to the information bit block, that is, a target sparse signal is obtained by modulating one information bit block. In this way, each information bit block in the target bit group is modulated to obtain the target sparse vector corresponding to each information bit block. Based on the same principle, any check bit block in the target bit group is modulated to obtain the target sparse signal corresponding to the check bit block, that is, a check bit block is modulated to obtain a target sparse signal. In this way, each check bit block in the target bit group is modulated to obtain the target sparse vector corresponding to each check bit block.

[0094] For example, Figure 3 As shown, the table on the left is an information bit group, which includes X rows and Y columns (in Figure 3 Only 6 rows and 10 columns of information bits are shown in the figure. One column of information bits constitutes an information bit block. The table on the right shows the check bit group corresponding to the information bit group. The check bit group includes X rows and Z columns (in Figure 3 Only 6 rows and 3 columns of parity bits are shown in FIG. , and one column of parity bits constitutes a parity bit block. Figure 3 The table shown is a target bit group, which includes an information bit group on the left and a parity bit group on the right. When modulating this target bit group, one information bit block is modulated to obtain a target sparse signal. Similarly, each information bit block is modulated to obtain a corresponding target sparse signal. Furthermore, one parity bit block is modulated to obtain a target sparse signal. Similarly, each parity bit block is modulated to obtain a corresponding target sparse signal.

[0095] In one possible implementation, position modulation processing is performed on each information bit block in any target bit group to obtain a target sparse signal corresponding to each information bit block in any target bit group. The target sparse signal includes only one non-zero element, and the position of the non-zero element represents the information of the information bit block.

[0096] For example, an information bit block includes 6 information bits, each of which is 0 or 1. This information bit block can represent 2 6 = Any one of 64 numbers, that is, this information bit block can represent any number from 0 to 63. The length of the target sparse signal obtained after position modulation processing of the information bit block is B = 2 6 =64, where the target sparse signal has only one non-zero element, and the position of the non-zero element represents the information of the information bit block. Assuming that the information bit block is (binary number) 100101, and the information bit block represents the number (decimal number) 36, then bits 1-35 of the target sparse signal are 0, bit 36 ​​is a non-zero element, and bits 37-64 are 0, achieving the representation of information 36 of the information bit block by the position 36 of the non-zero element.

[0097] Based on the same principle, position modulation processing is performed on each parity bit block in any target bit group to obtain target sparse signals corresponding to each parity bit block in any target bit group. A related description is provided in "Performing position modulation processing on each information bit block in any target bit group to obtain target sparse signals corresponding to each information bit block in any target bit group," and is not repeated here.

[0098] In another possible implementation, at least one target bit group is modulated to obtain multiple target sparse signals, including: performing bit interleaving on at least one target bit group to obtain at least one target bit group after bit interleaving; and performing modulation on at least one target bit group after bit interleaving to obtain multiple target sparse signals.

[0099] In the embodiment of the present application, a bit interleaver is used to perform bit interleaving on M target bit groups to rearrange the information bits and check bits in the M target bit groups to achieve error randomization. For some channels with burst errors, the errors can be dispersed throughout the entire space. The type of bit interleaver is not limited in the embodiment of the present application.

[0100] For any target bit group after bit interleaving, the target bit group still includes X rows and (Y+Z) columns of target bits, where one information bit is a target bit, one parity bit is also a target bit, and one column of target bits in the target bit group is a target bit block. When modulating the target bit group, position modulation is performed on each target bit block in the target bit group to obtain a target sparse signal corresponding to each target bit block in the target bit group. For related descriptions, see "Performing Position Modulation on Each Information Bit Block in Any Target Bit Group to Obtain a Target Sparse Signal Corresponding to Each Information Bit Block in Any Target Bit Group," which is not repeated here.

[0101] Step 204: compress the multiple target sparse signals into target codewords.

[0102] After obtaining M(Y+Z) target sparse signals, the compression matrix is ​​used to compress the M(Y+Z) target sparse signals into a target codeword. The target codeword consists of several code elements. In communication, symbols with the same time interval are often used to represent a binary digit. The signal within such a time interval is called a (binary) code element.

[0103] In a possible implementation, compressing multiple target sparse signals into target codewords includes: determining a compression matrix according to a transmission rate; and compressing the multiple target sparse signals based on the compression matrix to obtain the target codewords.

[0104] In an embodiment of the present application, a compression matrix is ​​required when compressing M (Y + Z) target sparse signals into target codewords. The compression matrix is ​​related to the transmission rate. According to different transmission rates, different compression matrices are used to compress the M (Y + Z) target sparse signals to obtain target codewords of different lengths. Among them, the correspondence between the transmission rate and the compression matrix is ​​not limited here. For example, when the transmission rate R = 0.5 bits per channel use (BPCU), the dimension of the compression matrix is ​​12000 × 69120, and when the transmission rate R = 1 BPCU, the dimension of the compression matrix is ​​6000 × 69120.

[0105] After the target codeword is obtained, the target codeword is transmitted based on the target channel. In the embodiment of the present application, the target channel is not limited, and illustratively, the target channel is an additive white Gaussian noise (AWGN) channel.

[0106] In a possible implementation, after compressing the multiple target sparse signals into target codewords, the method further includes: performing a limiting process on the target codewords to obtain target codewords after the limiting process; and transmitting the target codewords after the limiting process based on a target channel.

[0107] In the embodiment of the present application, the target codeword is a codeword with a near-Gaussian distribution and a high peak-to-average power ratio (PAPR). To reduce the PAPR of the target codeword, the target codeword is clipped and then transmitted over the target channel, thereby reducing the requirements on the transmitter.

[0108] There is no limitation on the way of performing the amplitude limiting processing on the target codeword. Exemplarily, the portion of the target codeword that is higher than the target amplitude is adjusted to the target amplitude, and the portion of the target codeword that is equal to or lower than the target amplitude remains unchanged.

[0109] The encoding method provided in the embodiment of the present application can carry verification information in the target codeword. Even if the target codeword changes, the correct information bits can still be obtained based on the verification information in the changed target codeword, thereby reducing errors in transmission frames, lowering the frame error rate, and improving the performance of the communication system.

[0110] The above describes the encoding method of the embodiment of the present application, and the following describes the decoding method of the embodiment of the present application. The decoding method of the embodiment of the present application is based on Figure 1 Please refer to the implementation environment shown in Figure 4 , which shows a flowchart of a decoding method provided by an embodiment of the present application, wherein the decoding method provided by an embodiment of the present application is Figure 1 The encoding method is performed by the device 102 in the embodiment, and includes steps 401 to 404.

[0111] Step 401: Obtain a first codeword.

[0112] In the embodiment of the present application, the target codeword is obtained based on steps 201 to 204, and then the target codeword is transmitted in the target channel. Since there is noise in the target channel, the receiving end receives the first codeword containing noise.

[0113] Step 402: decompress the first codeword into a plurality of first sparse signals.

[0114] In the embodiment of the present application, the number of first sparse signals is recorded as M(Y+Z), where M, Y and Z are all positive integers.

[0115] The method for decompressing the first codeword is not limited. Exemplarily, at least one of a generalized approximate message passing (GAMP) algorithm, an approximate message passing (AMP) algorithm, an orthogonal approximate message passing (OAMP) algorithm, or a generalized orthogonal approximate message passing (GOAMP) algorithm is used to decompress the first codeword into multiple first sparse signals. The decompression process is also called sparse signal recovery processing, and the number of the first sparse signals is equal to the number of the target sparse signals.

[0116] It should be noted that the first codeword contains noise. Therefore, any one of the multiple first sparse signals obtained after decompressing the first codeword is an estimated value of a target sparse signal. Exemplarily, the target sparse signal is {0, 0, 0, 1, 0, 0}, and the target codeword obtained based on the target sparse signal becomes the first codeword after transmission over the target channel. After decompressing the first codeword, the obtained first sparse signal may be {0, 0, 0, 0.6, 0.4, 0}. The first sparse signal is a symbol-by-symbol probability. For example, 0.6 indicates that the probability that this symbol is equal to 1 is 0.6.

[0117] In one possible implementation, when the target codeword is a codeword subjected to clipping processing, the first codeword is also a codeword subjected to clipping processing. In this case, decompressing the first codeword into a plurality of first sparse signals includes: performing clipping compensation processing on the first codeword to obtain the clipping-compensated first codeword; and decompressing the clipping-compensated first codeword into the plurality of first sparse signals.

[0118] It is understandable that the clipping compensation process is the inverse of the clipping process. Since the clipping process is not limited, the embodiments of the present application also do not limit the method for performing clipping compensation on the first codeword. Exemplarily, clipping compensation is performed on the first codeword so that the first codeword after clipping compensation is a Gaussian-distributed codeword. Subsequently, the clipped first codeword is decompressed into multiple first sparse signals. The decompression process is described in detail in step 402 and will not be repeated here. Through clipping compensation, while maintaining a low PAPR, the bit error rate and frame error rate performance are improved under medium and low bit rate conditions.

[0119] Step 403 : Demodulate the multiple first sparse signals to obtain at least one first demodulated bit group. A first demodulated bit group includes a first group and a second group. The first group includes multiple information bits, and the second group includes multiple check bits.

[0120] In an embodiment of the present application, the number of first demodulation bit groups is M, and one first demodulation bit group includes a first group and a second group. The number of information bits in the first group is a positive integer multiple of X*Y, and the number of check bits in the second group is a positive integer multiple of X*Z, where X is a positive integer.

[0121] Among them, demodulating multiple first sparse signals to obtain at least one first demodulation bit group includes: for any first sparse signal, demodulating any first sparse signal to obtain at least one demodulation bit block corresponding to any first sparse signal, the demodulation bit block includes multiple information bits or multiple check bits; based on at least one demodulation bit block corresponding to each of the multiple first sparse signals, determining at least one first demodulation bit group, the first demodulation bit group includes multiple rows and columns of information bits and multiple rows and columns of check bits, one column of information bits is a demodulation bit block, and one column of check bits is a demodulation bit block.

[0122] For any first sparse signal among the M(Y+Z) first sparse signals, demodulation processing is performed on any first sparse signal to obtain at least one demodulation bit block corresponding to any first sparse signal, where one demodulation bit block includes X demodulation bits.

[0123] One information bit is one demodulation bit, and one parity bit is also one demodulation bit. The first group of the first demodulation bit group includes multiple information bits denoted as T1(X*Y), and the T1(X*Y) information bits are arranged into X rows and T1*Y columns of information bits. The second group of the first demodulation bit group includes multiple parity bits denoted as T2(X*Y), and the T2(X*Y) parity bits are arranged into X rows and T2*Y columns of parity bits. Therefore, the first demodulation bit group includes (T1+T2)(X*Y) demodulation bits, and the (T1+T2)(X*Y) demodulation bits are divided into X rows and Y (T1+T2) columns of demodulation bits, and one column of demodulation bits constitutes a demodulation bit block.

[0124] In the embodiment of the present application, any first sparse signal is demodulated using a demodulation processing method corresponding to the modulation processing method in step 203. Exemplarily, position demodulation is performed on any first sparse signal to obtain at least one demodulated bit block.

[0125] Optionally, any first sparse signal is demodulated to obtain at least one demodulated bit block corresponding to any first sparse signal, including: converting any first sparse signal into at least one sparse estimation signal, the sparse estimation signal being an estimated value of any first sparse signal; for any sparse estimation signal, demodulating any sparse estimation signal to obtain a demodulated bit block.

[0126] In an embodiment of the present application, when demodulating multiple first sparse signals, for any first sparse signal, the first sparse signal is first converted into at least one sparse estimation signal. The probability of each sparse estimation signal being a target sparse signal is determined. For example, the first sparse signal is {0, 0, 0, 0.6, 0.4, 0}, and the first sparse signal is converted into a sparse estimation signal A {0, 0, 0, 1, 0, 0} (the probability of which is the target sparse signal is 0.6) and a sparse estimation signal B {0, 0, 0, 0, 1, 0} (the probability of which is the target sparse signal is 0.4), wherein the sparse estimation signal has only one non-zero element, and the position of the non-zero element represents the information of the demodulated bit block. Then, each sparse estimation signal is converted into a demodulation bit block corresponding to each sparse estimation signal, where the demodulation bit block includes at least one demodulation bit. For example, a sparse estimation signal whose 1st to 35th bits are 0, the 36th bit is a non-zero element, and the 37th to 64th bits are 0 is converted into a bit block 100101 (the binary number 100101 is equal to the decimal number 36).

[0127] In an embodiment of the present application, there are M(Y+Z) first sparse signals, each of which corresponds to at least one sparse estimation signal. Any two first sparse signals may correspond to the same number of sparse estimation signals or to different numbers of sparse estimation signals, which is not limited in the embodiment of the present application. Each sparse estimation signal corresponds to a demodulation bit block, that is, each first sparse signal corresponds to at least one demodulation bit block. At least one first demodulation bit group can be determined based on at least one demodulation bit block corresponding to each of the multiple first sparse signals.

[0128] Optionally, demodulating multiple first sparse signals to obtain at least one first demodulation bit group includes: demodulating multiple first sparse signals to determine at least one second demodulation bit group; and performing bit deinterleaving on at least one second demodulation bit group to obtain at least one first demodulation bit group.

[0129] In an embodiment of the present application, M(Y+Z) first sparse signals are first demodulated to obtain at least one demodulation bit block corresponding to each of the M(Y+Z) first sparse signals. Based on the at least one demodulation bit block corresponding to each of the M(Y+Z) first sparse signals, M second demodulation bit groups are obtained. The process of determining the second demodulation bit group is detailed in the above description of determining the first demodulation bit group. The implementation principles of the two are similar and will not be repeated here.

[0130] Then, a debit interleaver is used to perform debit interleaving on the M second demodulation bit groups to rearrange the demodulation bits in the M second demodulation bit groups. The debit interleaver and the bit interleaver exist in pairs, and the debit interleaving performed by the debit interleaver is the inverse of the bit interleaving performed by the bit interleaver. The type of debit interleaver is not limited in this embodiment of the present application. The first demodulation bit group and the second demodulation bit group include the same number of demodulation bits.

[0131] Step 404: For any first demodulated bit group, perform check decoding processing on the first group in any first demodulated bit group based on the second group in any first demodulated bit group to obtain an information bit group, where the information bit group includes multiple information bits.

[0132] It is understandable that the check decoding process is the inverse of the check encoding process. Since the check encoding process is not limited, the embodiments of the present application do not limit the check decoding process. Exemplary check decoding processes include but are not limited to CRC check decoding processes.

[0133] Optionally, based on the second group in any one of the first demodulated bit groups, a check decoding process is performed on the first group in any one of the first demodulated bit groups to obtain an information bit group, including: determining an information log-likelihood ratio (LLR) group based on the first group in any one of the first demodulated bit groups, where the information LLR group includes multiple LLRs; determining a check LLR group based on the second group in any one of the first demodulated bit groups, where the check LLR group includes multiple LLRs; and performing a check decoding process on the information LLR group based on the check LLR group to obtain an information bit group.

[0134] In this embodiment of the present application, the information LLR group includes multiple LLRs arranged in X rows and Y columns, and the check LLR group includes multiple LLRs arranged in X rows and Z columns. An LLR is a bit probability, representing the ratio of the probability that an object is 0 to the probability that the object is 1. That is, an LLR is a real number. For example, an LLR of 2 / 3 indicates that the probability that the object is 0 is 0.4 and the probability that the object is 1 is 0.6.

[0135] Optionally, any first demodulation bit group includes at least one demodulation bit block corresponding to each of the multiple first sparse signals; determining an information LLR group based on the first group in any first demodulation bit group and determining a check LLR group based on the second group in any first demodulation bit group includes: for any first sparse signal, determining an LLR block based on at least one demodulation bit block corresponding to any first sparse signal, the LLR block including multiple LLRs; determining an information LLR group based on each LLR block corresponding to the first group in any first demodulation bit group; and determining a check LLR group based on each LLR block corresponding to the second group in any first demodulation bit group.

[0136] In the embodiment of the present application, at least one demodulation bit block corresponding to each of the M(Y+Z) first sparse signals constitutes M first demodulation bit groups. A demodulation bit group includes at least one demodulation bit block corresponding to each of the (Y+Z) first sparse signals.

[0137] For any first sparse signal, at least one sparse estimation signal corresponding to the first sparse signal can be determined, and the demodulated bit blocks corresponding to each sparse estimation signal and the probability that each sparse estimation signal is a target sparse signal can be determined. Then, based on the demodulated bit blocks corresponding to each sparse estimation signal and the probability that each sparse estimation signal is a target sparse signal, an LLR block is obtained, where the LLR block includes X LLRs. In this way, an LLR block corresponding to each first sparse signal is determined.

[0138] Since one demodulated bit group corresponds to (Y+Z) first sparse signals, and each first sparse signal corresponds to an LLR block, one demodulated bit group corresponds to (Y+Z) LLR blocks. These (Y+Z) LLR blocks are divided into Y LLR blocks corresponding to the first group and Z LLR blocks corresponding to the second group. The Y LLR blocks corresponding to the first group form an information LLR group, and the Z LLR blocks corresponding to the second group form a check LLR group. The information LLR group and the check LLR group form a first LLR group.

[0139] It should be noted that for any first LLR group, the first LLR group includes an information LLR group and a check LLR group. The information LLR group includes LLRs in rows X and columns Y, and the check LLR group includes LLRs in rows X and columns Z. That is, the first LLR group includes LLRs in rows X and columns (Y+Z). A column of LLRs constitutes an LLR block. Optionally, a column of LLRs in an information LLR group constitutes an information LLR block, and a column of LLRs in a check LLR group constitutes a check LLR block.

[0140] like Figure 5 As shown, Figure 5This is a schematic diagram of a first LLR group provided by an embodiment of the present application, wherein R1 to R19 all represent LLRs. The first LLR group includes X rows (Y+Z) and columns (in Figure 5 Only 6 rows and 13 columns are shown in the figure. The first LLR group is divided into an information LLR group and a check LLR group. The information LLR group is the table on the left. The information LLR group includes X rows and Y columns (in Figure 5 Only 6 rows and 10 columns are shown in the figure. One column of LLR in the information LLR group is an information LLR block. The check LLR group is the table on the right. The check LLR group includes X rows and Z columns (in Figure 5 Only 6 rows and 3 columns of LLRs are shown in FIG. 1 , and one column of LLRs in the check LLR group constitutes a check LLR block.

[0141] In the embodiment of the present application, the first codeword corresponds to M first LLR groups. For any first LLR group, a check decoding process is performed on the information LLR group in any first LLR group based on the check LLR group in any first LLR group to obtain an information bit group, where the information bit group includes X rows and Y columns of information bits.

[0142] Optionally, the information LLR group includes multiple information LLR units, and the check LLR group includes multiple check LLR units; the information LLR group is checked and decoded based on the check LLR group to obtain an information bit group, including: decoding each target LLR unit in the first LLR group to obtain at least one candidate bit unit corresponding to each target LLR unit, a target LLR unit includes an information LLR unit and a check LLR unit, and a candidate bit unit includes an information bit unit and a check bit unit; for any candidate bit unit, based on the check bit unit in any candidate bit unit, the information bit unit in any candidate bit unit is checked to obtain a check result of any candidate bit unit; in response to each target LLR unit in the first LLR group meeting a condition, an information bit group is obtained based on the target bit unit corresponding to each target LLR unit in the first LLR group, a target LLR unit meeting the condition is that the check result of the target bit unit exists in at least one candidate bit unit corresponding to the target LLR unit is successful, and the information bit unit in the target bit unit is a row of information bits in the information bit group.

[0143] In the embodiment of the present application, for any first LLR group, the first LLR group includes multiple rows and columns of LLRs, wherein a row of LLRs constitutes a target LLR unit. Since the first LLR group includes X rows and (Y + Z) columns of LLRs, a target LLR unit includes (Y + Z) LLRs. Furthermore, since a first LLR group includes an information LLR group and a check LLR group, the information LLR group includes X rows and Y columns of LLRs, a row of LLRs in the information LLR group constitutes an information LLR unit, and an information LLR unit includes Y LLRs. The check LLR group includes X rows and Z columns of LLRs, a row of LLRs in the check LLR group constitutes a check LLR unit, and a check LLR unit includes Z LLRs. Therefore, a target LLR unit includes an information LLR unit and a check LLR unit.

[0144] like Figure 5 In FIG, a row of LLRs in the information LLR group on the left is an information LLR unit, and a row of LLRs in the check LLR group on the right is a check LLR unit. The information LLR unit and the check LLR unit constitute a target LLR unit.

[0145] For any first LLR group, a list decoder is used to decode any target LLR unit in the first LLR group to obtain at least one candidate bit unit corresponding to the target LLR unit. Since the target LLR unit includes (Y+Z) LLRs, each LLR represents the ratio of the probability of an object being 0 to the probability of the object being 1. Therefore, when decoding the target LLR unit, the list decoder can translate any LLR in the target LLR unit to 0 and determine the probability of this LLR (in this case, the probability of this LLR is the probability of an object being 0), or translate this LLR to 1 and determine the probability of this LLR (in this case, the probability of this LLR is the probability of an object being 1). In this way, the list decoder can translate the (Y+Z) LLRs in the target LLR unit to 0 or 1, determine the probability of each LLR, and thus determine the probability of the decoding result.

[0146] For any LLR in a target LLR unit, the list decoder can translate the LLR into 0 or 1. Therefore, for a target LLR unit containing (Y+Z) LLRs, there are 2(Y+Z) decoding results, each of which corresponds to a probability. In this embodiment of the present application, the list decoder outputs the S decoding results with the highest probability, and each output decoding result is a candidate bit unit, where S is a positive integer.

[0147] In this embodiment of the present application, a candidate bit unit includes an information bit unit and a check bit unit. For any first LLR group, any target LLR unit in the first LLR group corresponds to S candidate bit units. For any candidate bit unit, the information bit unit in the candidate bit unit is checked based on the check bit unit in the candidate bit unit to obtain a check result for the candidate bit unit.

[0148] Optionally, based on the check bit unit in any candidate bit unit, the information bit unit in any candidate bit unit is checked to obtain a check result of any candidate bit unit, including: performing check coding processing on the information bit unit in any candidate bit unit to obtain a check bit unit to be compared; comparing the check bit unit to be compared with the check bit unit in any candidate bit unit, and obtaining a check result of any candidate bit unit based on the comparison result.

[0149] The manner of performing check coding processing on the information bit unit in any candidate bit unit is not limited in the embodiments of the present application. Exemplarily, the manner of check coding processing includes but is not limited to the check coding manner of CRC. After performing check coding processing on the information bit unit in any candidate bit unit, a check bit unit to be compared is obtained. When the check bit unit to be compared is consistent with the check bit unit in any candidate bit unit, the check result of any candidate bit unit is a successful check; when the check bit unit to be compared is inconsistent with the check bit unit in any candidate bit unit, the check result of any candidate bit unit is a failed check.

[0150] When the verification results of the S candidate bit units corresponding to any target LLR unit are all verification failures, the first candidate bit unit can be output as the target bit unit corresponding to this target LLR unit. Of course, this target LLR unit can also be re-verified and decoded, which is not limited in the embodiments of the present application.

[0151] Using the above method, the verification results of each candidate bit unit in any target LLR unit can be determined. If the verification result of one candidate bit unit among at least one candidate bit unit corresponding to the target LLR unit is successful, then this candidate bit unit is the target bit unit, which is recorded as Case A1. If the verification results of all candidate bit units in the target LLR unit are failures, the target LLR unit needs to be re-verified and decoded to determine the target bit unit corresponding to the target LLR unit, which is recorded as Case A2.

[0152] Since one target LLR unit corresponds to Case A1 and Case A2, one first LLR group includes X target LLR units and there are M first LLR groups. Therefore, during the check and decoding process of the M first LLR groups, it is possible to directly determine the target bit unit corresponding to each target LLR unit (this possibility is recorded as Case B1), or it is possible that the target bit unit corresponding to some target LLR units cannot be determined (this possibility is recorded as Case B2). Case B1 and Case B2 are described in detail below.

[0153] In case B1, for any first LLR group, each target LLR unit in the first LLR group satisfies the conditions. This means that the target bit units corresponding to each target LLR unit are directly determined. In this case, the information bit units in each target bit unit are extracted to obtain an information bit group corresponding to the first LLR group. This method allows us to obtain the information bit groups corresponding to each first LLR, resulting in M ​​information bit groups, achieving successful decoding.

[0154] Case B2, based on the check bit unit in any candidate bit unit, the information bit unit in any candidate bit unit is checked, and after obtaining the check result of any candidate bit unit, it also includes: in response to the existence of at least one target LLR unit that does not meet the conditions in any first LLR group, obtaining a first bit group corresponding to any first demodulation bit group, the first bit group corresponding to any first demodulation bit group includes the target bit units corresponding to each target LLR unit that meets the conditions in the first LLR group; determining a second codeword based on the first bit group corresponding to each first demodulation bit group; determining a second bit group corresponding to any first demodulation bit group based on the second codeword, the second bit group corresponding to any first demodulation bit group includes the information bit units in the target bit units corresponding to each target LLR unit that does not meet the conditions in the first LLR group; determining an information bit group based on the first bit group corresponding to any first demodulation bit group and the second bit group corresponding to any first demodulation bit group.

[0155] In the embodiment of the present application, a first demodulation bit group corresponds to a first LLR group. Therefore, the first bit group corresponding to any first demodulation bit group is the first bit group corresponding to any first LLR group, and the second bit group corresponding to any first demodulation bit group is the second bit group corresponding to any first LLR group.

[0156] For any first LLR group, at least one target LLR unit in the first LLR group does not meet the conditions. That is, while the target bit units corresponding to some target LLR units can be directly determined, the target bit units corresponding to other target LLR units cannot be determined. In this case, the target bit units corresponding to this portion of target LLR units constitute a first bit group. In this manner, the first bit group corresponding to each first LLR group can be determined, where the number of first bit groups is less than or equal to M.

[0157] Since the target bit unit is a candidate bit unit, and each candidate bit unit includes an information bit unit and a parity bit unit, the first bit group corresponding to any first LLR group includes multiple information bit units and multiple parity bit units. Assuming that a first bit group includes N information bit units and N parity bit units, since each information bit unit includes Y information bits and each parity bit unit includes Z parity bits, a first bit group includes information bits in X rows and Y columns and parity bits in X rows and Z columns.

[0158] Then, a second codeword is determined based on the first bit groups corresponding to each first LLR group. Optionally, determining the second codeword based on the first bit groups corresponding to each first demodulated bit group includes: performing modulation processing on the first bit groups corresponding to each first demodulated bit group to obtain multiple second sparse signals; compressing the multiple second sparse signals into a third codeword; and determining the second codeword based on the first codeword and the third codeword.

[0159] In an embodiment of the present application, when modulating the first bit groups corresponding to the first LLR groups, for any first bit group, each column of information bits of the first bit group is modulated to obtain Y second sparse signals, and each column of parity bits of the first bit group is modulated to obtain Z second sparse signals. For details, please refer to the relevant description of step 203. The implementation principles of the two are similar and will not be repeated here.

[0160] Then, the plurality of second sparse signals are compressed into a third codeword based on the compression matrix. For details, please refer to the relevant description of step 204. The implementation principles of the two are similar and will not be repeated here.

[0161] Then, the third codeword is subtracted from the first codeword to obtain a second codeword. Based on the second codeword, the second bit group corresponding to each first LLR group is determined. That is, the second codeword is sequentially decompressed, demodulated, and parity-decoded to obtain the second bit group corresponding to each first LLR group. For details, please refer to the description of steps 402 to 404, which will not be repeated here.

[0162] For any first LLR group, the second bit group corresponding to the first LLR group includes information bit units in target bit units corresponding to respective target LLR units that do not meet the conditions in the first LLR group, and the first bit group corresponding to the first LLR group includes target bit units corresponding to respective target LLR units that meet the conditions in the first LLR group. Therefore, the second bit group corresponding to the first LLR group and the information bit units in the first bit group corresponding to the first LLR group constitute the information bit group corresponding to the first LLR group.

[0163] For example, Figure 5 For the first LLR group shown, assuming that the target LLR units corresponding to the first, second, and fourth rows meet the requirements, while the target LLR units corresponding to the third, fifth, and sixth rows do not, the target bit units corresponding to the first, second, and fourth rows constitute a first bit group. Modulation and compression are performed on this first bit group to obtain a third codeword. Decompression, demodulation, and parity decoding are performed on the second codeword to obtain a second bit group. This second bit group includes the information bit units in the target bit units corresponding to the third, fifth, and sixth rows. Subsequently, the information bit group corresponding to the first LLR group is constructed based on the information bit units in the first bit group (i.e., the information bit units in the target bit units corresponding to the first, second, and fourth rows) and this second bit group.

[0164] The decoding method provided in the embodiment of the present application can obtain a first LLR group based on a first codeword, perform check decoding processing on an information LLR group in the first LLR group based on a check LLR group in the first LLR group, and obtain an information bit group. This method achieves correct information bits based on the check information in the changed target codeword, reduces errors in transmission frames, lowers the frame error rate, and improves the performance of the communication system.

[0165] The encoding method and decoding method are respectively explained above from the perspective of method steps, and will be further explained below in conjunction with a scenario. The scenario of the embodiment of the present application can be a massive machine type communication (mMTC) scenario. The mMTC scenario supports a large number of devices, including but not limited to smart grid monitoring equipment, agricultural environment detection equipment, wildlife tracking equipment, etc. Each device only needs to upload monitoring data sporadically, but because the equipment is massive, the requirements for the total transmission rate are relatively high. The scenario of the embodiment of the present application can also be an ultra-high reliability, ultra-low latency communication (URLLC) scenario. The URLLC scenario includes but is not limited to industrial asset monitoring scenarios, smart home and security scenarios, smart logistics scenarios, critical infrastructure monitoring scenarios, etc. These scenarios have high requirements for reliability and low latency, and catastrophic results may occur if the delay is too high. Through the encoding method and decoding method of the embodiment of the present application, the frame error rate can be reduced to meet the requirements of the mMTC scenario and the URLLC scenario.

[0166] See Figure 6 , Figure 6 This is a transmission diagram of an information bit provided by an embodiment of the present application. The information bit to be transmitted is input into the encoder, which sequentially performs processing such as adding a check bit, position modulation, and compression on the information bit, and then outputs a target codeword. After the target codeword is subjected to amplitude limiting processing, the target codeword subjected to amplitude limiting processing is transmitted in an additive white Gaussian noise channel. Due to the presence of noise in the additive white Gaussian noise channel, the target codeword subjected to amplitude limiting processing becomes a first codeword after transmission. The first codeword is input into the decoder, which sequentially performs processing such as a generalized message passing algorithm, a list decoder, and a check bit removal process on the first codeword, and then outputs the information bit.

[0167] The encoder is hardware or software, or a combination of hardware and software. For example, the encoder is an electronic chip or computer software, or a combination of an electronic chip and computer software. Some processing within the encoder can be ignored or not executed, and the encoder can also include other processing, such as bit interleaving. Similarly, the decoder is also hardware or software, or a combination of hardware and software. Some processing within the decoder can be ignored or not executed, and the decoder can also include other processing, such as deinterleaving.

[0168] Assume that there are J information bits to be transmitted, and divide the J information bits into L information bit blocks, each of which contains J / L (i.e., X mentioned above) information bits. g (i.e., the M information bit groups mentioned above), each of which contains (i.e., Y mentioned above) information bit blocks, each information bit group contains information bits.

[0169] Next, the encoder adds the parity bits. g The information bit blocks are CRC-encoded to obtain a check bit group, which includes L CRC (i.e., Z mentioned above) check bit blocks (the number of check bit blocks is determined by the length of the CRC polynomial), where each check bit block includes J / L check bits, then the total number of check bits in the check bit group is That is, add For details, please refer to the above description of step 202, which will not be repeated here.

[0170] Next, the encoder performs position modulation processing. Each information bit group corresponds to L g information bit blocks and L CRC check bit blocks, that is, each information bit group corresponds to L′=L g +L CRC These L′ bit blocks are modulated by position to obtain L′ bit blocks of length B=2 J / L The target sparse signal. That is, the encoder performs position modulation processing on each information bit block to obtain L g The length is B=2 J / L The target sparse signal has only one non-zero element, the position of which represents J / L information bits, and the encoder performs position modulation on each check bit block to obtain L CRC The length is B=2 J / L The target sparse signal has only one non-zero element, and the position of the non-zero element carries J / L check bits, and finally obtains L′×N g Target sparse signals. The values ​​of the non-zero elements of each target sparse signal are the same, and the values ​​of the non-zero elements are related to the power during position modulation. For details, please refer to the relevant description of step 203 above, which will not be repeated here.

[0171] After that, the encoder performs compression processing, and the encoder converts L′×N gThe target sparse signal is compressed into a target codeword. The compression matrix is ​​determined according to the transmission rate. Then, the target codeword output by the encoder is limited to ensure a low PAPR. The target codeword after the limit processing is transmitted in the additive white Gaussian noise channel.

[0172] With J=6000, L=1000, N g =10, L CRC =8 as an example. The transmitter needs to transmit 6000 information bits. These 6000 information bits are evenly divided into 1000 information bit blocks, each containing 6 information bits. The 1000 information bit blocks are then divided into 10 information bit groups, each containing 100 information bit blocks. Since each information bit block contains 6 information bits, each information bit group contains 600 information bits. The 600 information bits in each information bit group are arranged into 6 rows and 100 columns, with each column forming an information bit block.

[0173] Next, the encoder encodes the 100 information bits in each row of each information bit group using the 100+8 CRC encoding scheme, obtaining the 8 parity bits corresponding to each row of 100 information bits. This adds a parity bit group to each information bit group. A parity bit group consists of 48 parity bits, which are arranged in 6 rows and 8 columns, with each column forming a parity bit block.

[0174] Next, the encoder performs position modulation processing on the 100 information bit blocks in each information bit group, and obtains 100 information bit blocks of length B=2 corresponding to the information bit group. 6 = 64 target sparse signal c l , the target sparse signal has only one non-zero element, and the position of the non-zero element represents 6 information bits. The 10 information bit groups correspond to a total of 1000 target sparse signals of length 64, denoted as c = [c1, c2, ..., c 1000 Similarly, the encoder performs position modulation on the 8 check bit blocks corresponding to each information bit group to obtain 8 target sparse signals corresponding to the information bit group. 10 information bit groups correspond to a total of 80 target sparse signals. In summary, 1080 target sparse signals are finally obtained.

[0175] Afterwards, the encoder compresses the 1080 target sparse signals into target codewords through a compression matrix, performs clipping on the target codewords, and transmits the clipped target codewords in an additive white Gaussian noise channel.

[0176] After the target codeword is transmitted in the additive white Gaussian noise channel, it becomes the first codeword. The first codeword is input into the decoder, which sequentially processes it using the generalized message passing algorithm, the list decoder, and the parity bit removal process, and then outputs the information bits.

[0177] The decoder first processes the first codeword using the generalized message passing algorithm. Figure 7 As shown, Figure 7 This is a processing diagram of a generalized message transmission algorithm provided by an embodiment of the present application. The generalized message transmission algorithm sequentially performs limiting compensation processing, decompression processing, and sparse signal denoising processing on the first codeword to obtain multiple first sparse signals, the number of which is L′×N g Please refer to the above description of step 402 for details, which will not be repeated here.

[0178] Next, multiple first sparse signals are input to a list decoder, which outputs target bit units corresponding to each target LLR unit. Figure 8 As shown, Figure 8 : This is a schematic diagram of a list decoder provided in an embodiment of the present application. The list decoder includes a list generator and a list selector. A plurality of first sparse signals are input to the list generator, and the list generator outputs S candidate bit units (i.e., a candidate bit unit list) corresponding to a target LLR unit, and the S candidate bit units are sorted in descending order of probability. The list selector verifies the information bit unit in each candidate bit unit based on the check bit unit in the candidate bit unit, so as to filter out the target bit unit from the S candidate bit units and obtain a target bit unit corresponding to a target LLR unit. Afterwards, the list generator outputs the S candidate bit units corresponding to the next target LLR unit, and the list selector filters out the target bit unit corresponding to the next target LLR unit, thereby obtaining the target bit units corresponding to each target LLR unit. For details, please refer to the relevant description of steps 403 and 404 above, which will not be repeated here.

[0179] In another possible implementation, for any target LLR unit, the list selector may filter out the target bit unit corresponding to the target LLR unit, or may not filter out the target bit unit corresponding to the target LLR unit. When a portion of the target LLR units fail to filter out their respective corresponding target bit units, the list decoder will perform decoding again based on the target bit units corresponding to another portion of the target LLR units and the first codeword. Figure 9 As shown, Figure 9It is a schematic diagram of another list decoder provided in an embodiment of the present application. After the first codeword passes through the generalized message passing algorithm, it becomes a plurality of first sparse signals. The list generator outputs S candidate bit units corresponding to a target LLR unit based on the plurality of first sparse signals. The list selector screens out the target bit unit corresponding to a target LLR unit, thereby obtaining the target bit units corresponding to some (not all) target LLR units. The target bit units corresponding to this part of the target LLR units constitute a plurality of first bit groups, and the third codeword is determined based on the plurality of first bit groups. The second codeword is determined based on the first codeword and the third codeword. After the second codeword is processed by the generalized message passing algorithm and the list decoder in turn, the target bit units corresponding to another part of the target LLR units are obtained, thereby obtaining the target bit units corresponding to each target LLR unit. For details, please refer to the relevant description of steps 403 and 404 above, which will not be repeated here.

[0180] After obtaining the target bit units corresponding to the target LLR units, the decoder removes the check bits to obtain information bits.

[0181] Assume that the transmitter processes 6000 information bits into a target codeword according to the encoding method mentioned above, transmits the target codeword over an additive white Gaussian noise channel, and then receives the first codeword at the receiver. The receiver inputs the first codeword into a decoder, which, after passing it through a generalized message passing algorithm, outputs 1080 first sparse signals. These 1080 first sparse signals are input into a list decoder. The list generator outputs S candidate bit units corresponding to a target LLR unit, and the list selector selects the target bit unit corresponding to a target LLR unit. Based on the target bit units corresponding to each target LLR unit, 10 information bit groups are obtained, namely the 6000 information bits transmitted by the transmitter.

[0182] The check bits in the embodiment of the present application increase the protection capability between information bit blocks, and the list decoder increases the error correction capability between information bit blocks, which can reduce the bit error rate and frame error rate. Figure 10 and Figure 11 , Figure 10 and Figure 11 All of these results are obtained through experimental simulation when the length of the target sparse signal is B=64, the total number of information bit blocks is L=1000, 8 check bit blocks are added for every 100 information bit blocks, each check bit block contains 6 check bits, and the number of candidate bit units corresponding to one target LLR unit output by the list generator is S=64. Figure 10 is a schematic diagram of a bit error rate and frame error rate provided in an embodiment of the present application, Figure 11 This is another schematic diagram of bit error rate and frame error rate provided in an embodiment of the present application.

[0183] in, Figure 10 The following are simulation results at a transmission rate of 0.5 BPCU. The dotted line represents the bit error rate (BER). The BER curves with and without parity bits clearly show that at high signal-to-noise ratios (SNRs), parity bits reduce the BER, but at low SNRs, they increase it. The solid line represents the frame error rate (FR). The FR curves with and without parity bits clearly show that FR is reduced across the entire SNR range, with parity bits significantly reducing the FR at high SNRs.

[0184] Figure 11 The following are simulation results at a transmission rate of 1 BPCU. The dotted line represents the bit error rate (BER). The BER curves with and without parity bits clearly show that at high signal-to-noise ratios (SNRs), parity bits reduce the BER, but at low SNRs, they increase it. The solid line represents the frame error rate (FR). The FR curves with and without parity bits clearly show that FR significantly reduces BER across the entire SNR range, with higher SNRs leading to greater reductions in FR.

[0185] The above describes the encoding method provided by the embodiment of the present application. Corresponding to the above encoding method, the embodiment of the present application also provides an encoding device. Figure 12 This is a schematic diagram of the structure of an encoding device provided by an embodiment of the present application. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiment of the present application does not limit this. Figure 12 As shown, the device includes: an acquisition module 1201, a check coding module 1202, a modulation module 1203 and a compression module 1204.

[0186] The acquisition module 1201 is configured to acquire at least one information bit group, where the information bit group includes multiple information bits.

[0187] The check coding module 1202 is configured to perform check coding processing on any information bit group to obtain a check bit group corresponding to the information bit group. The check bit group corresponding to the information bit group includes multiple check bits.

[0188] The modulation module 1203 is configured to perform modulation processing on at least one target bit group to obtain multiple target sparse signals, where one target bit group includes an information bit group and a check bit group corresponding to the information bit group.

[0189] The compression module 1204 is configured to compress multiple target sparse signals into target codewords.

[0190] In one possible implementation, the information bit group includes multiple rows and columns of information bits, and a row of information bits is one information bit unit; the check coding module 1202 is used to perform check coding processing on any information bit unit in any information bit group to obtain a check bit unit corresponding to any information bit unit, and the check bit unit includes multiple check bits; based on the check bit units corresponding to each information bit unit in any information bit group, the check bit group corresponding to any information bit group is determined, and the check bit group corresponding to any information bit group includes multiple rows and columns of check bits, and a row of check bits is one check bit unit.

[0191] In a possible implementation, the compression module 1204 is configured to determine a compression matrix according to a transmission rate; and perform compression processing on multiple target sparse signals based on the compression matrix to obtain target codewords.

[0192] In a possible implementation, the apparatus further includes: a limiting module configured to perform limiting processing on the target codeword to obtain the target codeword after the limiting processing; and a transmission module configured to transmit the target codeword after the limiting processing based on the target channel.

[0193] In one possible implementation, the information bit group includes multiple rows and columns of information bits, and one column of information bits constitutes an information bit block; the check bit group includes multiple rows and columns of check bits, and one column of check bits constitutes a check bit block; the modulation module 1203 is used to, for any target bit group, perform modulation processing on each information bit block in any target bit group to obtain a target sparse signal corresponding to each information bit block in any target bit group; and perform modulation processing on each check bit block in any target bit group to obtain a target sparse signal corresponding to each check bit block in any target bit group.

[0194] In one possible implementation, the modulation module 1203 is used to perform bit interleaving processing on at least one target bit group to obtain at least one target bit group after bit interleaving processing; and perform modulation processing on at least one target bit group after bit interleaving processing to obtain multiple target sparse signals.

[0195] In one possible implementation, the acquisition module 1201 is used to obtain multiple information bits to be transmitted; block-process the multiple information bits to obtain multiple information bit blocks, each of which includes multiple information bits; and group-process the multiple information bit blocks to obtain at least one information bit group, each of which includes multiple rows and columns of information bits, with one column of information bits being one information bit block.

[0196] An embodiment of the present application provides an encoding device that can carry verification information in a target codeword. Even if the target codeword changes, the correct information bits can still be obtained based on the verification information in the changed target codeword, thereby reducing errors in transmission frames, lowering the frame error rate, and improving the performance of the communication system.

[0197] It should be understood that the above Figure 12 The provided device is illustrated only by the division of the above-mentioned functional modules when implementing its functions. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0198] The above describes the decoding method provided by the embodiment of the present application. Corresponding to the above decoding method, the embodiment of the present application also provides a decoding device. Figure 13 This is a schematic diagram of the structure of a decoding device provided by an embodiment of the present application. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiment of the present application does not limit this. Figure 13 As shown, the device includes: an acquisition module 1301, a decompression module 1302, a demodulation module 1303 and a check decoding module 1304.

[0199] The acquisition module 1301 is configured to acquire a first codeword.

[0200] The decompression module 1302 is configured to decompress the first codeword into a plurality of first sparse signals.

[0201] The demodulation module 1303 is configured to demodulate the plurality of first sparse signals to obtain at least one first demodulation bit group, wherein the first demodulation bit group includes a first group and a second group, the first group includes a plurality of information bits, and the second group includes a plurality of check bits.

[0202] The check and decoding module 1304 is configured to perform check and decoding processing on the first group of any first demodulated bit groups based on the second group of any first demodulated bit groups to obtain an information bit group including a plurality of information bits.

[0203] In one possible implementation, the demodulation module 1303 is used to perform demodulation processing on any first sparse signal to obtain at least one demodulation bit block corresponding to any first sparse signal, where the demodulation bit block includes multiple information bits or multiple check bits; based on the at least one demodulation bit block corresponding to each of the multiple first sparse signals, determine at least one first demodulation bit group, where the first demodulation bit group includes multiple rows and columns of information bits and multiple rows and columns of check bits, where one column of information bits constitutes a demodulation bit block, and one column of check bits constitutes a demodulation bit block.

[0204] In one possible implementation, the demodulation module 1303 is used to convert any first sparse signal into at least one sparse estimation signal, where the sparse estimation signal is an estimated value of any first sparse signal; for any sparse estimation signal, any sparse estimation signal is demodulated to obtain a demodulated bit block.

[0205] In one possible implementation, the check decoding module 1304 is configured to determine an information LLR group based on a first group in any first demodulated bit group, where the information LLR group includes multiple LLRs; determine a check LLR group based on a second group in any first demodulated bit group, where the check LLR group includes multiple LLRs; and perform check decoding on the information LLR group based on the check LLR group to obtain an information bit group.

[0206] In one possible implementation, the information LLR group includes multiple information LLR units, and the check LLR group includes multiple check LLR units. The check decoding module 1304 is configured to decode each target LLR unit in the first LLR group to obtain at least one candidate bit unit corresponding to each target LLR unit, where each target LLR unit includes an information LLR unit and a check LLR unit, and each candidate bit unit includes an information bit unit and a check bit unit. For any candidate bit unit, the information bit unit in any candidate bit unit is checked based on the check bit unit in any candidate bit unit to obtain a check result for the candidate bit unit. In response to each target LLR unit in the first LLR group meeting a condition, an information bit group is obtained based on the target bit unit corresponding to each target LLR unit in the first LLR group. A target LLR unit meets the condition that the check result of the target bit unit is successful in at least one candidate bit unit corresponding to the target LLR unit, and the information bit unit in the target bit unit is a row of information bits in the information bit group.

[0207] In one possible implementation, the check decoding module 1304 is used to perform check coding processing on the information bit unit in any candidate bit unit to obtain a check bit unit to be compared; the check bit unit to be compared is compared with the check bit unit in any candidate bit unit, and the check result of any candidate bit unit is obtained based on the comparison result.

[0208] In a possible implementation, the device further includes the following information.

[0209] The acquisition module 1301 is further configured to, in response to the presence of at least one target LLR unit that does not meet the conditions in the first LLR group, acquire a first bit group corresponding to any first demodulated bit group, where the first bit group corresponding to any first demodulated bit group includes the target bit units corresponding to each target LLR unit that meets the conditions in the first LLR group.

[0210] A determination module is configured to determine a second codeword based on a first bit group corresponding to each first demodulation bit group; determine a second bit group corresponding to any first demodulation bit group based on the second codeword, where the second bit group corresponding to any first demodulation bit group includes information bit units in target bit units corresponding to respective target LLR units in the first LLR group that do not meet the conditions; and determine an information bit group based on the first bit group corresponding to any first demodulation bit group and the second bit group corresponding to any first demodulation bit group.

[0211] In one possible implementation, the determination module is configured to perform modulation processing on the first bit group corresponding to each first demodulated bit group to obtain multiple second sparse signals; compress the multiple second sparse signals into a third codeword; and determine the second codeword based on the first codeword and the third codeword.

[0212] In one possible implementation, any first demodulation bit group includes at least one demodulation bit block corresponding to each of the multiple first sparse signals; the demodulation module 1303 is configured to determine, for any first sparse signal, an LLR block based on the at least one demodulation bit block corresponding to the any first sparse signal, where the LLR block includes multiple LLRs; determine an information LLR group based on the respective LLR blocks corresponding to the first group in any first demodulation bit group; and determine a check LLR group based on the respective LLR blocks corresponding to the second group in any first demodulation bit group.

[0213] In a possible implementation, the demodulation module 1303 is configured to perform demodulation processing on the multiple first sparse signals to determine at least one second demodulation bit group; and perform debit interleaving processing on the at least one second demodulation bit group to obtain at least one first demodulation bit group.

[0214] In a possible implementation, the decompression module 1302 is configured to perform clipping compensation processing on the first codeword to obtain a clipping compensated first codeword; and decompress the clipping compensated first codeword into a plurality of first sparse signals.

[0215] An embodiment of the present application provides a decoding device that can obtain a first LLR group based on a first codeword, perform check decoding processing on an information LLR group in the first LLR group based on a check LLR group in the first LLR group, and obtain an information bit group, thereby obtaining correct information bits based on the check information in the changed target codeword, reducing errors in transmission frames, lowering the frame error rate, and improving the performance of the communication system.

[0216] It should be understood that the above Figure 13 The provided device is illustrated only by the division of the above-mentioned functional modules when implementing its functions. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0217] See also Figure 14 , Figure 14 A schematic structural diagram of a network device 2000 provided by an exemplary embodiment of the present application is shown. Figure 14 The network device 2000 shown is used to perform the above Figure 2-9 The operations involved in the encoding method or decoding method shown are as follows: The network device 2000 is, for example, a switch, a router, etc. The network device 2000 can be implemented by a general bus architecture.

[0218] like Figure 14 As shown, the network device 2000 includes at least one processor 2001 , a memory 2003 and at least one communication interface 2004 .

[0219] The processor 2001 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing units (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, a transistor logic device, a hardware component, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute the various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present invention. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0220] Optionally, the network device 2000 further includes a bus. The bus is used to transmit information between the components of the network device 2000. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 14 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0221] The memory 2003 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, or a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0222] The communication interface 2004 uses any transceiver-like device for communicating with other devices or communication networks. The communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). The communication interface 2004 can include a wired communication interface or a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a Wireless Local Area Network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In an embodiment of the present application, the communication interface 2004 can be used for the network device 2000 to communicate with other devices.

[0223] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as Figure 12 0 and CPU1 are shown in FIG. Each of these processors can be a single-CPU processor or a multi-CPU processor. A processor herein can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0224] In a specific implementation, as an embodiment, the network device 2000 may include multiple processors, such as Figure 12 1 and 2. Each of these processors may be a single-CPU or a multi-CPU. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0225] In a specific implementation, as an embodiment, the network device 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and can display information in a variety of ways. For example, the output device can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and can receive user input in a variety of ways. For example, the input device can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0226] In some embodiments, the memory 2003 is used to store program code 2005 for executing the solution of the present application, and the processor 2001 can execute the program code 2005 stored in the memory 2003. That is, the network device 2000 can implement the encoding method or decoding method provided by the method embodiment through the processor 2001 and the program code 2005 in the memory 2003. The program code 2005 may include one or more software modules. Optionally, the processor 2001 itself may also store program code or instructions for executing the solution of the present application.

[0227] In a specific embodiment, the network device 2000 of the embodiment of the present application may correspond to the control device in each of the above-mentioned network management method embodiments, and the processor 2001 in the network device 2000 reads the instruction in the memory 2003, so that Figure 14 The illustrated network device 2000 is capable of performing all or part of the operations performed by a control device.

[0228] Specifically, the processor 2001 is configured to send the candidate policy configuration gain to the display interface via the communication interface, where the candidate policy configuration gain is obtained by configuring the candidate policy. Other optional implementations are not described here for the sake of brevity.

[0229] For another example, the processor 2001 of the network device 2000 of the embodiment of the present application reads the instruction in the memory 2003, so that Figure 14The network device 2000 shown is capable of executing all or part of the operations provided by the method embodiment.

[0230] Specifically, the processor 2001 is configured to receive, via the communication interface, a candidate policy configuration gain sent by the control device to the display interface, where the candidate policy configuration gain is obtained by configuring the candidate policy. Other optional implementations are not described here for brevity.

[0231] The network device 2000 may also correspond to the above Figure 12 The encoding device shown or Figure 13 The decoding device, encoding device, or each functional module in the decoding device is implemented using software of the network device 2000. In other words, the functional modules included in the encoding device or decoding device are generated by the processor 2001 of the network device 2000 after reading the program code 2005 stored in the memory 2003.

[0232] in, Figure 2-9 Each step of the encoding method or decoding method shown is completed by the hardware integrated logic circuit or software instructions in the processor of the network device 2000. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware. To avoid repetition, it will not be described in detail here.

[0233] See also Figure 15 , Figure 15 A schematic structural diagram of a network device 2100 provided in another exemplary embodiment of the present application is shown. Figure 15 The network device 2100 shown is used to perform the above Figure 2-9 All or part of the operations involved in the encoding method or decoding method shown. The network device 2100 is, for example, a switch, a router, etc. The network device 2100 can be implemented by a general bus architecture.

[0234] like Figure 13 As shown, the network device 2100 includes: a main control board 2110 and an interface board 2130 .

[0235] The main control board (2110), also known as the main processing unit (MPU) or route processor card, is used to control and manage various components in network device 2100, including routing calculations, device management, device maintenance, and protocol processing. It includes a central processing unit (CPU) 2111 and memory 2112.

[0236] Interface board 2130 is also known as a line processing unit (LPU), line card, or service board. It provides various service interfaces and implements data packet forwarding. Service interfaces include, but are not limited to, Ethernet interfaces and POS (packet over SONET / SDH) interfaces. Ethernet interfaces, for example, are interfaces for flexible Ethernet clients (FlexE Clients). Interface board 2130 includes a central processing unit (CPU) 2131, a network processor (NPU) 2132, a forwarding table memory 2134, and a physical interface card (PIC) 2133.

[0237] The central processing unit 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processing unit 2111 on the main control board 2110 .

[0238] The network processor 2132 is used to implement message forwarding processing. The network processor 2132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward received messages based on the forwarding table stored in the forwarding entry memory 2134. If the destination address of the message is the address of the network device 2100, the message is sent to the CPU (such as the central processing unit 2131) for processing. If the destination address of the message is not the address of the network device 2100, the next hop and outgoing interface corresponding to the destination address are searched in the forwarding table based on the destination address, and the message is forwarded to the outgoing interface corresponding to the destination address. The processing of uplink messages may include processing the message inbound interface and forwarding table lookup; the processing of downlink messages may include forwarding table lookup, etc. In some embodiments, the central processing unit may also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, thereby eliminating the need for a forwarding chip in the interface board.

[0239] Physical interface card 2133 implements physical layer interconnection. Raw traffic enters interface board 2130 through this card, and processed packets are sent out from this physical interface card 2133. Physical interface card 2133, also known as a daughter card, can be installed on interface board 2130. It converts optical and electrical signals into packets, performs a validity check on these packets, and then forwards them to network processor 2132 for processing. In some embodiments, central processing unit 2131 can also perform the functions of network processor 2132, such as implementing software forwarding based on a general-purpose CPU, thus eliminating the need for network processor 2132 in physical interface card 2133.

[0240] Optionally, the network device 2100 includes multiple interface boards. For example, the network device 2100 further includes an interface board 2140. The interface board 2140 includes a central processing unit 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143. The functions and implementation of each component in the interface board 2140 are the same as or similar to those of the interface board 2130 and are not described in detail here.

[0241] Optionally, network device 2100 also includes a switching fabric board 2120. Switching fabric board 2120 may also be referred to as a switch fabric unit (SFU). If the network management device has multiple interface boards, switching fabric board 2120 is used to exchange data between the interface boards. For example, interface board 2130 and interface board 2140 can communicate via switching fabric board 2120.

[0242] The main control board 2110 is coupled to the interface board. For example, the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane via a system bus to achieve intercommunication. In one possible implementation, an inter-process communication (IPC) channel is established between the main control board 2110 and the interface boards 2130 and 2140, and communication is performed between the main control board 2110 and the interface boards 2130 and 2140 via the IPC channel.

[0243] Logically, network device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processing unit (CPU) 2111. The forwarding plane includes various components that perform forwarding, such as a forwarding table entry memory 2134, physical interface cards 2133, and a network processor 2132. The control plane performs routing functions, generates forwarding tables, processes signaling and protocol messages, and configures and maintains the network device's status. The control plane sends the generated forwarding tables to the forwarding plane. On the forwarding plane, the network processor 2132 forwards messages received by the physical interface card 2133 based on the forwarding tables sent by the control plane. The forwarding tables sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and forwarding plane can be completely separate and not located on the same network device.

[0244] It's worth noting that there may be one or more main control boards (SPUs), which can include both active and standby SPUs. There may also be one or more interface boards. The higher the network management device's data processing capabilities, the more interface boards it provides. Interface boards can also have one or more physical interface cards. There may be no SPUs, one or more SPUs, and multiple SPUs can be used to achieve load balancing and redundant backup. In a centralized forwarding architecture, a network management device may not require SPUs; the interface boards handle the entire system's service data processing. In a distributed forwarding architecture, a network management device may have at least one SPU, which enables data exchange between multiple interface boards, providing high-capacity data exchange and processing capabilities. Therefore, network management devices with distributed architectures have greater data access and processing capabilities than those with centralized architectures. Alternatively, the network management device can consist of a single board, without a switching network board. The functions of the interface board and the main control board are integrated on this single board. In this case, the central processing unit (CPU) on the interface board and the CPU on the main control board can be combined into a single CPU on this single board to perform the combined functions of the two. This type of network management device has lower data exchange and processing capabilities (for example, low-end network devices such as switches or routers). The specific architecture to be used depends on the specific network deployment scenario and is not specified here.

[0245] In a specific embodiment, the network device 2100 corresponds to the above Figure 12 In some embodiments, Figure 12 The acquisition module 1201 in the encoding device shown is equivalent to the physical interface card 2133 in the network device 2100; the check coding module 1202, the modulation module 1203 and the compression module 1204 are equivalent to the central processing unit 2111 or the network processor 2132 in the network device 2100. The network device 2100 may also correspond to the above Figure 13 In some embodiments, Figure 13 The acquisition module 1301 in the decoding device shown is equivalent to the physical interface card 2133 in the network device 2100; the decompression module 1302, the demodulation module 1303, the determination module 1304 and the check decoding module 1305 are equivalent to the central processing unit 2111 or the network processor 2132 in the network device 2100.

[0246] Based on the above Figure 14 and Figure 15 The network device shown in the embodiment of the present application also provides a network system, which includes: a control device. Optionally, the control device is Figure 14 The network device 2000 or Figure 15 Network device 2100 is shown.

[0247] The encoding method or decoding method performed by the network device can be found in the above Figure 2-9 The relevant description of the illustrated embodiment will not be repeated here.

[0248] The present application also provides a communication device, comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other via an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals. When the processor executes the instructions stored in the memory, the processor performs the encoding method or decoding method involved in the method embodiment.

[0249] It should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. It is worth noting that the processor may be a processor that supports the Advanced RISC Machine (ARM) architecture.

[0250] Furthermore, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store device type information.

[0251] The memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache memory. By way of example and not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (DR RAM).

[0252] An embodiment of the present application also provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor to implement any of the encoding methods or decoding methods described above.

[0253] The embodiments of the present application also provide a computer program (product), which, when executed by a computer, can enable a processor or computer to execute the various steps and / or processes of the corresponding encoding method or decoding method in the above method embodiments.

[0254] An embodiment of the present application also provides a chip, including a processor, for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes the encoding method or decoding method in the above aspects.

[0255] An embodiment of the present application also provides another chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the encoding method or decoding method in the above aspects.

[0256] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive).

[0257] Those skilled in the art will appreciate that the various method steps and modules described in conjunction with the embodiments disclosed herein can be implemented in software, hardware, firmware, or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0258] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0259] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target. Generally speaking, a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure. In various embodiments, the function of the program module can be merged or split between the described program modules. The machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.

[0260] The computer program code for realizing the method for the embodiment of the application can be written in one or more programming languages.These computer program codes can be provided to the processor of general-purpose computer, special-purpose computer or other programmable data processing device, so that program code, when being executed by computer or other programmable data processing device, causes the function / operation specified in flow chart and / or block diagram to be implemented.Program code can be executed completely on computer, partly on computer, as independent software package, partly on computer and partly on remote computer or completely on remote computer or server.

[0261] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like.

[0262] Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0263] A machine-readable medium may be any tangible medium that contains or stores a program for or in connection with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0264] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0265] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or can be electrical, mechanical or other forms of connection.

[0266] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0267] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0268] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0269] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items that have substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on quantity or order of execution. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described examples, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image. Both the first image and the second image may be images, and in some cases, may be separate and different images.

[0270] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0271] In this application, the term "at least one" means one or more, and the term "plurality" means two or more. For example, "plurality of second messages" means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0272] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0273] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items. The term "and / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this application generally indicates that the associated objects are in an "or" relationship.

[0274] It will also be understood that the term “comprise” (also known as “includes,” “including,” “comprises,” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0275] It should also be understood that the terms “if” and “if” may be interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting.” Similarly, the phrases “if it is determined that ” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining ” or “in response to determining ” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event],” depending on the context.

[0276] It should be understood that determining B based on A does not mean determining B based solely on A. B can also be determined based on A and / or other information.

[0277] It should also be understood that references throughout this specification to "one embodiment," "an embodiment," or "one possible implementation" mean that specific features, structures, or characteristics associated with that embodiment or implementation are included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "one possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0278] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A coding method, characterized in that: The method comprises: Acquire at least one information bit group, where the information bit group includes a plurality of information bits; For any information bit group, perform check coding processing on the any information bit group to obtain a check bit group corresponding to the any information bit group, where the check bit group corresponding to the any information bit group includes multiple check bits; Performing modulation processing on at least one target bit group to obtain multiple target sparse signals, where one target bit group includes an information bit group and a check bit group corresponding to the information bit group; The plurality of target sparse signals are compressed into target codewords.

2. The method according to claim 1, characterized in that The information bit group includes multiple rows and columns of information bits, and a row of information bits constitutes an information bit unit; The performing check coding processing on any one of the information bit groups to obtain a check bit group corresponding to the any one of the information bit groups includes: For any information bit unit in any information bit group, perform check coding processing on the any information bit unit to obtain a check bit unit corresponding to the any information bit unit, where the check bit unit includes multiple check bits; Based on the check bit units corresponding to the information bit units in any one of the information bit groups, the check bit group corresponding to the any one of the information bit groups is determined, wherein the check bit group corresponding to the any one of the information bit groups includes multiple rows and columns of check bits, and a row of check bits constitutes a check bit unit.

3. The method according to any one of claims 1-2, characterized in that After compressing the multiple target sparse signals into target codewords, the method further includes: performing a clipping process on the target codeword to obtain a target codeword after the clipping process; The target codeword after the clipping process is transmitted based on a target channel.

4. The method according to any one of claims 1 to 2, characterized in that The information bit group includes multiple rows and columns of information bits, one column of information bits constitutes an information bit block, and the check bit group includes multiple rows and columns of check bits, one column of check bits constitutes a check bit block; The modulating process is performed on at least one target bit group to obtain a plurality of target sparse signals, including: For any target bit group, performing modulation processing on each information bit block in the target bit group to obtain a target sparse signal corresponding to each information bit block in the target bit group; Modulation processing is performed on each check bit block in any target bit group to obtain a target sparse signal corresponding to each check bit block in any target bit group.

5. The method according to any one of claims 1-2, characterized in that The modulating process is performed on at least one target bit group to obtain a plurality of target sparse signals, including: Performing bit interleaving processing on the at least one target bit group to obtain at least one target bit group after bit interleaving processing; Modulation processing is performed on at least one target bit group after the bit interleaving processing to obtain multiple target sparse signals.

6. A decoding method, characterized in that: The method comprises: Get the first codeword; decompressing the first codeword into a plurality of first sparse signals; Demodulating the plurality of first sparse signals to obtain at least one first demodulated bit group, wherein the first demodulated bit group includes a first group and a second group, the first group includes a plurality of information bits, and the second group includes a plurality of check bits; For any first demodulation bit group, a check decoding process is performed on the first group of any first demodulation bit groups based on the second group of any first demodulation bit groups to obtain an information bit group, where the information bit group includes multiple information bits.

7. The method according to claim 6, characterized in that The demodulating the plurality of first sparse signals to obtain at least one first demodulated bit group includes: For any first sparse signal, demodulate the signal to obtain at least one demodulated bit block corresponding to the first sparse signal, where the demodulated bit block includes multiple information bits or multiple check bits; Based on at least one demodulation bit block corresponding to each of the multiple first sparse signals, determine the at least one first demodulation bit group, wherein the first demodulation bit group includes multiple rows and columns of information bits and multiple rows and columns of check bits, one column of information bits constitutes a demodulation bit block, and one column of check bits constitutes a demodulation bit block.

8. The method according to claim 7, characterized in that The demodulating any one of the first sparse signals to obtain at least one demodulated bit block corresponding to the any one of the first sparse signals includes: Converting any one of the first sparse signals into at least one sparse estimation signal, where the sparse estimation signal is an estimated value of the any one of the first sparse signals; For any sparse estimation signal, demodulation processing is performed on the sparse estimation signal to obtain a demodulated bit block.

9. The method according to any one of claims 6 to 8, characterized in that The performing check decoding processing on the first group of the any first demodulated bit groups based on the second group of the any first demodulated bit groups to obtain an information bit group includes: determining an information log-likelihood ratio (LLR) group based on a first group of any one of the first demodulated bit groups, wherein the information LLR group includes a plurality of LLRs; Determine a check LLR group based on a second group of any one of the first demodulated bit groups, the check LLR group including a plurality of LLRs; The information LLR group is subjected to a check decoding process based on the check LLR group to obtain an information bit group.

10. The method according to claim 9, characterized in that The information LLR group includes a plurality of information LLR units, and the check LLR group includes a plurality of check LLR units; performing check decoding processing on the information LLR group based on the check LLR group to obtain an information bit group includes: Decoding each target LLR unit in the first LLR group to obtain at least one candidate bit unit corresponding to each target LLR unit, where each target LLR unit includes an information LLR unit and a check LLR unit, and each candidate bit unit includes an information bit unit and a check bit unit; For any candidate bit unit, verify the information bit unit in the any candidate bit unit based on the check bit unit in the any candidate bit unit to obtain a verification result of the any candidate bit unit; In response to each target LLR unit in the first LLR group satisfying a condition, an information bit group is obtained based on the target bit units corresponding to each target LLR unit in the first LLR group. A target LLR unit satisfies the condition that a verification result of a target bit unit exists in at least one candidate bit unit corresponding to the target LLR unit is a successful verification, and the information bit unit in the target bit unit is a row of information bits in the information bit group.

11. The method according to claim 10, characterized in that The verifying, based on the check bit unit in any one of the candidate bit units, the information bit unit in any one of the candidate bit units to obtain a verification result of the any one of the candidate bit units, includes: Performing check coding processing on the information bit unit in any candidate bit unit to obtain a check bit unit to be compared; The check bit unit to be compared is compared with the check bit unit in any one of the candidate bit units, and a check result of the any one of the candidate bit units is obtained according to the comparison result.

12. The method according to claim 10, characterized in that After verifying the information bit unit in any candidate bit unit based on the check bit unit in any candidate bit unit and obtaining the verification result of any candidate bit unit, the method further includes: In response to the presence of at least one target LLR unit that does not meet the condition in the first LLR group, obtaining a first bit group corresponding to any one of the first demodulated bit groups, where the first bit group corresponding to any one of the first demodulated bit groups includes target bit units corresponding to respective target LLR units that meet the condition in the first LLR group; determining a second codeword based on the first bit group corresponding to each first demodulated bit group; determining, based on the second codeword, a second bit group corresponding to any one of the first demodulated bit groups, where the second bit group corresponding to any one of the first demodulated bit groups includes information bit units in target bit units corresponding to respective target LLR units in the first LLR group that do not meet the condition; The one information bit group is determined based on a first bit group corresponding to any one of the first demodulated bit groups and a second bit group corresponding to any one of the first demodulated bit groups.

13. The method according to claim 12, characterized in that The determining the second codeword based on the first bit group corresponding to each first demodulated bit group includes: performing modulation processing on the first bit groups corresponding to the respective first demodulated bit groups to obtain a plurality of second sparse signals; compressing the plurality of second sparse signals into a third codeword; The second codeword is determined based on the first codeword and the third codeword.

14. The method according to claim 9, characterized in that Any one of the first demodulation bit groups includes at least one demodulation bit block corresponding to each of the plurality of first sparse signals; The determining of the information LLR group based on the first group in any one of the first demodulated bit groups and the determining of the check LLR group based on the second group in any one of the first demodulated bit groups include: For any first sparse signal, determine an LLR block based on at least one demodulated bit block corresponding to the any first sparse signal, where the LLR block includes a plurality of LLRs; Determine the information LLR group based on each LLR block corresponding to the first group in any one of the first demodulated bit groups; The check LLR group is determined based on each LLR block corresponding to the second group in any one of the first demodulated bit groups.

15. The method according to any one of claims 6-8, 10-14, characterized in that: The demodulating the plurality of first sparse signals to obtain at least one first demodulated bit group includes: Demodulating the plurality of first sparse signals to determine at least one second demodulated bit group; Perform bit deinterleaving processing on the at least one second demodulation bit group to obtain the at least one first demodulation bit group.

16. The method according to any one of claims 6-8, 10-14, characterized in that: The decompressing the first codeword into a plurality of first sparse signals includes: performing a limiting compensation process on the first codeword to obtain a first codeword after the limiting compensation process; The first codeword after the amplitude limiting compensation processing is decompressed into a plurality of first sparse signals.

17. An encoding device, characterized in that: The device comprises: An acquisition module, configured to acquire at least one information bit group, wherein the information bit group includes a plurality of information bits; a check coding module, configured to perform check coding processing on any information bit group to obtain a check bit group corresponding to the any information bit group, wherein the check bit group corresponding to the any information bit group includes a plurality of check bits; a modulation module, configured to perform modulation processing on at least one target bit group to obtain a plurality of target sparse signals, wherein one target bit group includes an information bit group and a check bit group corresponding to the information bit group; A compression module is used to compress the multiple target sparse signals into target codewords.

18. The device according to claim 17, characterized in that The information bit group includes multiple rows and columns of information bits, and a row of information bits constitutes an information bit unit; The check coding module is used to perform check coding processing on any information bit unit in any information bit group to obtain a check bit unit corresponding to the any information bit unit, where the check bit unit includes multiple check bits; based on the check bit units corresponding to each information bit unit in the any information bit group, determine the check bit group corresponding to the any information bit group, where the check bit group corresponding to the any information bit group includes multiple rows and columns of check bits, and one row of check bits constitutes one check bit unit.

19. The device according to any one of claims 17-18, characterized in that The device further comprises: A clipping module, configured to perform clipping processing on the target codeword to obtain the target codeword after clipping processing; A transmission module is used to transmit the target codeword after the limiting processing based on a target channel.

20. The device according to any one of claims 17-18, characterized in that The information bit group includes multiple rows and columns of information bits, one column of information bits constitutes an information bit block, and the check bit group includes multiple rows and columns of check bits, one column of check bits constitutes a check bit block; The modulation module is configured to perform modulation processing on each information bit block in any target bit group to obtain a target sparse signal corresponding to each information bit block in the any target bit group; Modulation processing is performed on each check bit block in any target bit group to obtain a target sparse signal corresponding to each check bit block in any target bit group.

21. The device according to any one of claims 17-18, characterized in that The modulation module is used to perform bit interleaving processing on the at least one target bit group to obtain at least one target bit group after bit interleaving processing; and perform modulation processing on the at least one target bit group after bit interleaving processing to obtain multiple target sparse signals.

22. A decoding device, characterized in that: The device comprises: An acquisition module, configured to acquire a first codeword; a decompression module, configured to decompress the first codeword into a plurality of first sparse signals; a demodulation module, configured to perform demodulation processing on the plurality of first sparse signals to obtain at least one first demodulation bit group, wherein the first demodulation bit group includes a first group and a second group, the first group includes a plurality of information bits, and the second group includes a plurality of check bits; The check decoding module is used to perform check decoding processing on the first group of any first demodulated bit groups based on the second group of any first demodulated bit groups to obtain an information bit group, where the information bit group includes multiple information bits.

23. The device according to claim 22, characterized in that The demodulation module is configured to convert any first sparse signal into at least one sparse estimation signal, where the sparse estimation signal is an estimated value of the first sparse signal; perform demodulation processing on any sparse estimation signal to obtain a demodulated bit block, where the demodulated bit block includes multiple information bits or multiple check bits; and determine the at least one first demodulated bit group based on at least one demodulated bit block corresponding to each of the multiple first sparse signals, where the first demodulated bit group includes multiple rows and columns of information bits and multiple rows and columns of check bits, where one column of information bits constitutes one demodulated bit block, and one column of check bits constitutes one demodulated bit block.

24. The device according to any one of claims 22-23, characterized in that Any one of the first demodulation bit groups includes at least one demodulation bit block corresponding to each of the plurality of first sparse signals; The check and decoding module is configured to determine, for any first sparse signal, an LLR block based on at least one demodulated bit block corresponding to the any first sparse signal, the LLR block including multiple LLRs; determine an information LLR group based on each LLR block corresponding to a first group in the any first demodulated bit groups, the information LLR group including multiple LLRs; determine a check LLR group based on each LLR block corresponding to a second group in the any first demodulated bit groups, the check LLR group including multiple LLRs; and perform check and decoding processing on the information LLR group based on the check LLR group to obtain an information bit group.

25. The device according to claim 24, characterized in that The information LLR group includes a plurality of information LLR units, and the check LLR group includes a plurality of check LLR units; The check decoding module is configured to decode each target LLR unit in the first LLR group to obtain at least one candidate bit unit corresponding to each target LLR unit, where a target LLR unit includes an information LLR unit and a check LLR unit, and a candidate bit unit includes an information bit unit and a check bit unit; for any candidate bit unit, perform check coding on the information bit unit in the candidate bit unit to obtain a check bit unit to be compared; compare the check bit unit to be compared with the check bit unit in the candidate bit unit, and obtain a check result for the candidate bit unit based on the comparison result; in response to each target LLR unit in the first LLR group meeting a condition, obtain an information bit group based on the target bit unit corresponding to each target LLR unit in the first LLR group, where a target LLR unit meets the condition that a check result of a target bit unit exists in at least one candidate bit unit corresponding to the target LLR unit, and the information bit unit in the target bit unit is a row of information bits in the information bit group.

26. The device according to claim 25, characterized in that The device further comprises: The acquisition module is further configured to, in response to at least one target LLR unit that does not meet the condition existing in the first LLR group, acquire a first bit group corresponding to any one of the first demodulated bit groups, the first bit group corresponding to any one of the first demodulated bit groups including target bit units corresponding to respective target LLR units that meet the condition in the first LLR group; A determination module is configured to perform modulation processing on first bit groups corresponding to the respective first demodulation bit groups to obtain multiple second sparse signals; compress the multiple second sparse signals into a third codeword; determine a second codeword based on the first codeword and the third codeword; determine a second bit group corresponding to any one of the first demodulation bit groups based on the second codeword, the second bit group corresponding to any one of the first demodulation bit groups including information bit units in target bit units corresponding to respective target LLR units in the first LLR group that do not meet the conditions; and determine the one information bit group based on the first bit group corresponding to any one of the first demodulation bit groups and the second bit group corresponding to any one of the first demodulation bit groups.

27. The device according to any one of claims 22, 23, 25 or 26, characterized in that The demodulation module is configured to perform demodulation processing on the multiple first sparse signals to determine at least one second demodulation bit group; and perform debit interleaving processing on the at least one second demodulation bit group to obtain the at least one first demodulation bit group.

28. The device according to any one of claims 22, 23, 25 or 26, characterized in that The decompression module is configured to perform a limiting compensation process on the first codeword to obtain a first codeword after the limiting compensation process; and decompress the first codeword after the limiting compensation process into a plurality of first sparse signals.

29. A data processing system, characterized in that: The system includes a network controller, which is used to execute the encoding method described in any one of claims 1 to 5, or execute the decoding method described in any one of claims 6 to 16.

30. A network device, characterized in that: The invention comprises a processor and a computer program. When the processor executes the computer program, the network device implements the encoding method described in any one of claims 1 to 5, or executes the decoding method described in any one of claims 6 to 16.

Images