Solid-state imaging device

Abstract

A solid-state imaging device is provided, in which an image quality of image data is improved, with a comparator provided for each column. The solid-state imaging device includes a first comparison element and a transistor. An input voltage corresponding to a voltage of a vertical signal line is input to a source of the first comparison element, and the first comparison element outputs a drain voltage corresponding to a voltage between a gate and the source from a drain. A signal corresponding to the voltage of the vertical signal line is input to a gate of the transistor, and a source of the transistor is connected to the drain of the first comparison element.

Description

TECHNICAL FIELD

[0001] The present technology relates to a solid-state imaging device. Specifically, the present technology relates to a solid-state imaging device that performs analog-digital conversion for each column. BACKGROUND

[0002] Generally, a single-slope ADC (analog-digital converter) is used for AD (analog-digital) conversion in a solid-state imaging device and the like due to its simple structure. The single-slope ADC generally includes a comparator and a counter that performs counting based on a comparison result of the comparator. For example, a solid-state imaging device has been proposed in which a pMOS (p-channel metal-oxide-semiconductor) transistor in which a pixel signal is input to a source and a reference signal is input to a gate is provided in the comparator (see, for example, Patent Literature 1). A drain and a source of the pMOS transistor are short-circuited by an auto-zero switch.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: US 2018 / 0103222 A SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In the above-described solid-state imaging device, a power supply of a pixel circuit is shared by the comparator so as to reduce power consumption compared to a configuration in which a power supply is also provided in the comparator separate from the pixel circuit. However, in the above-described solid-state imaging device, image quality of captured image data can be degraded. Factors of the image quality degradation can include, for example, reset feedthrough during operation of the auto-zero switch and insufficient dynamic range.

[0008] The present technology is made in view of such circumstances, and an object thereof is to improve image quality of image data in a solid-state imaging device in which a comparator is provided per column.

[0009] SOLUTION TO THE PROBLEM

[0010] The present technology is made to solve the above-described problem, and a first aspect of the present technology provides a solid-state imaging device including: a first comparison element to which an input voltage related to a voltage of a vertical signal line is input to a source, the first comparison element outputting a drain voltage corresponding to a gate-source voltage from a drain; and a transistor to which a signal corresponding to the voltage of the vertical signal line is input to a gate, a source being connected to the drain of the first comparison element. This configuration provides an effect of improving image quality.

[0011] Further, in the first aspect, a source of the first comparison element can be connected to the vertical signal line, a predetermined reference voltage input can be input to a gate of the first comparison element, the first comparison element can be turned from an off state to an on state in a case where the input voltage and the reference voltage substantially coincide with each other, and the transistor can include a first clamp transistor that fixes a drain voltage in the off state to a clamp voltage corresponding to the input voltage. This configuration provides an effect of ensuring linearity.

[0012] Further, in the first aspect, the solid-state imaging element can further include a clamp voltage controller that supplies a signal to a gate of the first clamp transistor, and the first clamp transistor can be inserted between a drain and a source of the first comparison element. This configuration provides an effect of supplying a gate voltage corresponding to a voltage of the vertical signal line.

[0013] Further, in the first aspect, the solid-state imaging element can further include a second clamp transistor connected in parallel with the first clamp transistor, and a fixed voltage can be applied to a gate of the second clamp transistor.

[0014] Further, in the first aspect, the clamp voltage controller can include a capacitor inserted between the vertical signal line and the gate of the first clamp transistor.

[0015] Further, in the first aspect, the clamp voltage controller can divide a voltage between a voltage of the vertical signal line and a predetermined reference potential and supply the divided voltage to the gate of the first clamp transistor. Examples of a method for dividing the voltage include a method for dividing a potential between the vertical signal line and the predetermined reference potential by a capacitor or a resistor. This configuration provides an effect of expanding a dynamic range.

[0016] Further, in the first aspect, the solid-state imaging element can further include an initialization circuit that samples a voltage of the vertical signal line, holds the sampled voltage as a hold voltage, and initializes a gate voltage of the first clamp transistor based on the hold voltage. When a capacitor is provided, the gate of the first clamp transistor becomes a high-impedance node. This configuration provides an effect of initializing the clamp voltage to a value corresponding to the voltage of the vertical signal line.

[0017] Further, in the first aspect, the initialization circuit can sample and hold a pixel signal of a pixel circuit.

[0018] Further, in the first aspect, the initialization circuit can sample and hold a pixel signal of a light-shielded light-shielded pixel.

[0019] Further, in the first aspect, the initialization circuit can sample and hold a pixel signal of a dummy pixel.

[0020] Further, in the first aspect, the driver can sample and hold a pixel signal of a dummy pixel that is shielded from light.

[0021] Further, in the first aspect, the solid-state imaging device can include a counter that counts a count value during a period before the drain voltage is inverted. This configuration provides an effect of converting an analog signal into a digital signal. As the counter described here, a dedicated counter can be provided, or an AD output result can be used.

[0022] Further, in the first aspect, the solid-state imaging device can include a correction coefficient calculation unit that calculates a correction coefficient for correcting a conversion gain that is a ratio between an input voltage and a count value, and a correction unit that corrects a digital signal indicating the count value based on the correction coefficient. This configuration provides an effect of improving sensitivity.

[0023] Further, in the first aspect, the solid-state imaging device can further include a controller that calculates a correction coefficient for correcting a conversion gain that is a ratio between an input voltage and a count value, and controls a reference voltage based on the correction coefficient. This configuration provides an effect of improving sensitivity.

[0024] Further, in the first aspect, the transistor can include an auto-zero switch that shorts a gate and a drain of the first comparison element according to a signal. This configuration provides an effect of reducing noise.

[0025] Further, in the first aspect, a source of the first comparison element can be connected to a vertical signal line, and a predetermined reference voltage can be input to a gate of the first comparison element. This configuration provides an effect of reducing noise in a comparator.

[0026] Further, in the first aspect, the solid-state imaging device can further include a driver that generates a predetermined control signal as a signal based on a voltage of the vertical signal line. This configuration provides an effect of driving the auto-zero switch.

[0027] Further, in the first aspect, the driver can provide one of two values as the control signal. This configuration provides an effect of realizing binary driving of the auto-zero switch.

[0028] Further, in the first aspect, the driver can sample and hold a pixel signal of a pixel circuit, and generate the control signal based on the held pixel signal. This configuration provides an effect of suppressing reset feedthrough.

[0029] Further, in the first aspect, the driver can sample and hold a pixel signal of a shielded pixel that is shielded from light, and generate the control signal based on the held pixel signal. This configuration provides an effect of suppressing reset feedthrough.

[0030] Further, in the first aspect, the driver can generate the control signal based on the pixel signal of the dummy pixel. This configuration provides an effect of suppressing reset feedthrough.

[0031] Further, in the first aspect, the driver can generate the control signal based on the pixel signal of the dummy pixel. This configuration provides an effect of suppressing reset feedthrough.

[0032] Further, in the first aspect, the first comparison element can be arranged in a column amplifier that amplifies a voltage of the vertical signal line and supplies the amplified voltage to an analog-digital converter. This configuration provides an effect of suppressing reset feedthrough in the column amplifier.

[0033] Further, in the first aspect, the solid-state imaging element can further include a second comparison element, a gate to which a voltage of the vertical signal line is input, a drain connected to a power supply voltage, and a source connected to the source of the first comparison element. This configuration provides an effect of lowering a voltage of a reference signal. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a block diagram showing a configuration example of an imaging device according to the first embodiment of the present technology.

[0035] Figure 2 is a diagram showing an example of a stacked structure of a solid-state imaging element according to the first embodiment of the present technology.

[0036] Figure 3 is a block diagram showing a configuration example of a solid-state imaging element according to the first embodiment of the present technology.

[0037] Figure 4 is a circuit diagram showing a configuration example of a pixel circuit in the first embodiment of the present technology.

[0038] Figure 5 is a block diagram showing a configuration example of a column signal processor in the first embodiment of the present technology.

[0039] Figure 6 is a circuit diagram showing a configuration example of a comparator in the first embodiment of the present technology.

[0040] Figure 7 is a diagram for describing a dynamic range of a solid-state imaging element according to the first embodiment of the present technology.

[0041] Figure 8 is a timing chart showing an example of an operation of a solid-state imaging element according to the first embodiment of the present technology.

[0042] Figure 9 is a graph showing an example of a relationship between an output of a first stage of a comparator in the first embodiment of the present technology and a light intensity.

[0043] Figure 10 is a graph showing an example of a relationship between a digital signal and an input voltage in the first embodiment of the present technology.

[0044] Figure 11 is a flowchart showing an example of an operation of the solid-state imaging device according to the first embodiment of the present technology.

[0045] Figure 12 is a circuit diagram showing a configuration example of a comparator in the first modification of the first embodiment of the present technology.

[0046] Figure 13 is a circuit diagram showing a configuration example of a comparator that performs voltage division using a resistor in the first modification of the first embodiment of the present technology.

[0047] Figure 14 is a graph showing an example of a relationship between an output of the first stage of the comparator and a light intensity in the first modification of the first embodiment of the present technology.

[0048] Figure 15 is a block diagram showing a configuration example of the solid-state imaging device according to the second modification of the first embodiment of the present technology.

[0049] Figure 16 is a circuit diagram showing a configuration example of the pixel array unit in the second modification of the first embodiment of the present technology.

[0050] Figure 17 is a circuit diagram showing a configuration example of the comparator in the second modification of the first embodiment of the present technology.

[0051] Figure 18 is a circuit diagram showing a configuration example of the initialization circuit in the second modification of the first embodiment of the present technology.

[0052] Figure 19 is a timing chart showing an example of an operation of the solid-state imaging device according to the second modification of the first embodiment of the present technology.

[0053] Figure 20 is a circuit diagram showing a configuration example of the comparator in the third modification of the first embodiment of the present technology.

[0054] Figure 21 is a circuit diagram showing a configuration example of the pixel array unit in the third modification of the first embodiment of the present technology.

[0055] Figure 22 is a block diagram showing a configuration example of the solid-state imaging device according to the third modification of the first embodiment of the present technology.

[0056] Figure 23 FIG. 3 is a block diagram showing a configuration example of an image processor in a third modification of the first embodiment of the present technology.

[0057] Figure 24 FIG. 4 is a graph showing an example of a relationship between a digital signal and an input voltage in the third modification of the first embodiment of the present technology.

[0058] Figure 25 FIG. 5 is a circuit diagram showing a configuration example of a DAC in a fourth modification of the first embodiment of the present technology.

[0059] Figure 26 FIG. 6 is a circuit diagram showing an example of a waveform of a reference signal in the fourth modification of the first embodiment of the present technology.

[0060] Figure 27 FIG. 7 is a circuit diagram showing a configuration example of a timing controller in the second embodiment of the present technology.

[0061] Figure 28 FIG. 8 is a timing chart showing an example of an operation of a solid-state imaging device according to the second embodiment of the present technology.

[0062] Figure 29 FIG. 9 is a circuit diagram showing a configuration example of a driver in the second embodiment of the present technology.

[0063] Figure 30 FIG. 10 is a timing chart showing an example of an operation of a timing controller in the second embodiment of the present technology.

[0064] Figure 31 FIG. 11 is a circuit diagram showing a configuration example of a pixel array section in a first modification of the second embodiment of the present technology.

[0065] Figure 32 FIG. 12 is a timing chart showing an example of an operation of a solid-state imaging device according to the first modification of the second embodiment of the present technology.

[0066] Figure 33 FIG. 13 is a circuit diagram showing a configuration example of a pixel array section in a second modification of the second embodiment of the present technology.

[0067] Figure 34 FIG. 14 is a timing chart showing an example of an operation of a solid-state imaging device according to the second modification of the second embodiment of the present technology.

[0068] Figure 35 FIG. 15 is a circuit diagram showing a configuration example of a timing controller in the second modification of the second embodiment of the present technology.

[0069] Figure 36is a timing chart showing an example of operation of a solid-state imaging device according to a third modification of the second embodiment of the present technology.

[0070] Figure 37 is a circuit diagram showing a configuration example of a pixel array section and a timing controller in a fourth modification of the second embodiment of the present technology.

[0071] Figure 38 is a circuit diagram showing a configuration example of a comparator in the fourth modification of the second embodiment of the present technology.

[0072] Figure 39 is a block diagram showing a configuration example of a solid-state imaging device according to a fifth modification of the second embodiment of the present technology.

[0073] Figure 40 is a circuit diagram showing a configuration example of a pixel array section, a constant current source, and a timing controller in the fifth modification of the second embodiment of the present technology.

[0074] Figure 41 is a circuit diagram showing a configuration example of a column amplifier in the fifth modification of the second embodiment of the present technology.

[0075] Figure 42 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0076] Figure 43 is a diagram showing an example of a mounting position of an imaging section. DETAILED DESCRIPTION

[0077] A mode for implementing the present technology (hereinafter, referred to as an embodiment) will be described below. The description will be given in the following order.

[0078] 1. First embodiment (example in which a gate voltage corresponding to a voltage of a vertical signal line is supplied to a clamp transistor)

[0079] 2. Second embodiment (example in which a control signal corresponding to a voltage of a vertical signal line is supplied to an auto-zero switch)

[0080] 3. Application example for moving objects

[0081] <1. First Embodiment>

[0082] [Configuration Example of Imaging Device]

[0083] Figure 1is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. The imaging device 100 is a device for imaging image data, and includes an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display section 130, an operation section 140, a bus 150, a frame memory 160, a memory 170, and a power supply 180. As the imaging device 100, a camera mounted on a smartphone, a vehicle-mounted camera, or the like is assumed.

[0084] The optical unit 110 collects light from an object and guides the light to the solid-state imaging element 200. The solid-state imaging element 200 generates image data by photoelectric conversion. The solid-state imaging element 200 supplies the generated image data to the DSP circuit 120 via a signal line 209.

[0085] The DSP circuit 120 performs predetermined signal processing on the image data. The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150.

[0086] The display section 130 displays the image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display section 130. The operation section 140 generates an operation signal according to an operation of a user.

[0087] The bus 150 is a common path through which the optical unit 110, the solid-state imaging element 200, the DSP circuit 120, the display section 130, the operation section 140, the frame memory 160, the memory 170, and the power supply 180 exchange data with each other.

[0088] The frame memory 160 holds the image data. The memory 170 stores various types of data such as the image data. The power supply 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display section 130, and the like.

[0089] Figure 2 is a diagram showing an example of a stacked structure of the solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and a light-receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection portion such as a via. Note that they can be connected using Cu-Cu bonding or bumps instead of the via.

[0090] [Configuration Example of Solid-state Imaging Element]

[0091] Figure 3is a block diagram showing a configuration example of a solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a vertical scanning circuit 210, a timing controller 220, a DAC (Digital-to-Analog Converter) 230, a pixel array section 240, a column signal processor 260, and a horizontal scanning circuit 270. A plurality of pixel circuits 250 are arranged in the pixel array section 240 in a two-dimensional lattice pattern.

[0092] For example, the pixel array section 240 is arranged on a light-receiving chip 201, and the remaining circuits are arranged on a circuit chip 202. Note that the circuits arranged in each chip are not limited to the circuits shown in the drawing.

[0093] The vertical scanning circuit 210 selects and drives the rows in the pixel array section 240 in turn.

[0094] The timing controller 220 controls the operation timing of the vertical scanning circuit 210, the DAC 230, the column signal processor 260, and the horizontal scanning circuit 270 in synchronization with a vertical synchronization signal VSYNC.

[0095] The DAC 230 generates a sawtooth ramp signal and supplies the generated ramp signal as a reference signal to the column signal processor 260.

[0096] The pixel circuit 250 generates an analog pixel signal by photoelectric conversion under the control of the vertical scanning circuit 210. The pixel circuit 250 of each column outputs the pixel signal to the column signal processor 260 via a vertical signal line (not shown).

[0097] In the column signal processor 260, an ADC (not shown) is configured for each column of pixel circuits 250. Each ADC converts the pixel signal of the corresponding column into a digital signal and outputs the digital signal to the DSP circuit 120 under the control of the horizontal scanning circuit 270.

[0098] The horizontal scanning circuit 270 controls the column signal processor 260 to output the digital signal in turn.

[0099] [Configuration example of pixel circuit]

[0100] Figure 4 is a circuit diagram showing a configuration example of the pixel circuit 250 in the first embodiment of the present technology. The pixel circuit 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256. Further, in the pixel array section 240, a vertical signal line 259 is wired in columns in the vertical direction.

[0101] The photoelectric conversion element 251 photoelectrically converts incident light to generate electric charges. The transfer transistor 252 transfers the electric charges from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with a transfer signal TRG from the vertical scanning circuit 210.

[0102] The reset transistor 253 extracts electric charges from the floating diffusion layer 254 and performs initialization in accordance with a reset signal RST from the vertical scanning circuit 210.

[0103] The floating diffusion layer 254 accumulates electric charges and generates a voltage corresponding to the amount of electric charges. The amplification transistor 255 amplifies the voltage of the floating diffusion layer 254.

[0104] The selection transistor 256 outputs the amplified voltage signal as a pixel signal to the column signal processor 260 via the vertical signal line 259 in accordance with a selection signal SEL from the vertical scanning circuit 210.

[0105] [Configuration example of column signal processor]

[0106] Figure 5 is a block diagram illustrating a configuration example of the column signal processor 260 in the first embodiment of the present technology. The column signal processor 260 includes a comparator 300, a counter 261, and a latch 262, which are provided for each column. In a case where the number of columns is N (N is an integer), N comparators 300, N counters 261, and N latches 262 are arranged.

[0107] The comparator 300 compares a reference signal from the DAC 230 with a pixel signal from the corresponding column. The voltage of the reference signal is hereinafter referred to as a reference voltage V RMP , and the voltage of the vertical signal line 259 that transfers the pixel signal is hereinafter referred to as an input voltage V VSL . The comparator 300 provides an output signal VCO indicating the comparison result to the counter 261 of the corresponding column.

[0108] Further, the level of the pixel signal at the time of initialization of the pixel circuit 250, that is, the input voltage V VSL , is hereinafter referred to as a “reset level”, and the level of the pixel signal at the time of charge transfer to the floating diffusion layer 254 is referred to as a “signal level”.

[0109] The counter 261 counts a count value during a period until the output signal VCO inverts. For example, the counter 261 decrements the count during a period until the output signal VCO corresponding to the reset level inverts, and increments the count during a period until the output signal VCO corresponding to the signal level inverts. As a result, a CDS (Correlated Double Sampling) process of obtaining a difference between the reset level and the signal level is implemented.

[0110] Then, the counter 261 holds the digital signal indicating the count value by the latch 262. The AD conversion process of converting the analog pixel signal into a digital signal is achieved by the comparator 300 and the counter 261. That is, the comparator 300 and the counter 261 function as an ADC. An ADC using a comparator and a counter as described above is generally called a single slope ADC.

[0111] Note that, although the CDS process is achieved by the up-counting and the down-counting, the configuration is not limited to this. The counter 261 can perform only the up-counting or the down-counting, and the CDS process for obtaining the difference can be performed by a circuit in a subsequent stage.

[0112] The latch 262 holds the digital signal. The latch 262 outputs the held digital signal under the control of the horizontal scanning circuit 270.

[0113] [Configuration Example of Comparator]

[0114] Figure 6 is a circuit diagram showing a configuration example of the comparator 300 in the first embodiment of the present technology. The comparator 300 includes an input capacitor 311, an input transistor 312, an auto-zero switch 313, a current source 314, and a band-pass capacitor 315. Further, the comparator 300 includes a clamp voltage controller 330, clamp transistors 316 and 317, an output transistor 318, an initialization switch 319, and a current source 320.

[0115] The input capacitor 311 is inserted between the DAC 230 and the gate of the input transistor 312.

[0116] The source of the input transistor 312 is connected to the vertical signal line 259, and an input voltage V VSL is input to the source. Further, a reference voltage V RMP is input to the gate via the input capacitor 311. When the input voltage V VSL input to the source and the reference voltage V RMP input to the gate are substantially identical to each other, the input transistor 312 outputs, from the drain, a voltage corresponding to the input voltage V VSL as a comparison result Vout. Here, the expression "substantially identical" means that the comparison voltages are completely identical to each other or that a difference between them is within a predetermined allowable value. The allowable value is set to the threshold voltage Vt of the input transistor 312. As the input transistor 312, for example, a pMOS transistor is used. Note that the input transistor 312 is an example of the first comparison element set forth in the claims.

[0117] Further, it is desirable that the back gate and the source of the input transistor 312 are short-circuited so as to suppress the back gate effect.

[0118] The automatic zeroing switch 313 shorts the gate and the drain of the input transistor 312 in accordance with a control signal AZSW from the timing controller 220. As the automatic zeroing switch 313, for example, a pMOS transistor is used.

[0119] The current source 314 is inserted between the drain of the input transistor 312 and a predetermined reference potential. The current source 314 supplies a constant current. The current source 314 is realized by an nMOS (n-channel metal oxide semiconductor) transistor or the like.

[0120] The band-gap capacitor 315 is inserted between the source and the drain of the input transistor 312.

[0121] The clamp transistor 316 is inserted between the source and the drain of the input transistor 312, and the gate is connected to the clamp voltage controller 330. As the clamp transistor 316, for example, an nMOS transistor is used.

[0122] The clamp voltage controller 330 supplies a gate voltage corresponding to the voltage (input voltage V VSL ) of the vertical signal line 259 to the gate of the clamp transistor 316. The clamp voltage controller 330 includes a capacitor 331 inserted between the vertical signal line 259 and the gate of the clamp transistor 316.

[0123] The clamp transistor 317 is inserted between the source and the drain of the input transistor 312, and a predetermined bias voltage Vbias is applied to the gate. As the clamp transistor 317, for example, an nMOS transistor is used.

[0124] When the input transistor 312 is off, the clamp transistors 316 and 317 suppress reduction of the comparison result Vout (in other words, a low level). In the clamp transistors, the clamp transistor 316 fixes the low level to a clamp voltage V VSL corresponding to the voltage (input voltage V CLP ) of the vertical signal line 259 in accordance with the gate voltage from the clamp voltage controller 330. In the above configuration, the low level is fixed to the clamp voltage V VSL which is lower than the input voltage V CLP by a predetermined value. The amplitude of the comparison result Vout can be made constant by the clamp transistor 316, and thus linearity can be ensured. Here, linearity means that the output (count value) of the ADC including the comparator 300 and the counter 261 is proportional to the input (input voltage V VSL ).

[0125] In addition, as the input voltage V VSL decreases, the low level (clamp voltage V CLP) also decreases. Here, it is assumed that when the low level drops to a predetermined saturation voltage V sat The transistors in the current source 314 operate in the linear region. The clamp transistor 317 limits the low level so that it does not drop to the saturation voltage V sat The clamp transistor 317 allows the transistor in the current source 314 to operate in the saturation region.

[0126] The source of the output transistor 318 is connected to the vertical signal line 259, and the input voltage V VSL Input to the source. In addition, the gate of the output transistor 318 is connected to the drain of the input transistor 312, and the comparison result Vout is input thereto. As the output transistor 318, for example, a pMOS transistor is used. In addition, it is desirable that the back gate and source of the output transistor 318 are short-circuited.

[0127] The output transistor 318 outputs an input voltage V from the drain to the source. VSL The output signal VCO is input to the counter 261 as a signal indicating whether the difference between the comparison result Vout input to the gate exceeds a predetermined threshold voltage.

[0128] Here, when the pixel signal and the reference signal are substantially consistent with each other, the drain voltage of the input transistor 312 (i.e., the comparison result Vout) changes according to the level of the pixel signal. Therefore, when the comparison result Vout is directly input to the subsequent circuit, the timing of the drain voltage inversion may deviate from the ideal timing of the pixel signal and the reference signal being substantially consistent with each other.

[0129] because Figure 6 With the connection in [ 1 ], the drain-source voltage of input transistor 312 is input as the gate-source voltage of output transistor 318. The amount of change in the drain voltage of input transistor 312 is equal to the amount of change in the voltage of the pixel signal, and therefore, the output signal VCO from output transistor 318 is inverted at the ideal timing when the pixel signal and the reference signal substantially coincide with each other. As described above, by adding output transistor 318, errors in inversion timing can be suppressed.

[0130] The initialization switch 319 opens and closes the path between the gate and the drain of the output transistor 318 according to the control signal GDSW from the timing controller 220 .

[0131] The current source 320 is inserted between the drain of the output transistor 318 and the reference potential and provides a constant current. The current source 320 is implemented by an nMOS transistor, etc. The drain-source voltage of the transistor is hereinafter referred to as the "current source operating voltage".

[0132] Note that although the band-limiting capacitor 315, the clamp transistor 317, and the output transistor 318 are arranged in the comparator 300, at least one of them can not be provided. In the case where the output transistor 318 is not provided, the initialization switch 319 and the current source 320 are not needed.

[0133] Further, a logic gate (inverter or the like) having a different power supply voltage from the previous stage can be inserted between the output transistor 318 and the counter 261. The power supply voltage can be converted by the logic gate.

[0134] Reference voltage V RMP is set to be higher than the reference voltage during the auto-zeroing, and decreases as time elapses during the AD conversion period. Here, the AD conversion period is a period during which the counter 261 performs counting. At the start of the AD conversion period, the input transistor 312 in the first stage is turned off, a current flows through the clamp transistor 316, and the clamp voltage determined by the clamp transistor 316 is output as the comparison result Vout. The output transistor 318 in the second stage is turned on and outputs the input voltage V VSL as the output signal VCO.

[0135] Then, when the reference voltage V RMP decreases and the gate voltage of the input transistor 312 becomes lower than the value obtained by subtracting the threshold voltage Vt of the input transistor 312 from the input voltage V VSL , the input transistor 312 in the first stage turns to the on state, and the comparison result Vout is inverted from the input voltage V VSL . The output transistor 318 in the second stage turns to the off state, and the output signal VCO is inverted to the current source operation voltage.

[0136] In this way, the comparator 300 compares the input voltage V VSL with the reference voltage V RMP , and outputs the input voltage V VSL or the current source operation voltage as the output signal VCO.

[0137] Figure 7 is a graph for describing the dynamic range of the solid-state imaging device 200 according to the first embodiment of the present technology. The drain-source voltage of the amplification transistor 255 in the on state in the pixel circuit 250 to which no light ray is incident is set to 1.0 volt (V). Further, the power supply voltage of the pixel circuit 250 is set to 2.8 volts (V). In this case, the maximum value of the voltage of the vertical signal line 259, that is, the input voltage V VSL is 1.8 volts (V), which is 1.0 volt (V) lower than the power supply voltage of the pixel circuit 250.

[0138] Further, the current source operation voltage of the current source 314 is 0.4 volts (V), and the drain-source voltage of the input transistor 312 before inversion is 0.6 volts (V). In this case, the minimum value of the voltage of the vertical signal line 259 that ensures linearity is 1.0 volts (V).

[0139] The voltage range of the vertical signal line 259 that ensures linearity is from 1.0 volts (V) to 1.8 volts (V). The ratio between the minimum and maximum values of the voltage range corresponds to the dynamic range.

[0140] [Operation example of solid-state imaging device]

[0141] Figure 8 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. In Figure 8 , V FD represents the voltage of the floating diffusion layer 254.

[0142] During the auto-zero period from timing TO to timing T1, the DAC 230 sets the reference voltage V RMP to the auto-zero potential. Further, the timing controller 220 sets the control signal AZSW to the low level. Thus, the output signal VCO is at the auto-zero potential.

[0143] During the period from timing T1 to T8, the timing controller 220 sets the control signal AZSW to the high level.

[0144] During the period from timing T1 to timing T2, the DAC 230 sets the reference voltage V RMP to a value higher than during the auto-zero period. Thus, the input transistor 312 is cut off, and the clamp voltage is output as the comparison result Vout.

[0145] Then, during the period from timing T2 to T4, the DAC 230 decreases the reference voltage V RMP over time. This period corresponds to the reset level AD conversion period. It is assumed that the difference between the reference voltage V RMP and the input voltage V VSL becomes smaller than the threshold voltage Vt of the input transistor 312 at timing T3 within this period. At this time, the input transistor 312 transitions to the on state, and the comparison result Vout is inverted to the reset level.

[0146] Further, during the period from timing T5 to timing T6, the DAC 230 sets the reference voltage V RMP to a value higher than during the auto-zero period. Thus, the input transistor 312 is cut off, and the clamp voltage is output as the comparison result Vout. The clamp voltage at this time is lower than the clamp voltage corresponding to the reset level.

[0147] Then, in the period from timing T6 to T8, the DAC 230 decreases the reference voltage V RMP over time. This period corresponds to a signal level AD conversion period. It is assumed that the difference between the reference voltage V RMP and the input voltage V VSL becomes smaller than the threshold voltage Vt at timing T7 in this period. At this time, the comparison result Vout is inverted to a signal level.

[0148] Figure 9 is a graph showing an example of the relationship between the output of the first stage of the comparator in the first embodiment of the present technology (comparison result Vout) and the light intensity. In Figure 9 , the vertical axis indicates the high level and the low level of the comparison result Vout, and the horizontal axis indicates the light intensity.

[0149] When the light intensity is the smallest, the high level of the comparison result Vout (i.e., the voltage of the vertical signal line 259) is the highest 1.8 volts (V). The clamp transistor 316 clamps the low level of the comparison result Vout to 1.2 volts, which is 0.6 volts (V) lower than the voltage of the vertical signal line 259.

[0150] Then, as the light intensity increases, the high level (the voltage of the vertical signal line 259) and the low level (the clamp voltage) of the comparison result Vout decrease. However, since the transistor in the current source 314 operates in the saturation region, the clamp transistor 317 limits the low level to 0.4 volts (V) or more. The light intensity at which the clamp transistor 317 operates is referred to as the "saturation light intensity". The high level corresponding to the saturation light intensity is 1.0 volts (V).

[0151] As shown in Figure 9 , the amplitude of the comparison result Vout is constant in the region up to the saturation light intensity at which only the clamp transistor 316 operates. Figure 9 The dotted line in indicates the trajectory when the comparison result Vout is inverted. Since the amplitude of the comparison result Vout is constant, linearity is ensured.

[0152] On the other hand, in the region where the light intensity is equal to or greater than the saturation light intensity and the clamp transistor 317 operates, the amplitude of the comparison result Vout decreases as the light intensity increases. As the amplitude of the comparison result Vout decreases, the linearity decreases.

[0153] When the linearity decreases, the image quality of the image data decreases, and therefore, the voltage range for AD conversion up to the saturation light intensity in which the linearity is ensured and the high level of Vout decreases from 1.8 volts (V) to 1.0 volts (V). The difference between the minimum value and the maximum value in the voltage range corresponds to the dynamic range.

[0154] Figure 10 is a diagram showing the digital signal Dout and the input voltage V in the first embodiment of the present technology. VSL A graph showing an example of the relationship between . Figure 10 The vertical axis in represents the digital signal Dout output from the ADC. The unit of the digital signal Dout is, for example, LSB (least significant bit). Figure 10 The horizontal axis represents the input voltage V VSL , and for example, the unit is millivolt (mV).

[0155] In the voltage range from 0 to 800 millivolts (mV), the clamp transistor 316 fixes the low level of the comparison result Vout to correspond to the input voltage V VSL The clamping voltage of the comparator 300 is used to make the amplitude of the output of the comparator 300 constant. Therefore, the output of the ADC (digital signal Dout) can be compared with the input (input voltage V VSL ) changes in proportion to the value of . Within this range, the slope of the digital signal Dout is constant.

[0156] On the other hand, the slope of the digital signal Dout changes by 800 millivolts (mV) in which the clamp transistor 317 and the clamp transistor 316 operate. As described above, linearity is maintained within a voltage range up to 800 millivolts (mV) in which only the clamp transistor 316 operates. Therefore, AD conversion is performed within this range, and the ratio between the maximum value and the minimum value of the range is 1 / 4 of the input voltage V VSL dynamic range.

[0157] Figure 11 1 is a flowchart showing an example of the operation of the solid-state imaging element 200 according to the first embodiment of the present technology. For example, when a predetermined application for capturing image data is executed, this operation is started.

[0158] The vertical scanning circuit 210 selects and exposes the row to be read (step S901). The auto-zero switch 313 performs auto-zero adjustment based on the control signal AZSW (step S902). The column signal processor 260 performs A / D conversion on the reset level of each column (step 903) and on the signal level (step 904). The vertical scanning circuit 210 then determines whether the row to be read is the last row (step S905).

[0159] If the read row is not the last row (step S905: No), the solid-state imaging element 200 repeats step S901 and subsequent steps. On the other hand, if the read row is the last row (step S905: Yes), the solid-state imaging element 200 ends the operation for imaging.

[0160] Note that Figure 8 The operation of the timing chart shown in FIG. 8 corresponds to Figure 11 steps S902 to S904 in FIG. 7.

[0161] When a plurality of image data are successively captured, steps S901 to S905 are repeatedly executed in synchronization with the vertical synchronization signal.

[0162] As described above, according to the first embodiment of the present technology, the clamp transistor 316 fixes the low level of the comparison result Vout to the clamping voltage corresponding to the input voltage V VSL , and thus the amplitude of the output of the comparator 300 is made constant. Therefore, the output (digital signal Dout) of the ADC can be changed in proportion to the input (input voltage V VSL ). In other words, the linearity of the ADC can be ensured.

[0163] [First Modification]

[0164] The first embodiment has described the configuration in which the low level of the comparison result Vout is fixed to the clamping voltage corresponding to the input voltage V VSL by adding the clamp transistor 316. However, in this configuration, the dynamic range can be insufficient. The first modification of the first embodiment is different from the first embodiment in that a voltage dividing circuit is provided in the clamp voltage controller 330 to expand the dynamic range.

[0165] Figure 12 is a circuit diagram showing a configuration example of the comparator 300 of the first modification of the first embodiment of the present technology. The comparator 300 is different from the comparator of the first embodiment in that the capacitor 332 is added in the clamp voltage controller 330.

[0166] The capacitors 331 and 332 are connected in series between the vertical signal line 259 and the reference potential, and the connection node therebetween is connected to the gate of the clamp transistor 316. With this configuration, the voltage between the input voltage V VSL of the vertical signal line 259 and the reference potential is divided and supplied to the gate of the clamp transistor 316.

[0167] Note that, although the voltage is divided by the capacitors 331 and 332, the configuration of the voltage dividing circuit is not limited thereto. For example, as shown in Figure 13 , the capacitors 331 and 332 can also be replaced with resistors 333 and 334. Further, an nMOS transistor having a gate to which a fixed potential is applied can be further connected in parallel with the clamp transistor 316. Note that the clamp transistor 316 is an example of the first clamp transistor set forth in the claims. The added nMOS transistor is an example of the second clamp transistor set forth in the claims.

[0168] Figure 14 is a graph showing an example of a relationship between the output (comparison result Vout) of the comparator 300 of the first modification example of the first embodiment of the present technology and the light intensity. In Figure 14 , the vertical axis indicates the high level and the low level of the comparison result Vout, and the horizontal axis indicates the light intensity. In addition, the broken line indicates the change in the low level of the first embodiment in which no voltage division is performed.

[0169] As Figure 14 indicated, the inclination of the low level when voltage division is performed is smaller than when no voltage division is performed. As a result, the value of the high level corresponding to the saturated light intensity at which the clamp transistor 317 operates is lower than in the case where no voltage division is performed.

[0170] For example, the high level value corresponding to the saturated light intensity is 1.0 volt (V) in the case where no voltage division is performed, whereas the high level value corresponding to the saturated light intensity is 0.8 volt (V) in the case where voltage division is performed. Thus, in the case where voltage division is performed, the voltage range in which linearity is maintained can be expanded compared to the case where no voltage division is performed. Due to the expansion of the voltage range, the dynamic range can be widened.

[0171] Here, an example of setting the capacitance values of the capacitors 331 and 332 will be described. The following equation is obtained from the operating point in the initial state.

[0172] Q1 init = (V VSL_init -VG init ) x C1... Equation 1

[0173] Q2 init = (VG init ) x C2... Equation 2

[0174] Q1 init in Equation 1 indicates the amount of charge in the capacitor 331 at the time of initialization. V VSL_init indicates the initial value of the voltage (input voltage V VSL ) of the vertical signal line 259. VG init indicates the initial value of the gate voltage of the clamp transistor 316. C1 indicates the capacitance value of the capacitor 331. Methods for setting various initial values will be described later. Furthermore, Q2 init in Equation 2 indicates the amount of charge in the capacitor 332 at the time of initialization, and C2 indicates the capacitance value of the capacitor 332.

[0175] Furthermore, the following equation is obtained from the operating point at the time of saturation.

[0176] Q1 sat = (V VSL_sat -VG sat)×C1 ... Formula 3

[0177] Q2 sat =(VG sat )×C2 ... Formula 4

[0178] Q1 in Equation 3 sat Indicates the amount of charge in capacitor 331 when saturated. V VSL_sat VG represents the voltage of the vertical signal line 259 when saturated. sat Indicates the gate voltage at saturation. In addition, Q2 in Equation 4 sat Indicates the amount of charge in capacitor 332 when saturated.

[0179] Furthermore, since the change in the amount of charge during initialization is the same as the change in the amount of charge during saturation, the following equation is established.

[0180] Q1 init -Q1 sat =Q2 init -Q2 sat ... Equation 5

[0181] When Equations 1 to 4 are substituted into Equation 5 and transformed, the following equation is obtained.

[0182] (V VSL_init -V VSL_sat ) / (VG init -VG sat )= C2 / C1 ... Formula 6

[0183] Given V VSL_init is 1.8 volts (V), V VSL_sat 0.8 volts (V), VG init is 1.4 volts (V), and VG sat =0.6V, C2 is 1 / 4 of C1 according to Formula 6. Therefore, when C1 is, for example, 10 femtofarads (fF), C2 is 2.5 femtofarads (fF).

[0184] As described above, according to the first modification of the first embodiment of the present technology, the clamp voltage controller 330 divides the input voltage V and the reference potential, thereby widening the voltage range in which linearity is maintained compared to a case where voltage division is not performed. With this configuration, the dynamic range can be expanded compared to a case where voltage division is not performed.

[0185] [Second Modification]

[0186] In the first modification of the first embodiment, the gate voltage of the clamp transistor 316 is controlled by a voltage divider circuit. VSLThe initial value of the gate voltage is set as a reference. The solid-state imaging device 200 according to the second modification example of the first embodiment differs from the solid-state imaging device 200 of the first modification example of the first embodiment in that the input voltage V VSL Sampling is performed and initialization is performed based on the sampling voltage.

[0187] Figure 15 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the second modification example of the first embodiment of the present technology. The solid-state imaging device 200 according to the second modification example of the first embodiment differs from the solid-state imaging device 200 of the first modification example of the first embodiment in that an initialization circuit 280 is further included. Details of the initialization circuit 280 will be described later.

[0188] Figure 16 is a circuit diagram showing a configuration example of the pixel array unit 240 in the second modification example of the first embodiment of the present technology. The pixel array unit 240 according to the second modification example of the first embodiment differs from the first modification example of the first embodiment in that a horizontal connection switch 241 is further provided per column.

[0189] When the number of columns is N, N horizontal connection switches 241 are provided. In addition, an nth (n is an integer from 1 to N) vertical signal line 259 is defined as a vertical signal line 259-n.

[0190] The horizontal connection switch 241 in the first column opens and closes a path between the vertical signal line 259-1 and the initialization circuit 280 according to an enable signal EN from the timing controller 220. The horizontal connection switch 241 in the nth column from the second column opens and closes a path between the vertical signal line 259-(n-1) and the vertical signal line 259-n according to the enable signal EN. Through these horizontal connection switches 241, the N vertical signal lines 259 are horizontally connected in the row direction during the auto-zero time period. These horizontal connection switches 241 are provided in the light-receiving chip 201 or the circuit chip 202 (for example, the circuit chip 202).

[0191] Figure 17 is a circuit diagram showing a configuration example of the comparator 300 in the second modification example of the first embodiment of the present technology. The comparator 300 according to the second modification example of the first embodiment differs from the comparator of the first modification example of the first embodiment in that an initialization switch 335 is further included.

[0192] The initialization switch 335 opens and closes a path between the gate of the clamp transistor 316 and the initialization circuit 280 according to a control signal CLP_SH from the timing controller 220. VG init is supplied from the initialization circuit 280 as an initial value of the gate voltage.

[0193] Figure 18 is a circuit diagram showing a configuration example of the initialization circuit 280 in the second modification of the first embodiment of the present technology. Figure 18 of a is a circuit diagram showing a configuration example of the initialization circuit 280, and Figure 18 of b is a graph for describing a method for setting an initial value of the gate voltage.

[0194] As Figure 18 shown, the initialization circuit 280 includes sampling switches 281 and 282, holding capacitors 283 and 289, a variable resistor 284, a current source 285, and a replication circuit 286.

[0195] The sampling switch 282 opens and closes a path between the lateral connection switch 241 and one end of the holding capacitor 283 in accordance with a control signal CLP_SH from the timing controller 220. The other end of the holding capacitor 283 is grounded. The sampling switch 281 opens and closes a path between one end of the holding capacitor 283 and one end of the variable resistor 284 in accordance with the control signal CLP_SH. The other end of the variable resistor 284 is connected to one end of the current source 285. The other end of the current source 285 is grounded.

[0196] Further, the replication circuit 286 includes a current source 287 and an nMOS transistor 288. The current source 287 and the nMOS transistor 288 are connected in series between a power supply voltage and a connection node of the variable resistor 284 and the current source 285. Further, the gate and the drain of the nMOS transistor 288 are short-circuited. The voltage at the connection node of the current source 287 and the nMOS transistor 288 is supplied as the gate voltage VG init to each column of the comparators 300.

[0197] In addition, the current of the current source 287 in the replication circuit 286 is set to M times the current of the current source 314 per column. Further, for each column, the gate width of the nMOS transistor 288 is set to M times the gate width of the clamp transistor 316. Here, M can be a number different from N.

[0198] During the auto-zero time period, the timing controller 220 closes the lateral connection switch 241 by the enable signal EN and closes the sampling switches 281 and 282 by the control signal CLP_SH. As a result, the vertical signal lines 259-1 to 259-N are connected laterally, and the average of their voltages is sampled as V AVG . The sampled average voltage V AVG is held in the holding capacitor 283. The sampling voltage V AVGThe potential of the gate electrode VG drops through the variable resistor 284, and the amount of drop is defined as Voff. In addition, when the drain-source voltage of the nMOS transistor 288 is Vds, the gate voltage VG init It is expressed by the following formula.

[0199] VG init =V AVG -Voff+Vds

[0200] Since the voltage of vertical signal line 259 is maximum during auto-zero, the gate voltage can be initialized to a value corresponding to the maximum value by sampling during auto-zero. In addition, Voff in the above equation is set to the desired amplitude of comparison result Vout. The resistance value of variable resistor 284 is determined according to the desired amplitude value.

[0201] like Figure 18 As shown in b, the voltage V AVG The difference between the amplitude Voff corresponds to the clamping voltage V CLP .like Figure 18 As shown, the initialization circuit 280 samples and holds the average value of the voltage of the vertical signal line 259, and initializes the gate voltage based on the held voltage. Using this gate voltage, the clamp voltage V CLP It is controlled to an appropriate value corresponding to the average value of the voltage of the vertical signal line 259. Note that the initialization circuit 280 can also sample and hold a signal of any of the OPB pixel, dummy non-OPB pixel, and dummy OPB pixel to be described later.

[0202] Figure 19 : is a timing chart showing an example of the operation of the solid-state imaging element 200 according to the second modification example of the first embodiment of the present technology.

[0203] During the auto-zero period from timing T0 to T1, the timing controller 220 sets the control signal AZSW to a low level and closes the auto-zero switch 313. In addition, the timing controller 220 sets the control signal CLP_SH to a high level to sample the voltage of the vertical signal line 259, and sets the enable signal EN to a high level to close the horizontal connection switch 241. During the period from timing T1 to the next auto-zero period, the control signal AZSW is controlled to a high level, and the control signal CLP_SH and the enable signal EN are controlled to a low level.

[0204] As described above, in the second modified example of the first embodiment of the present technology, the initialization circuit 280 samples the average value of the voltage of the vertical signal line 259, holds the sampled voltage, and initializes the gate voltage based on the held voltage. This gate voltage is used to control the clamp voltage to an appropriate value corresponding to the average value of the voltage of the vertical signal line 259.

[0205] [Third Modification]

[0206] In the first modified example of the first embodiment, the clamping voltage controller 330 is configured to control the input voltage V VSL Voltage division is performed between the reference potential and the reference potential. However, when voltage division is performed, the conversion gain of the ADC decreases compared to when voltage division is not performed. The solid-state imaging element 200 according to the third modification of the first embodiment differs from the solid-state imaging element 200 according to the first modification of the first embodiment in that the conversion gain is corrected using a digital circuit.

[0207] Figure 20 This is a circuit diagram showing a configuration example of a comparator 300 in a third modification of the first embodiment of the present technology. The comparator 300 according to the third modification of the first embodiment differs from the first modification of the first embodiment in that a capacitor connection switch 336 is further included in the clamp voltage controller 330.

[0208] The capacitor connection switch 336 is connected to the capacitor according to the control signal SW from the timing controller 220. C2 A path between one end of the open / close capacitor 332 and the gate of the clamp transistor 316 is provided.

[0209] In the third modification of the first embodiment, a calibration period for correcting the conversion gain of the ADC is provided before imaging starts. The calibration period includes a voltage division period and a non-voltage division period.

[0210] The timing controller 220 controls the voltage division period of the calibration period by controlling the signal SW C2 The capacitor connection switch 336 is controlled to be closed, and is controlled to be open during the non-voltage division period. After the calibration period has passed, the capacitor connection switch 336 is controlled to be closed.

[0211] Figure 21 This is a circuit diagram showing an example configuration of a pixel array section 240 in a third modification of the first embodiment of the present technology. In the pixel array section 240 according to the third modification of the first embodiment, a test voltage supply unit 290 is provided for each column. The test voltage supply unit 290 includes an nMOS transistor 291.

[0212] The nMOS transistor 291 is inserted between the vertical signal line 259 of the corresponding column and the power voltage. A control signal TEST from the timing controller 220 is input to the gate of the nMOS transistor 291. The nMOS transistor 291 supplies a test voltage V test The nMOS transistor 291 is provided in the light-receiving chip 201 or the circuit chip 202 (for example, the circuit chip 202).

[0213] Figure 22 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the third modification of the first embodiment of the present technology. The solid-state imaging device 200 according to the third modification of the first embodiment differs from the solid-state imaging device 200 of the first modification of the first embodiment in further including an image processor 340.

[0214] Figure 23 is a block diagram showing a configuration example of the image processor 340 in the third modification of the first embodiment of the present technology. The image processor 340 includes a correction coefficient calculation unit 341, a selector 342, a memory 343, and a correction unit 344.

[0215] The selector 342 switches the output destination of the digital signal Dout from the column signal processor 260 according to a mode signal MODE from the timing controller 220. The mode signal MODE is a signal indicating one of a plurality of modes including a calibration mode and an imaging mode. The calibration mode is set within a calibration period, and the imaging mode is set within an imaging period.

[0216] The selector 342 supplies the digital signal Dout to the correction coefficient calculation unit 341 in the calibration mode, and supplies the digital signal Dout to the correction unit 344 in the imaging mode.

[0217] The correction coefficient calculation unit 341 calculates a correction coefficient for correcting the conversion gain of the ADC using the digital signal Dout. The method for calculating the correction coefficient will be described later. The correction coefficient calculation unit 341 causes the memory 343 to hold the calculated correction coefficient.

[0218] The correction unit 344 reads the correction coefficient from the memory 343 and corrects the digital signal Dout with the correction coefficient. The correction unit 344 supplies the corrected digital signal Dout to the DSP circuit 120.

[0219] Figure 24 is a graph showing an example of the relationship between the digital signal Dout and the input voltage V VSL in the third modification of the first embodiment of the present technology. In the graph, the horizontal axis represents the input voltage V Figure 24In this case, the vertical axis represents the digital signal Dout, and the horizontal axis represents the input voltage V VSL In addition, the dashed line represents the input-output characteristic of the first embodiment in which the voltage division is not performed.

[0220] The slope of the digital signal Dout (in other words, the conversion gain) is smaller when the voltage division is performed than when the voltage division is not performed. In view of this, the correction coefficient calculation unit 341 sets the conversion gain in the case where the voltage division is not performed as a target value, and corrects the conversion gain in the case where the voltage division is performed to the target value in the calibration mode.

[0221] During a non-voltage division period in which the voltage division is not performed during the calibration, the test voltage supply unit 290 in each column sequentially supplies the black level V0 and the white level V1 as the test voltage. The digital signal corresponding to the black level V0 in this case is set to Y1', and the digital signal corresponding to the white level V1 in this case is set to Y1.

[0222] Further, during a voltage division period in which the voltage division is performed, the test voltage supply unit 290 of each column sequentially supplies the black level V0 and the white level V1 as the test voltage. The digital signal corresponding to the black level V0 in this case is set to Y2', and the digital signal corresponding to the white level V1 in this case is set to Y2.

[0223] The correction coefficient calculation unit 341 calculates the correction coefficient k of each column from the digital signals Y1, Y2, Y1', and Y2' of each column by using, for example, the following equation.

[0224] k = (Y1 - Y1') / (Y2 - Y2')... Equation 7

[0225] In the imaging mode, the correction unit 344 multiplies the digital signal Dout by the corresponding correction coefficient k for each column. As a result, the conversion gain is corrected to a value equal to that in the case where the voltage division is not performed. Due to the correction of the conversion gain, the sensitivity of the solid-state imaging device 200 can be improved compared to before the correction of the conversion gain.

[0226] Note that although all of the digital signals Y1, Y2, Y1', and Y2' are used, the configuration is not limited to this. The digital signals Y1' and Y2' corresponding to the black level V0 have substantially the same value, and thus a configuration in which these values are not obtained can also be adopted. In this case, the correction coefficient k is calculated only from the digital signals Y1 and Y2.

[0227] In addition, although the correction coefficient k is calculated for each column, the configuration is not limited thereto. For example, the correction coefficient calculation unit 341 can calculate the statistical values (such as the sum, average, or the like) of the digital signals Y1, Y2, Y1', and Y2' of all columns and calculate the same correction coefficient in all columns from the statistical values. For example, when the average of the digital signals Y1, Y2, Y1', and Y2' is Y1 AVG , Y2 AVG , Y1 AVG ', and Y2 AVG ', the correction coefficient k' is calculated by the following formula instead of Formula 7.

[0228] k' = (Y1 AVG - Y1 AVG ') / (Y2 AVG - Y2 AVG ')

[0229] In addition, the second modification example for performing initialization can also be applied to the third modification example of the first embodiment.

[0230] As described above, according to the third modification example of the first embodiment of the present technology, the image processor 340 corrects the conversion gain of the ADC, whereby it is possible to improve the sensitivity of the solid-state imaging element 200.

[0231] [Fourth Modification Example]

[0232] In the first modification example of the above-described first embodiment, the clamp voltage controller 330 performs voltage division between the input voltage V VSL and the reference potential. However, in the case where the voltage is divided, the conversion gain of the ADC decreases compared to the case where the voltage is not divided. The solid-state imaging element 200 according to the fourth modification example of the first embodiment is different from the first modification example of the first embodiment in that the conversion gain is corrected by an analog circuit.

[0233] Figure 25 is a circuit diagram illustrating a configuration example of the DAC 230 in the fourth modification example of the first embodiment of the present technology. The DAC 230 according to the fourth modification example of the first embodiment includes a variable current source 231, a current converter 232, and a resistor 235. The current converter 232 includes a plurality of current sources 233 and a plurality of switches 234. The switches 234 are provided for each of the current sources 233.

[0234] The current sources 233 are connected in parallel to a power supply voltage. The switches 234 open and close the path between the corresponding current sources 233 and one end of the resistor 235 according to the digital signal from the timing controller 220. The other end of the resistor 235 is grounded. The voltage at the connection node between the resistor 235 and the current converter 232 serves as the reference voltage V RMPis supplied to the comparator 300.

[0235] Further, the solid-state imaging device 200 according to the fourth modification of the first embodiment differs from the solid-state imaging device 200 according to the first modification of the first embodiment in further including the current controller 295.

[0236] The current of the variable current source 231 is copied to each of the plurality of current sources 233 by the current mirror circuit. Further, the digital signal is converted into an analog current signal by the current converter 232. The current signal is converted into the reference voltage V RMP .

[0237] The current controller 295 controls the reference voltage V RMP In the calibration mode, the current controller 295 obtains k from Equation 7 and holds the obtained k. However, it should be noted that, in the fourth modification of the first embodiment, k is not used for correcting the digital signal. The more the current controller 295 makes k large, the smaller the amount of current of the variable current source 231. Therefore, the reference voltage V RMP decreases, and the conversion gain of the ADC increases. Thus, the conversion gain is corrected by the analog circuit. Note that, instead of the current controller 295, a control circuit that controls the slope and the offset voltage of the reference voltage based on the correction coefficient k can be provided. The control circuit and the current controller 295 are examples of the controller set forth in the claims.

[0238] Figure 26 is a circuit diagram showing an example of a waveform of the reference signal in the fourth modification of the first embodiment of the present technology. Figure 26 The solid line in FIG. 28 indicates the waveform of the reference signal before correction, and the dotted line indicates the waveform of the reference signal after correction. As shown in FIG. 28, the current controller 295 decreases the voltage of the reference signal as k increases. Therefore, the time until the output of the comparator 300 is inverted increases, and the conversion gain increases. That is, the current controller 295 corrects the conversion gain. This makes it possible to improve the sensitivity of the solid-state imaging device 200. Figure 26

[0239] In addition, the second modification for performing initialization can also be applied to the fourth modification of the first embodiment.

[0240] As described above, according to the fourth modification of the first embodiment of the present technology, the current controller 295 corrects the conversion gain of the ADC, whereby it is possible to improve the sensitivity of the solid-state imaging device 200.

[0241] <2. Second Embodiment>

[0242] ​In the above-described first embodiment, the timing controller 220 controls the auto-zero switch 313 from the on state to the off state by the control signal AZSW. However, in this configuration, when the auto-zero switch 313 is switched from the on state to the off state, the drain voltage of the input transistor 312 can fluctuate due to the reset feedthrough. Thus, noise such as fixed pattern noise can occur, and the image quality of the image data can be degraded. The solid-state imaging device 200 according to the second embodiment differs from the solid-state imaging device of the first embodiment in that the reset feedthrough is suppressed by providing the control signal AZSW corresponding to the voltage of the vertical signal line 259.

[0243] Figure 27 is a circuit diagram showing a configuration example of the timing controller 220 in the second embodiment of the present technology. The timing controller 220 in the second embodiment includes a control signal generator 221 and a driver 400. The driver 400 includes a sampling switch 410, a holding capacitor 420, a level shifter 430, and a selector 440.

[0244] Further, as in the second modification example of the first embodiment, the solid-state imaging device 200 according to the second embodiment provides the lateral connection switch 241 per vertical signal line.

[0245] The control signal generator 221 generates signals such as the enable signal EN, the control signal AZ_SH, and the control signal AZDp. The enable signal EN is supplied to the lateral connection switch 241, and the control signal AZ_SH and the control signal AZDp are supplied to the driver 400.

[0246] The sampling switch 410 opens and closes a path between the lateral connection switch 241 and one end of the holding capacitor 420 according to the control signal AZ_SH. The other end of the holding capacitor 420 is grounded. The level shifter 430 shifts the voltage held in the holding capacitor to a voltage higher than a predetermined voltage V ADD and outputs the addition result to the selector 440.

[0247] The selector 440 selects either the shifted result from the level shifter 430 or the power supply voltage VDD according to the control signal AZDp, and outputs the selected result as the control signal AZSW to the comparator 300.

[0248] As shown in Figure 6 , the control signal AZSW is input to the gate of the auto-zero switch 313 in the comparator 300. Further, the source of the auto-zero switch 313 (pMOS transistor) is connected to the drain of the input transistor 312. Thus, the minimum gate-source voltage required to turn on the auto-zero switch 313 is according to the source voltage of the input transistor 312 (i.e., the input voltage V VSL) and changes.

[0249] In view of this, the driver 400 samples and holds the average value of the input voltage V VSL during the auto-zeroing of the pixels that are reset, and adds a voltage for realizing the minimum gate-source voltage required as V ADD . Then, the driver 400 outputs the addition result as the control signal AZSW to the comparator 300 during the auto-zeroing. Thus, the driver 400 can control the gate-source voltage of the auto-zeroing switch 313 to the minimum value required to turn on the auto-zeroing switch 313. This control can suppress the reset feedthrough when the auto-zeroing switch 313 is switched from the on state to the off state, thereby reducing noise and improving the image quality of the image data.

[0250] Figure 28 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the second embodiment of the present technology.

[0251] During the auto-zeroing period from timing TO to timing T1, the control signal generator 221 provides the enable signal EN at a high level and closes the horizontal connection switch 241 during the pulse period from timing TO to timing T12. After timing T12, the enable signal EN is controlled to a low level.

[0252] Further, in the pulse period from timing TO to timing T11, the control signal generator 221 provides the control signal AZ_SH at a high level to close the sampling switch 410, and holds the average value of the input voltage V VSL . After timing T11, the control signal AZ_SH is controlled to a low level.

[0253] The control signal generator 221 provides the control signal AZDp at a low level during the auto-zeroing period from timing TO to T1, and causes the selector 440 to select the output of the level shifter 430. Further, the driver 400 provides the control signal AZSW at a low level corresponding to the held voltage. After timing T1, the control signal AZDp and the control signal AZSW are controlled to a high level.

[0254] Figure 29 is a circuit diagram showing a configuration example of the driver 400 in the second embodiment of the present technology. Figure 29 shows a specific example of the driver 400 shown in Figure 27 . For example, Figure 29The driver 400 in FIG. 4 includes a sampling switch 410 , a holding capacitor 420 , pMOS transistors 431 to 436 , current sources 437 and 438 , and an nMOS transistor 439 .

[0255] The pMOS transistors 431 and 432 are connected in parallel to the power supply voltage VDD. A current source 437 is inserted between the drain of the pMOS transistor 431 and a predetermined reference potential.

[0256] The sampling switch 410 opens and closes the path between the lateral connection switch 241 and one end of the holding capacitor 420 according to the control signal AZ_SH. The other end of the holding capacitor 420 is grounded.

[0257] The pMOS transistor 433 has a gate connected to one end of the holding capacitor 420 and a source connected to the drain of the pMOS transistor 432. The nMOS transistor 439 is inserted between the drain of the pMOS transistor 433 and a reference potential, with the gate and the drain short-circuited.

[0258] PMOS transistors 434-436 and current source 438 are connected in series between the drain of pMOS transistor 432 and a reference potential. Furthermore, the gates and drains of pMOS transistors 434-436 are short-circuited. The size of pMOS transistor 436 can be adjusted as needed.

[0259] The source of the pMOS transistor 443 is connected to the power supply voltage VDD. The control signal AZDP2 from the control signal generator 221 is input to the gate of the pMOS transistor 443.

[0260] Furthermore, an nMOS transistor 441 and a pMOS transistor 442 are connected in parallel between the connection node of the pMOS transistor 436 and the current source 438, and the drain of the pMOS transistor 443. A control signal AZdp1 from the control signal generator 221 is input to the gate of the nMOS transistor 441. A signal xAZdp1 obtained by inverting the control signal AZdp1 is input to the gate of the pMOS transistor 442.

[0261] With the above connection configuration, the circuit including the pMOS transistors 431 to 436, the current sources 437 and 438, and the nMOS transistor 439 functions as Figure 27 In addition, a circuit including an nMOS transistor 441 and pMOS transistors 442 and 443 is used as a level shifter 430. Figure 27 Selector 440 in .

[0262] It should be noted that although Figure 27 The driver 400 inFigure 29 The circuit shown in FIG. 12 can be implemented by the circuit in the driver 400, but the circuit in the driver 400 is not limited to the circuit shown in FIG. 12 as long as the functions described in FIG. 12 can be implemented. Figure 29 The circuit shown in FIG. 12 can be implemented by the circuit in the driver 400, but the circuit in the driver 400 is not limited to the circuit shown in FIG. 12 as long as the functions described in FIG. 12 can be implemented. Figure 27 The circuit shown in FIG. 12 can be implemented by the circuit in the driver 400, but the circuit in the driver 400 is not limited to the circuit shown in FIG. 12 as long as the functions described in FIG. 12 can be implemented.

[0263] Figure 30 is a timing chart showing an example of the operation of the timing controller in the second embodiment of the present technology. Figure 30 The timing chart in FIG. 13 is used to control the driver 400 shown in FIG. 12. Figure 29 The timing chart in FIG. 13 is used to control the driver 400 shown in FIG. 12.

[0264] The control signal generator 221 supplies the enable signal EN at a high level during the pulse period from timing TO to timing T12. After timing T12, the enable signal EN is controlled to a low level.

[0265] Further, the control signal generator 221 supplies the control signal AZ_SH at a high level during the pulse period from timing TO to timing T11. After timing T11, the control signal AZ_SH is controlled to a low level.

[0266] The control signal generator 221 sets the control signal AZdp1 to a high level during the auto-zero period from timing TO to T1. After timing T1, the control signal AZdp1 is controlled to a low level.

[0267] The control signal generator 221 supplies the control signal AZDP2 at a high level during the auto-zero period from timing TO to timing T1. Further, the driver 400 supplies the control signal AZSW at a low level corresponding to the hold voltage. After timing T1, the control signal AZDP2 is controlled to a low level and the control signal AZSW is controlled to a high level.

[0268] Note that the input voltage V VSL may be sampled by row or by frame. When the number of rows is M (M is an integer), the input voltage V VSL is sampled for each row, the input voltage V VSL is sampled M times for each frame.

[0269] In addition, the first to fourth modified examples of the first embodiment can also be applied to the second embodiment.

[0270] As described above, according to the second embodiment of the present technology, the driver 400 samples the input voltage V VSL , holds the sampled voltage, and supplies the control signal AZSW corresponding to the held voltage, whereby the gate-source voltage of the auto-zero switch 313 can be controlled to a minimum value. This configuration can suppress reset feedthrough, thereby reducing noise and improving the image quality of the image data.

[0271] [First Modification]

[0272] In the above-described second embodiment, the driver 400 samples the pixel signal of the pixel circuit 250. In this case, it is desirable that the value to be sampled has a black level. The solid-state imaging device 200 according to the first modification of the second embodiment is different from the solid-state imaging device 200 of the second embodiment in that the pixel signal of the light-shielded pixel is sampled.

[0273] Figure 31 is a circuit diagram showing a configuration example of the pixel array unit 240 in the first modification of the second embodiment of the present technology. The pixel array unit 240 in the first modification of the second embodiment is different from the pixel array unit of the second embodiment in that a plurality of effective pixels 510 and a plurality of OPB (optical black) pixels 520 are arranged. For example, at least one row of OPB pixels 520 is arranged.

[0274] The effective pixel 510 is a pixel that is not light-shielded, and includes a photoelectric conversion element 511, a transfer transistor 512, a reset transistor 513, a floating diffusion layer 514, an amplification transistor 515, and a selection transistor 516.

[0275] The OPB pixel 520 is a pixel that is light-shielded, and includes a photoelectric conversion element 521, a transfer transistor 522, a reset transistor 523, a floating diffusion layer 524, an amplification transistor 525, and a selection transistor 526. A selection signal OPB_SEL and a reset signal OPB_RST are supplied to the OPB pixel 520.

[0276] The circuit configuration of the effective pixel 510 and the OPB pixel 520 is similar to the circuit configuration of the pixel circuit 250 shown in Figure 4 .

[0277] During the auto-zeroing period, the vertical scanning circuit 210 drives the OPB pixel 520 so that the OPB pixel 520 outputs a pixel signal via the vertical signal line 259. Since the OPB pixel 520 is light-shielded, the pixel signal to be read has a black level. The driver 400 samples and holds the average value of the pixel signal of the black level, and supplies a control signal AZSW of a voltage corresponding to the held voltage.

[0278] Figure 32 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the first modification of the second embodiment of the present technology.

[0279] The vertical scanning circuit 210 supplies the selection signal OPB_SEL and the reset signal OPB_RST to the OPB pixel 520 from time T0 to time T12 to allow the OPB pixel 520 to output a pixel signal of a black level.

[0280] The waveforms of the enable signal EN, the control signal AZ_SH, the control signal AZDp, and the control signal AZSW of the first modification of the second embodiment are similar to those of the second embodiment. The driver 400 samples and holds the average value of the pixel signal of the black level, and provides the control signal AZSW based on the held voltage. Since the OPB pixel 520 is light-shielded, the black level does not change due to incident light, and by sampling the constant level, it is possible to reliably suppress noise.

[0281] In addition, the first to fourth modifications of the first embodiment can be applied to the first modification of the second embodiment.

[0282] As described above, according to the first modification of the second embodiment of the present technology, the driver 400 samples and holds the pixel signal of the black level of the OPB pixel 520, and generates the control signal AZSW based on the held voltage, so that it is possible to reliably suppress noise.

[0283] [Second Modification]

[0284] In the above-described second embodiment, the driver 400 samples the average value of the pixel signal, but in this configuration, the switch 241 needs to be connected laterally by column. The solid-state imaging element 200 according to the second modification of the second embodiment differs from the solid-state imaging element of the second embodiment in that the pixel signal of the dummy pixel is sampled and the lateral connection switch 241 is eliminated.

[0285] Figure 33 is a circuit diagram showing a configuration example of the pixel array unit 240 in the second modification of the second embodiment of the present technology. The pixel array unit 240 in the second modification of the second embodiment differs from the pixel array unit of the second embodiment in that a plurality of effective pixels 510, a plurality of OPB pixels 520, a plurality of dummy non-OPB pixels 530, and a plurality of dummy OPB pixels 540 are arranged. For example, at least one row of OPB pixels 520 is arranged, and at least one column of dummy non-OPB pixels 530 and dummy OPB pixels 540 are arranged.

[0286] Further, the pixel array unit 240 according to the second modification of the second embodiment differs from the pixel array unit of the second embodiment in that the horizontal connection switch 241 is not provided.

[0287] The dummy non-OPB pixel 530 and the dummy OPB pixel 540 are pixels that do not perform AD conversion of the pixel signal (in other words, from which the pixel signal is not read). The ADC is not arranged in the dummy column. The vertical signal line 259 of the dummy column is connected to the timing controller 220. Further, the dummy non-OPB pixel 530 is not light-shielded, and the dummy OPB pixel 540 is light-shielded.

[0288] The pseudo non-OPB pixel 530 includes a photoelectric conversion element 531, a transfer transistor 532, a reset transistor 533, a floating diffusion layer 534, an amplification transistor 535, and a selection transistor 536. A selection signal DUMn_SEL and a reset signal DUMn_RST are supplied to the pseudo non-OPB pixel 530.

[0289] The pseudo OPB pixel 540 includes a photoelectric conversion element 541, a transfer transistor 542, a reset transistor 543, a floating diffusion layer 544, an amplification transistor 545, and a selection transistor 546. A selection signal DUMo_SEL and a reset signal DUMo_RST are supplied to the pseudo OPB pixel 540.

[0290] The circuit configuration of the pseudo non-OPB pixel 530 and the pseudo OPB pixel 540 is similar to that of the pixel circuit 250 shown in the first embodiment. Figure 4

[0291] During the auto-zeroing period, the vertical scanning circuit 210 drives the pseudo non-OPB pixel 530 so that the pseudo non-OPB pixel 530 outputs a pixel signal via the vertical signal line 259. The driver 400 samples the pixel signal and supplies a control signal AZ_SW based on the voltage thereof. As shown in FIG. 8, it is not necessary to obtain the average of the pixel signals of all the columns by sampling the pixel signals of the pseudo column, and thus it is not necessary to provide the horizontal connection switch 241. Figure 33

[0292] Figure 34 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the second modification of the second embodiment of the present technology.

[0293] The vertical scanning circuit 210 supplies the selection signal OPBn_SEL and the reset signal OPBn_RST to the pseudo non-OPB pixel 530 during the period from time TO to time T12 to allow the pseudo non-OPB pixel 530 to output a pixel signal.

[0294] The waveforms of the enable signal EN, the control signal AZ_SH, the control signal AZDp, and the control signal AZ_SW in the second modification of the second embodiment are similar to those in the second embodiment. The driver 400 samples the pixel signals of the pseudo column and supplies the control signal AZ_SW based on the voltage thereof.

[0295] Figure 35 is a circuit diagram showing a configuration example of the timing controller 220 in the second modification of the second embodiment of the present technology. The timing controller 220 in the second modification of the second embodiment differs from the timing controller in the second embodiment in that the sampling switch 410 and the holding capacitor 420 are not provided in the driver 400.​​

[0296] The level shifter 430 in the driver 400 samples the V ADD The pixel signal added to the dummy column is provided to the selector 440.

[0297] Note that the driver 400 in the second modification of the second embodiment can be provided with the sampling switch 410 and the holding capacitor 420.

[0298] In addition, the first to fourth modifications of the first embodiment can be applied to the second modification of the second embodiment, respectively.

[0299] As described above, according to the second modification of the second embodiment of the present technology, the driver 400 samples the pixel signal of the dummy column so that it is not necessary to obtain the average of the pixel signals of all columns. Thereby, the lateral connection switch 241 can be eliminated.

[0300] [Third Modification]

[0301] In the above-described second modification of the second embodiment, the driver 400 samples the pixel signal of the dummy non-OPB pixel 530 which is not shaded, but it is desirable that the sampled value has a black level. The solid-state imaging element 200 according to the third modification of the second embodiment differs from the solid-state imaging element 200 of the second modification of the second embodiment in that the pixel signal of the dummy OPB pixel 540 which is shaded is sampled.

[0302] Figure 36 is a timing chart showing an example of the operation of the solid-state imaging element 200 according to the third modification of the second embodiment of the present technology.

[0303] The vertical scanning circuit 210 provides the selection signal OPBo SEL and the reset signal OPBo_RST to the dummy OPB pixel 540 during the period from the time T0 to the time T12 to allow the dummy OPB pixel 540 to output the pixel signal of the black level.

[0304] The waveforms of the enable signal EN, the control signal AZ_SH, the control signal AZDp, and the control signal AZSW of the third modification of the second embodiment are similar to those of the second embodiment. The driver 400 samples the pixel signal of the black level of the dummy OPB pixel 540 and provides the control signal AZSW based on the voltage thereof.

[0305] In addition, the first to fourth modifications of the first embodiment can be applied to the third modification of the second embodiment.

[0306] As described above, according to the third modification of the second embodiment of the present technology, the driver 400 samples the pixel signal of the black level of the dummy OPB pixel 540 and generates the control signal AZSW based on the voltage thereof, so that it is possible to reliably suppress noise.

[0307] [Fourth Modification]

[0308] In the above-described second embodiment, the comparator 300 connected directly to the source of the input transistor 312 of the vertical signal line 259 is used for the ADC, but it is also possible to use a comparator 300 having another configuration. The solid-state imaging device 200 according to the fourth modification of the second embodiment differs from the solid-state imaging device 200 of the second embodiment in that the comparator 300 connected to the source of the input transistor 312 using an nMOS transistor is used.

[0309] Figure 37 is a circuit diagram showing a configuration example of the pixel array unit 240 and the timing controller 220 in the fourth modification of the second embodiment of the present technology. The solid-state imaging device 200 according to the fourth modification of the second embodiment differs from the solid-state imaging device of the second embodiment in that the load current source 242 is connected to each vertical signal line 259.

[0310] The operation of the driver 400 in the fourth modification of the second embodiment is similar to that of the second embodiment.

[0311] Figure 38 is a circuit diagram showing a configuration example of the comparator 300 in the fourth modification of the second embodiment of the present technology. The comparator 300 according to the fourth modification of the second embodiment includes a VSL switch 351, an input capacitor 352, an auto-zero switch 353, and an nMOS transistor 354. Further, the comparator 300 further includes an input amplifier 355, an input capacitor 311, an input transistor 312, an auto-zero switch 313, a current source 314, and an output amplifier 356.

[0312] The VSL switch 351 opens and closes a path between the vertical signal line 259 and one end of the input capacitor 352 according to a control signal VSL_SW from the timing controller 220. The other end of the input capacitor 352 is connected to the gate of the nMOS transistor 354.

[0313] The auto-zero switch 353 shorts the gate and the drain of the nMOS transistor 354 according to a control signal AZSW. The nMOS transistor 354 is inserted between the power supply voltage and the source of the input transistor 312 (pMOS transistor). Note that the nMOS transistor 354 is an example of the second comparison element set forth in the claims.

[0314] The input amplifier 355 amplifies the reference signal and supplies the amplified reference signal to one end of the input capacitor 311. The connection configuration of the input capacitor 311, input transistor 312, auto-zero switch 313, and current source 314 is similar to that of the first embodiment.

[0315] The output amplifier 356 amplifies the voltage of the connection node between the input transistor 312 and the current source 314 and outputs the amplified voltage as the output signal VCO.

[0316] like Figure 38 As shown, since the source of the input transistor 312 is connected to the vertical signal line 259 via the nMOS transistor 354, the source voltage can be lowered compared to the case where the source is directly connected to the vertical signal line 259. The voltage of the reference signal can be reduced in accordance with the reduction of the power supply voltage.

[0317] In addition, the first, second, and third modified examples of the second embodiment can be applied to the fourth modified example of the second embodiment.

[0318] As described above, according to the fourth modification of the second embodiment of the present technology, the source of the input transistor 312 is connected to the vertical signal line 259 via the nMOS transistor 354, thereby reducing the source voltage. As a result, the voltage of the reference signal can be reduced.

[0319] [Fifth Modification]

[0320] In the second embodiment described above, the driver 400 drives the auto-zero switch 313 in the comparator 300, but may also drive the auto-zero switch 313 in the column amplifier. The solid-state imaging element 200 according to the fifth modification of the second embodiment differs from the solid-state imaging element of the second embodiment in that the driver 400 drives the auto-zero switch 313 in the column amplifier.

[0321] Figure 39 This is a block diagram illustrating a configuration example of a solid-state imaging element 200 according to a fifth modification of the second embodiment of the present technology. The solid-state imaging element 200 according to the fifth modification of the second embodiment differs from the solid-state imaging element of the second embodiment in that a constant current source unit 600 is provided between the pixel array section 240 and the column signal processor 260. The constant current source unit 600 is provided in, for example, the circuit chip 202.

[0322] Figure 40 : is a circuit diagram showing a configuration example of the pixel array section 240 , the constant current source unit 600 , and the timing controller 220 in the fifth modification example of the second embodiment of the present technology.

[0323] The constant current source unit 600 is provided with the column amplifier 610 per column. The column amplifier 610 amplifies the voltage of the vertical signal line 259 and supplies the amplified voltage to the comparator 300 in the ADC. Further, the timing controller 220 in the fifth modification of the second embodiment supplies the control signal AZSW to the column amplifier 610. The operation of the driver 400 in the timing controller 220 in the fifth modification of the second embodiment is similar to that of the second embodiment. As a result, the reset feedthrough in the column amplifier 610 can be suppressed.

[0324] Figure 41 FIG. 19 is a circuit diagram illustrating a configuration example of the column amplifier 610 in the fifth modification of the second embodiment of the present technology. The column amplifier 610 includes the current-multiplying column amplifier 620 and the boost circuit 650. The current-multiplying column amplifier 620 includes the input stage 621 and the folding stage 640.

[0325] The input stage 621 includes the input transistor 622, the input-side auto-zero switch 624, the feedback capacitor 625, the reference-side capacitor 626, and the reference-side current source transistor 627. Further, for example, a pMOS transistor is used as the input transistor 622. For example, an nMOS transistor is used as the reference-side current source transistor 627.

[0326] The source of the input transistor 622 is connected to the vertical signal line 259-n, and the drain is connected to the drain of the reference-side current source transistor 627. The input-side auto-zero switch 624 cuts off the path between the gate and the drain of the input transistor 622 in accordance with the auto-zero signal AZ.

[0327] The feedback capacitor 625 is inserted between the drain of the input transistor 622 and the gate of the input transistor 622. Further, the reference-side capacitor 626 is inserted between the gate of the input transistor 622 and the reference voltage.

[0328] In addition, the source of the reference-side current source transistor 627 is connected to a predetermined reference voltage. A predetermined bias voltage nbias is applied to the gate of the reference-side current source transistor 627.

[0329] With the above configuration, the gate-source voltage of the input transistor 622 is varied in accordance with the input voltage Vin input to the source of the input transistor 622, and the voltage of the vertical signal line 259 is amplified by the input transistor 622. The amplified voltage is supplied to the comparator 300 in the ADC. VSLAnd the drain current of the input transistor 622 changes. Vout corresponding to the drain current is output from the drain of the input transistor 622. In this way, a voltage corresponding to the gate-source voltage of the input transistor 622 is output from its drain. Furthermore, a part of the constant bias current supplied from the reference-side current source transistor 627 is fed back to the gate of the input transistor 622 by a feedback circuit including the input-side auto-zero switch 624, the feedback capacitor 625, and the reference-side capacitor 626. Due to the feedback circuit, power consumption can be reduced.

[0330] The folding stage 640 includes a cascode capacitor 641, a power supply-side current source transistor 642, cascode transistors 643 and 645, an output-side auto-zero switch 644, an intermediate switch 646, and a reference-side current source transistor 647.

[0331] As the power supply-side current source transistor 642 and the cascode transistor 643, a pMOS transistor is used, and as the cascode transistor 645 and the reference-side current source transistor 647, an nMOS transistor is used.

[0332] The cascode capacitor 641 is inserted between a power node of a predetermined power supply voltage and the output-side auto-zero switch 644.

[0333] The power supply-side current source transistor 642, the cascode transistor 643, the cascode transistor 645, and the reference-side current source transistor 647 are connected in series to a power supply voltage. Furthermore, the gate of the power supply-side current source transistor 642 is connected to a node between the cascode capacitor 641 and the output-side auto-zero switch 644. A bias voltage pcas is applied to the gate of the cascode transistor 643. A predetermined bias voltage ncas is applied to the gate of the cascode transistor 645. The same bias voltage nbias as that of the reference-side current source transistor 627 is applied to the gate of the reference-side current source transistor 647.

[0334] The output-side auto-zero switch 644 opens and closes a path between the cascode capacitor 641 and the output node 628 in accordance with an auto-zero signal AZ. The intermediate switch 646 opens and closes a path between a node between the input transistor 622 and the reference-side current source transistor 627 and a node between the cascode transistor 645 and the reference-side current source transistor 647 in accordance with a feedback signal xAZ.

[0335] The addition of the folding stage 640 can expand the output range. Furthermore, the input stage 621 and the folding stage 640 can be separated by the intermediate switch 646 during auto-zero, and auto-zero can be performed separately.

[0336] The boost circuit 650 is provided with a boost-side capacitor 651, a boost-side current source transistor 652, a cascode transistor 653, and a boost transistor 654. As the boost-side current source transistor 652, the cascode transistor 653, and the boost transistor 654, pMOS transistors are used.

[0337] The boost-side current source transistor 652, the cascode transistor 653, and the boost transistor 654 are inserted in series between the power supply voltage and the reference potential. A predetermined bias voltage pbias is applied to the gate of the boost-side current source transistor 652, and a predetermined bias voltage pcas is applied to the gate of the cascode transistor 653. The gate of the boost transistor 654 is connected to the output node 628.

[0338] Further, the boost-side capacitor 651 is inserted between the vertical signal line 259-n and the node between the cascode transistor 653 and the boost transistor 654.

[0339] The comparison result Vout can be buffered by the source follower of the boost transistor 654 of the boost circuit 650, and coupled to the vertical signal line 259-n through the capacitor. As a result, the current for charging the boost-side capacitor 651 is extracted from the vertical signal line 259-n, and stabilization can be facilitated.

[0340] Note that the folding stage 640 and the boost circuit 650 are provided as needed.

[0341] In addition, the first to fourth modified examples of the first embodiment can be applied to the fifth modified example of the second embodiment, respectively. In addition, the first to third modified examples of the second embodiment can also be applied to the fifth modified example of the second embodiment.

[0342] As described above, according to the fifth modified example of the second embodiment of the present technology, the driver 400 provides the control signal AZSW to the column amplifier 610, whereby the reset feedthrough in the column amplifier 610 can be suppressed.

[0343] <3. Examples of applications for mobile objects>

[0344] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any type of mobile body such as a vehicle, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot.

[0345] Figure 42 is a block diagram that describes an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiments of the present disclosure can be applied.

[0346] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example shown, the vehicle control system 12000 includes a drive system control portion 12010, a body system control portion 12020, an outside information detecting portion 12030, an inside information detecting portion 12040, and an integrated control portion 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output portion 12052, and a vehicle-mounted network interface (I / F) 12053 are exemplified. Figure 42

[0347] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine, a drive motor, or the like, for a drive force transmission mechanism for transmitting a drive force to a wheel, for a steering mechanism for adjusting a steering angle of the vehicle, for a brake device for generating a braking force of the vehicle, and the like.

[0348] The body system control unit 12020 controls the operation of various devices provided on the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, and the like. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, a power window device, a lamp, or the like of the vehicle.

[0349] The outside information detecting unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, an imaging portion 12031 is connected to the outside information detecting unit 12030. The outside information detecting unit 12030 causes the imaging portion 12031 to capture an image outside the vehicle, and receives the captured image. In addition, the outside information detecting unit 12030 can also perform processing of detecting a person, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereof, or the like, based on the received image.

[0350] The imaging portion 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of light received. The imaging portion 12031 can output the electric signal as an image, or can output the electric signal as information on a measured distance. Furthermore, the light received by the imaging portion 12031 can be visible light, or can be non-visible light such as infrared rays.

[0351] ​The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is connected to, for example, a driver state detecting unit 12041 that detects the state of the driver. The driver state detecting unit 12041 includes, for example, a camera that captures the driver. Based on the detection information input from the driver state detecting unit 12041, the in-vehicle information detecting unit 12040 can calculate the degree of fatigue of the driver or the degree of concentration of the driver, or can determine whether the driver is dozing off.

[0352] The microcomputer 12051 can calculate a control target value of the driving force generation device, the steering mechanism, or the braking device based on information about the inside or outside of the vehicle obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing a function of an advanced driver assistance system (ADAS) including collision avoidance or shock mitigation for the vehicle, follow driving based on a following distance, maintenance of the vehicle speed of the vehicle, warning of a vehicle collision, warning of deviation of the vehicle from the lane, and the like.

[0353] In addition, the microcomputer 12051 can perform cooperative control for automatic driving by controlling the driving force generation device, the steering mechanism, the braking device, and the like based on information about the outside or inside information obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, which makes the vehicle automatically travel without depending on the operation of the driver or the like.

[0354] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the outside of the vehicle obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlamp to change from high beam to low beam in accordance with the position of the preceding vehicle or the oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0355] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or aurally notify information to an occupant of the vehicle or outside of the vehicle. In Figure 42 In the example, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. The display unit 12062 can include at least one on-vehicle display and a head-up display, for example.

[0356] Figure 43 is a diagram showing an example of a mounting position of the imaging unit 12031.

[0357] In Figure 43In this case, the imaging sections 12031 include imaging sections 12101, 12102, 12103, 12104, and 12105.

[0358] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100 and at a position on the upper portion of the interior windshield. The imaging section 12101 provided to the front nose portion inside the vehicle interior and the imaging section 12105 provided to the upper portion of the windshield mainly obtain images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side mirrors mainly obtain images of the side of the vehicle 12100. The imaging section 12104 provided to the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield inside the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, and the like.

[0359] Incidentally, Figure 43 Examples of the imaging ranges of the imaging sections 12101 to 12104 are described. The imaging range 12111 indicates the imaging range of the imaging section 12101 provided to the front nose. The imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging sections 12102 and 12103 provided to the side mirrors, respectively. The imaging range 12114 indicates the imaging range of the imaging section 12104 provided to the rear bumper or rear door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104.

[0360] At least one of the imaging sections 12101 to 12104 can have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera constituted by a plurality of imaging elements or can be an imaging element having pixels for phase difference detection.

[0361] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, thereby extracting a three-dimensional object present on the travel path of the vehicle 12100, moving in substantially the same direction as the vehicle 12100 at a prescribed speed (for example, equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), and the like. Thereby, it is possible to perform cooperative control for automatic driving that makes the vehicle automatically travel without depending on the operation of the driver or the like.

[0362] For example, the microcomputer 12051 can classify three-dimensional object data related to a three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a case where the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist the driver to avoid collision.

[0363] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, identify a pedestrian by determining whether a pedestrian is present in an imaging image of the imaging section 12101 to 12104. Such identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaging image of the imaging section 12101 to 12104 as an infrared camera and a process of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the imaging image of the imaging section 12101 to 12104 and thus identifies a pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output section 12052 can also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0364] Examples of a vehicle control system to which the technology according to the present disclosure can be applied have been described above. The technology according to the present disclosure can be applied to, for example, the imaging section 12031 and the like in the configuration described above. Specifically, Figure 1 The imaging device 100 in the configuration described in Embodiment 1 can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, the dynamic range can be widened and noise can be reduced, and thus a captured image that is easier to see can be obtained. Therefore, it is possible to reduce the fatigue of the driver.

[0365] Note that the above-described embodiments show examples for embodying the present technology, and matters in the embodiments and matters designated by the invention in the claims have a corresponding relationship. Similarly, matters designated by the invention in the claims and matters expressed by the same name as the matters designated by the invention in the embodiments of the present technology have a corresponding relationship. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the gist thereof.

[0366] Further, the effects described in the present specification are merely illustrative or illustrative, and further, there can be additional effects.

[0367] Note that the present technology can also have the following configurations. (1)

[0369] A solid-state imaging device, comprising:

[0370] a first comparison element to which an input voltage related to a voltage of a vertical signal line is input to a source, the first comparison element outputting a drain voltage corresponding to a gate-source voltage from a drain; and

[0371] a transistor to which a signal corresponding to the voltage of the vertical signal line is input to a gate, a source being connected to the drain of the first comparison element. (2)

[0373] The solid-state imaging device according to (1), wherein

[0374] the source of the first comparison element is connected to the vertical signal line,

[0375] a predetermined reference voltage is input to a gate of the first comparison element,

[0376] in a case where the input voltage and the reference voltage substantially coincide with each other, the first comparison element transitions from an off state to an on state, and

[0377] the transistor includes a first clamp transistor that fixes the drain voltage in the off state to a clamp voltage corresponding to the input voltage. (3)

[0379] The solid-state imaging device according to (2), further comprising: a clamp voltage controller that provides a signal to a gate of a first clamp transistor, wherein

[0380] the first clamp transistor is inserted between the drain of the first comparison element and the source. (4)

[0382] The solid-state imaging device according to (3), further comprising: a second clamp transistor connected in parallel with the first clamp transistor, wherein

[0383] A fixed voltage is applied to a gate of the second clamp transistor. (5)

[0385] The solid-state imaging device according to (4), wherein

[0386] The clamp voltage controller includes a capacitor inserted between the vertical signal line and the gate of the first clamp transistor. (6)

[0388] The solid-state imaging device according to (4), wherein

[0389] The clamp voltage controller divides a voltage between the voltage of the vertical signal line and a predetermined reference potential, and supplies the divided voltage to the gate of the first clamp transistor. (7)

[0391] The solid-state imaging device according to (6), further comprising: an initialization circuit that samples a voltage of a vertical signal line, holds the sampled voltage as a held voltage, and initializes a gate voltage of the first clamp transistor based on the held voltage. (8)

[0393] The solid-state imaging device according to (7), wherein

[0394] The initialization circuit samples and holds a pixel signal of the pixel circuit. (9)

[0396] The solid-state imaging device according to (7), wherein

[0397] The initialization circuit samples and holds a pixel signal of a light-shielded light-shielded pixel. (10)

[0399] The solid-state imaging device according to (7), wherein

[0400] The initialization circuit samples and holds a pixel signal of a dummy pixel. (11)

[0402] The solid-state imaging device according to (7), wherein

[0403] The driver samples and holds a pixel signal of a light-shielded dummy pixel. (12)

[0405] The solid-state imaging device according to any one of (6) to (11), further comprising: a counter that counts a count value during a period before the drain voltage is reversed. (13)

[0407] The solid-state imaging device according to (12), further comprising:

[0408] a correction coefficient calculation unit that calculates a correction coefficient for correcting a conversion gain that is a ratio between the input voltage and the count value; and

[0409] a correction unit that corrects a digital signal representing the count value based on the correction coefficient. (14)

[0411] The solid-state imaging device according to (12), further comprising:

[0412] a controller that calculates a correction coefficient for correcting a conversion gain that is a ratio between the input voltage and the count value, and controls a reference voltage based on the correction coefficient. (15)

[0414] The solid-state imaging device according to any one of (1) to (14), wherein

[0415] the transistor includes an auto-zero switch that shorts the gate of the first comparison element and the drain according to the signal. (16)

[0417] The solid-state imaging device according to (15), wherein,

[0418] a source of the first comparison element is connected to the vertical signal line, and

[0419] a predetermined reference voltage is input to a gate of the first comparison element. (17)

[0421] The solid-state imaging device according to (15) or (16), further comprising: a driver that generates a predetermined control signal as a signal based on a voltage of the vertical signal line. (18)

[0423] The solid-state imaging device according to (17), wherein,

[0424] the driver provides one of two values as the control signal. (19)

[0426] The solid-state imaging device according to (17) or (18), wherein,

[0427] The driver samples and holds a pixel signal of the pixel circuit, and generates the control signal based on the held pixel signal. (20)

[0429] The solid-state imaging device according to any one of (17) to (19), wherein

[0430] The driver samples and holds a pixel signal of the pixel circuit, and generates the control signal based on the held pixel signal. (21)

[0432] The solid-state imaging device according to any one of (17) to (19), wherein

[0433] The driver generates the control signal based on a pixel signal of the dummy pixel. (22)

[0435] The solid-state imaging device according to (21), wherein

[0436] The driver generates the control signal based on a pixel signal of the dummy pixel. (23)

[0438] The solid-state imaging device according to any one of (17) to (22), wherein

[0439] The first comparison element is arranged in a column amplifier that amplifies a voltage of the vertical signal line and supplies the amplified voltage to an analog-digital converter. (24)

[0441] The solid-state imaging device according to any one of (17) to (22), further comprising:

[0442] a second comparison element to which a voltage of the vertical signal line is input to a gate, a drain is connected to a power supply voltage, and a source is connected to a source of the first comparison element.

[0443] Symbol Explanation

[0444] 100 imaging device

[0445] 110 optical unit

[0446] 120 DSP circuit

[0447] 130 display section

[0448] 140 operation section

[0449] 150 bus

[0450] 160 frame memory

[0451] 170 memory

[0452] 180 power supply

[0453] 200 solid-state imaging device

[0454] 201 light-receiving chip

[0455] 202 circuit chip

[0456] 210 vertical scanning circuit

[0457] 220 timing controller

[0458] 221 control signal generator

[0459] 230 DAC

[0460] 231 variable current source

[0461] 232 current converter

[0462] 233, 285, 287, 314, 320, 437, 438 current source

[0463] 234 switch

[0464] 235, 333, 334 resistor

[0465] 240 pixel array section

[0466] 241 horizontal connection switch

[0467] 242 load current source

[0468] 250 pixel circuit

[0469] 251, 511, 521, 531, 541 photoelectric conversion element

[0470] 252, 512, 522, 532, 542 transfer transistor

[0471] 253, 513, 523, 533, 543 reset transistor

[0472] 254, 514, 524, 534, 544 floating diffusion

[0473] 255, 515, 525, 535, 545 amplifier transfer

[0474] 256, 516, 526, 536, 546 selection transistor

[0475] 260 column signal processor

[0476] 261 counter

[0477] 262 latch

[0478] 270 horizontal scan circuit

[0479] 280 initialization circuit

[0480] 281, 282, 410 employ switches

[0481] 283, 289, 420 hold capacitors

[0482] 284 variable resistor

[0483] 286 replica circuit

[0484] 288, 291, 354, 439, 441 nMOS transistors

[0485] 290 test voltage supply unit

[0486] 295 current controller

[0487] 300 comparator

[0488] 311, 352 input capacitors

[0489] 312, 622 input transistors

[0490] 313, 353, 644 auto-zero switches

[0491] 315 band-limiting capacitors

[0492] 316, 317 clamp transistors

[0493] 318 output transistors

[0494] 319, 335 initialization switches

[0495] 330 clamp voltage controller

[0496] 331, 332 capacitors

[0497] 336 capacitor connection switches

[0498] 340 image processor

[0499] 341 correction coefficient calculation unit

[0500] 342, 440 selectors

[0501] 343 memory

[0502] 344 correction unit

[0503] 351 VSL switch

[0504] 355 input amplifier

[0505] 356 output amplifier

[0506] 400 driver

[0507] 430 level shifter

[0508] 431-436, 442, 443 pMOS transistors

[0509] 510 active pixel

[0510] 520 OPB pixel

[0511] 530 pseudo non-OPB pixel

[0512] 540 pseudo OPB pixel

[0513] 600 constant current source unit

[0514] 610 column amplifier

[0515] 620 current-multiplying column amplifier

[0516] 621 input stage

[0517] 624 input-side auto-zero switch

[0518] 625 feedback capacitor

[0519] 626 reference-side capacitor

[0520] 627, 647 reference-side current source transistor

[0521] 640 folding stage

[0522] 641 cascode capacitor

[0523] 642 supply-side current source transistor

[0524] 643, 645, 653 cascode transistor

[0525] 644 output-side auto-zero switch

[0526] 646 intermediate switch

[0527] 650 boost circuit

[0528] 651 boost-side capacitor

[0529] 652 boost-side current source transistor

[0530] 654 boost transistor

[0531] 12031 imaging portion

Claims

1. A solid-state imaging device comprising: a first comparison element to which an input voltage corresponding to a voltage of a vertical signal line is input to a source, the first comparison element outputting a drain voltage corresponding to a gate-source voltage from a drain; and a transistor to which a signal corresponding to the voltage of the vertical signal line is input to a gate, a source being connected to the drain of the first comparison element.

2. The solid-state imaging device according to claim 1, wherein the source of the first comparison element is connected to the vertical signal line, a predetermined reference voltage is input to a gate of the first comparison element, in a case where the input voltage and the reference voltage substantially coincide with each other, the first comparison element transitions from an off state to an on state, and the transistor includes a first clamp transistor that fixes the drain voltage in the off state to a clamp voltage corresponding to the input voltage.

3. The solid-state imaging device according to claim 2, further comprising: a clamp voltage controller that supplies the signal to a gate of the first clamp transistor, wherein the first clamp transistor is inserted between a drain and a source of the first comparison element.

4. The solid-state imaging device according to claim 3, further comprising: a second clamp transistor is connected in parallel with the first clamp transistor, wherein a fixed voltage is applied to a gate of the second clamp transistor.

5. The solid-state imaging device according to claim 3, wherein the clamp voltage controller includes a capacitor inserted between the vertical signal line and the gate of the first clamp transistor.

6. The solid-state imaging device according to claim 3, wherein the clamp voltage controller divides a voltage between the voltage of the vertical signal line and a predetermined reference potential, and supplies the divided voltage to the gate of the first clamp transistor.

7. The solid-state imaging device according to claim 6, further comprising: an initialization circuit that samples the voltage of the vertical signal line, holds the sampled voltage as a hold voltage, and initializes a gate voltage of the first clamp transistor based on the hold voltage.

8. The solid-state imaging device according to claim 7, wherein the initialization circuit samples and holds a pixel signal of a pixel circuit.

9. The solid-state imaging device according to claim 7, wherein the initialization circuit samples and holds a pixel signal of a light-shielded light-shielded pixel.

10. The solid-state imaging device according to claim 7, wherein the initialization circuit samples and holds a pixel signal of a dummy pixel.

11. The solid-state imaging device according to claim 7, wherein a driver samples and holds a pixel signal of a dummy pixel that is light-shielded.

12. The solid-state imaging device according to claim 6, further comprising: a counter counts a count value for a period before the drain voltage is inverted.

13. The solid-state imaging device according to claim 12, further comprising: a correction coefficient calculation unit that calculates a correction coefficient for correcting a conversion gain that is a ratio between the input voltage and the count value; and a correction unit that corrects a digital signal representing the count value based on the correction coefficient.

14. The solid-state imaging device according to claim 12, further comprising: A controller calculates a correction coefficient for correcting a conversion gain, which is a ratio between the input voltage and the count value, and controls the reference voltage based on the correction coefficient.

15. The solid-state imaging device according to claim 1, wherein The transistor includes an auto-zero switch that shorts the gate and the drain of the first comparison element according to the signal.

16. The solid-state imaging device according to claim 15, wherein The source of the first comparison element is connected to the vertical signal line, and A predetermined reference voltage is input to the gate of the first comparison element.

17. The solid-state imaging device according to claim 15, further comprising: A driver generates a predetermined control signal as the signal based on the voltage of the vertical signal line.

18. The solid-state imaging device according to claim 17, wherein The driver supplies one of two values as the control signal.

19. The solid-state imaging device according to claim 17, wherein The driver samples and holds a pixel signal of a pixel circuit, and generates the control signal based on the held pixel signal.

20. The solid-state imaging device according to claim 17, wherein The driver samples and holds a pixel signal of a light-shielded light-shielded pixel, and generates the control signal based on the held pixel signal.

21. The solid-state imaging device according to claim 17, wherein The driver generates the control signal based on a pixel signal of a dummy pixel.

22. The solid-state imaging device according to claim 21, wherein The driver generates the control signal based on a pixel signal of a light-shielded dummy pixel.

23. The solid-state imaging device according to claim 17, wherein The first comparison element is arranged in a column amplifier that amplifies the voltage of the vertical signal line and supplies the amplified voltage to an analog-digital converter.

24. The solid-state imaging device according to claim 17, further comprising: A second comparison element to which the voltage of the vertical signal line is input to a gate, a drain is connected to a power supply voltage, and a source is connected to the source of the first comparison element.

Images