Design method of stable sub-slot measurement for quantum surface codes

Abstract

The present invention proposes a method for avoiding the introduction of logical errors when measuring stabilizers, which mainly solves the problem that the time slot sequence types of the traditional method are limited and the shape of the stabilizer time slot is single. The implementation scheme is: construct a surface code model of a quantum rotation lattice; analyze the situation of introducing logical X errors and logical Z errors in the given surface code model; derive the time slot law that effectively avoids the introduction of logical errors when measuring X stabilizers and Z stabilizers according to the situation of error introduction; design the time slot sequence according to the law of avoiding the introduction of logical errors; combine the designed time slot sequence in the surface code model as required; adjust the measurement circuit of the corresponding stabilizer according to the time slot combination, introduce the same type of errors in the stabilizer measurement circuit during the verification process, and check the verification result of the measurement circuit. The present invention can realize the design of logically immune stabilizer time slots, which can be used for quantum computing to avoid the introduction of logical errors.

Description

Technical Field

[0001] The invention belongs to the technical field of information processing, and in particular relates to a stable sub-measurement time slot design method, which can be used for quantum computing to avoid introducing logic errors. Background Art

[0002] Compared with traditional bits, qubits can describe more states, so quantum computing has super computing power. However, qubits are fragile, and quantum errors caused by noise will inevitably occur in practical applications, so it is necessary to use quantum error correction codes to encode logical qubits to improve accuracy. Since quantum surface codes are an important type of quantum error correction code, they are tolerant to local errors and have good scalability. Therefore, people use quantum surface codes to complete a set of fault-tolerant universal logic gates, so as to realize fault-tolerant quantum computing on this basis.

[0003] When using quantum surface codes for quantum computing, it is inevitable to track the state changes by measuring the stabilizers in the surface code model. When the error rate of each surface code operation is less than the threshold of 0.57%, the logical error rate in the surface code decreases rapidly with the increase of the code distance, which means that the larger the code distance d of the surface code model within the threshold, the higher the fault tolerance. Although quantum surface codes are fault-tolerant, when the number of erroneous bits exceeds the fault tolerance range of the current code distance, logical errors may be introduced. For example, the surface code model with a code distance of d = 3 can only correct the error of one bit. When there are 2 or 3 errors in the data bits in the logical operation, the surface code model will not be able to correct the error correctly and will introduce a logical error. Logical errors cannot be known by measuring stabilizers, and surface codes cannot correct logical errors. Logical errors will completely reverse the encoded information, that is, logical X errors will flip the state of the bit from 0 to 1 or 1 to 0, and logical Z errors will flip the phase of the bit from π to 0 or 0 to π. Therefore, when measuring stabilizers, if the order of stabilizer time slots that can easily lead to logical errors can be avoided, some accuracy can be improved in quantum circuits.

[0004] In quantum circuits, there are two types of logical errors according to the location of the error: one is that an error occurs in the data bit itself, which leads to the introduction of a logical error. This type of error cannot be prevented; the other is that an error occurs in the auxiliary bit, which is transmitted from the auxiliary bit to the data bit, leading to the introduction of a logical error. For this type of error, the existing technology mainly solves it by adjusting the order of CNOT gates in the quantum circuit, that is, the time slot order of the surface code stabilizer.

[0005] Rui Chao mentioned in the paper "Optimization of the surface code design for Majorana-based qubits" (arXiv, 10.22331 / q-2020-10-28-352[P].2020) how to adjust the time slot of the stabilizer to solve this type of error, that is, for two adjacent stabilizers A and B, the time slot of the two shared data bits in stabilizer A must be greater than the time slot in stabilizer B or less than the time slot in stabilizer B. Although this method can avoid the error in the stabilizer measurement line due to the error in the auxiliary bit and the error is transmitted to the data bit, thereby avoiding the introduction of logical errors. However, since it only provides the time slot arrangement of the stabilizer, and does not clearly state which key stabilizer time slot design can effectively avoid the introduction of logical errors, and the given stabilizer time slot shape is single, it cannot adjust the time slot order for quantum surface codes of different types and different code distances, and therefore cannot adapt to other application scenarios. Summary of the invention

[0006] The purpose of the present invention is to address the defects of the above-mentioned prior art and propose a method for designing stabilizer measurement time slots of quantum surface codes, so as to clarify the arrangement of key stabilizer time slots that effectively avoid introducing logical errors and increase the diversity of the order of stabilizer time slots in quantum bits.

[0007] The technical idea of ​​the present invention is: when designing the time slot shape and order of X-type and Z-type stabilizers, the two data bits involved in the same logical operation as the stabilizer type are avoided from being placed in the first half time slot or the second half time slot at the same time, so as to achieve the effect of logic error immunity when the surface code performs quantum computing. By exploring other shapes of time slots and verifying them based on the existing scheme, the diversity of the order of time slots of stabilizers in quantum surface codes is increased.

[0008] According to the above ideas, the technical solution of the present invention includes the following steps:

[0009] (1) Construct a boundary-based quantum rotation lattice surface code model:

[0010] Assume that the code distance of the surface code model is d, the number of X-type stabilizers and the number of Z-type stabilizers are both m, and the number of data bits is n=2m+1;

[0011] The number of encoded logic bits is the difference between the number of data bits and the number of stable sub-bits, and (2m+1)-2m=1, so that it can encode 1 logic bit;

[0012] (2) Design time slot sequence:

[0013] 2a) When measuring the X-type and Z-type stabilizers of the quantum surface code, according to the time slot sequence and stabilizer measurement circuit that introduce logical errors, the principle that two bits involved in the same logical operation of the stabilizer cannot be placed in the first half time slot or the second half time slot at the same time is set;

[0014] 2b) according to the above principle, its two data bits are respectively set in the first time slot and the third time slot, or respectively set in the second time slot and the fourth time slot, or respectively set in the first time slot and the fourth time slot, or respectively set in the second time slot and the third time slot;

[0015] (3) Set the time slot sequence in the surface code model as required:

[0016] 3a) According to the rule that the same type of stabilizers in the surface code model should have the same time slot sequence, a time slot sequence of an X-type stabilizer is selected from the time slot sequences designed in (2) and set in the surface code model;

[0017] 3b) According to the rule that the time slots of data bits shared by different types of stabilizers in the surface code model should be completely different, a Z-type time slot sequence that meets the requirements is selected from the time slot sequences designed in (2) and is set in the surface code, and the Z-type stable sub time slot sequence is paired with the existing X-type stable sub time slot sequence in the model;

[0018] (4) Verify whether the time slot sequence can effectively avoid the introduction of logical errors:

[0019] When the auxiliary bit of the stabilizer measurement line is wrong in the middle of the time slot, it is verified whether the lines corresponding to the various time slot sequence combinations of the X-type stabilizer and the Z-type stabilizer in step (3) are ultimately immune to logical errors:

[0020] If there is a time slot sequence in the verified time slot sequence combinations that introduces a logic error of the same type as the stable sub-type or the introduced error can be equivalent to a shorter error chain, then the time slot sequence combination is not a stable sub-time slot sequence immune to logic errors, and return to step 3 to reselect the time slot combination;

[0021] If the slot sequences in the verified slot sequence combinations can avoid introducing logical errors of the same type as the stabilizer or the introduced errors cannot be equivalent to a shorter error chain, then the arrangement of the key slots of the stabilizer in verification (2) is accurate, and the slots of the stabilizer are set according to their slot sequence in the quantum surface code calculation process to reduce the logical error rate of the overall quantum circuit.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] First, the present invention analyzes the stabilizer measurement circuit that introduces logic X errors and logic Z errors, and obtains the time slot arrangement that introduces logic errors. The time slot arrangement can be avoided in the design of the time slot sequence step, and the adjustment range of the CNOT gate in the stabilizer measurement circuit is clarified, thereby reducing the logic error rate of the quantum surface code during calculation.

[0024] Second, the present invention verifies the effectiveness of multiple groups of time slot sequence combinations to obtain a variety of stable sub-time slot arrangements that are immune to logical errors. The order of time slots can be adjusted for application scenarios of surface codes of different types and code distances, thereby increasing the diversity of time slot design and meeting different time slot requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a flow chart of the implementation of the present invention;

[0026] Figure 2 The present invention is applicable to the quantum rotation lattice surface code model with code distances d=3, d=5, and d=7;

[0027] Figure 3 It is a time slot sequence diagram for introducing a logic X error in an embodiment of the present invention and a stable sub-measurement circuit verification diagram thereof;

[0028] Figure 4 It is a time slot sequence diagram and a stable sub-measurement circuit verification diagram of the ...

[0029] Figure 5 is a time slot sequence diagram of an X-type stabilizer in an embodiment of the present invention;

[0030] Figure 6 is a time slot sequence diagram of a Z-type stabilizer in an embodiment of the present invention;

[0031] Figure 7 is a time slot sequence combination that meets the requirements in the embodiment of the present invention;

[0032] Figure 8 is a stable sub-measurement circuit diagram for verifying time slot arrangement 1 in an embodiment of the present invention;

[0033] Fig. 9 It is a stable sub-measurement circuit diagram for verifying time slot arrangement 2 in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Reference Figure 1 , the implementation steps of this embodiment are as follows:

[0035] Step 1: Construct a boundary-based quantum rotation lattice surface code model.

[0036] According to the situation that the rotating lattice surface code model uses the least number of data bits when the code distance is set, this example uses the rotating lattice surface code to construct a boundary-based quantum surface code model, which is implemented as follows:

[0037] 1.1) Set model parameters:

[0038] Assume that the code distance of the surface code model of the rotating lattice is d;

[0039] Assume that the number of X-type stabilizers and the number of Z-type stabilizers are both m;

[0040] The number of data bits is n=2m+1, the number of coded logic bits is the difference between the number of data bits and the number of stabilizers, and (2m+1)-2m=1, so that the surface code model as a whole can encode 1 logic bit of information;

[0041] In the boundary-based quantum rotation lattice surface code model, the boundary formed by the X-type stabilizers connected to the outside world is an X boundary, and the boundary formed by the Z-type stabilizers connected to the outside world is a Z boundary. The model includes a pair of X boundaries and a pair of Z boundaries. The X operation of the data bits involved in the horizontal grid lines connecting the two X boundaries constitutes a logical X operation, and the Z operation of the data bits involved in the vertical grid lines connecting the two Z boundaries constitutes a logical Z operation, wherein the number of data bits involved in the logical X operation and the logical Z operation is the same as the code distance d;

[0042] 1.2) Correct the errors that occur in the surface code model during the measurement process using the stabilizer:

[0043] If the erroneous data bits do not constitute a logical error or cannot be equivalent to a shorter error chain, the surface code model will correctly correct these errors.

[0044] If the erroneous data bits constitute a logical error or can be equivalent to a shorter error chain, the surface code model will not be able to correct the logical error. The logical error is as follows:

[0045] If the number of data bits with X errors on a certain horizontal grid line is greater than d / 2, the error will be equivalent to a shorter X error chain, introducing a logical X error. If the data bit states involved in the logical X operation in the model are all flipped, a logical X error will be introduced. These two situations will cause the information state encoded by the surface code model to flip, constituting a logical error.

[0046] If the number of data bits with Z errors on a certain vertical grid line is greater than d / 2, the error will be equivalent to a shorter Z error chain, introducing a logical Z error. If the phases of all data bits involved in the logical Z operation in the model are flipped, a logical Z error will be introduced. These two situations will cause the phase of the information encoded by the surface code model to be flipped, constituting a logical error.

[0047] 1.3) Select the quantum rotation lattice surface code model:

[0048] Reference Figure 2 This step lists boundary-based quantum rotation lattice surface code models with code distances d=3, d=5, and d=7, where:

[0049] Figure 2 (a) is a quantum rotation lattice surface code model with a code distance of d = 3. In this model, the number of X-type stabilizers and Z-type stabilizers is 4. There are 9 data bits, which can encode 1 logical bit of information. L =X 1 X 2 X 3 Indicates the logical X operation consisting of 3 data bits, X 4 X 5 X 6 , X 7 X 8 X 9 is the equivalent logical operation X, Z in the figure L =Z 1 Z 4 Z 7 Represents a logic Z operation consisting of 3 data bits, Z 2 Z 5 Z 8 , Z 3 Z 6 Z 9 is the equivalent logical Z operation;

[0050] Figure 2 (b) is a quantum rotation lattice surface code model with a code distance of d = 5. The number of X-type stabilizers and Z-type stabilizers in this model is 12 each. There are 25 data bits, which can encode 1 logical bit of information. L =X 1 X 2 X 3 X 4 X 5 Indicates the logical X operation consisting of 5 data bits, X 6 X 7 X 8 X 9 X 10 , X 11 X 12 X 13 X 14 X 15 , X 16 X 17 X 18 X 19 X 20 , X21 X 22 X 23 X 24 X 25 is the equivalent logical operation X, Z in the figure L =Z 1 Z 6 Z 11 Z 16 Z 21 Represents a logic Z operation consisting of 5 data bits, Z 2 Z 7 Z 12 Z 17 Z 22 , Z 3 Z 8 Z 13 Z 18 Z 23 , Z 4 Z 9 Z 14 Z 19 Z 24 , Z 5 Z 10 Z 15 Z 20 Z 25 is the equivalent logical Z operation;

[0051] Figure 2 (c) is a quantum rotation lattice surface code model with a code distance of d = 7. The number of X-type stabilizers and Z-type stabilizers in this model is 24. There are 49 data bits, which can encode 1 logical bit of information. L =X 1 X 2 X 3 X 4 X 5 X 6 X 7 Indicates the logical X operation consisting of 7 bits of data, X 8 X 9 X 10 X 11 X 12 X 13 X 14 , X 15 X 16 X 17 X 18 X 19 X 20 X 21 , X 22 X 23 X 24 X 25 X 26 X 27 X28 and X 29 X 30 X 31 X 32 X 33 X 34 X 35 and X 36 X 37 X 38 X 39 X 40 X 41 X 42 and X 43 X 44 X 45 X 46 X 47 X 48 X 49 are equivalent logical X operations, Z L = Z 1 Z 8 Z 15 Z 22 Z 29 Z 36 Z 43 represents a logical Z operation consisting of 7 data bits, Z 2 Z 9 Z 16 Z 23 Z 30 Z 37 Z 44 and Z 3 Z 10 Z 17 Z 24 Z 31 Z 38 Z 45 and Z 4 Z 11 Z 18 Z 25 Z 32 Z 39 Z 46 and Z 5 Z 12 Z 19 Z 26 Z 33 Z 40 Z 47 and Z 6 Z 13 Z 20 Z 27 Z 34 Z 41 Z 48 and Z 7 Z 14 Z 21 Z 28 Z35 Z 42 Z 49 is the equivalent logical Z operation;

[0052] Figure 2 It shows that as the surface code distance increases, the number of data bits used by the surface code model also increases exponentially. This change law only affects the fault tolerance rate and the size of the model. Since each data bit appears in at most four stabilizers, it has no effect on the time slot setting. This embodiment selects a quantum rotation lattice surface code model with a code distance of d=3 for ease of display.

[0053] Step 2: Design the time slot sequence.

[0054] 2.1) Set stable sub-time slot:

[0055] Based on the fact that the data bits in the surface code model need to participate in at most four stable sub-measurements, the process of all data bits in the model participating in the stable sub-measurement can be divided into four time periods and performed simultaneously to save time, so the time slots of the stable sub composed of data bits can be set to four, namely the 1st time slot, the 2nd time slot, the 3rd time slot and the 4th time slot.

[0056] The data bits in the model can first all participate in the stable sub-measurement of the first time slot at the same time, and then all participate in the stable sub-measurement of the second time slot at the same time, and so on to complete the stable sub-measurement of four time slots. At this point, all the stable subs of the surface code model will be measured.

[0057] 2.2) Logical errors are prone to occur during the execution of stable sub-measurement:

[0058] 2.2.1) Logical X errors in the given quantum rotation lattice surface code model with code distance d=3:

[0059] According to the error transmission property of the CNOT gate, the control bit of the CNOT gate will transfer the X error that can flip the state of a single data bit to the target bit of the CNOT gate. Since the auxiliary bit of the circuit in the X-type stabilizer measurement process is the control bit of the CNOT gate, the data bits involved in the stabilizer are used as the target bits of the CNOT gate. If the CNOT gates of the two data bits in the logical X operation direction are set in the second half of the circuit in the stabilizer measurement circuit at this time, when the auxiliary bit in the circuit has an X error, the auxiliary bit will pass the X error to the data bit in the circuit. After the X stabilizer measurement, the two data bits in the logical X operation will be wrong, so that the data bit errors in the logical operation accumulate after measuring one or more X stabilizers, causing the symptoms of the stabilizer to be traced to the surface code model data bit error. The surface code model will correct the erroneous data bits, and the logical X error may be introduced in the correction process:

[0060] If the number of data bits X errors on the same horizontal grid line does not exceed the error tolerance range of the surface code, the surface code model can correct the error;

[0061] If the number of data bits with X errors on the same horizontal grid exceeds the fault tolerance range of the surface code model, the surface code model will mistakenly flip the states of several data bits that have not erroneously appeared on the same horizontal grid line based on its own error correction capability and the symptoms of the stabilizer, thereby introducing a logical X error, such as Figure 3 As shown, Figure 3 (a) is a surface code model with time slot sequences marked to introduce logical X errors. Figure 3 (b) is based on Figure 3 (a) shows the stable sub-measurement circuit diagram obtained by the wrong time slot sequence.

[0062] exist Figure 3 (a) In the surface code model, the logical X operation of the model is X 1 X 2 X 3 , Figure 3 (b) is based on Figure 3 (a) The X-stable sub-substrate X obtained by the time slot sequence of the surface code model 1 X 2 X 4 X 5 The measurement circuit shows that after the auxiliary bit has an X error that flips its state at the red position shown in the figure, the X error will be transmitted to data bit 1 and data bit 2. At this time, the data bit error in the model is X 1 X 2 Since the surface code model with code distance d = 3 can only correct one data bit error, the surface code model will mistakenly correct the data bit X 3 Perform state flipping, and finally introduce the logic X error is the logic X operation X 1 X 2 X 3 .

[0063] 2.2.2) Logical Z error in the given quantum rotation lattice surface code model with code distance d=3:

[0064] According to the error transmission property of the CNOT gate, the target bit of the CNOT gate will transfer the Z error that can flip the phase of a single data bit to the control bit of the CNOT gate. Since the auxiliary bit of the circuit in the Z-type stabilizer measurement process is exactly the target bit of the CNOT gate, the data bits involved in the stabilizer are used as the control bits of the CNOT gate. If the CNOT gates of the two data bits in the logical Z operation direction are set in the second half of the circuit in the stabilizer measurement circuit at this time, when a Z error occurs in the auxiliary bit in the circuit, the auxiliary bit will pass the Z error to the data bit in the circuit. After the Z stabilizer measurement, the two data bits in the logical Z operation will be wrong, so that the data bit errors in the logical operation accumulate after measuring one or more Z stabilizers, causing the symptoms of the stabilizer to be traced to the surface code model data bit error. The surface code model will correct the erroneous data bits, and the logical Z error may be introduced in the correction process:

[0065] If the number of data bit Z errors on the same vertical grid line does not exceed the error tolerance range of the surface code, the surface code model can correct the error;

[0066] If the number of Z error bits of data bits on the same vertical grid exceeds the fault tolerance range of the surface code model, the surface code model will mistakenly flip the phases of several data bits that are not in error on the same vertical grid line according to its own error correction capability and the symptoms of the stabilizer, thereby introducing a logical Z error, such as Figure 4 As shown, Figure 4 (a) is a surface code model with time slot sequences marked to introduce logical Z errors. Figure 4 (b) is based on Figure 4 (a) shows the stable sub-measurement circuit diagram obtained by the wrong time slot sequence.

[0067] exist Figure 4 (a) In the surface code model, the logical Z operation of the model is Z 1 Z 4 Z 7 , Figure 4 (b) is based on Figure 4 (a) The Z-stable sub-substrate Z obtained by the time slot sequence of the surface code model 4 Z 5 Z 7 Z 8 The measurement circuit shows that the auxiliary bit will be transmitted to data bit 4 and data bit 7 after the Z error occurs at the red position of the auxiliary bit, which will flip its phase. At this time, the data bit error in the model is Z 4 Z 7 Since the surface code model with code distance d = 3 can only correct one data bit error, the surface code model will mistakenly correct the data bit Z 1Phase flipping is performed, and the final logic Z error introduced is the logic Z operation Z 1 Z 4 Z 7 .

[0068] 2.3) Inferring the stable sub-slot arrangement of logical immunity:

[0069] According to the introduction of logical X error and logical Z error in step 2.2), the following speculation is made on the time slot arrangement of logical immune stabilizers: when measuring X-type and Z-type stabilizers of quantum surface codes, the two bits involved in the logical operation of the same type in the stabilizer cannot be set in the first and second time slots at the same time, nor can they be set in the third and fourth time slots at the same time. One of them should be set in the first half time slot, and the other should be set in the second half time slot;

[0070] 2.4) Time slot order:

[0071] According to step 2.3), the time slot arrangement is obtained and the time slot sequence is set as follows:

[0072] 2.4.1) two data bits involved in the same type of logic operation in the stabilizer are respectively set in the first time slot and the third time slot, or in the second time slot and the fourth time slot;

[0073] 2.4.2) two data bits involved in the same type of logic operation in the stabilizer are respectively set in the first time slot and the fourth time slot, or in the second time slot and the third time slot;

[0074] The above time slot arrangement is reflected in Figure 5 , Figure 6 In which:

[0075] Figure 5 (c) Figure 5 (d) Figure 5 (i) Figure 5 (j) is the case where the X stabilizer sets the two data bits on the upper grid line involved in the logical X operation in the first time slot and the third time slot, Figure 5 (a) Figure 5 (b) Figure 5 (k) Figure 5 (1) is the case where the X stabilizer sets the two data bits on the upper grid line involved in the logic X operation in the second time slot and the fourth time slot;

[0076] Figure 6 (a) Figure 6 (j) Figure 6 (k) Figure 6(1) is the case where the Z stabilizer sets the two data bits on the left grid line involved in the logic Z operation in the first time slot and the third time slot. Figure 6 (b) Figure 6 (c) Figure 6 (d) Figure 6 (i) is the case where the Z stabilizer sets the two data bits on the left grid line involved in the logic Z operation in the second time slot and the fourth time slot;

[0077] Figure 5 (e) Figure 5 (g) Figure 5 (m), Figure 5 (o) is the case where the X stabilizer sets the two data bits on the upper grid line involved in the logical X operation in the 1st time slot and the 4th time slot. Figure 5 (f) Figure 5 (h) Figure 5 (n) Figure 5 (p) is the case where the X stabilizer sets the two data bits on the upper grid line involved in the logical X operation in the second and third time slots;

[0078] Figure 6 (e) Figure 6 (h) Figure 6 (m), Figure 6 (p) is the case where the Z stabilizer sets the two data bits on the left grid line involved in the logic Z operation in the 1st time slot and the 4th time slot. Figure 6 (f) Figure 6 (g) Figure 6 (n) Figure 6 (o) is the case where the Z stabilizer sets the two data bits on the left grid line involved in the logic Z operation in the second time slot and the third time slot.

[0079] Step 3: Set the time slot sequence in the surface code model as required.

[0080] According to the provisions in the surface code model that the same type of stabilizers should have the same time slot sequence and the time slots of the data bits shared by different types of stabilizers should be different, the time slot sequence of the X stabilizer and the time slot sequence of the Z stabilizer are selected, and the implementation is as follows:

[0081] In step 2, select an X-type stabilizer time slot shape from the X-stabilizer time slot sequence designed and set it in the surface code model, and then select a Z-type stabilizer time slot sequence that meets the requirements from the time slot sequence designed in step 2 and set it in the surface code, such as Figure 7 As shown, where:

[0082] Figure 7 The X-stable subslots in the first two surface code models in (a) are selected Figure 5 (a) the order;

[0083] Figure 7 The X-stable subslots in the last two surface code models in (a) are selected Figure 5 (b) the order;

[0084] Figure 7 The X-stable subslots in the first two surface code models in (b) are selected Figure 5 (c) the order;

[0085] Figure 7 The X-stable subslots in the last two surface code models in (b) are selected Figure 5 (d) order;

[0086] Figure 7 The X-stable subslots in the first two surface code models in (c) are selected Figure 5 (e) order;

[0087] Figure 7 The X-stable subslots in the last two surface code models in (c) are selected Figure 5 (f) order;

[0088] Figure 7 The X-stable subslots in the first two surface code models in (d) are selected Figure 5 (g) the order;

[0089] Figure 7 The X-stable subslots in the last two surface code models in (d) are selected Figure 5 (h) order;

[0090] Z-stable subslot selection Figure 6 (j) and Figure 6 (b) to match Figure 7 (a) The X-stable subslot order in the first two surface code models;

[0091] Z-stable subslot selection Figure 6 (i) and Figure 6 (a) to match Figure 7 (a) The X-stable subslot order in the latter two surface code models;

[0092] Z-stable subslot selection Figure 6 (k) and Figure 6 (d) to match Figure 7 (b) The X-stable subslot order in the first two surface code models;

[0093] Z-stable subslot selection Figure 6 (l) and Figure 6 (c) to match the order Figure 7 (b) The X-stable subslot order in the latter two surface code models;

[0094] Z-stable subslot selection Figure 6 (n) and Figure 6 (m) order to match Figure 7 (c) The X-stable subslot order in the first two surface code models;

[0095] Z-stable subslot selection Figure 6 (f) and Figure 6 (e) to match Figure 7 (c) The X-stable subslot order in the latter two surface code models;

[0096] Z-stable subslot selection Figure 6 (g) and Figure 6 (p) order to match Figure 7 (d) The X-stable subslot order in the first two surface code models;

[0097] Z-stable subslot selection Figure 6 (h) and Figure 6 (o) order to match Figure 7 (d) The X-stable subslot order in the latter two surface code models;

[0098] There are 16 other slot sequence combinations, among which X stable subslot selection Figure 5 (i) to Figure 5 (p), then from Figure 6 Find the matching Z stable sub-slots in the sequence of these slots, since the sequence combination of these slots can be obtained by Figure 7 The existing time slot sequence combination diagram is obtained by flipping it, so it is not shown here.

[0099] Step 4: Verify whether the time slot sequence can effectively avoid the introduction of logic errors.

[0100] In order to verify whether the time slot combination obtained in step 3 can effectively avoid the introduction of logic errors, it is necessary to introduce an X error in the middle of the measurement line of the X stabilizer and a Z error in the middle of the measurement line of the Z stabilizer, and verify the time slot sequence combination of step 3. The steps are as follows:

[0101] 4.1) According to the X stable sub-slot sequence in the slot sequence combination, set up the stable sub-measurement circuit, add an X error in the middle of the auxiliary bit of the circuit, and observe the quantum circuit verification result;

[0102] 4.2) According to the Z stable sub-slot sequence in the slot sequence combination, set up the stable sub-measurement circuit, add a Z error in the middle of the auxiliary bit of the circuit, and observe the quantum circuit verification result;

[0103] 4.3) Determine the verification results of 4.1) and step 4.2):

[0104] If the measurement line of the X stabilizer can avoid the introduction of logic X errors, and the measurement line of the Z stabilizer can avoid the introduction of logic Z errors, then this time slot combination can avoid the introduction of logic errors, verifying that the arrangement of the key time slots of the stabilizers in step 2.3) is accurate, and the correct time slot sequence combination can be set to the surface code model according to the time slot sequence to avoid the introduction of logic errors;

[0105] If the measurement line of the X stabilizer introduces a logic X error or the measurement line of the Z stabilizer introduces a logic Z error, and the time slot combination cannot effectively avoid the introduction of logic errors, then return to step 3 to reselect the time slot sequence combination and continue verification.

[0106] In this embodiment, Figure 7 All time slot combinations are verified as follows:

[0107] A) Verification of the time slot arrangement of step 2.4.1):

[0108] because Figure 7 (a) and Figure 7 The time slot arrangements of (b) are all the time slot arrangements of step 2.4.1). You only need to verify one of the situations. Select Figure 7 (b) is used to verify the first time slot combination. Figure 7 (b) The stable sub-measurement line in the first time slot combination is as follows Figure 8 As shown, where:

[0109] Figure 8 (a) is to verify the validity of the X-stable sub-time slot sequence when the auxiliary bit of the X-stable sub-measurement circuit introduces an X error in the middle of the time slot. The quantum circuit verification results show that it can avoid the introduction of logical X errors.

[0110] Figure 8 (b) is to verify the validity of the Z-stable sub-time slot sequence when the auxiliary bit of the Z-stable sub-measurement circuit introduces a Z error in the middle of the time slot. The quantum circuit verification results show that it can avoid introducing logical Z errors.

[0111] The verification results show that Figure 7 (a) and Figure 7 All the time slot combinations in (b) can effectively avoid introducing logical errors.

[0112] B) Verification of time slot arrangement in step 2.4.2):

[0113] because Figure 7 (c) and Figure 7 The time slot arrangements of (d) are all the time slot arrangements of step 2.4.2). You only need to verify one of the situations. Select Figure 7 (d) is verified by the first time slot combination. Figure 7 (d) The quantum circuit corresponding to the stable sub-measurement in the first time slot combination is as follows Fig. 9 As shown, where:

[0114] Fig. 9 (a) is to verify the validity of the X-stable sub-time slot sequence when the auxiliary bit of the X-stable sub-measurement circuit introduces an X error in the middle of the time slot. The quantum circuit verification results show that it can avoid the introduction of logical X errors.

[0115] Fig. 9 (b) is to verify the validity of the Z-stable sub-time slot sequence when the auxiliary bit of the Z-stable sub-measurement circuit introduces a Z error in the middle of the time slot. The quantum circuit verification results show that it can avoid introducing logical Z errors.

[0116] The verification results show that Figure 7 (c) and Figure 7 The time slot combinations in (d) all effectively avoid introducing logical errors.

[0117] The above verification Figure 7 The results that all time slot sequence combinations can effectively avoid the introduction of logical errors show that the present invention uses a boundary-based quantum rotation lattice surface code model, infers a time slot arrangement rule that is immune to logical errors, and designs the measurement time slots of the stabilizers in the model according to the rule, which can avoid logical errors introduced by X errors or Z errors in the auxiliary bits in the stabilizer measurement process in the middle of the time slot, thereby realizing a logic-immune stabilizer time slot design.

Claims

1. A logically immune quantum surface code stabilizer measurement time slot design method, characterized in that: include: (1) Construct a boundary-based quantum rotation lattice surface code model: Assume that the side length of the surface code model is the code distance d, the number of X-type stabilizers and the number of Z-type stabilizers are both m, and the number of data bits is n=2m+1; The number of encoded logic bits is the difference between the number of data bits and the number of stable sub-bits, and (2m+1)-2m=1, so that it can encode 1 logic bit; (2) Design time slot sequence: 2a) When measuring the X-type and Z-type stabilizers of the quantum surface code, according to the time slot sequence and stabilizer measurement circuit that introduce logical errors, the principle that two bits involved in the same logical operation of the stabilizer cannot be placed in the first half time slot or the second half time slot at the same time is set; 2b) according to the above principle, its two data bits are respectively set in the first time slot and the third time slot, or respectively set in the second time slot and the fourth time slot, or respectively set in the first time slot and the fourth time slot, or respectively set in the second time slot and the third time slot; (3) Set the time slot sequence in the surface code model as required: 3a) According to the rule that the same type of stabilizers in the surface code model should have the same time slot sequence, a time slot sequence of an X-type stabilizer is selected from the time slot sequences designed in (2) and set in the surface code model; 3b) According to the rule that the time slots of data bits shared by different types of stabilizers in the surface code model should be completely different, a Z-type time slot sequence that meets the requirements is selected from the time slot sequences designed in (2) and is set in the surface code, so as to match the Z-type stable sub time slot sequence with the X-type stable sub time slot sequence already in the model; (4) Verify whether the time slot sequence can effectively avoid the introduction of logical errors: When the auxiliary bit of the stabilizer measurement circuit has an error in the middle of the time slot, it is verified whether the measurement circuit corresponding to the various time slot sequence combinations of the X-type stabilizer and the Z-type stabilizer in step (3) can eventually be immune to logical errors: If there is a time slot sequence in the verified time slot sequence combinations that introduces a logical error of the same type as the stable sub-type or the introduced error can be equivalent to a shorter error chain, then the time slot sequence combination is not a stable sub-time slot sequence immune to logical errors, and the process returns to step (3) to reselect the time slot combination; If the slot sequences in the verified slot sequence combinations can avoid introducing logical errors of the same type as the stabilizer and the introduced errors cannot be equivalent to shorter error chains, then the arrangement of the key slots of the stabilizer in verification (2) is accurate, and the slots of the stabilizer are set according to their slot sequence in the quantum surface code calculation process to reduce the logical error rate of the overall quantum circuit.

2. The method according to claim 1, characterized in that In 2a), according to the stable sub measurement circuit that introduces the logical error time slot sequence, the principle that two bits involved in the same type of logical operation in the stable sub cannot be placed in the first half time slot or the second half time slot at the same time is set, which is implemented as follows: 2a1) The arrangement of the error time slots in the X-stable sub-measurement of the line for determining the order of the logical error time slots is to set the CNOT gates of the two data bits in the logical X operation direction in the second half of the line; 2a2) The arrangement of the error time slots in the Z-stable sub-measurement of the line for determining the order of the logic error time slots is to set the CNOT gates of the two data bits in the logic Z operation direction in the second half of the line; 2a3) Based on the above determination that the arrangement of the error time slots in the X stabilizer and the Z stabilizer will introduce the same type of logic error conditions, the CNOT gates of the two data bits in the same direction as the logic X operation in the X stabilizer are respectively arranged in the first half and the second half of the measurement circuit; The CNOT gates of the two data bits in the same direction as the logic Z operation in the Z stabilizer are respectively arranged in the first half and the second half of the measurement circuit.

3. The method according to claim 1, characterized in that In step (4), it is verified whether the measurement lines corresponding to the various time slot sequence combinations of the X-type stabilizer and the Z-type stabilizer in step (3) can avoid introducing the same type of logical errors and whether the errors introduced can be equivalent to a shorter error chain, which is implemented as follows: 4a) According to the time slot combination in step (3), set the CNOT gate sequence of the X stabilizer and Z stabilizer measurement circuits; 4b) adding an X error at the middle of the X-stable sub-measurement line and adding a Z error at the middle of the Z-stable sub-measurement line; 4c) Determine the position of the data bit error of the surface code according to the position of the error in 4b), and perform correction operation by the surface code model: If the correction operation of the surface code and the error data bit are added together to equal the logic operation, it indicates that the time slot sequence has a similar logic error introduced by the auxiliary bit error in the middle of the time slot; If the sum of the correction operation of the surface code and the erroneous data bit is not equal to the logical operation, it means that the time slot sequence can avoid the same kind of logical error introduced by the auxiliary bit error in the middle of the time slot.

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