LED chip and light emitting device
By adjusting the welding electrode structure in GaN-based flip-chip semiconductor diodes and employing a stress buffer layer design with multiple aluminum and titanium metal layers, the problem of chip detachment on flexible substrates was solved, improving the reliability and stability of the chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUBEI SANAN OPTOELECTRONICS CO LTD
- Filing Date
- 2022-09-07
- Publication Date
- 2026-07-24
AI Technical Summary
Existing GaN-based flip-chip semiconductor diodes are prone to chip detachment on flexible substrates due to stress in the nickel metal layer. The existing stress buffer layer design is insufficient and cannot meet reliability requirements.
By adjusting the welding electrode structure, a stress buffer layer design with multiple aluminum and titanium metal layers is adopted. The aluminum metal layer closest to the nickel metal layer is thicker than the other layers. Combined with the protection of the gold metal layer, the adhesion and stress buffering capacity of the solder pads are enhanced.
It effectively buffers external stress, preventing the chip from falling off when the flexible substrate is bent, thus improving the chip's reliability and stability.
Smart Images
Figure CN116053389B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor light-emitting devices, and more particularly to an LED chip and a light-emitting device. Background Technology
[0002] GaN-based flip-chip diodes (LED chips) have advantages such as good heat dissipation, high luminous efficiency, and good stability, and are increasingly favored by the market. High-voltage chips can simplify the driving power supply. Combining the two can bring out even greater advantages.
[0003] GaN-based flip-chip semiconductor diodes (LED chips) include a semiconductor light-emitting layer and two pads with different electrical properties on the semiconductor light-emitting layer. The pads are used to mount the chip on a circuit board to form a packaged product by using solder paste and reflow soldering process, or to make a tin metal layer on the surface of the pads and mount it on the circuit board by reflow soldering.
[0004] The solder pads typically also include a nickel layer. This serves two purposes: firstly, it forms a eutectic with the tin after reflow soldering to connect the chip to the circuit board; secondly, the nickel layer needs to be thick enough to prevent tin from diffusing into the chip. However, this nickel layer experiences significant stress.
[0005] During use, it was found that the physical stress generated by the nickel metal layer during bending of highly flexible substrates can cause chips to detach. Since the chip's electrode pads are directly bonded to the substrate, optimization and improvement of the chip's electrode pads are necessary to mitigate the stress impact on the chip during flexible substrate bending, prevent detachment, and increase chip reliability.
[0006] Existing technologies also propose setting up stress buffer layers to buffer the stress of nickel layers. However, the existing stress buffer layers cannot achieve the best stress buffering effect and are difficult to meet the reliability requirements of chip mounting on highly flexible substrates. Summary of the Invention
[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an LED chip that solves the problem of easy detachment when bonded to a flexible substrate in the prior art. This invention improves the chip's resistance to detachment by changing the structure of the welding electrodes and modifying the internal design of the stress buffer layer, thereby better buffering the impact of external stress on the chip.
[0008] To achieve the above and other related objectives, the present invention provides an LED chip, the LED chip comprising:
[0009] Emitting epitaxial layer;
[0010] A first insulating layer covers the top of the light-emitting epitaxial layer and around the sidewalls, and the first insulating layer has a plurality of through holes;
[0011] A first pad and a second pad with opposite electrical polarities are located on the first insulating layer and fill the through-holes of the first insulating layer to electrically connect the light-emitting epitaxial layer.
[0012] The first pad and the second pad include a stress buffer layer and a nickel metal layer stacked sequentially from bottom to top; the stress buffer layer includes multiple aluminum metal layers, and the thickness of the aluminum metal layer closest to the nickel metal layer is greater than the thickness of each of the other aluminum metal layers.
[0013] Optionally, the stress buffer layer includes alternating layers of aluminum and titanium.
[0014] Optionally, the thickness of the nickel metal layer is 200–1200 nm, and more preferably, the thickness of the nickel metal layer is 500–1200 nm.
[0015] Optionally, the first pad and the second pad may further include a protective layer stacked on the nickel metal layer, wherein the protective layer is a gold metal layer.
[0016] Optionally, the titanium metal layer of each layer is 60-300 nm.
[0017] Optionally, the thickness of each aluminum metal layer is 300-2000 nm.
[0018] Optionally, the stress buffer layer includes 3 to 5 pairs of periodically arranged titanium and aluminum metal layers.
[0019] Optionally, the ratio of the thickness of a titanium layer to the thickness of an aluminum layer in each cycle of the stress buffer layer is less than or equal to 1:3.
[0020] Optionally, the stress buffer layer includes an aluminum metal layer closest to the nickel metal layer with a thickness ratio greater than or equal to 1:1.
[0021] Optionally, the thickness of the titanium metal layer most closely adjacent to the nickel metal layer is greater than the thickness of each of the remaining titanium metal layers.
[0022] Optionally, a titanium metal layer is in contact with the nickel metal layer.
[0023] Optionally, the nickel metal layer may also have a tin metal layer.
[0024] Optionally, the aluminum metal layer closest to the nickel metal layer is the thickest, and the remaining aluminum metal layers are of equal thickness.
[0025] Alternatively, the thickness of the aluminum metal layer gradually increases when viewed from a direction that gradually approaches the nickel metal layer.
[0026] The present invention also provides an LED chip, the LED chip comprising:
[0027] Emitting epitaxial layer;
[0028] A first insulating layer covers the top of the light-emitting epitaxial layer and around the sidewalls, and the first insulating layer has a plurality of through holes;
[0029] A first pad and a second pad with opposite electrical polarities are located on the first insulating layer and fill the through-holes of the first insulating layer to electrically connect the light-emitting epitaxial layer.
[0030] The first pad and the second pad include a stress buffer layer and a nickel metal layer stacked sequentially from bottom to top; the stress buffer layer includes several pairs of periodically arranged aluminum metal layers and titanium metal layers, and the thickness of the titanium metal layer closest to the nickel metal layer is greater than the thickness of each of the other titanium metal layers.
[0031] Optionally, the thickness of the nickel metal layer is 200–1200 nm.
[0032] Optionally, the thickness of the nickel metal layer is 500–1200 nm.
[0033] Optionally, the first pad and the second pad may further include a protective layer stacked on the nickel metal layer, wherein the protective layer is a gold metal layer.
[0034] Optionally, the titanium metal layer of each layer is 60-300 nm.
[0035] Optionally, the thickness of each aluminum metal layer is 300-2000 nm.
[0036] Optionally, the stress buffer layer includes 3 to 5 pairs of periodically arranged titanium and aluminum metal layers.
[0037] Optionally, the ratio of the thickness of a titanium layer to the thickness of an aluminum layer in each cycle of the stress buffer layer is less than or equal to 1:3.
[0038] Optionally, a titanium metal layer is in contact with the nickel metal layer.
[0039] Optionally, the nickel metal layer may also have a tin metal layer.
[0040] The present invention also provides a light-emitting device, which includes an LED chip as described above.
[0041] As described above, the present invention provides an LED chip and a light-emitting device. The LED chip includes a light-emitting epitaxial layer, a first insulating layer covering the light-emitting epitaxial layer, and a first pad and a second pad located on the first insulating layer. The first pad and the second pad include a stress buffer layer, a nickel metal layer, and a protective layer. The stress buffer layer comprises multiple aluminum metal layers. The present invention thickens the aluminum metal layers by adjusting their thickness distribution, particularly ensuring that the thickness of the aluminum metal layer closest to the nickel metal layer is greater than or equal to the thickness of the nickel metal layer. This utilizes the ductility and tensile strength of aluminum to act as a stress buffer. Its ductility can effectively withstand the stress impact caused by substrate bending, preventing electrode breakage or detachment and increasing reliability. The titanium metal layer between the aluminum metal layer closest to the nickel metal layer is the thickest, enhancing adhesion and protection. Attached Figure Description
[0042] Figure 1 The diagram shown is a structural schematic of the LED chip in this invention.
[0043] Figure 2 Displayed as Figure 1 Enlarged schematic diagram of region A in the middle.
[0044] Figure 3 The diagram shows the structure of an LED chip with two sub-chips.
[0045] Figures 4-9 The diagram shows the manufacturing process of LED chips.
[0046] Component designation explanation
[0047] 11 First contact electrode
[0048] 12 First pad
[0049] 21 Second contact electrode
[0050] 22 Second pad
[0051] 23 Transparent conductive layer
[0052] 24 Barrier Layers
[0053] 31 Interconnect electrodes
[0054] 33 Transparent conductive layer
[0055] 34. Barrier layer
[0056] 40 trenches
[0057] 101 substrate
[0058] 102 Light-emitting epitaxial layer
[0059] 103 First Insulation Layer
[0060] 104 Second Insulation Layer
[0061] 110 First countertop
[0062] 220 Adhesive Layer
[0063] 221 Stress Buffer Layer
[0064] 222 Nickel metal layer
[0065] 223 Protective Layer
[0066] 1021 First conductivity type semiconductor layer
[0067] 1023 Active Layer
[0068] 1022 Second type of conductivity semiconductor layer
[0069] 2212 Titanium metal layer
[0070] 2211 Aluminum Metal Layer Detailed Implementation
[0071] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0072] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0073] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.
[0074] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0075] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0076] Example 1
[0077] like Figures 1-2 As shown, this embodiment provides an LED chip, specifically including:
[0078] 102 light-emitting epitaxial layer;
[0079] A first insulating layer 103 covers the top of the light-emitting epitaxial layer 102 and around the sidewalls, and the first insulating layer 103 has a plurality of through holes;
[0080] The first pad 12 and the second pad 22, which are electrically opposite, are located on the first insulating layer 103 and fill the through-holes of the first insulating layer 103 to electrically connect the light-emitting epitaxial layer 102.
[0081] The first pad 12 and the second pad 22 include an adhesive layer 220, a stress buffer layer 221, a nickel metal layer 222, and a protective layer 223 stacked from bottom to top.
[0082] The layer in contact with the first insulating layer 103 is an adhesive layer, specifically a titanium metal layer. The adhesive layer primarily serves an adhesive function, ensuring stable adhesion of the solder pads to the first insulating layer 103. The thickness of the adhesive layer is between 0.1 and 10 nm, allowing for a certain degree of light transmittance.
[0083] Furthermore, the stress buffer layer 221 includes several pairs of periodically arranged aluminum metal layers 2211 and titanium metal layers 2212, with the aluminum metal layers 2211 and titanium metal layers 2212 stacked alternately. The titanium metal layer 2212 is in contact with the nickel metal layer 222, and the aluminum metal layer 2211 is in contact with the adhesive layer. The thickness of the aluminum metal layer 2211 closest to the nickel metal layer 222 is greater than the thickness of each of the other aluminum metal layers.
[0084] The nickel metal layer 222 comprises nickel metal, and the protective layer 223 comprises a gold metal layer. The stress buffering effect of the aluminum and titanium layers on the nickel metal layer (nickel layer) reduces the risk of excessive stress on the nickel metal layer causing the solder pads to easily detach. The aluminum layer needs a layered design; the aluminum layer in contact with the adhesive layer can act as a reflective layer. More preferably, 3-5 pairs of periodically arranged aluminum metal layers 2211 and titanium metal layers 2212, with one aluminum layer serving as a reflective layer and the remaining aluminum layers being at least two layers, prevent each aluminum layer from being too thick, which could lead to unstable aluminum migration performance.
[0085] Even better, except for the aluminum metal layer closest to the nickel metal layer which is the thickest, the thickness of each of the other aluminum metal layers is equal.
[0086] Or better yet, the thickness of the aluminum metal layer gradually increases when viewed from the direction that gradually approaches the nickel metal layer.
[0087] The titanium layer can protect the aluminum layer between the aluminum and nickel layers, while also acting as a stress transition between the aluminum and nickel layers. It can also act as an adhesive, allowing the nickel layer to adhere stably to the underlying layers.
[0088] The layer in contact with the adhesive layer is an aluminum metal layer 2211, and there is a titanium metal layer 2212 between the nickel metal layer and the aluminum layer closest to the nickel metal layer.
[0089] More preferably, the thickness of the titanium metal layer 2211 closest to the nickel metal layer 222 is greater than the thickness of the other titanium metal layers, so as to provide sufficient adhesion and protection.
[0090] The nickel metal layer 222 serves two purposes: firstly, it is used to bond a portion of the nickel metal layer with tin to form a eutectic alloy during soldering of the diode and the driver substrate using solder paste, typically through a combination of solder paste and reflow soldering; secondly, the nickel metal layer 222 also prevents tin from penetrating into other metal layers (especially the stress buffer layer 221) and causing melting and damage. Before the LED chip is mounted on the packaging substrate, the protective layer 223 protects the nickel metal layer 222 from oxidation.
[0091] Furthermore, the thickness of the nickel metal layer is 200-1200 nm. If the substrate is a flexible substrate, for example, if the reflow soldering is performed twice, the thickness of the nickel layer can be appropriately increased to increase the thickness of the eutectic layer formed by nickel and tin and improve the die bonding capability. For example, the thickness of the nickel layer is 500 nm-1200 nm, for example, greater than 550 nm, for example, 550-1000 nm, and more preferably 600-800 nm, to ensure that it can fully bond with the tin layer during soldering and to prevent the tin layer from penetrating into other metal layers.
[0092] Further, the stress buffer layer 221 preferably comprises 2-5 pairs of periodically arranged aluminum metal layers 2211 and titanium metal layers 2212. Each titanium metal layer has a thickness of 60-300 nm. More preferably, the titanium metal layer 2212 closest to the nickel metal layer 222 has a thickness of 100-300 nm, and the thickness of each of the remaining titanium metal layers 2212 is 50-150 nm. Each aluminum metal layer 2211 has a thickness of 300-2000 nm. More preferably, the aluminum metal layer 2211 closest to the nickel metal layer 222 has a thickness of 800-2000 nm, and the thickness of each of the remaining aluminum metal layers 2211 is 300-1500 nm.
[0093] In one implementation, among the three pairs of periodically arranged aluminum metal layers 2211 and titanium metal layers 2212, the thickness of each of the two titanium metal layers is 120 nm, and the thickness of the last titanium layer is 150 nm; the thickness of the aluminum metal layer 2211 closest to the nickel metal layer 222 is 1500 nm, and the thickness of each of the remaining aluminum metal layers 2211 is 550 nm.
[0094] More preferably, the aluminum layer can also be appropriately increased, or even greater than or equal to the thickness of the nickel metal layer 222, to improve the buffering capacity.
[0095] Specifically, because aluminum has good ductility and tensile strength, by adjusting the thickness distribution of the aluminum layers, the aluminum metal layer 2211 closest to the nickel metal layer is set to be the thickest, and the titanium metal layer between the aluminum metal layer closest to the nickel metal layer and the nickel metal layer is also the thickest. This can enhance adhesion and protection, thereby better playing a stress buffering role. After the diode is combined with the flexible substrate, its own ductility can withstand the stress impact caused by substrate bending, avoiding electrode breakage or detachment and increasing reliability.
[0096] In the above scheme, the effect is better when the thickness of the aluminum metal layer 2211 closest to the nickel metal layer 222 exceeds that of the nickel metal layer. It should be understood that... Figure 1 The image only illustrates the location of the solder pads; in reality, solder pads are not plug-like structures, but rather more like... Figure 2 The layered structure in it. Figure 2 The image only shows the structure of the second pad; the structure of the first pad is the same as that of the second pad.
[0097] Specifically, the light-emitting epitaxial layer 102 includes a first conductivity type semiconductor layer 1021, an active layer 1023, and a second conductivity type semiconductor layer 1022 stacked sequentially. The first pad 12 is electrically connected to the first conductivity type semiconductor layer 1021, and the second pad 22 is electrically connected to the second conductivity type semiconductor layer 1022. The light-emitting epitaxial layer 102 is formed on a substrate 101, which can be made of a transparent, semi-transparent, or non-transparent material. For example, it can be any one of silicon carbide, silicon, magnesium aluminum oxide, magnesium oxide, gallium nitride, and sapphire. In this embodiment, the substrate 101 is preferably a sapphire substrate 101. The upper surface of the substrate 101 can have a patterned structure (i.e., the protrusions shown in the figure), which can improve the external light extraction efficiency and the crystal quality of the epitaxial layer constituting the light-emitting epitaxial layer 102. As an example, the patterned structure on the upper surface of the substrate 101 can be formed in various shapes, such as a cone, a triangular pyramid, a hexagonal pyramid, or a quasi-conical shape.
[0098] The first pad 12 is electrically connected to the first mesa 110 on the surface of the first conductivity type semiconductor layer 1021. This is a common structure in LED chips, typically obtained after epitaxy by etching a portion of the second conductivity type semiconductor layer 1022 and the active layer 1023. The first mesa 110 removes a portion of the second conductivity type semiconductor layer 1022 and the active layer 1023, exposing a portion of the upper surface of the first conductivity type semiconductor layer 1021. There can be multiple first mesa 110s, and each first mesa 110 can be located inside the light-emitting epitaxial layer 102, at the edge of the light-emitting epitaxial layer 102, or simultaneously at both the interior and edge of the light-emitting epitaxial layer 102 for electrode connection.
[0099] Furthermore, the first insulating layer 103 has a reflective function, used to reflect the light emitted by the active layer 1023. The first insulating layer 103 can be a DBR structure. As an example, the first insulating layer 103 includes at least one of SiO2, SiN, SiOxNy, TiO2, Si3N4, Al2O3, TiN, and AlN. In this embodiment, a DBR structure is used as an example. DBR (distributed Bragg reflection) is a periodic structure composed of two materials with different refractive indices arranged alternately in an ABAB pattern, such as an alternating arrangement of TiO2 and SiO2. When the first insulating layer 103 is selected as a DBR layer, the thickness is preferably more than 1 micrometer. Optionally, in this embodiment, a second insulating layer 104 is also formed on the lower surface of the substrate 101, thereby forming reflection both above and below the epitaxial layer, allowing light to exit from the side. Similar to the first insulating layer 103, the second insulating layer 104 also has a reflective function and can be a DBR structure. In addition, the first insulating layer 103 must also ensure good insulation performance to block conductive materials of different polarities in the LED chip.
[0100] Furthermore, a first contact electrode 11 is provided between the first pad 12 and the light-emitting epitaxial layer 102, and a second contact electrode 21 is provided between the second pad 22 and the light-emitting epitaxial layer 102. The first contact electrode 11 and the second contact electrode 21 can be metal electrodes, such as one or any combination of nickel, gold, chromium, titanium, platinum, palladium, chromium, argon, aluminum, tin, indium, zinc, copper, cobalt, iron, tungsten, molybdenum. As a preferred embodiment, both the first contact electrode 11 and the second contact electrode 21 include a base layer (e.g., Cr), a reflective layer (e.g., Al) on the base layer, and a capping layer (e.g., Ti, Pt, or Ni) on the reflective layer. The base layer ensures ohmic contact between the contact electrode and the light-emitting epitaxial layer 102, and the thickness of the base layer is less than 10 nm, thereby avoiding any impact on reflectivity.
[0101] Furthermore, a barrier layer 24 and a transparent conductive layer 23 are provided between the second contact electrode 21 and the light-emitting epitaxial layer 102 (second conductivity type semiconductor layer 1022). The barrier layer 24 is sandwiched between the light-emitting epitaxial layer 102 and the transparent conductive layer 23. The second contact electrode 21 and the barrier layer 24 (also known as CB, i.e., current block) are vertically aligned, meaning that the projection of the second contact electrode 21 onto the barrier layer 24 is located inside the barrier layer 24. The barrier layer 24 serves to block current, preventing current congestion directly below the second contact electrode 21 and causing the current to spread out. The transparent conductive layer 23 serves as a channel for current flow. This design allows current to flow through the transparent conductive layer 23 across the entire surface of the second conductivity type semiconductor layer 1022, preventing current congestion and ensuring that the current spreads as widely as possible across the surface of the second conductivity type semiconductor layer 1022 to improve luminous efficiency. As an example, the barrier layer 24 can be SiO2, Si3N4, SiON, or a composite structure thereof. The transparent conductive layer 23 may include at least one of indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO). In this embodiment, the transparent conductive layer 23 is preferably an ITO (indium tin oxide semiconductor transparent conductive film) layer formed by vapor deposition or sputtering process.
[0102] Table 1 below shows the control experiment. In the three control groups, only the thickness of the aluminum metal layer of the stress buffer layer was adjusted, and the tests were conducted under the same thermal shock conditions. Specifically, the chip was die-bonded onto the FPC flexible circuit board by applying solder paste and reflow soldering. Thermal shock was performed between -45℃ and 125℃ with a transition time of 10 seconds. After long-term testing for 1008 hours (H is hours) and 2016 hours, the percentage of solder pads falling off was observed as the defect rate. The number of chips tested was 300.
[0103] The experimental results show that, compared to Comparative Example 1, Comparative Example 2, by increasing the thickness of each aluminum layer in the stress buffer layer, significantly reduced the defect rate under thermal shock. Comparative Example 3, compared to Comparative Example 1, only increased the thickness of the aluminum layer closest to the nickel layer, resulting in a defect rate of 0 under thermal shock, demonstrating an even more significant reduction. This indicates that increasing the thickness of the aluminum layer to be greater than that of the nickel layer allows the aluminum's ductility and tensile strength to better buffer stress, preventing electrode breakage or detachment. In particular, thickening the aluminum layer closest to the nickel layer achieves even better anti-detachment effects.
[0104] Table 1
[0105]
[0106]
[0107] Example 2
[0108] This embodiment also provides an LED chip, which is similar to the LED chip in Embodiment 1, except that the light-emitting epitaxial layer 102 is divided into multiple sub-chips and interconnected, such as... Figure 3 As shown, the LED chip specifically includes:
[0109] The light-emitting epitaxial layer 102 is divided into n sub-chips arranged in sequence, including a first sub-chip, a second sub-chip, ..., an nth sub-chip, where 2 ≤ n; adjacent sub-chips are separated by trenches 40 penetrating the light-emitting epitaxial layer 102, and adjacent sub-chips are electrically connected by interconnecting electrodes 31.
[0110] Further, the interconnect electrode 31 is connected from the second conductivity type semiconductor layer 1022 of the k-th sub-chip to the first conductivity type semiconductor layer 1021 of the (k+1)-th sub-chip via the trench 40, where 1≤k≤n-1. The first pad 12 is electrically connected to the first conductivity type semiconductor layer 1021 of the first sub-chip, and the second pad 22 is electrically connected to the second conductivity type semiconductor layer 1022 of the n-th sub-chip.
[0111] Specifically, such as Figure 3 The diagram shows the structure corresponding to n=2. The interconnect electrode 31 is connected from the second conductivity type semiconductor layer 1022 of the first sub-chip to the first conductivity type semiconductor layer 1021 of the second sub-chip via the trench 40. It should be understood that the structure for n=3, 4, ... is similar, only requiring the interconnect electrode 31 to be set between the k-th sub-chip and the (k+1)-th sub-chip. In this embodiment, the structure of the first pad 12 and the second pad 22 is the same as in Embodiment 1. At the same time, the first contact electrode 11, the second contact electrode 21, the barrier layer 24, and the transparent conductive layer 23 can be set between the pad and the light-emitting epitaxial layer 102. For the specific structure, please refer to the relevant description in Embodiment 1 above, which will not be repeated here. The interconnect electrode 31 is made of the same material as the first contact electrode 11 or the second contact electrode 21, and preferably includes a bottom layer (e.g., Cr), a reflective layer on the bottom layer (e.g., Al), and a capping layer on the reflective layer (e.g., Ti, Pt, or Ni). The interconnect electrode 31 is fabricated simultaneously with the first contact electrode 11 and the second contact electrode 21.
[0112] Furthermore, a barrier layer 34 is provided between the interconnect electrode 31 and the light-emitting epitaxial layer 102, and a transparent conductive layer 33 is provided between the barrier layer 34 on the second conductivity type semiconductor layer 1022 of the kth sub-chip and the light-emitting epitaxial layer 102.
[0113] Specifically, similar to the barrier layer 34 and transparent conductive layer 33 in Embodiment 1, the barrier layer 34 is sandwiched between the light-emitting epitaxial layer 102 and the interconnect electrode 31. The interconnect electrode 31 and the barrier layer 34 (also known as CB, i.e., current block) are vertically aligned, meaning the projection of the interconnect electrode 31 onto the barrier layer 34 is located inside the barrier layer 34. The barrier layer 34 serves to block current, preventing current congestion directly below the interconnect electrode 31 and causing the current to spread out. The transparent conductive layer 33 serves as a channel for current flow. This design allows current to flow through the transparent conductive layer 33 across the entire surface of the third conductivity type semiconductor layer, preventing current congestion and ensuring that the current spreads as much as possible across the surface of the second conductivity type semiconductor layer 1022, thereby improving luminous efficiency. As an example, the barrier layer 34 can be SiO2, Si3N4, SiON, or a composite structure thereof. The transparent conductive layer 33 may include at least one of indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO). In this embodiment, the transparent conductive layer 33 is preferably an ITO (indium tin oxide semiconductor transparent conductive film) layer formed by vapor deposition or sputtering process.
[0114] See Figures 4-9 The LED chip fabrication method described in this embodiment specifically includes the following steps:
[0115] Etching the second conductivity type semiconductor layer 1022 and the active layer 1023 forms the first mesa 110, as shown below. Figure 5 As shown;
[0116] Next, the first conductive semiconductor layer 1021 is etched further at the first mesa 110 to form a trench 40 penetrating the light-emitting epitaxial layer 102, thereby dividing the light-emitting epitaxial layer 102 into multiple sub-chips, such as... Figure 6 As shown;
[0117] Next, the barrier layer 24 and barrier layer 34 are formed simultaneously, as follows: Figure 7 As shown;
[0118] Next, the transparent conductive layer 23 and the transparent conductive layer 33 are formed simultaneously, such as... Figure 8As shown;
[0119] Next, the interconnect electrode 31, the first contact electrode 11, and the second contact electrode 21 are formed simultaneously, as follows: Figure 9 As shown;
[0120] Next, the first insulating layer 103 is formed, and through-holes are formed in the first insulating layer 103. Finally, the first pad 12 and the second pad 22 are formed on the first insulating layer 103, as follows. Figure 3 As shown.
[0121] Example 3
[0122] In the above embodiments, each nickel metal layer serves as an independent solder layer. As another implementation, the first solder pad 12 and the second solder pad 22, in addition to the nickel metal layer, also include a tin metal layer, meaning the nickel metal layer and the tin metal layer together form the solder layer. Optionally, the thickness of the tin metal layer is 4–30 micrometers, and the tin metal layer is located above the nickel metal layer. The tin metal layer eliminates the need for solder paste application when mounting the chip on the substrate.
[0123] In summary, this invention provides an LED chip and a light-emitting device. The LED chip includes a light-emitting epitaxial layer, a first insulating layer covering the light-emitting epitaxial layer, and first and second pads located on the first insulating layer. The first and second pads include a stress-buffered layer, a nickel metal layer, and a protective layer. The stress-buffered layer comprises multiple aluminum metal layers. This invention adjusts the thickness distribution of the aluminum layers, setting the layer closest to the nickel metal layer to be the thickest. Specifically, the thickness of the aluminum metal layer closest to the nickel metal layer is greater than or equal to the thickness of the nickel metal layer. This utilizes the ductility and tensile strength of aluminum to act as a stress buffer. After the diode is bonded to a flexible substrate, its own ductility can effectively withstand the stress impact caused by substrate bending, preventing electrode breakage or detachment and increasing reliability. The titanium metal layer between the aluminum metal layer closest to the nickel metal layer is the thickest, enhancing adhesion and protection.
[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. An LED chip, characterized in that, The LED chip includes: Light-emitting epitaxial layer; A first insulating layer covers the top of the light-emitting epitaxial layer and around the sidewalls, and the first insulating layer has a plurality of through holes; A first pad and a second pad with opposite electrical polarities are located on the first insulating layer and fill the through-holes of the first insulating layer to electrically connect the light-emitting epitaxial layer. The first pad and the second pad include a stress buffer layer and a nickel metal layer stacked sequentially from bottom to top; the stress buffer layer includes multiple aluminum metal layers, and the thickness of the aluminum metal layer closest to the nickel metal layer is greater than the thickness of each of the other aluminum metal layers.
2. The LED chip according to claim 1, characterized in that: The thickness of the nickel metal layer is 500-1200 nm, and the stress buffer layer includes alternating stacked aluminum and titanium metal layers.
3. The LED chip according to claim 1, characterized in that: The thickness of the nickel metal layer is 200–1200 nm.
4. The LED chip according to claim 1, characterized in that: The thickness of the nickel metal layer is 500–1200 nm.
5. The LED chip according to claim 1, characterized in that: The first pad and the second pad also include a protective layer stacked on the nickel metal layer, the protective layer being a gold metal layer.
6. The LED chip according to claim 2, characterized in that: Each titanium metal layer is 60-300nm in size.
7. The LED chip according to claim 1, characterized in that: The thickness of each aluminum metal layer is 300-2000nm.
8. The LED chip according to claim 2, characterized in that: The stress buffer layer comprises 3 to 5 pairs of periodically arranged titanium and aluminum metal layers.
9. The LED chip according to claim 2, characterized in that: The ratio of the thickness of a titanium layer to the thickness of an aluminum layer in each cycle of the stress buffer layer is less than or equal to 1:
3.
10. The LED chip according to claim 2, characterized in that: The stress buffer layer includes an aluminum metal layer closest to the nickel metal layer with a thickness ratio greater than or equal to 1:
1.
11. The LED chip according to claim 2, characterized in that: The thickness of the titanium metal layer closest to the nickel metal layer is greater than the thickness of each of the remaining titanium metal layers.
12. The LED chip according to claim 2, characterized in that: The nickel metal layer is in contact with a titanium metal layer.
13. The LED chip according to claim 2, characterized in that: There is also a tin metal layer on the nickel metal layer.
14. The LED chip according to claim 8, characterized in that: The aluminum metal layer closest to the nickel metal layer is the thickest, and the remaining aluminum metal layers are of equal thickness.
15. The LED chip according to claim 8, characterized in that: The thickness of the aluminum metal layer gradually increases when viewed from the direction that is gradually approaching the nickel metal layer.
16. An LED chip, characterized in that, The LED chip includes: Light-emitting epitaxial layer; A first insulating layer covers the top of the light-emitting epitaxial layer and around the sidewalls, and the first insulating layer has a plurality of through holes; A first pad and a second pad with opposite electrical polarities are located on the first insulating layer and fill the through-holes of the first insulating layer to electrically connect the light-emitting epitaxial layer. The first pad and the second pad include a stress buffer layer and a nickel metal layer stacked sequentially from bottom to top; the stress buffer layer includes several pairs of periodically arranged aluminum metal layers and titanium metal layers, and the thickness of the titanium metal layer closest to the nickel metal layer is greater than the thickness of each of the other titanium metal layers.
17. The LED chip according to claim 16, characterized in that: The thickness of the nickel metal layer is 200–1200 nm.
18. The LED chip according to claim 16, characterized in that: The thickness of the nickel metal layer is 500–1200 nm.
19. The LED chip according to claim 16, characterized in that: The first pad and the second pad also include a protective layer stacked on the nickel metal layer, the protective layer being a gold metal layer.
20. The LED chip according to claim 16, characterized in that: Each titanium metal layer is 60-300nm in size.
21. The LED chip according to claim 16, characterized in that: The thickness of each aluminum metal layer is 300-2000nm.
22. The LED chip according to claim 16, characterized in that: The stress buffer layer comprises 3 to 5 pairs of periodically arranged titanium and aluminum metal layers.
23. The LED chip according to claim 16, characterized in that: The ratio of the thickness of a titanium layer to the thickness of an aluminum layer in each cycle of the stress buffer layer is less than or equal to 1:
3.
24. The LED chip according to claim 16, characterized in that: The nickel metal layer is in contact with a titanium metal layer.
25. The LED chip according to claim 16, characterized in that: There is also a tin metal layer on the nickel metal layer.
26. A light-emitting device, characterized in that, Includes the LED chip as described in any one of claims 1-25.