Method for controlling HBS transceiver circuit, HBS transceiver circuit and chip

Abstract

The present invention discloses a HOMEBUS transceiver circuit, a method for controlling the HOMEBUS transceiver circuit, and a HOMEBUS transceiver chip, which are applicable to the field of power carrier communication. The receiving circuit is used to obtain a final signal by combining the signals output by two comparators when the positive and negative values ​​of the differential signals on the two HBS buses alternate, and the sending circuit is used to output the first input signal and the second input signal to the HBS bus. The transceiver circuit only uses relatively common and inexpensive separation devices, and completes data reception through a circuit unit that is combined with a comparator and a capacitive resistor device, replacing the receiving part of a dedicated chip, and uses software logic to control the H-bridge circuit built by cheap triodes to complete the functions of maintaining and reversing the transmission, replacing the transmission of the dedicated chip. Solve the bottleneck technology and facilitate the large-scale promotion and application of HBS technology.

Description

Technical Field

[0001] The present invention relates to the field of power line carrier communication, and in particular to a HOMEBUS transceiver circuit, a method for controlling the HOMEBUS transceiver circuit, and a HOMEBUS transceiver chip. Background Art

[0002] HOMEBUS can realize two-wire non-polar communication, is easy to install, the bus can carry load, and can achieve 8-40V power supply. When small facilities cannot guarantee power supply to the equipment end, power can be shared through transmission lines.

[0003] The existing HOMEBUS technology requires the use of expensive imported dedicated transceiver chips. This integrated chip cannot be used directly and needs to be added with a filtering auxiliary circuit, which increases the physical space and complexity of the entire circuit. Since the principle of the integrated chip is not transparent, chip damage caused by overload cannot be repaired by replacing low-cost components, but can only be replaced with a new chip, making the chip heavily dependent on import channels and delivery time, affecting the normal operation of the HOMEBUS circuit.

[0004] Therefore, it is an urgent problem for those skilled in the art to find a HOMEBUS transceiver circuit. Summary of the invention

[0005] The purpose of the present invention is to provide a HOMEBUS transceiver circuit, a method for controlling a HOMEBUS transceiver circuit and a HOMEBUS transceiver chip, so as to solve the bottleneck technology and facilitate the large-scale promotion and application of HBS technology.

[0006] In order to solve the above technical problems, the present invention provides a HOMEBUS transceiver circuit, which includes a receiving circuit, a sending circuit and a processor;

[0007] The receiving circuit at least includes a first receiving circuit and a second receiving circuit, two HBS buses are respectively connected to the voltage isolation capacitors and voltage divider resistors corresponding to the first receiving circuit and the second receiving circuit in sequence, the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the in-phase end and the inverting end of the first comparator, and the connection relationship between the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the second receiving circuit and the second comparator is opposite to that of the first comparator; the output end of the first comparator is connected to the output end of the second comparator, and the receiving circuit is used to obtain a final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses alternate;

[0008] The transmitting circuit at least comprises an H-bridge driving circuit and an isolation capacitor; the first input signal and the second input signal are respectively connected to the H-bridge driving circuit, the two output ends of the H-bridge driving circuit are respectively connected to the corresponding isolation capacitors, and the other ends of the corresponding isolation capacitors are respectively connected to the two HBS buses, and the transmitting circuit is used to output the first input signal and the second input signal to the HBS bus;

[0009] The processor is connected to the comparator output terminal of the receiving circuit, the first input signal and the second input signal of the sending circuit respectively.

[0010] Preferably, the voltage-dividing resistor includes a first voltage-dividing resistor and a second voltage-dividing resistor, the two HBS buses include a first HBS bus and a second HBS bus, and the other ends of the voltage-dividing resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the non-inverting end and the inverting end of the first comparator, including:

[0011] The other end of the voltage isolation capacitor corresponding to the first HBS bus side is respectively connected to one end of the first voltage-dividing resistor, one end of the second voltage-dividing resistor and the inverting end of the first comparator, the other end of the first voltage-dividing resistor is grounded, and the other end of the second voltage-dividing resistor is connected to a power supply;

[0012] The other end of the voltage isolation capacitor corresponding to the second HBS bus side is respectively connected to one end of the second voltage dividing resistor, one end of the first voltage dividing resistor and the non-inverting end of the first comparator.

[0013] Preferably, the first receiving circuit and the second receiving circuit further include a third voltage-dividing resistor;

[0014] The other end of the voltage isolation capacitor corresponding to the first HBS bus side is connected to one end of the third voltage dividing resistor, and the other end of the third voltage dividing resistor is respectively connected to one end of the first voltage dividing resistor, one end of the second voltage dividing resistor and the inverting end of the first comparator.

[0015] Preferably, the isolation capacitor includes a first isolation capacitor and a second isolation capacitor, and the H-bridge driving circuit includes:

[0016] The first input signal is connected to the base of the first transistor, the emitter of the first transistor is connected to the power supply, the collector of the first transistor is connected to the first isolation capacitor and to the collector of the third transistor, the emitter of the third transistor is grounded, and the base of the third transistor is connected to the second input signal;

[0017] The second input signal is connected to the base of the second transistor, the emitter of the second transistor is connected to the power supply, the collector of the second transistor is connected to the second isolation capacitor and to the collector of the fourth transistor, the emitter of the fourth transistor is grounded, and the base of the fourth transistor is connected to the first input signal.

[0018] Preferably, the transmitting circuit further includes a fifth transistor and a sixth transistor;

[0019] The emitter of the fifth transistor is connected to a power supply, the base of the fifth transistor is connected to the first input signal, and the collector of the fifth transistor is connected to the base of the fourth transistor;

[0020] The emitter of the sixth transistor is connected to a power supply, the base of the sixth transistor is connected to the second input signal, and the collector of the sixth transistor is connected to the base of the third transistor.

[0021] Preferably, the transmitting circuit further includes a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor and a fourth resistor;

[0022] One end of the first capacitor is grounded, and the other end is connected to the emitter of the fifth transistor and the emitter of the first transistor; one end of the second capacitor is grounded, and the other end is connected to the emitter of the second transistor and the emitter of the second transistor;

[0023] One end of the first resistor is connected to the base of the fifth transistor, and the other end is connected to the base of the first transistor; one end of the second resistor is connected to the base of the second transistor, and the other end is connected to the base of the sixth transistor; one end of the third resistor is connected to the collector of the sixth transistor, and the other end is connected to the base of the third transistor; the fourth resistor is connected to the collector of the fifth transistor, and the other end is connected to the base of the fourth transistor.

[0024] Preferably, the transmitting circuit further comprises a first diode and a second diode;

[0025] The anode of the first diode is connected to the anode of the second diode and is grounded, the cathode of the first diode is connected to the collector of the first transistor; and the cathode of the second diode is connected to the collector of the second diode.

[0026] In order to solve the above technical problems, the present invention further provides a method for controlling a HOMEBUS transceiver circuit, which is applied to the above HOMEBUS transceiver circuit, comprising:

[0027] Control the receiving circuit to obtain a final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses are alternating;

[0028] The transmitting circuit is controlled to output the first input signal and the second input signal to an HBS bus.

[0029] Preferably, when the differential signals of the two HBS buses are dominant, the control of the receiving circuit to obtain a final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses are alternating comprises:

[0030] Determine the signals output by the two comparators, wherein at least one of the output signals is a low level signal;

[0031] The signals output by the two comparators are subjected to an AND process to determine that the final signal is a low level.

[0032] Preferably, controlling the sending circuit to output the first input signal and the second input signal to the HBS bus includes:

[0033] When the first input signal and the second input signal are both at a high level, determining that the signal state of the first input signal and the second input signal is a transmission stop state, and outputting to the HBS bus is a recessive level;

[0034] When the first input signal or the second input signal is at a low level, the signal states of the first input signal and the second input signal are determined to be a differential transmission state, and a differential signal is output to the HBS bus.

[0035] In order to solve the above technical problem, the present invention further provides a HOMEBUS transceiver chip, comprising the above-mentioned HOMEBUS transceiver circuit.

[0036] The present invention provides a HOMEBUS transceiver circuit, which comprises a receiving circuit, a sending circuit and a processor; the receiving circuit comprises at least a first receiving circuit and a second receiving circuit, two HBS buses are respectively connected to voltage isolation capacitors and voltage divider resistors corresponding to the first receiving circuit and the second receiving circuit in sequence, the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the in-phase end and the inverting end of the first comparator, the connection relationship between the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the second receiving circuit and the second comparator is opposite to the connection relationship of the first comparator; the output end of the first comparator is connected to the output end of the second comparator; the sending circuit comprises at least an H-bridge driving circuit and an isolation capacitor; the first input signal and the second input signal are respectively connected to the H-bridge driving circuit, the two output ends of the H-bridge driving circuit are respectively connected to the corresponding isolation capacitors, and the other ends of the corresponding isolation capacitors are respectively connected to the two HBS buses. The receiving circuit in the transceiver circuit is used to obtain the final signal by the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses alternate, and the sending circuit is used to output the first input signal and the second input signal to the HBS bus, and the processor is respectively connected to the comparator output end of the receiving circuit and the first input signal and the second input signal of the sending circuit. In this application, the transceiver circuit only uses relatively common and inexpensive separation devices, and completes data reception through a circuit unit that combines a comparator with a capacitive resistor device, replacing the receiving part of the dedicated chip, and uses software logic to control the H-bridge circuit built by cheap triodes to complete the functions of maintaining and reversing the transmission, replacing the transmission of the dedicated chip. At the same time, there is no need for the logic circuit and driving circuit part of the filtering auxiliary circuit and the T trigger, which solves the bottleneck technology and facilitates the large-scale promotion and application of HBS technology.

[0037] In addition, the present invention also provides a method for controlling a HOMEBUS transceiver circuit and a HOMEBUS transceiver chip, which have the same beneficial effects as the above-mentioned HOMEBUS transceiver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 This is the working principle diagram of the existing transceiver chip MM1107;

[0040] Figure 2 A structural diagram of a HOMEBUS transceiver circuit provided in an embodiment of the present invention;

[0041] Figure 3A flow chart of a method for controlling a HOMEBUS transceiver circuit is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The core of the present invention is to provide a HOMEBUS transceiver circuit, a method and device for controlling the HOMEBUS transceiver circuit, and a HOMEBUS transceiver chip to solve the bottleneck technology and facilitate the large-scale promotion and application of HBS technology.

[0044] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0045] It should be noted that the existing HOMEBUS (HBS) transceiver circuits, such as MM1192 or MM1007 chips, Figure 1 The working principle diagram of the existing transceiver chip MM1107 is as follows: Figure 1 As shown, the received bus signal and differential signal enter the chip through capacitors C1 and C2. If the bus voltage suddenly changes (the bus voltage difference suddenly increases or decreases, which is dominant), the chip pin 1 outputs a low level, otherwise it outputs a high level (the bus voltage difference is stable, which is recessive). When sending, the input signal is operated to the chip pins 7 and 8 to control the bus output differential signal waveform. Mm1192 only needs a single pin signal input, and the internal trigger "register" gate circuit controls the output commutation.

[0046] Figure 2 A structural diagram of a HOMEBUS transceiver circuit provided in an embodiment of the present invention, such as Figure 2 As shown, the transceiver circuit includes a receiving circuit, a sending circuit and a processor;

[0047] The receiving circuit at least includes a first receiving circuit and a second receiving circuit, and two HBS buses are respectively connected to the voltage isolation capacitors and the voltage divider resistors corresponding to the first receiving circuit and the second receiving circuit in sequence, and the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the in-phase end and the inverting end of the first comparator, and the connection relationship between the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the second receiving circuit and the second comparator is opposite to that of the first comparator; the output end of the first comparator is connected to the output end of the second comparator, and the receiving circuit is used to obtain the final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses are alternating;

[0048] The sending circuit at least includes an H-bridge driving circuit and an isolation capacitor; the first input signal and the second input signal are respectively connected to the H-bridge driving circuit, the two output ends of the H-bridge driving circuit are respectively connected to the corresponding isolation capacitors, the other ends of the corresponding isolation capacitors are respectively connected to two HBS buses, and the sending circuit is used to output the first input signal and the second input signal to the HBS bus;

[0049] The processor is connected to the comparator output terminal of the receiving circuit, the first input signal and the second input signal of the sending circuit respectively.

[0050] It can be understood that the first receiving circuit is Figure 2 The receiving circuit 1 is a receiving circuit 2, and the second receiving circuit is Figure 2 Receiving circuit 2. The connection relationship between the two HBS buses of the two receiving circuits and the comparator is the same, and the difference is that the two HBS buses are connected to different non-inverting ends of the comparator. One end of the first HBS bus is connected to the first end of the voltage isolation capacitor, the second end of the voltage isolation capacitor is connected to the first end of the voltage divider resistor, and the second end of the voltage divider resistor is connected to the inverting end of the first comparator; one end of the second HBS bus is connected to the first end of the voltage isolation capacitor, the second end of the voltage isolation capacitor is connected to the first end of the voltage divider resistor, and the second end of the voltage divider resistor is connected to the non-inverting end of the first comparator.

[0051] There are two voltage isolation capacitors and two voltage divider resistors, respectively. As an embodiment, the voltage divider resistors include a first voltage divider resistor and a second voltage divider resistor, the two HBS buses include a first HBS bus and a second HBS bus, and the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the in-phase end and the inverting end of the first comparator, including:

[0052] The other end of the voltage isolation capacitor corresponding to the first HBS bus side is respectively connected to one end of the first voltage-dividing resistor, one end of the second voltage-dividing resistor and the inverting end of the first comparator, the other end of the first voltage-dividing resistor is grounded, and the other end of the second voltage-dividing resistor is connected to the power supply;

[0053] The other end of the voltage isolation capacitor corresponding to the second HBS bus side is respectively connected to one end of the second voltage-dividing resistor, one end of the first voltage-dividing resistor and the non-inverting end of the first comparator.

[0054] It can be understood that, taking the first receiving circuit as an example, the voltage isolation capacitor includes a first voltage isolation capacitor C1 and a second voltage isolation capacitor C2, the other end of the first HBS bus side connected to the first voltage isolation capacitor C1 is respectively connected to one end of the first voltage divider resistor R1, one end of the second voltage divider resistor R2 and the inverting end of the first comparator U1, the other end of the first voltage divider resistor R1 is grounded, and the other end of the second voltage divider resistor R2 is connected to the power supply; the other end of the second HBS bus side connected to the second voltage isolation capacitor C2 is respectively connected to one end of the second voltage divider resistor R3, one end of the first voltage divider resistor R4 and the in-phase end of the first comparator U1.

[0055] The voltage isolation capacitor realizes voltage isolation. The voltage divided by the resistor connected to the 6-pin (inverting end) of the first comparator will be slightly smaller than the voltage divided by the 5-pin (non-inverting end) (the voltage divider resistor on the 5+ and 6-pins can adjust the receiving sensitivity). In this way, when a differential signal appears on the bus, it is transmitted through the capacitor, causing the voltage on the first comparator 6- to be greater than the voltage on the first comparator 5+. The first comparator 7-pin outputs a low level. At this time, the second comparator will not output because the wiring is opposite to the first comparator, and it is in an open-drain state. It should be noted that the voltage isolation capacitor and the voltage divider resistor on the HBS bus are the same model. In terms of sensitivity, if there is a slight fluctuation interference on the bus, the common mode form will not be affected. If the sensitivity is reduced, it will be more, and it will not be triggered by mistake. When the threshold of the sensitivity is adjusted to a higher level, the effective data is weak and the real signal will not be captured.

[0056] As an embodiment, the first receiving circuit and the second receiving circuit further include a third voltage-dividing resistor;

[0057] The other end of the voltage isolation capacitor corresponding to the first HBS bus side is connected to one end of the third voltage dividing resistor, and the other end of the third voltage dividing resistor is respectively connected to one end of the first voltage dividing resistor, one end of the second voltage dividing resistor and the inverting end of the first comparator.

[0058] Specifically, there are four third voltage-dividing resistors in the two transceiver circuits, and each HBS bus side is connected to a third voltage-dividing resistor. The specific connection relationship is that in the first receiving circuit, the other end of the first HBS bus side connected to the first voltage isolation capacitor C1 is connected to one end of the third voltage-dividing resistor R5, and the other end of the third voltage-dividing resistor R5 is respectively connected to one end of the first voltage-dividing resistor R1, one end of the second voltage-dividing resistor R2 and the inverting end of the first comparator U1, the other end of the first voltage-dividing resistor R1 is grounded, and the other end of the second voltage-dividing resistor R2 is connected to the power supply, the other end of the second HBS bus side connected to the second voltage isolation capacitor C2 is connected to one end of the third voltage-dividing resistor R6, and the other end of the third voltage-dividing resistor R6 is respectively connected to one end of the second voltage-dividing resistor R3, one end of the first voltage-dividing resistor R4 and the in-phase end of the first comparator Y1.

[0059] In the second receiving circuit, the other end of the first voltage isolation capacitor C3 on the first HBS bus side is connected to one end of the third voltage-dividing resistor R11, the other end of the third voltage-dividing resistor R11 is respectively connected to one end of the first voltage-dividing resistor R7, one end of the second voltage-dividing resistor R8 and the in-phase end of the second comparator U2, the other end of the first voltage-dividing resistor R7 is grounded, the other end of the second voltage-dividing resistor R8 is connected to the power supply, the other end of the second HBS bus side is connected to the second voltage isolation capacitor C4 is connected to one end of the third voltage-dividing resistor R12, the other end of the third voltage-dividing resistor R12 is respectively connected to one end of the second voltage-dividing resistor R9, one end of the first voltage-dividing resistor R10 and the inverting end of the second comparator U2.

[0060] The third voltage-dividing resistor provides a common-mode range. If the third voltage-dividing resistor does not exist, the bus will be 2V grounded, and its HBS bus side will be reduced by 2V, providing a 1:1 reduction. If the third voltage-dividing resistor exists, a non-1:1 reduction is achieved, allowing the comparator to expand its detection range.

[0061] The connection relationship between the two comparators is such that the two comparators will not output low level at the same time, but will both output high level. Therefore, the HBS_RX level is the state of the output pin 7 of the first comparator and the output pin 1 of the second comparator. If at least one of them is low level, it is low level, otherwise it outputs high level signal. The circuit and principle of the second comparator are exactly the same as the first comparator circuit, the only difference is that the wiring at the input is opposite.

[0062] The role of the two receiving circuits: In practical applications, there are situations where the relative differential voltage is positive and negative alternately. Therefore, it is necessary to make judgment outputs for both situations, and it is also necessary to perform phase or sum of the two outputs to get a receiving pin.

[0063] In addition, if Figure 2As shown, the processor is connected to the output terminal HBS_RX of the comparator of the receiving circuit, and is connected to the first input signal HBS_TA and the second input signal HBS_TB of the transmitting circuit.

[0064] A HOMEBUS transceiver circuit provided by an embodiment of the present invention comprises a receiving circuit, a sending circuit and a processor; the receiving circuit comprises at least a first receiving circuit and a second receiving circuit, two HBS buses are respectively connected to the voltage isolation capacitors and the voltage divider resistors corresponding to the first receiving circuit and the second receiving circuit in sequence, the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the in-phase end and the inverting end of the first comparator, and the connection relationship between the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the second receiving circuit and the second comparator is opposite to the connection relationship of the first comparator; the output end of the first comparator is connected to the output end of the second comparator; the sending circuit comprises at least an H-bridge driving circuit and an isolation capacitor; the first input signal and the second input signal are respectively connected to the H-bridge driving circuit, the two output ends of the H-bridge driving circuit are respectively connected to the corresponding isolation capacitors, and the other ends of the corresponding isolation capacitors are respectively connected to the two HBS buses, and the processor is respectively connected to the comparator output end of the receiving circuit and the first input signal and the second input signal of the sending circuit. The receiving circuit in the transceiver circuit is used to obtain the final signal by ANDing the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses alternate, and the sending circuit is used to output the first input signal and the second input signal to the HBS bus. In this application, the transceiver circuit only uses relatively common and inexpensive separation devices, and completes data reception through a circuit unit that combines a comparator with a capacitive resistor device, replacing the receiving part of the dedicated chip, and uses software logic to control the H-bridge circuit built with cheap triodes to complete the maintenance and reversal of the transmission, replacing the transmission of the dedicated chip. At the same time, there is no need for the logic circuit and driving circuit part of the filtering auxiliary circuit and the T trigger, which solves the bottleneck technology and facilitates the large-scale promotion and application of HBS technology.

[0065] On the basis of the above embodiment, the isolation capacitor in the transmitting circuit includes a first isolation capacitor and a second isolation capacitor, and the H-bridge driving circuit includes:

[0066] The first input signal HBS_TA is connected to the base of the first transistor Q1, the emitter of the first transistor Q1 is connected to the power supply, the collector of the first transistor Q1 is connected to the first isolation capacitor C5, and is connected to the collector of the third transistor Q3, the emitter of the third transistor Q3 is grounded, and the base of the third transistor Q3 is connected to the second input signal HBS_TB;

[0067] The second input signal HBS_TB is connected to the base of the second transistor Q2, the emitter of the second transistor Q2 is connected to the power supply, the collector of the second transistor Q2 is connected to the second isolation capacitor C6 and to the collector of the fourth transistor Q4, the emitter of the fourth transistor Q4 is grounded, and the base of the fourth transistor Q4 is connected to the first input signal HBS_TA.

[0068] Specifically, the H-bridge driving circuit includes a first diode, a second transistor, a third transistor and a fourth transistor, and the connection relationship thereof is as described above. When the first input signal and the second input signal are both at a high level, the first transistor is not conducting, the second transistor is not conducting, and no signal is sent to the HBS bus. When the first input signal is at a low level, the first transistor is conducting, and the second HBS bus outputs. When the second input signal is at a high level, the second transistor is not conducting, and the first HBS bus has no output. When the first input signal is at a high level, the first transistor is not conducting, and the second HBS bus has no output. When the second input signal is at a low level, the second transistor is conducting, and the first HBS bus has an output.

[0069] As an embodiment, the transmitting circuit further includes a fifth transistor Q5 and a sixth transistor Q6;

[0070] The emitter of the fifth transistor Q5 is connected to the power supply, the base of the fifth transistor Q5 is connected to the first input signal HBS_TA, and the collector of the fifth transistor Q5 is connected to the base of the fourth transistor Q4;

[0071] An emitter of the sixth transistor Q6 is connected to a power supply, a base of the sixth transistor Q6 is connected to the second input signal HBS_TB, and a collector of the sixth transistor Q6 is connected to the base of the third transistor Q3.

[0072] Specifically, when the first input signal and the second input signal are both at high levels, the six transistors are all off, outb has no signal, and the first HBS bus and the second HBS bus have no output; when the first input signal is at a low level, the first transistor is turned on, the fifth transistor is turned on, the fourth transistor is turned on, the second HBS bus has output, the second input signal is at a high level, the second transistor, the sixth transistor, and the third transistor are all off, and the first HBS bus has no output. When the first input signal is at a high level, the first transistor and the fifth transistor are turned on, the fourth transistor is all off, and the second HBS bus has no output; the second input signal is at a low level, the second transistor, the sixth transistor, and the third transistor are turned on, and the first HBS bus has output.

[0073] As an embodiment, the sending circuit further includes a first capacitor C7, a second capacitor C8, a first resistor R13, a second resistor R14, a third resistor R15 and a fourth resistor R16;

[0074] One end of the first capacitor C7 is grounded, and the other end is connected to the emitter of the fifth transistor Q5 and the emitter of the first transistor Q1; one end of the second capacitor C8 is grounded, and the other end is connected to the emitter of the second transistor Q2 and the emitter of the second transistor Q2;

[0075] One end of the first resistor R13 is connected to the base of the fifth transistor Q5, and the other end is connected to the base of the first transistor Q1; one end of the second resistor R14 is connected to the base of the second transistor Q2, and the other end is connected to the base of the sixth transistor Q6; one end of the third resistor R15 is connected to the collector of the sixth transistor Q6, and the other end is connected to the base of the third transistor Q3; the fourth resistor R16 is connected to the collector of the fifth transistor Q5, and the other end is connected to the base of the fourth transistor Q4.

[0076] Specifically, the first capacitor and the second capacitor play a role of energy storage. The first capacitor, the second capacitor, the first resistor, the second resistor, the third resistor and the fourth resistor play a role of current limiting.

[0077] As an embodiment, the transmitting circuit further includes a first diode D1 and a second diode D2;

[0078] The anode of the first diode D1 is connected to the anode of the second diode D2 and is grounded. The cathode of the first diode D1 is connected to the collector of the first transistor Q1 ; the cathode of the second diode D2 is connected to the collector of the second transistor Q2 .

[0079] Specifically, the first diode and the second diode do not play a substantial role, but can protect the device and avoid damaging the subsequent circuit when there is a large fluctuation in the bus. The first diode and the second diode are added.

[0080] The transmitting circuit provided in this embodiment uses software logic to control the H-bridge circuit built by cheap triodes to complete the functions of maintaining and reversing the transmission, replacing the transmission of the dedicated chip. The transmitting circuit adopts a standard H-bridge driving circuit, and then the transmission is connected to the bus through the transmission capacitor.

[0081] Based on the above embodiments, Figure 3 A flowchart of a method for controlling a HOMEBUS transceiver circuit is provided for an embodiment of the present invention, and is applied to the above-mentioned HOMEBUS transceiver circuit. The method includes:

[0082] S11: When the positive and negative values ​​of the differential signals on the two HBS buses of the control receiving circuit are alternating, the signals output by the two comparators are ANDed to obtain the final signal;

[0083] S12: Control the sending circuit to output the first input signal and the second input signal to the HBS bus.

[0084] Specifically, the role of the two receiving circuits is: in practical applications, there are situations where the relative differential voltage is positive and negative alternately. Therefore, it is necessary to make judgment outputs for both situations, and it is also necessary to perform phase-OR on the two outputs to obtain a receiving pin. It should be noted that the two control processes of the receiving circuit and the transmitting circuit can be synchronized, or the differential signal of the transmitting circuit can be used for the receiving circuit, which is not limited here.

[0085] As an embodiment, when the differential signals of the two HBS buses are dominant, the control receiving circuit in step S11 obtains the final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses are alternating, including:

[0086] Determine the output signals of the two comparators, wherein at least one of the output signals has a low level signal;

[0087] The signals output by the two comparators are processed by AND and the final signal is determined to be a low level.

[0088] Specifically, the first voltage isolation capacitor, the voltage divided by the resistor connected to the first comparator 6-pin will be slightly smaller than the voltage divided on the 5-pin + (the voltage dividing resistors on the 5+ and 6-pins can adjust the receiving sensitivity). In this way, when a differential signal appears on the bus, it is transmitted through the capacitor, causing the voltage on the first comparator 6- to be greater than the voltage on the first comparator 5+. The first comparator 7-pin outputs a low level. At this time, the second comparator will not output because the wiring is opposite to the first comparator, and it is in an open drain state. Therefore, the HBS_RX level is the state of the first comparator output pin 7 and the second comparator output pin 1. At least one low level is a low level, otherwise a high level signal is output.

[0089] As an embodiment, the controlling sending circuit in step S12 to output the first input signal and the second input signal to the HBS bus includes:

[0090] When the first input signal and the second input signal are both at high levels, the signal states of the first input signal and the second input signal are determined to be a transmission stop state, and the output to the HBS bus is a recessive level;

[0091] When the first input signal or the second input signal is at a low level, the signal states of the first input signal and the second input signal are determined to be a differential transmission state, and the differential signal is output to the HBS bus.

[0092] Specifically, HBS_TA and HBS_TB are control output pins. When TA and TB are both high, it is the transmission stop state, the bus is at the invisible level, TA is low, TB is high, it is the differential transmission state 1, outa = 5v, outb = 0v, at this time HBS_1-HBS_2 is -5v compared to the invisible level. When TB is low and TA is high, it is the differential transmission state 1, outb = 5v, outa = 0v, at this time HBS_1-HBS_2 is +5v compared to the invisible level. Since the transmission adopts capacitor isolation, these two transmission states need to be operated alternately.

[0093] The method for controlling the HOMEBUS transceiver circuit provided in this embodiment uses only relatively common and inexpensive separation devices in the transceiver circuit, completes data reception through a circuit unit that combines a comparator with a capacitive resistor device, replaces the receiving part of a dedicated chip, and uses software logic to control the H-bridge circuit built with cheap triodes to complete the functions of maintaining and reversing transmission, replacing the transmission of a dedicated chip. At the same time, there is no need for the logic circuit and drive circuit part of the filtering auxiliary circuit and the T trigger, which solves the bottleneck technology and facilitates the large-scale promotion and application of HBS technology.

[0094] On the basis of the above-mentioned embodiment, an embodiment of the present invention provides a HOMEBUS transceiver chip, including the above-mentioned HOMEBUS transceiver circuit.

[0095] For an introduction to a HOMEBUS transceiver chip provided by the present invention, please refer to the above method embodiment, and the present invention will not be described in detail here. It has the same beneficial effects as the above HOMEBUS transceiver circuit.

[0096] The above is a detailed introduction to a HOMEBUS transceiver circuit, a method for controlling a HOMEBUS transceiver circuit, a device for controlling a HOMEBUS transceiver circuit, and a HOMEBUS transceiver chip provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0097] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A HOMEBUS transceiver circuit, characterized in that: The transceiver circuit includes a receiving circuit, a sending circuit and a processor; The receiving circuit at least includes a first receiving circuit and a second receiving circuit, two HBS buses are respectively connected to the voltage isolation capacitors and voltage divider resistors corresponding to the first receiving circuit and the second receiving circuit in sequence, the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the in-phase end and the inverting end of the first comparator, and the connection relationship between the other ends of the voltage divider resistors corresponding to the two HBS bus sides in the second receiving circuit and the second comparator is opposite to that of the first comparator; the output end of the first comparator is connected to the output end of the second comparator, and the receiving circuit is used to obtain a final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses alternate; The transmitting circuit at least comprises an H-bridge driving circuit and an isolation capacitor; the first input signal and the second input signal are respectively connected to the H-bridge driving circuit, the two output ends of the H-bridge driving circuit are respectively connected to the corresponding isolation capacitors, and the other ends of the corresponding isolation capacitors are respectively connected to the two HBS buses, and the transmitting circuit is used to output the first input signal and the second input signal to the HBS bus; The processor is connected to the comparator output terminal of the receiving circuit, the first input signal and the second input signal of the sending circuit respectively.

2. The HOMEBUS transceiver circuit according to claim 1, characterized in that: The voltage-dividing resistor includes a first voltage-dividing resistor and a second voltage-dividing resistor, the two HBS buses include a first HBS bus and a second HBS bus, and the other ends of the voltage-dividing resistors corresponding to the two HBS bus sides in the first receiving circuit are respectively connected to the in-phase end and the inverting end of the first comparator, including: The other end of the voltage isolation capacitor corresponding to the first HBS bus side is respectively connected to one end of the first voltage-dividing resistor, one end of the second voltage-dividing resistor and the inverting end of the first comparator, the other end of the first voltage-dividing resistor is grounded, and the other end of the second voltage-dividing resistor is connected to a power supply; The other end of the voltage isolation capacitor corresponding to the second HBS bus side is respectively connected to one end of the second voltage dividing resistor, one end of the first voltage dividing resistor and the non-inverting end of the first comparator.

3. The HOMEBUS transceiver circuit according to claim 2, characterized in that: The first receiving circuit and the second receiving circuit further include a third voltage-dividing resistor; The other end of the voltage isolation capacitor corresponding to the first HBS bus side is connected to one end of the third voltage dividing resistor, and the other end of the third voltage dividing resistor is respectively connected to one end of the first voltage dividing resistor, one end of the second voltage dividing resistor and the inverting end of the first comparator.

4. The HOMEBUS transceiver circuit according to claim 1, characterized in that: The isolation capacitor includes a first isolation capacitor and a second isolation capacitor, and the H-bridge driving circuit includes: The first input signal is connected to the base of the first transistor, the emitter of the first transistor is connected to the power supply, the collector of the first transistor is connected to the first isolation capacitor and to the collector of the third transistor, the emitter of the third transistor is grounded, and the base of the third transistor is connected to the second input signal; The second input signal is connected to the base of the second transistor, the emitter of the second transistor is connected to the power supply, the collector of the second transistor is connected to the second isolation capacitor and to the collector of the fourth transistor, the emitter of the fourth transistor is grounded, and the base of the fourth transistor is connected to the first input signal.

5. The HOMEBUS transceiver circuit according to claim 4, characterized in that: The transmitting circuit also includes a fifth transistor and a sixth transistor; The emitter of the fifth transistor is connected to a power supply, the base of the fifth transistor is connected to the first input signal, and the collector of the fifth transistor is connected to the base of the fourth transistor; The emitter of the sixth transistor is connected to a power supply, the base of the sixth transistor is connected to the second input signal, and the collector of the sixth transistor is connected to the base of the third transistor.

6. The HOMEBUS transceiver circuit according to claim 5, characterized in that: The transmitting circuit further includes a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor and a fourth resistor; One end of the first capacitor is grounded, and the other end is connected to the emitter of the fifth transistor and the emitter of the first transistor; one end of the second capacitor is grounded, and the other end is connected to the emitter of the second transistor and the emitter of the second transistor; One end of the first resistor is connected to the base of the fifth transistor, and the other end is connected to the base of the first transistor; one end of the second resistor is connected to the base of the second transistor, and the other end is connected to the base of the sixth transistor; one end of the third resistor is connected to the collector of the sixth transistor, and the other end is connected to the base of the third transistor; the fourth resistor is connected to the collector of the fifth transistor, and the other end is connected to the base of the fourth transistor.

7. The HOMEBUS transceiver circuit according to claim 6, characterized in that: The transmitting circuit also includes a first diode and a second diode; The anode of the first diode is connected to the anode of the second diode and is grounded, the cathode of the first diode is connected to the collector of the first transistor; and the cathode of the second diode is connected to the collector of the second diode.

8. A method for controlling a HOMEBUS transceiver circuit, characterized in that: The HOMEBUS transceiver circuit applied to claim 1 comprises: Control the receiving circuit to obtain a final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses are alternating; The transmitting circuit is controlled to output the first input signal and the second input signal to an HBS bus.

9. The method for controlling a HOMEBUS transceiver circuit according to claim 8, characterized in that: When the differential signals of the two HBS buses are dominant, the control of the receiving circuit to obtain a final signal by performing AND operation on the signals output by the two comparators when the positive and negative values ​​of the differential signals on the two HBS buses are alternating comprises: Determine the signals output by the two comparators, wherein at least one of the output signals is a low level signal; The signals output by the two comparators are subjected to an AND process to determine that the final signal is a low level.

10. The method for controlling a HOMEBUS transceiver circuit according to claim 8, characterized in that: Controlling the sending circuit to output the first input signal and the second input signal to the HBS bus, comprising: When the first input signal and the second input signal are both at a high level, determining that the signal states of the first input signal and the second input signal are in a transmission stop state, and outputting to the HBS bus is a recessive level; When the first input signal or the second input signal is at a low level, the signal states of the first input signal and the second input signal are determined to be a differential transmission state, and a differential signal is output to the HBS bus.

11. A HOMEBUS transceiver chip, characterized in that: The HOMEBUS transceiver circuit comprises any one of claims 1 to 7.

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