A MCU access system

Abstract

The application discloses an MCU access system, which comprises a cache memory and an MCU. The MCU is used for accessing a DDR memory through the cache memory. The cache memory is connected between the MCU and the DDR memory. The cache memory and the DDR memory are arranged outside the MCU. The cache memory is used for accessing the DDR memory in a burst transfer operation mode. The MCU is used for accessing the cache memory in a single transfer operation mode or in a burst transfer operation mode.

Description

Technical Field

[0001] This invention relates to the technical field of computer architecture and processor microarchitecture design, and specifically to an MCU access system. Background Technology

[0002] Microcontroller units (MCUs) are characterized by high real-time performance and rapid response, making them widely used in real-time operating systems (RTOS). However, in RTOS, MCUs accessing external memories such as DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is slow. Therefore, dedicated SRAM (Static Random Access Memory) or eFlash (e stands for embedding, meaning flash memory embedded in the chip) needs to be embedded within the MCU to form embedded memory (also known as on-chip memory or internal memory) for storing relevant instruction data.

[0003] To handle more complex applications, large-capacity SRAM and flash memory need to be embedded inside the MCU for instruction execution and storage. However, the high cost of embedded SRAM and flash memory hinders cost control of the MCU and results in low instruction execution efficiency, which greatly limits the development of MCU applications. Summary of the Invention

[0004] This application discloses an MCU access system, the specific technical solution of which is as follows:

[0005] An MCU access system includes a cache memory and an MCU; the MCU accesses a DDR memory through the cache memory; the cache memory is connected to the MCU; the cache memory and the DDR memory are located outside the MCU; the cache memory accesses the DDR memory in a burst transfer operation manner; the MCU accesses the cache memory in a single transfer operation manner or in a burst transfer operation manner.

[0006] Furthermore, when the MCU accesses the cache memory in a target type transfer operation within one clock cycle, the amount of data retrieved from the cache memory is greater than the amount of data retrieved from the DDR memory; wherein, the target type transfer operation is a burst transfer operation or a single transfer operation; the number of address units that the MCU has accessed through a burst transfer operation to the cache memory within one clock cycle is equal to the number of address units that the MCU has accessed through a single transfer operation to the cache memory within one clock cycle.

[0007] Furthermore, the MCU does not have a target on-chip memory, so that the cache memory replaces the target on-chip memory to buffer the data transmitted between the MCU and the DDR memory; wherein the capacity of the DDR memory is greater than the capacity of the cache memory.

[0008] Furthermore, the target on-chip memory includes embedded SRAM or embedded flash; when the target on-chip memory, the MCU, the cache memory and the DDR memory are disposed on the same circuit board, the MCU is not embedded in the target on-chip memory.

[0009] Furthermore, the cache memory includes multiple cache lines; the cache memory is used to read the first target data stored in the DDR memory and store it in the corresponding cache line according to the read request instruction of the MCU, and then notify the MCU to read the data in the corresponding cache line so that the MCU can index the first target data; the cache memory is also used to receive the second target data output by the MCU and store it in the corresponding cache line according to the write request instruction of the MCU; wherein, the read request instruction is configured under burst transfer operation; the write request instruction is configured under single transfer operation or burst transfer operation.

[0010] Furthermore, before each time the MCU reads the first target data from the cache memory, it sequentially indexes each cache line. If the first target data exists in a cache line of the current index, the first target data is read from that cache line. If the first target data does not exist in any cache line of the cache memory, the cache memory is triggered to read a burst length of data from the DDR memory at once and store it to update the data in the corresponding cache line, until the MCU reads the first target data from a cache line of the current index. The method by which the cache memory reads data in an address unit of a burst length from the DDR memory at once is a burst read operation. The burst length represents the number of consecutive address units transferred in a burst transfer operation. The burst transfer operation is either a burst read operation or a burst write operation.

[0011] Furthermore, the burst length is equal to the product of the first preset parameter and the cache line length; wherein, the burst length is less than or equal to the cache line length; the cache line length is the number of consecutive address units set in a cache line; when the first preset parameter is equal to the value 1, the data read by the cache memory from the DDR memory at one time updates all the data in the cache line that was first read by the MCU; when the first preset parameter is less than the value 1 and greater than the value 0, the data read by the cache memory from the DDR memory at one time updates part of the data in the cache line that was first read by the MCU, and the ratio of the number of address units occupied by this part of the data to the total number of address units in the cache line that was first read by the MCU is the first preset parameter; wherein, the data storage capacity of each address unit is equal.

[0012] Furthermore, the MCU's read operation on the cache memory is a single read operation or a burst read operation, and the MCU's write operation on the cache memory is a burst write operation or a single write operation; wherein, the single length represents the number of consecutive address units transmitted in a single transmission operation, and the single length is less than the burst length; wherein, the single transmission operation is a single read operation or a single write operation.

[0013] Furthermore, in the cache memory, the number of address units in each cache line is equal, and the data bit width set for each address unit is equal, so that the cache memory consists of data blocks with multiple rows and columns.

[0014] Furthermore, the capacity of the cache memory is equal to the product of the total number of cache lines, the length of the cache line, and the preset data width, wherein each address unit stores instructions of the preset data width.

[0015] The technical advantages of this application are as follows:

[0016] This application discloses a dedicated cache memory connected between the MCU and the DDR memory. This cache memory replaces the target on-chip memory in the data path between the MCU and the DDR memory. The cache memory accesses the DDR memory via burst transfer operations; the MCU accesses the cache memory via single transfer operations or burst transfer operations. This ensures that the MCU's data retrieval rate from the DDR memory via the cache memory is generally higher than its rate of retrieval directly from the DDR memory. Thus, the cooperation between the cache memory and the DDR memory guarantees fast and efficient instruction fetching operations for the MCU.

[0017] Since the number of address units accessed by the MCU in a burst transfer operation to the cache memory within one clock cycle is equal to the number of address units accessed by the MCU in a single transfer operation to the cache memory within one clock cycle, the amount of data transferred by the MCU in the same clock cycle when accessing the cache memory using burst transfer operations and when accessing the cache memory using single transfer operations is the same. Therefore, the MCU's access to DDR memory through the cache memory without setting up target on-chip memory is not affected by single transfer operations (due to the efficiency constraint of the MCU accessing DDR memory in a single transfer operation manner).

[0018] Since accessing the cache memory is faster than accessing the DDR memory when the MCU performs a target-type transfer operation within a single clock cycle, the MCU will prioritize searching the corresponding cache line in the cache memory using either a burst transfer operation or a single transfer operation, thus improving the efficiency of accessing the DDR memory. Furthermore, when the cache memory is configured to access the DDR memory using a burst transfer operation and the MCU is configured to access the cache memory using a single transfer operation, the resulting read / write efficiency is higher than that of an MCU with on-chip SRAM accessing the DDR memory using a single transfer operation. This solves the problem of excessively low efficiency when an MCU with on-chip target memory directly accesses the DDR memory using a single transfer operation. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating the connection relationship between an MCU, a cache memory, and a DDR memory, as disclosed in one embodiment. Implementation

[0020] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. All modules involved in the following embodiments are logic circuit units. In practical applications, a logic circuit unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of the present invention, units that are not closely related to solving the technical problem proposed by the present invention are not introduced in the embodiments of the present invention. However, this does not mean that other units are absent from the embodiments of the present invention.

[0021] In embedded devices upon which current RTOS systems rely, embedded memory refers to memory integrated on-chip and forming a single chip together with various logic and mixed-signal IPs within the system. It becomes a fundamental component of the SOC chip, used to store programs and data, overcoming the inefficiency and slow speed of MCUs accessing external memories like DDR when running RTOS systems. In designs configuring dedicated embedded SRAM or eFlash within the MCU, as the memory usage of the application increases, the area occupied by the embedded SRAM or eFlash needs to increase to accommodate the MCU's capacity, leading to higher overall design costs. It's worth noting that DDR memory, with its larger storage capacity, is relatively inexpensive, especially when used as a discrete memory device. Although both are memory, there are some differences. The most significant difference between embedded memory and discrete memory is that embedded memory is often highly dependent on the process technology of the application IC itself. For example, the size of the internal embedded memory differs significantly between chips manufactured using 45nm and those manufactured using 22nm processes. Discrete memory devices, on the other hand, are primarily optimized around the memory device's manufacturing process.

[0022] As one embodiment, this embodiment discloses an MCU access system, which includes a cache memory and an MCU. The MCU access system is used to access DDR memory. The cache memory, DDR memory, and MCU can be electrically connected in the same circuit entity. The MCU is used to access the DDR memory through the cache memory. The cache memory and DDR memory are located externally to the MCU. The cache memory is connected between the MCU and the DDR memory. The cache memory is used to access the DDR memory in a burst transfer operation manner; the MCU is used to access the cache memory in a single transfer operation manner. See also... Figure 1 As can be seen, the cache memory and DDR memory are located outside the MCU and belong to the MCU's off-chip memory. In this embodiment, the MCU is configured to access the DDR memory through the cache memory. The MCU may access one or more DDR memories required by the system, and the MCU may access one or more cache memories within the system. Moreover, the cache memory is connected between the MCU and the DDR memory, so that the cache memory replaces the target on-chip memory and joins the data path between the MCU and the DDR memory.

[0023] like Figure 1 As shown, the DDR memory and the cache memory are connected. A right-pointing arrow between the DDR memory and the cache memory indicates that the cache memory reads data from the DDR memory interface, and a left-pointing arrow indicates that the cache memory writes data to the DDR memory interface. Similarly, the MCU and the cache memory are connected. A right-pointing arrow between the MCU and the cache memory indicates that the MCU reads data from the cache memory through its instruction fetch interface, and a left-pointing arrow indicates that the MCU writes data to the cache memory. To improve the access efficiency of the MCU, in this embodiment, the cache memory is used to access the DDR memory in a burst transfer operation manner to achieve higher access efficiency to the DDR memory. The MCU accesses the cache memory in a single transfer operation or a burst transfer operation manner, which is faster than accessing the DDR memory in the same type of transfer operation manner. This makes the overall rate at which the MCU retrieves data from the DDR memory through the cache memory greater than that of directly retrieving data from the DDR memory. Thus, the cooperation between the cache memory and the DDR memory ensures that the MCU's instruction fetch operation can be performed quickly and efficiently.

[0024] In this embodiment, when the MCU accesses the external memory using a target type transfer operation within one clock cycle, the amount of data retrieved from the cache memory is greater than the amount of data retrieved from the DDR memory. This ensures that when the MCU accesses the external memory using the same type of transfer operation, the access rate to the cache memory is greater than the access rate to the DDR memory. Specifically, the delay between the MCU retrieving the first data from the DDR memory and retrieving the first data from the cache memory depends on factors such as the number of hosts (e.g., cache memory or MCU) currently accessing the DDR memory, the access priority of each host, and the latency required by the data read mechanism in the DDR memory. In this embodiment, the target type transfer operation is either a burst transfer operation or a single transfer operation. Specifically, when the MCU is configured to access the cache memory in a single-transfer operation mode, the resulting read / write efficiency is higher than that of an MCU with on-chip target memory configured to access DDR memory in a single-transfer operation mode. Similarly, when the MCU is configured to access the cache memory in a burst-transfer operation mode, the resulting read / write efficiency is higher than that of an MCU with on-chip target memory configured to access DDR memory in a burst-transfer operation mode. Since the number of address units accessed by the MCU in a burst-transfer operation to the cache memory in one clock cycle is equal to the number of address units accessed by the MCU in a single-transfer operation to the cache memory in one clock cycle, the access rate of the MCU to DDR memory in this MCU access system is not affected by the specific bus transmission type when no target on-chip memory is configured. Therefore, when the cache memory pre-stores the data that the MCU needs to access, the MCU will first search in the corresponding cache line in the cache memory in a burst-transfer operation mode or a single-transfer operation mode, instead of directly accessing the DDR memory in a single-transfer operation mode, thereby solving the problem of low efficiency of an MCU with on-chip target memory accessing DDR memory in a single-transfer operation mode.

[0025] In some embodiments, when the MCU is configured to access the cache memory in a single-transfer operation manner, the number of address units accessed by the MCU in a burst transfer operation to the cache memory within one clock cycle is equal to the number of address units accessed by the MCU in a single-transfer operation to the cache memory within one clock cycle. Therefore, the access rate of the MCU to the DDR memory without a target on-chip memory is not affected by the specific bus transfer type. Thus, when the cache memory is configured to access the DDR memory in a burst transfer operation manner, even if the MCU is configured to access the cache memory in a single-transfer operation manner, the resulting read / write efficiency is higher than that of an MCU with a target on-chip memory configured to access the DDR memory in a single-transfer operation manner. On the other hand, when the cache memory is SRAM memory, there is no difference in access speed between the burst transfer operation and the single-transfer operation for the cache memory. Therefore, compared to the MCU accessing external flash memory, there is no speed difference between input / output interfaces, reducing the need for additional buffers to balance the speed difference, reducing resource consumption by external bus arbitration, and simplifying the MCU's access control logic.

[0026] It should be noted that, for DDR memory, the efficiency of a burst transfer operation initiated by the MCU or cache memory to the DDR memory is higher than the efficiency of a single transfer operation. That is, the amount of data that the MCU bursts and transfers to the DDR memory within the same clock cycle is greater than the amount of data transferred to the DDR memory in a single transfer. However, for cache memory, the efficiency of a burst transfer operation initiated by the MCU to the cache memory is equal to the efficiency of a single transfer operation. That is, the amount of data that the MCU bursts and transfers to the cache memory within the same clock cycle is equal to the amount of data transferred to the cache memory in a single transfer. Both burst transfer operations and single transfer operations are bus transfer operation types defined under the AHB bus protocol.

[0027] As one embodiment, the MCU does not have a target on-chip memory. The target on-chip memory can be an on-chip memory that does not include embedded SRAM and embedded flash memory, which serve as high-speed instruction fetch interfaces. An MCU without a target on-chip memory can constitute a general-purpose microcontroller. An MCU without SRAM can, but is not limited to, integrate independent resources such as hardware multipliers, hardware dividers, hardware frequency dividers, and nested vector interrupt controllers (NVICs), but does not include embedded SRAM or other large-capacity on-chip memories (e.g., flash). In some implementation scenarios, it belongs to certain types of general-purpose microcontrollers under the ARM Cortex-M series architecture, and performs single-transfer operations to external memory under the AHB bus protocol. In this embodiment, the MCU does not have a target on-chip memory, so that cache memory replaces the target on-chip memory to buffer data transferred between the MCU and DDR memory; wherein, the capacity of the DDR memory is larger than the capacity of the cache memory; preferably, the capacity of the cache memory is larger than the capacity of the target on-chip memory. Compared to the MCU, the data stored in the DDR memory is external data, including instructions and data blocks that need to be retrieved by the MCU. To meet the storage requirements of the application, the capacity of the DDR memory is larger than that of the cache memory, which in turn is larger than the capacity of the target on-chip memory. Furthermore, the larger capacity of the DDR memory provides sufficient off-chip storage space for the MCU. By leveraging the off-chip capacity advantage of the DDR memory, the MCU does not need on-chip memory, allowing the DDR memory to replace the instruction buffering function of the target on-chip memory, thereby reducing the design cost of the MCU and consequently reducing the design cost of the peripheral hardware circuitry. Therefore, without using large-capacity embedded SRAM and embedded flash for data caching, introducing DDR memory externally to the MCU to perform large-capacity application storage functions instead of the target on-chip memory eliminates the need to develop a larger-capacity MCU chip. This overcomes the problem of needing to increase the MCU chip area when the application exceeds the capacity of the embedded memory, leveraging the large capacity advantage of DDR memory while reducing the development cost of the MCU.

[0028] Specifically, the MCU accesses the DDR memory via a cache memory without requiring on-chip memory. This includes read and write operations on the DDR memory, particularly read and write operations on a batch of data used for loop calculations. In each burst transfer operation, the MCU only reads the data for one round of loop calculations and caches it in the cache memory—that is, a small portion of the data in the batch used for loop calculations. This reduces the cache pressure on the MCU without using on-chip memory for external data storage, and to some extent solves the aforementioned cost and capacity issues without requiring excessive embedded memory in the MCU. On the other hand, during high-speed data exchange between the MCU and the DDR memory, when the MCU accesses the cache memory, it first searches in the corresponding cache line. Only when the data required by the MCU is not found in the cache memory does it initiate access to the DDR memory, thus improving the data access efficiency of the MCU to the DDR memory.

[0029] It should be noted that DDR SDRAM (or simply DDR) is Double Data Rate Synchronous Dynamic Random Access Memory. DDR memory can establish an electrical connection with an external bus of the MCU via a DDR interface, thereby setting the external memory access space of the MCU as a Double Data Rate (DDR) memory system. The DDR interface of DDR memory can significantly improve the data transfer rate without changing the maximum signal frequency of the system; even if the maximum frequency of the data signal is doubled, the DDR signal allows external access devices to double the throughput while maintaining the current maximum feasible clock frequency.

[0030] In some embodiments, the target on-chip memory includes embedded SRAM or embedded flash. When the target on-chip memory, the MCU, the cache memory, and the DDR memory are located on the same circuit board, if the target on-chip memory is embedded inside the chip containing the MCU, the design cost of embedded SRAM and embedded flash is very high, thus limiting their wafer area and restricting the use of the MCU. Therefore, it is necessary to use the cache memory and DDR memory disclosed in the aforementioned embodiments as off-chip memory, without retaining some data caching functions of embedded SRAM and embedded flash. In the case where the target on-chip memory, the MCU, the cache memory, and the DDR memory are located on the same circuit board, and the MCU does not embed the target on-chip memory, then the cache memory and DDR memory disclosed in the aforementioned embodiments are directly used as off-chip memory, and the target on-chip memory is no longer used for data caching, saving the design cost of the MCU. It should be noted that when the MCU, the cache memory, and the DDR memory are located on the same circuit board, the MCU, the cache memory, and the DDR memory become three types of chips on the circuit board.

[0031] It should be noted that the MCU internally includes an AHB bus parsing module (not shown in the figure), which serves a transmission control function. The MCU can use the AHB bus parsing module (which can be understood as a register module) to interact with the cache memory on the AHB bus, and the cache memory can also use the AHB bus parsing module (which can be understood as a register module) to interact with the DDR memory on the AHB bus. The AHB bus parsing module is used to parse bus protocol instructions, convert the data signals and address signals transmitted on the bus, and access the cache memory according to the bus address after the MCU issues an address fetch instruction. The bus protocol used in this embodiment is preferably the AHB bus. The protocol, which controls burst transfer operations (including burst read and burst write operations) and single transfer operations (single write and single read operations), is defined by the AHB bus protocol specification (the on-chip system bus protocol for SOCs). During burst transfer operations of data by the MCU or cache memory, the addresses issued are aligned, and the memory space (logical bank) is divided in the form of aligned addresses. External access to burst read or burst write data is based on this division. The aligned address is determined by the width of the data transmitted in each clock cycle. Aligned addresses are contiguous addresses, and the number of such addresses is the burst length. During a single data transfer operation of the MCU or cache memory, the number of contiguous addresses transmitted at once is the single length. During external single read or single write operations, the single length is determined by the number of consecutive data addresses transmitted in each clock cycle. Wherein, the single length is less than the burst length, and the single length is greater than or equal to 1; the burst length represents the number of consecutive address units transmitted in a single burst transfer operation; the burst transfer operation is a burst read operation or a burst write operation; the single length represents the number of consecutive address units transmitted in a single single transfer operation; the single transfer operation is a single read operation or a single write operation. In this embodiment, the ratio of the number of data read in a burst to the number of data read in a single single operation is a preset integer value, such that the number of data or address units obtained by the cache memory or the MCU with the on-chip target memory performing a single read operation of the preset integer value on the DDR memory is equal to the number of data or address units obtained by the cache memory performing a burst read operation on the DDR memory.

[0032] It should be noted that the cache memory, or simply cache, is used to cache data that the MCU needs to read from the DDR memory, as well as data that the MCU needs to write to the DDR memory. Therefore, the MCU can indirectly access the DDR memory through the cache memory (acting as a data cache in place of the target on-chip memory). Each time, it can read a portion of the data to be accessed from the cache memory (equivalent to several instructions from an instruction set originally stored in the DDR memory, which are pre-fetched into the cache memory). Of course, the MCU can also write a small portion of the instructions into the cache memory for data backup. It is worth noting that the input rate supported by the cache memory interface should ideally be the same as its output rate. This eliminates the need for a data buffer in the device accessing the cache memory to balance this difference, reducing the complexity of the access control logic.

[0033] As one embodiment, the cache memory includes multiple cache lines. The cache memory is used to read the first target data stored in the DDR memory and store it in the corresponding cache line according to the read request instruction from the MCU, and then notify the MCU to read the data in the corresponding cache line, so that the MCU can index the first target data. The read request instruction from the MCU is sent to the cache memory in advance, and the read request instruction from the MCU includes the storage address of the first target data in the DDR memory or the storage address of the first target data in the corresponding cache line of the cache memory. When the first target data is pre-stored in the cache memory, the read request instruction from the MCU can also support the MCU reading the first target data from the corresponding cache line in the cache memory, which is faster than reading the first target data from the DDR memory in the same transfer operation. The read request instruction is configured for burst transfer operations so that the cache memory can burst-read a batch of data from the DDR memory each time, which may include the first target data.

[0034] The cache memory is also used to receive the second target data output by the MCU according to the write request instruction of the MCU, and store the second target data in the corresponding cache line, which can play a data backup role. Of course, when the capacity of the cache memory is limited, it can instruct the DDR memory to read the data in the corresponding cache line so that the MCU can write the second target data into the DDR memory. The write request instruction of the MCU includes the storage address of the second target data in the DDR memory or the storage address of the second target data in the corresponding cache line of the cache memory. The write request instruction is configured under burst transfer operation or single transfer operation so that the MCU can burst write or single write a batch of data into the cache memory each time, which may include the second target data.

[0035] It should be noted that both the write request instruction and the read request instruction of the MCU are controlled by the MCU's instruction fetch interface and follow the timing characteristics of the access bus protocol supported by the MCU to ensure that the MCU can access the cache memory normally. The MCU typically accesses external memory through a single transfer operation. The MCU can be composed of dedicated control logic; the MCU can also refer to a processor core or other application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement this embodiment. The cache memory can be connected to the MCU's instruction fetch interface through a separate memory interface, and the DDR interface of the DDR memory is connected to other interfaces of the cache memory. The MCU may not have an internal target on-chip memory.

[0036] During data interaction within the MCU access system, when the MCU accesses data, it first searches the corresponding cache line in the cache memory, either via a burst transfer operation or a single transfer operation. Only when the cache memory does not contain the required data does it access the DDR memory, typically via a burst transfer operation, thus accelerating the MCU's access speed. Specifically, before each read of the first target data from the cache memory, the MCU sequentially indexes each cache line, including indexing each cache line in ascending order of index number; and within the current cache line, it indexes each address unit in ascending order of address value, then moves to the next cache line to continue indexing the address units in the next cache line.

[0037] If the first target data exists in a cache line of the current index, then the first target data is read from that cache line. If the first target data does not exist in any cache line of the cache memory, then the cache memory is triggered to read a burst of data from the DDR memory at once and store it to update the data in the corresponding cache line. Since the cache memory is used to access the DDR memory in a burst transfer manner, the cache memory accesses the DDR memory in a burst transfer manner to obtain a burst of data. Therefore, the cache memory accesses the DDR memory only when there is no data required by the MCU in the cache memory, thus improving the data access efficiency for the MCU. After updating the data in the corresponding cache line, the cache memory notifies the MCU to read the updated data in the cache line (which can also be regarded as the data in a cache line of the current index), and determines whether the first target data exists in the data of a cache line of the current index. If it does, the address is determined to match and the indexing is completed, but the entire cache line is not necessarily traversed; otherwise, the cache is determined to be lost, and the cache memory needs to be triggered to read a new burst of data from the DDR memory. This process of updating and indexing is repeated until the MCU reads the first target data from a cache line of the current index and determines that valid data and a matching address have been obtained. In this embodiment, the entire indexing process can be regarded as being controlled by the hardware read and write operation logic inside the MCU issuing corresponding access commands to complete the process. Specifically, it can be a burst read operation specified under burst transfer operation.

[0038] Since the MCU accesses data in a burst transfer operation within one clock cycle, the amount of data retrieved from the cache memory is greater than the amount of data retrieved from the DDR memory. That is, the MCU accesses the cache memory faster than the DDR memory under the same transfer operation. Therefore, if the data (first target data) that the MCU needs to access is pre-stored in the cache memory, the MCU will first search in the corresponding cache line in the cache memory in a burst transfer operation or a single transfer operation, instead of searching in the DDR memory in a single transfer operation, thereby improving the access efficiency of the MCU.

[0039] Based on the aforementioned embodiments, the burst length is equal to the product of a first preset parameter and the cache line length; wherein, the cache line length is the number of consecutive address units set in a cache line, and also represents the number of consecutive data addresses in a cache line; if the burst length is less than or equal to the cache line length, then the first preset parameter is greater than 0, but less than or equal to 1. Since the data storage capacity of each address unit is equal, the maximum data capacity cached in a cache line is equal to the product of the cache line length and the data bit width of a single address unit; one address unit stores one piece of data in a cache line, and the cache line length is equal to the number of data stored in a cache line. Preferably, the interface bit width of the cache memory is equal to the bit width of the DDR interface of the DDR memory, and the interface bit width of the cache memory is equal to the bit width of the instruction fetch interface of the MCU, reducing the need to split transmitted data due to bit width incompatibility and facilitating the formation of an efficient data path.

[0040] When the first preset parameter equals 1, the cache memory reads data from the DDR memory at once to update the data in the earliest cache line read by the MCU, enabling the MCU to access data in units of one cache line. The number of data lines read from the DDR memory at once by the cache memory is equal to the cache line length. This implementation can occur when the MCU detects that the first target data does not exist in any of the cache lines, or before the MCU begins accessing the cache memory. Therefore, the cache memory can read a cache line of data from a large-capacity DDR memory at once to update the corresponding cache line in the cache memory, thus refreshing the cache data at a granularity of one cache line length. This assists the MCU in indexing the required first target data from the corresponding external cache line at a granularity of one cache line length, balancing the accuracy and real-time performance of MCU data access with consideration for the space capacity burden of the MCU's embedded memory.

[0041] When the first preset parameter is less than 1 and greater than 0, the data read from the DDR memory at one time updates a portion of the data in the earliest cache line read by the MCU. The ratio of the number of address units occupied by this portion of data to the total number of address units in the earliest cache line read by the MCU is the first preset parameter. If the amount of data read from the DDR memory at one time is less than the length of the cache line, then only a portion of the data in one cache line can be replaced. This implementation can occur when the MCU detects that the first target data does not exist in any of the cache lines in the cache memory, or it can occur before the MCU starts accessing the cache memory.

[0042] In the MCU access system, the MCU's access to the cache memory is designed based on the AHB or AXI protocol, so that the MCU's read operation on the cache memory is a burst read operation or a single read operation, and the MCU's write operation on the cache memory is a burst write operation or a single write operation. This hardware-based access to the cache memory involves at least the MCU's instruction fetch interface and transmits data according to the AHB or AXI protocol. The MCU's read operation on the cache memory is a burst read operation or a single read operation, and the MCU's write operation on the cache memory is a burst write operation or a single write operation. Here, the single-transfer length represents the number of consecutive address units transmitted in a single transfer operation, i.e., the number of consecutive data address units transmitted in a single transfer operation. The single-transfer length is less than the burst length, preferably two. A burst transfer operation is a burst read operation or a burst write operation, and a single transfer operation is a single read operation or a single write operation. The cache memory is configured to access the DDR memory in a burst transfer operation manner.

[0043] It should be noted that the cache memory reads data from the DDR memory in a burst-length address space at once using a burst read operation. This means the cache memory reads a burst-length number of data units from the DDR memory in one read clock cycle, which can be controlled by a burst read mode state machine built into the cache memory, MCU, or DDR memory. The cache memory also supports burst write operations to write a burst-length number of data units into the DDR memory at once. This means the cache memory writes a burst-length number of data units into the DDR memory in one write clock cycle, which can be controlled by a burst write mode state machine built into the cache memory, MCU, or DDR memory. The preferred burst lengths are 64, 32, 16, 8, or 4 units.

[0044] The burst length represents the number of consecutive address units transferred in a single burst transfer operation. A burst transfer operation can be either a burst read or a burst write operation, depending on the operating state of the cache memory. A burst read operation belongs to the operation implemented by the burst read mode state machine in burst read mode, and a burst write operation belongs to the operation implemented by the burst write mode state machine in burst write mode. Burst read mode and burst write mode each have dedicated registers for configuring their operating modes.

[0045] Preferably, the cache memory is an SRAM memory. For the cache memory, there is no difference in access speed between the burst transfer operation and the single transfer operation. Therefore, compared with the MCU accessing the external flash, there is no speed difference between the input and output interfaces, which reduces the need to set up additional buffers to balance the speed difference, reduces the resource occupation of the external bus arbitration of the MCU, and simplifies the access control logic of the MCU.

[0046] In summary, when accessing the cache memory using the same type of transfer operation, the MCU's access rate to the cache memory is greater than its access rate to the DDR memory. This results in the MCU retrieving more data from the cache memory than from the DDR memory within the same clock cycle. Furthermore, since the number of address units accessed by the MCU in a burst transfer operation to the cache memory within one clock cycle is equal to the number of address units accessed by the MCU in a single transfer operation within one clock cycle, the amount of data transferred by the MCU using burst transfer operations and single transfer operations within the same clock cycle is the same. Therefore, without on-chip memory, the MCU's access to the DDR memory via the cache memory is not affected by single transfer operations (due to the access efficiency limitations of single transfer operations). Based on this, when the cache memory is configured to access the DDR memory using burst transfer operations and the MCU is configured to access the cache memory using single transfer operations, the read / write efficiency of the MCU accessing the system's DDR memory is higher than the read / write efficiency of an MCU with built-in SRAM accessing the DDR memory using single transfer operations. This addresses the issue of low efficiency when an MCU with an on-chip target memory directly accesses DDR memory in a single transfer operation.

[0047] As one embodiment, in the cache memory, the number of address units in each cache line is equal, and the data bit width of each address unit is equal, so that the cache memory is composed of data blocks in multiple rows and columns. A data block in a certain row and column is equivalent to the address unit in the corresponding column of a cache line located in that row. The length of the cache line is used as the standard for dividing a row of addresses. When accessing, reading or storing data externally, this division must be taken into account. The data capacity of the divided address can be determined by the width of the data transmitted in each clock cycle. Preferably, the data bit width of each address unit is 64 bits, 32 bits, or 16 bits, which can be used as the smallest unit for the MCU to access the cache memory.

[0048] Specifically, when the cache line length is the number of consecutive address units set in a cache line, the capacity of the cache memory is equal to the product of the total number of cache lines, the cache line length, and the preset data width. The number of consecutive addresses indicated in each cache line is equal and fixed. Each address unit stores an instruction with a preset data width, which can be set to 32 bits. When the cache line length is set to 16, one cache line stores 16 32-bit instructions. Furthermore, when the cache memory has 32 cache lines, the capacity of the cache memory is 32 * 16 * 32 bits.

[0049] Preferably, in order to improve the data transfer speed of the cache memory, the frequency of the working clock used during the burst read operation of the cache memory is preferably greater than the frequency of the working clock used during the burst read operation of the MCU, which can also be understood as the maximum clock frequency in the MCU access system.

[0050] In the embodiments provided in this application, it should be understood that the disclosed systems and chips can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

Claims

1. An MCU access system, characterized in that, The MCU access system includes cache memory and the MCU; The MCU is used to access the DDR memory through the cache memory; The cache memory is connected to the MCU, while the cache memory and DDR memory are located outside the MCU. The cache memory is used to access the DDR memory in a burst transfer operation manner; the MCU is used to access the cache memory in a single transfer operation manner or a burst transfer operation manner. The MCU does not have a target on-chip memory, so that the cache memory can replace the target on-chip memory to buffer the data transferred between the MCU and the DDR memory. The capacity of the DDR memory is greater than the capacity of the cache memory.

2. The MCU access system according to claim 1, characterized in that, When the MCU accesses the memory in a target-type transfer operation within one clock cycle, the amount of data retrieved from the cache memory is greater than the amount of data retrieved from the DDR memory; where the target-type transfer operation is either a burst transfer operation or a single transfer operation. The number of address units that the MCU performs a burst transfer operation on the cache memory within one clock cycle is equal to the number of address units that the MCU performs a single transfer operation on the cache memory within one clock cycle.

3. The MCU access system according to claim 2, characterized in that, The target on-chip memory includes embedded SRAM or embedded flash; When the target on-chip memory, the MCU, the cache memory, and the DDR memory are located on the same circuit board, the MCU is not embedded in the target on-chip memory.

4. The MCU access system according to claim 1, characterized in that, The cache memory includes multiple cache lines; The cache memory is used to read the first target data stored in the DDR memory and store it in the corresponding cache line according to the read request instruction of the MCU, and then notify the MCU to read the data in the corresponding cache line so that the MCU can index the first target data; The cache memory is also used to receive the second target data output by the MCU and store it into the corresponding cache line according to the write request instruction of the MCU; The read request command is configured for burst transfer operations; the write request command is configured for single transfer operations or burst transfer operations.

5. The MCU access system according to claim 4, characterized in that, Before each time the MCU reads the first target data from the cache memory, it sequentially indexes each cache line. If the first target data exists in a cache line of the current index, then read the first target data from a cache line of the current index; If the first target data does not exist in all cache lines in the cache memory, the cache memory is triggered to read a burst of data from the DDR memory at once and store it to update the data in the corresponding cache line, until the MCU reads the first target data from a cache line of the current index; The method by which the cache memory reads data from the DDR memory in one burst of an address unit is called a burst read operation; the burst length represents the number of consecutive address units transferred in a burst transfer operation; the burst transfer operation is either a burst read operation or a burst write operation.

6. The MCU access system according to claim 5, characterized in that, The burst length is equal to the product of the first preset parameter and the cache line length; wherein, the burst length is less than or equal to the cache line length; the cache line length is the number of consecutive address units set in a cache line; When the first preset parameter is equal to the value 1, the data read from the DDR memory by the cache memory at one time updates all the data in the cache line that was first read by the MCU. When the first preset parameter is less than 1 and greater than 0, the data read from the DDR memory by the cache memory at one time updates part of the data in the earliest cache line read by the MCU. The ratio of the number of address units occupied by this part of the data to the total number of address units in the earliest cache line read by the MCU is the first preset parameter. Each address unit has the same data storage capacity.

7. The MCU access system according to claim 4, characterized in that, The MCU's read operation on the cache memory is a single read operation or a burst read operation, and the MCU's write operation on the cache memory is a burst write operation or a single write operation. Wherein, single length represents the number of consecutive address units transmitted in a single transmission operation, and single length is less than burst length; The single transmission operation is either a single read operation or a single write operation.

8. The MCU access system according to claim 7, characterized in that, In the cache memory, the number of address units in each cache line is equal, and the data bit width set for each address unit is equal, so that the cache memory consists of data blocks with multiple rows and columns.

9. The MCU access system according to claim 8, characterized in that, The capacity of the cache memory is equal to the product of the total number of cache lines, the length of the cache line, and the preset data width, wherein each address unit stores an instruction of the preset data width.

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