Electronic fuse control circuit, semiconductor element, and method for manufacturing the same

Abstract

The present disclosure provides an electronic fuse control circuit, a semiconductor element, and a method of manufacturing a semiconductor element having an electronic fuse control circuit. The electronic fuse control circuit includes a programming voltage pad, a fuse element, a latch, an operation switch unit, a resistor selection pad, and a junction option unit. The fuse element includes a first end coupled to the programming voltage pad, and a second end. The operation switch unit forms an electrical connection between the second end of the fuse element and a ground during a programming operation, and forms an electrical connection between the second end of the fuse element and an input of the latch during a read operation. Each junction option unit includes a resistor and a selection switch, connected in series between the input of the latch and the resistor selection pad.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 517,525 and 17 / 517,794 (i.e., priority dates of November 2, 2021 and November 3, 2021), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure provides an electronic fuse control circuit and a method for fabricating the same, particularly an electronic fuse control circuit and a method for fabricating the same that provides different bonding options. Background Technology

[0003] An antifuse is a type of electronic fuse element and has been adopted in one-time programmable (OTP) non-volatile memory. Figure 1 The structure of the anti-fuse AF1 is illustrated. For example... Figure 1 As shown, the structure of the antifuse element AF1 is similar to that of a transistor; the antifuse AF1 includes a gate G1 and an active region A1. In this case, since the gate G1 comprises gate oxide, there is a relatively high resistance between the gate G1 and the active region A1. However, when a programming voltage VH is applied to the gate G1 and a ground voltage is applied to the active region A1, the high voltage applied to the antifuse element AF1 will damage the gate oxide of the gate G1, thus creating a low-resistance path between the gate G1 and the active region A1. Therefore, the antifuse element AF1 can be programmed.

[0004] Because the resistance of antifuse AF1 changes significantly during programming, the system can identify whether it has been programmed by detecting its resistance. For example, a reference resistor can be used to divide the voltage between the antifuse AF1 and the reference resistor, and the resulting voltage distribution can be used to identify the state of the antifuse AF1. However, due to variations in the manufacturing process, the resistance values ​​of different antifuses may differ. For instance, typically, the resistance of an antifuse may be greater than 5000 kΩ before programming, while after programming, it may be less than 400 kΩ. However, some antifuses may have a resistance less than 1500 kΩ before programming, while others may still have a resistance greater than 800 kΩ even after programming. In this situation, the reference resistor selected for one antifuse may fail to correctly identify the state of the other antifuse. This could necessitate additional processes to replace the reference resistor, increasing costs and reducing fabrication efficiency.

[0005] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not establish prior art for this disclosure, and no description of "prior art" above should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides an electronic fuse control circuit, including: a programming voltage pad, a fuse element, a latch, an operating switch unit, a plurality of resistor selection pads, and a plurality of engagement option units. The programming voltage pad is configured to receive the programming voltage. The fuse element includes a first terminal and a second terminal coupled to the programming voltage pad. The latch includes an input terminal and an output terminal. The operating switch unit is configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and is configured to form an electrical connection between the second terminal of the fuse element and the input terminal of the latch during a read operation. Each of the plurality of engagement option units includes a resistor and a selection switch connected in series between the input terminal of the latch and a corresponding resistor selection pad among the plurality of resistor selection pads.

[0007] In some embodiments, the fuse element is an antifuse.

[0008] In some embodiments, the resistors of the plurality of engagement option units have different resistors.

[0009] In some embodiments, the electronic fuse control circuit further includes a read switch, the read switch including a first terminal coupled to the first terminal of the fuse element, a second terminal coupled to the ground terminal, and a control terminal configured to receive a read control signal.

[0010] In some embodiments, the operating switch unit includes a first switch, a second switch, and a third switch. The first switch includes a first terminal coupled to the second terminal of the fuse element, a second terminal, and a control terminal configured to receive a read and program control signal. The second switch includes a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the ground terminal, and a control terminal configured to receive a programming control signal. The third switch includes a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the input terminal of the latch, and a control terminal configured to receive a read control signal.

[0011] In some embodiments, the latch further includes a first inverter and a second inverter. The first inverter includes an input coupled to the input terminal of the latch and an output coupled to the output terminal of the latch. The second inverter includes an input coupled to the output terminal of the latch and an output coupled to the input terminal of the latch.

[0012] In some embodiments, at least one of the plurality of resistor selection pads receives a read voltage during the read operation, wherein the read voltage is less than the programming voltage.

[0013] Another embodiment of this disclosure provides a semiconductor device including a chip and a substrate. The chip includes an electronic fuse control circuit, which includes a programming voltage pad, a fuse element, a latch, an operating switch unit, a plurality of resistor selection pads, and a plurality of bonding option units. The programming voltage pad is configured to receive a programming voltage. The fuse element includes a first terminal and a second terminal coupled to the programming voltage pad. The latch includes an input terminal and an output terminal. The operating switch unit is configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and is configured to form an electrical connection between the second terminal of the fuse element and the input terminal of the latch during a read operation. Each of the plurality of bonding option units includes a resistor and a selection switch connected in series between the input terminal of the latch and a corresponding resistor selection pad among the plurality of resistor selection pads. The substrate includes a first voltage bonding pad and a plurality of second voltage bonding pads. The first voltage bonding pad is bonded to the programming voltage pad, and at least one of the plurality of second voltage bonding pads is bonded to at least one of the plurality of resistor selection pads.

[0014] In some embodiments, the fuse element is an anti-fuse.

[0015] In some embodiments, the resistors of the plurality of engagement option units have different resistors.

[0016] In some embodiments, the electronic fuse control circuit further includes a read switch, which includes a first terminal coupled to the first terminal of the fuse element, a second terminal coupled to the ground terminal, and a control terminal configured to receive a read control signal.

[0017] In some embodiments, the operating switch unit includes a first switch, a second switch, and a third switch. The first switch includes a first terminal coupled to the second terminal of the fuse element, a second terminal, and a control terminal configured to receive a read and program control signal. The second switch includes a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the ground terminal, and a control terminal configured to receive a programming control signal. The third switch includes a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the input terminal of the latch, and a control terminal configured to receive a read control signal.

[0018] In some embodiments, the latch further includes a first inverter and a second inverter. The first inverter includes an input coupled to the input terminal of the latch and an output coupled to the output terminal of the latch. The second inverter includes an input coupled to the output terminal of the latch and an output coupled to the input terminal of the latch.

[0019] In some embodiments, a resistor selection pad of one of the plurality of second voltage bonding pads is configured to receive a read voltage during the read operation, wherein the read voltage is less than the programming voltage.

[0020] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a chip including an electronic fuse control circuit, wherein the electronic fuse control circuit includes a programming voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option units. The programming voltage pad is coupled to a first terminal of the fuse element, and each of the plurality of bonding option units includes a resistor and a selection switch connected in series between the input terminal of the latch and a corresponding resistor selection pad among the plurality of resistor selection pads. The fabrication method further includes providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads, disposing the chip on the substrate, bonding the first voltage bonding pad to the programming voltage pad, and bonding at least one of the plurality of second voltage bonding pads to at least one of the plurality of resistor selection pads.

[0021] In some embodiments, the fabrication method further includes performing a test operation based on the state of the fuse element to determine whether at least one of the plurality of resistor selection pads is bonded to at least one of the plurality of second voltage bonding pads.

[0022] In some embodiments, performing the test operation based on the state of the fuse element to determine whether to bond at least one of the plurality of resistor selection pads to at least one of the plurality of second voltage bonding pads includes: reading the fuse element with a first bonding option unit of the plurality of bonding option units to generate a first read result, and when the first read result is determined to be negative, performing a read operation on the fuse element with a second bonding option unit of the plurality of bonding option units to generate a second read result.

[0023] In some embodiments, when the second read result is determined to be positive, performing the test operation further includes deciding to couple a resistor selection pad coupled to the second bonding option unit to at least one of the plurality of second voltage bonding pads.

[0024] In some embodiments, reading the fuse element with the first bonding option unit of the plurality of bonding option units to generate a first reading result includes: applying a reading voltage to a resistor selection pad coupled to the first bonding option unit, turning on a selection switch of the first bonding option unit, applying a ground voltage to the first terminal of the fuse element, and coupling a second terminal of the fuse element to the input terminal of the latch.

[0025] In some embodiments, before performing the read operation on the fuse element, a programming operation is performed on the fuse element by applying a programming voltage to the programming voltage pad and a grounding voltage to the second terminal of the fuse element.

[0026] The electronic fuse control circuit, semiconductor element, and method for fabricating the semiconductor element provided in this disclosure allow users to select appropriate bonding option units during the wafer probing process, and further allow users to subsequently connect the selected bonding option units to the bonding pads of the substrate during the packaging process. Therefore, even if the resistance of the fuse element cannot be predicted before chip fabrication, manufacturers can select appropriate bonding option units with suitable resistance after chip fabrication to ensure the accuracy of readout operations and avoid the additional processes required to change the reference resistor in the prior art.

[0027] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages that define the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended patent claims. Attached Figure Description

[0028] When the drawings are considered in conjunction with the embodiments and the scope of the disclosed patent, a more comprehensive understanding of the disclosure can be obtained. The same element symbols in the drawings refer to the same elements.

[0029] Figure 1 This is a schematic diagram illustrating the structure of an anti-fuse coil.

[0030] Figure 2 This is a circuit diagram illustrating an electronic fuse control circuit according to an embodiment of the present disclosure.

[0031] Figure 3 This is a sequence diagram, for example. Figure 2 The timing of the electronic fuse control circuit receiving control signals during programming and reading operations.

[0032] Figure 4 This is a circuit diagram, for example. Figure 2 During the programming operation of the electronic fuse control circuit.

[0033] Figure 5 This is a circuit diagram, for example. Figure 2 During the read operation of the electronic fuse control circuit.

[0034] Figure 6 This is a circuit diagram, for example. Figure 2 The equivalent circuit of the electronic fuse control circuit during the read operation.

[0035] Figure 7 This is a top view illustrating a semiconductor element according to an embodiment of the present disclosure.

[0036] Figure 8 This is a sectional view illustrating an embodiment of the present disclosure. Figure 7 The semiconductor element shown.

[0037] Figure 9 This is a top view illustrating a semiconductor element according to another embodiment of the present disclosure.

[0038] Figure 10This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0039] Figure 11 This is a flowchart illustrating the execution steps of a test operation according to an embodiment of this disclosure.

[0040] Figure 12 This is a flowchart illustrating the execution steps of a read operation according to an embodiment of this disclosure.

[0041] The reference numerals in the attached figures are explained as follows:

[0042] 10: Semiconductor components

[0043] 12: Chip

[0044] 14: Base

[0045] 100: Electronic fuse control circuit

[0046] 110: Fuse element

[0047] 120: Latch

[0048] 122: First inverter

[0049] 124: Second inverter

[0050] 130: Operating switch unit

[0051] 132: First Switch

[0052] 134: Second Switch

[0053] 136: Third Switch

[0054] 150: Read switch

[0055] 200: Preparation method

[0056] 1401~140N: Joining Option Unit

[0057] 1421~142N: Selector switch

[0058] 1441~144N: Resistors

[0059] A1: Active Zone

[0060] AF1: Anti-fuse

[0061] BPA1: First voltage bonding pad

[0062] BPB1~BPBN: Second voltage bonding pads

[0063] BW1: Joint line

[0064] BW2: Joint line

[0065] BW3: Joint line

[0066] CP1: Current path

[0067] CP2: Current path

[0068] G1: Gate

[0069] PP1: Programming Voltage Pad

[0070] PS1~PSN: Resistor selection pads

[0071] S210: Steps

[0072] S220: Steps

[0073] S221: Steps

[0074] S222: Steps

[0075] S223: Steps

[0076] S224: Steps

[0077] S225: Steps

[0078] S230: Steps

[0079] S240: Steps

[0080] S250: Steps

[0081] S260: Steps

[0082] S2221: Steps

[0083] S2222: Steps

[0084] S2223: Steps

[0085] S2224: Steps

[0086] SIGC1~SIGCN: Control signals

[0087] SIGD: Data signal

[0088] SIGP: Programmable Control Signal

[0089] SIGR: Read control signals

[0090] SIGRP: Read and program control signals

[0091] T1: Period

[0092] T2: Period

[0093] VF: Voltage

[0094] VH: Programming voltage

[0095] VP: Programming Voltage

[0096] VR: Read voltage Detailed Implementation

[0097] The following disclosure provides numerous different embodiments or examples of various features as implementations of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to impose limitations. For example, the dimensions of an element are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the element. Furthermore, the description of a first feature being formed "above" or "on" a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, features may be drawn at various scales. In the drawings, some layers / features may be omitted for simplicity.

[0098] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figure and another (other) element or feature. These spatial relative terms are intended to encompass not only the orientation shown in the figure but also different orientations of the element in use or operation. The element may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be translated accordingly.

[0099] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there may be an intermediate component or layer.

[0100] It should be understood that although various elements may be described using terms such as first, second, etc., these elements should not be limited by the terms. Unless otherwise stated, terms are used only to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of this disclosure.

[0101] Unless the context otherwise requires, when referring to orientation, layout, location, shape, size, quantity, or other measures, the terms such as “identical,” “equal,” “planar,” or “coplanar” do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measures, but rather that they are substantially identical, including such similar orientation, layout, location, shape, size, quantity, or other measures, within the range of acceptable variations that may occur, such as due to manufacturing processes. The term “substantially” may be used to reflect this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” can be exactly the same, equal, or planar, or they can be identical, equal, or planar within the range of acceptable variations, such as those that may occur due to manufacturing processes.

[0102] In this disclosure, semiconductor elements generally refer to elements that can function using the properties of semiconductors. Electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic components are all included in this disclosure. Categories of semiconductor elements are also discussed. Specifically, the semiconductor element in the embodiments of this disclosure can be a dynamic random access memory (DRAM) element.

[0103] Figure 2 This is a circuit diagram illustrating an electronic fuse control circuit 100 according to an embodiment of the present disclosure. The electronic fuse control circuit 100 includes a programming voltage pad PP1, a plurality of resistor selection pads PS1 to PSN, a fuse element 110, a latch 120, an operation switch unit 130, and a plurality of engagement option units 1401 to 140N, where N is a positive integer greater than 1.

[0104] The fuse element 110 includes a first terminal and a second terminal, with the first terminal of the fuse element 110 coupled to the programming voltage pad PP1. In this embodiment, the fuse element 110 may be an antifuse and may have a connection with... Figure 1 The anti-fuse AF1 shown has the same structure. In this case, the first end of the fuse element 110 can be the gate G1 of the anti-fuse element AF1, and the second end of the fuse element 110 can be the active region A1 of the anti-fuse element AF1.

[0105] The latch 120 includes an input terminal and an output terminal. The operating switch unit 130 is coupled to the second terminal of the fuse element 110, the input terminal of the latch 120, and the ground terminal. In this embodiment, the operating switch unit 130 can form an electrical connection between the second terminal of the fuse element 110 and the ground terminal, or between the second terminal of the fuse element 110 and the input terminal of the latch 120, depending on the operation to be performed.

[0106] Furthermore, each of the engagement option units 1401 to 140N includes a resistor and a selection switch connected in series between the input of latch 120 and a corresponding resistor selection pad among resistor selection pads PS1 to PSN. For example, engagement option unit 1401 may be coupled to resistor selection pad PS1, while engagement option unit 140N may be coupled to resistor selection pad PSN. Additionally, in this embodiment, the resistors 1441 to 144N of engagement option units 1401 to 140N may have different resistance values, and the selection switches 1421 to 142N may be controlled respectively and correspondingly by the control signal SIG. C1 To control signal SIG CN .

[0107] The latch 120 includes a first inverter 122 and a second inverter 124. The first inverter 122 includes an input coupled to the input terminal of the latch 120 and an output coupled to the output terminal of the latch 120. The second inverter 124 includes an input coupled to the output terminal of the latch 120 and an output coupled to the input terminal of the latch 120.

[0108] Furthermore, the operating switch unit 130 includes a first switch 132, a second switch 134, and a third switch 136. The first switch 132 includes a first terminal coupled to the second terminal of the fuse element 110, a second terminal, and a terminal for receiving a read and programmable control signal SIG. RP The second switch 134 includes a first terminal coupled to the second terminal of the first switch 132, a second terminal coupled to the ground terminal, and a control terminal for receiving the programming control signal SIG. P The third switch 136 includes a first terminal coupled to the second terminal of the first switch 132, a second terminal coupled to the input terminal of the latch 120, and a control terminal for receiving the read control signal SIG. R One of the control terminals.

[0109] In this embodiment, the electronic fuse control circuit 100 may further include a read switch 150. The read switch 150 includes a first terminal coupled to a first terminal of the fuse element 110, a second terminal coupled to a ground terminal, and a terminal for receiving a read control signal SIG. R A control terminal. In some embodiments, switches 132, 134, 136, and 150 may be, for example, but not limited to, formed by transistors. In this embodiment, switches 132, 134, 136, and 150 may be implemented by N-type metal-oxide-semiconductor (MOS) transistors.

[0110] Figure 3 This is a sequence diagram, for example. Figure 2The electronic fuse control circuit 100 receives control signals during programming and reading operations. For example... Figure 3 As shown, programming operations are performed during T1, and reading operations are performed during T2. Figure 4 This is a circuit diagram, for example. Figure 2 During the programming operation of the electronic fuse control circuit 100.

[0111] During T1, the programming control signal SIG P With read and programmable control signal SIG RP The logic is at a high voltage level, while the read control signal SIG is active. R The system is at a logic low voltage level. In this state, the first switch 132 and the second switch 134 of the operating switch unit 130 are turned on, while the third switch 136 and the read switch 150 are turned off.

[0112] In addition, such as Figure 4 As shown, the programming voltage pad PP1 can receive the programming voltage VP during programming operations. Due to the conduction of the first switch 132 and the second switch 134 of the operating switch unit 130, an electrical connection is formed between the second terminal of the fuse element 110 and the ground terminal, thereby pulling the second terminal of the fuse element 110 down to the ground voltage. In this embodiment, the programming voltage VP can be a high voltage sufficient to burn out the fuse element 110. In this case, the gate oxide of the fuse element 110 can be broken down by the high voltage applied to the fuse element 110, thus forming a low-resistance path between the first and second terminals of the fuse element 110. Therefore, as... Figure 4 As shown, a current path CP1 is formed from the programming voltage pad PP1 to the ground terminal, passing through the fuse element 110, the first switch 132, and the second switch 134.

[0113] After programming operations, such as Figure 3 As shown, a read operation is performed in period T2. Figure 5 This is a circuit diagram, for example. Figure 2 During the read operation of the electronic fuse control circuit 100, the programming control signal SIG is activated. P The logic voltage level is low, while the read and programmable control signal SIG is active. RP and read control signal SIG R The circuit is at a logic high voltage level. In this state, the second switch 134 is off, while the first switch 132, the third switch 136, and the read switch 150 are on. Therefore, an electrical connection is formed between the second terminal of the fuse element 110 and the input terminal of the latch 120.

[0114] In addition, Figure 5In the illustrated embodiment, during the read operation, the selection switches 1421 to 142N of the bonding option units 1401 to 140N are turned on. Furthermore, since the resistor selection pad PS1 is bonded to an external bonding pad and receives the read voltage VR during the read operation, the read operation is performed using the bonding option unit 1401 in this embodiment. In this case, as... Figure 5 As shown, a current path CP2 can be formed from the resistor selection pad PS1 to the ground terminal. This current path passes through the resistor 1441 of the bonding option unit 1401, the third switch 136, the first switch 132, the fuse element 110, and the read switch 150. Therefore, the latch 120 can sense the voltage VF on the second terminal of the fuse element 110 and output the data signal SIG accordingly. D In some embodiments, to prevent the fuse element 110 from being burned out by the read voltage VR, the read voltage VR should be less than the programming voltage VP. For example, the programming voltage VP may be 6V, while the read voltage VR may be 2V. It should be understood that in some other embodiments, other bonding option units may also be used to perform the read operation. In this case, the resistor selection pad coupled to the desired bonding option unit will be bonded to an external bonding pad to receive the read voltage VR during the read operation.

[0115] In this embodiment, the voltage VF at the second terminal of the fuse element 110 is a division of the read voltage VR generated based on the ratio of the resistance of the resistor 1441 to the resistance of the fuse element 110. Figure 6 This is a circuit diagram, for example. Figure 2 The equivalent circuit of the electronic fuse control circuit 100 during the read operation. For example... Figure 6 As shown, the voltage VF at the second terminal of the fuse element 110 can be expressed by formula (1).

[0116]

[0117] In formula (1), R 110 The resistor R represents the fuse element 110. 1441 This represents the resistance of resistor 1441. In some embodiments, if the voltage VF is greater than 0.6V, latch 120 will set the data signal SIG. D Latch to a logic low voltage level. If the voltage VF is less than 0.6V, latch 120 will release the data signal SIG. D Latched to a logic high voltage level. In this case, in order to correctly identify the state of fuse element 110 according to voltage VF, the resistance R of resistor 1441 is adjusted before programming fuse element 110. 1441 It should be related to the resistance R of fuse element 110 110Very close, so the resistance R of fuse element 110 is... 110 Changes in voltage VF can be clearly reflected in the voltage.

[0118] In this embodiment, the resistance R of resistor 1441 1441 It can be 4 megohms (MΩ), and the resistance R of fuse element 110 is... 110 Before the fuse element 110 is programmed, it can be 5 megohms, and the resistance R of the fuse element 110 is... 110 After fuse element 110 is programmed, it can become 100 kiloohms (kΩ). In this case, since fuse element 110 has been programmed in the previous period T1, the voltage VF will be 0.029V, and latch 120 will set the data signal SIG. D Latched to a logic high voltage level. However, if fuse element 110 is not programmed, the voltage VF will be 0.67V, and latch 120 will latch the data signal SIG. D Latched to a logic low level. Therefore, it can be used based on the data signal SIG. D The voltage level is used to identify the state of fuse element 110.

[0119] However, in some other embodiments, the resistance R of the fuse element 110 110 Before being programmed, the voltage may be less than 5 megohms, for example, 5 megohms, but after being programmed, it may become 100 kilohms. Therefore, if fuse element 110 is not programmed, the voltage VF will be 0.33V, and if fuse element 110 is programmed, the voltage VF will be 0.029V. Since the voltage VF is less than 0.6V in both cases, latch 120 will set the data signal SIG regardless of whether fuse element 110 is programmed. D Latched to a logic high voltage level. In this case, the resistor 1441 of the bonding option unit 1401 may not be suitable as a reference circuit for identifying the state of the fuse element 110, and other bonding option units with smaller resistances may be used instead.

[0120] To ensure that the results of the read operation reflect the state of the fuse element 110, different fuse elements 110 can employ different bonding option units to achieve different resistances. In some embodiments, a test operation can be performed to find the appropriate bonding option unit with the appropriate resistance by performing read operations on different bonding option units.

[0121] Furthermore, in this embodiment, the programming voltage pad PP1 and resistor selection pads PS1 to PSN can be probe pads that can receive voltage from a probe card to perform programming and reading operations on the fuse element 110 during the wafer probing process. That is, appropriate bonding option units can be determined and selected before the chip of the electronic fuse control circuit 100 is packaged. In this case, after selecting an appropriate bonding option unit, the resistor selection pad correspondingly coupled to the selected bonding option unit can be bonded to the bonding pad of the package substrate during the packaging process, while the remaining resistor selection pads can remain unbonded after the packaging process. In this way, different chips of the electronic fuse control circuit 100 can have different bonding options, thus ensuring accurate reading operations and avoiding the additional processes required to change the reference resistor in the prior art.

[0122] Figure 7 This is a top view illustrating a semiconductor element 10 according to an embodiment of the present disclosure. Figure 8 This is a sectional view illustrating an embodiment of the present disclosure along... Figure 7 The semiconductor device 10 is shown in the image taken along line A-A'. The semiconductor device 10 includes a chip 12 and a substrate 14. The chip 12 includes an electronic fuse control circuit 100. In some embodiments, the chip 12 may further include other circuitry, and the fuse element 110 of the electronic fuse control circuit 100 may serve as storage for other circuitry or as an electronic identifier. For example, the chip 12 may further include dynamic random access memory (DRAM), and the fuse element 110 of the electronic fuse control circuit 100 may serve as an identifier for the DRAM. In some embodiments, the chip 12 may further include additional electronic fuse control circuitry 100 for storing more data bits as required by the system.

[0123] The substrate 14 includes a first voltage bonding pad BPA1 and a plurality of second voltage bonding pads BPB1 to BPBN, and the chip 12 can be disposed on the substrate 14. In this embodiment, the first voltage bonding pad BPA1, the second voltage bonding pads BPB1 to BPBN, the programming voltage pad PP1, and the resistor selection pads PS1 to PSN all face upward, so the first voltage bonding pad BPA1 and the second voltage bonding pads BPB1 to BPBN can be connected to the programming voltage pad PP1 and the resistor selection pads PS1 to PSN by corresponding bonding wires.

[0124] For example, such as Figure 7As shown, the first voltage bonding pad BPA1 is bonded to the programming voltage pad PP1 via bonding line BW1, while the second voltage bonding pad BB1 can be bonded to the resistor selection pad PS1 via bonding line BW2. In this case, the second voltage bonding pad BPB1 can receive the read voltage VR during the read operation, and the bonding option unit 1401 coupled to the resistor selection pad PS1 will be used to perform the read operation. Furthermore, since the second voltage bonding pads BPB2 to BPBN are not bonded to the resistor selection pads PS2 to PSN, the bonding option units 1402 to 140N will not be used during the read operation.

[0125] However, in some other embodiments, if bonding option unit 1402 is selected to perform the read operation, the second voltage bonding pad BPB2 will be bonded to the resistor selection pad PS2, while the second voltage bonding pad BPB1 may not be bonded to the resistor selection pad PS1. That is, the electronic fuse control circuit 100 allows the user to select an appropriate bonding option unit from bonding option units 1401 to 140N based on the test results of the wafer probing process. This selected bonding option unit can be wire-bonded to the bonding pads of the substrate in subsequent packaging processes. Therefore, even if the resistance of the fuse element 110 of the electronic fuse control circuit 100 is unpredictable, the manufacturer can select an appropriate bonding option unit with suitable resistance after the chip 10 is fabricated to ensure the accuracy of the read operation.

[0126] Furthermore, in some embodiments, the resistors in different bonding option units can be connected in parallel and combined for read operations, thus providing more resistance level options. Figure 9 This is a top view illustrating a semiconductor element 20 according to another embodiment of the present disclosure. Semiconductor element 20 and semiconductor element 10 have similar structures and can operate according to the same principles. However, in semiconductor element 20, a second voltage bonding pad BPB1 is bonded to a resistor selection pad PS1 via bonding line BW2, and a second voltage bonding pad BPB2 is bonded to a resistor selection pad PS2 via bonding line BW3. In this case, during a read operation, the second voltage bonding pads BPB1 and BPB2 can simultaneously receive the read voltage VR, and the selection switches 1421 and 1422 of bonding option units 1401 and 1402 can simultaneously be turned on. Therefore, resistors 1441 and 1442 can be connected in parallel as a reference resistor to generate a distribution voltage VF with the fuse element 110. That is, the resistors of bonding option units 1401 to 140N can be used individually or in combination; therefore, bonding option units 1401 to 140N can provide up to (2 N -1) Options for different resistors.

[0127] Figure 10This is a flowchart illustrating a method 200 for fabricating a semiconductor element 10 according to an embodiment of the present disclosure. The fabrication method 200 includes steps S210 to S260. In step S210, a chip 12 including an electronic fuse control circuit 100 is provided, and in step S220, a test operation is performed on the fuse element 110 of the electronic fuse control circuit 100. In this embodiment, the test operation is performed based on the state of the fuse element 110 to determine the resistor selection pad to be bonded to the second voltage bonding pad. After determining the resistor selection pad to be bonded to the second voltage bonding pad, a substrate 14 is provided in step S230, and the chip 12 is disposed on the substrate 14 in step S240. Furthermore, in step S250, a first voltage bonding pad BPA1 is bonded to a programming voltage pad PP1, and in step S260, at least one of the second voltage bonding pads BPB1 to BPBN is bonded to the resistor selection pad determined and selected in step S220.

[0128] Figure 11 This is a flowchart illustrating a sub-step of the test operation execution step S220 according to an embodiment of this disclosure. For example... Figure 11 As shown, step S220 includes steps S221 to S225. In step S221, a programming operation is performed on fuse element 110 by applying a programming voltage VP to programming voltage pad PP1 and a ground voltage to the second terminal of fuse element 110. However, in some embodiments, fuse element 110 may be left unprogrammed depending on the data to be stored. In this case, step S221 can be omitted, and fuse element 110 will remain unprogrammed. Next, in step S222, a read operation is performed on fuse element 110 using at least one bonding option unit selected from bonding option units 1401 to 140N to produce a read result.

[0129] Figure 12 This is a flowchart illustrating the execution steps of a read operation according to an embodiment of this disclosure. Figure 12As shown, the read operation may include steps S2221 to S2224. In step S2221, a read voltage VR is applied to a resistor selection pad coupled to a bonding option unit used in the read operation. In step S2222, the selection switch of the bonding option unit is turned on. In step S2223, a first terminal of the fuse element 110 is coupled to ground. In step S2224, a second terminal of the fuse element 110 is coupled to the input of the latch 120. In some embodiments, steps S2222 to S2224 may be performed by controlling the switching of the read switch 150 and the operation switch unit 130. Therefore, the distribution voltage VF of the read voltage VR can be generated according to the ratio of the resistance of the bonding selection unit to the resistance of the fuse element 110, and the latch 120 can latch the data signal SIG according to the distribution voltage VF. D .

[0130] In this embodiment, since the state of fuse element 110 is known before the test operation is performed, the expected read result can also be obtained. For example, if fuse element 110 has been programmed, signal data SIG with a logic high voltage level can be expected. D However, if fuse element 110 is not programmed, a logic high voltage level signal data SIG will not be expected. D .

[0131] In step S223, the read result can be compared with the expected result to determine whether the currently selected bonding option unit is appropriate. If the read result is determined to be negative, i.e., the read result does not match the expected state of the fuse element 110, this read result may indicate that the bonding option unit selected in step S221 is not an appropriate selection. In this case, another bonding option unit can be selected in step S224, and step S222 can be performed again with the newly selected bonding option unit. However, if the read result is determined to be positive, the bonding option unit currently used for the read operation can be determined to be an appropriate selection and selected. In this case, in step S225, the resistor selection pad coupled to the selected bonding option unit is determined to be bonded to the corresponding second voltage bonding pad, and in step S260, the resistor selection pad determined or selected by the test operation is bonded to the corresponding second voltage bonding pad.

[0132] In this embodiment, the test operation can be performed by wafer probing before chip 12 is packaged; therefore, after selecting the appropriate bonding option unit, the resistor selection pad and the second voltage bonding pad can be bonded later in the packaging process, thus ensuring that the read operation can be performed accurately and avoiding the additional process required to change the reference resistor in the prior art.

[0133] In summary, the electronic fuse control circuit, semiconductor element, and method for fabricating the semiconductor element provided by the embodiments of this disclosure allow users to select appropriate bonding option units during the wafer probing process, and users can subsequently connect the selected bonding option units to the bonding pads of the substrate during the packaging process. Therefore, even if the resistance of the fuse element cannot be predicted before chip fabrication, manufacturers can select appropriate bonding option units with suitable resistance after chip fabrication to ensure the accuracy of readout operations and avoid the additional processes required to change the reference resistance in the prior art.

[0134] While this disclosure and its advantages have been detailed, it should be understood that variations, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0135] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the patent disclosed in this disclosure.

Claims

1. An electronic fuse control circuit, comprising: A programming voltage pad, configured to receive a programming voltage; A fuse element includes a first end and a second end coupled to the programming voltage pad; A latch, comprising an input and an output; An operating switch unit is configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and is configured to form an electrical connection between the second terminal of the fuse element and the input terminal of the latch during a reading operation. Multiple resistor selection pads; as well as Multiple engagement option units, each of which includes a resistor and a selection switch connected in series between the input of the latch and a corresponding resistor selection pad among the multiple resistor selection pads.

2. The electronic fuse control circuit as claimed in claim 1, wherein the fuse element is an anti-fuse.

3. The electronic fuse control circuit of claim 1, wherein the resistors of the plurality of bonding option units have different resistance values.

4. The electronic fuse control circuit as claimed in claim 1, further comprising a readout switch, including: A first end is coupled to the first end of the fuse element; The second terminal is coupled to the grounding terminal; as well as A control terminal is configured to receive a read control signal.

5. The electronic fuse control circuit as claimed in claim 1, wherein the operation switch unit comprises: A first switch, comprising: A first end is coupled to the second end of the fuse element; One second end; and A control terminal, configured to receive a read and programmable control signal; A second switch, comprising: A first terminal is coupled to the second terminal of the first switch; A second terminal, coupled to the ground terminal; and A control terminal, configured to receive a programmable control signal; and A third switch, comprising: A first terminal is coupled to the second terminal of the first switch; A second terminal is coupled to the input terminal of the latch; and A control terminal is configured to receive a read control signal.

6. The electronic fuse control circuit as claimed in claim 1, wherein the latch further comprises: A first inverter, comprising: One input terminal, coupled to the input terminal of the latch; and One output terminal, coupled to the output terminal of the latch; and A second inverter, comprising: An input terminal is coupled to the output terminal of the latch; and One output terminal is coupled to the input terminal of the latch.

7. The electronic fuse control circuit of claim 1, wherein at least one of the plurality of resistor selection pads receives a read voltage during the read operation, wherein the read voltage is less than the programming voltage.

8. A semiconductor element, comprising: A chip, including an electronic fuse control circuit, the electronic fuse control circuit comprising: A programming voltage pad, configured to receive a programming voltage; A fuse element includes a first end and a second end coupled to the programming voltage pad; A latch includes an input terminal and an output terminal; An operating switch unit is configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and is configured to form an electrical connection between the second terminal of the fuse element and the input terminal of the latch during a reading operation. Multiple resistor selection pads; and A plurality of engagement option units, each of which includes a resistor and a selection switch, connected in series between the input terminal of the latch and a corresponding resistor selection pad among the plurality of resistor selection pads; and A base, comprising: A first voltage bonding pad is bonded to the programming voltage pad; and A plurality of second voltage bonding pads, wherein at least one of the plurality of second voltage bonding pads is bonded to at least one of the plurality of resistor selection pads.

9. The semiconductor element of claim 8, wherein the fuse element is an anti-fuse.

10. The semiconductor element of claim 8, wherein the resistors of the plurality of bonding option units have different resistance values.

11. The semiconductor device of claim 8, wherein the electronic fuse control circuit further includes a readout switch, comprising: A first end is coupled to the first end of the fuse element; The second terminal is coupled to the grounding terminal; as well as A control terminal is configured to receive a read control signal.

12. The semiconductor element of claim 8, wherein the operating switch unit comprises: A first switch, comprising: A first end is coupled to the second end of the fuse element; One second end; and A control terminal, configured to receive a read and programmable control signal; A second switch, comprising: A first terminal is coupled to the second terminal of the first switch; A second terminal, coupled to the ground terminal; and A control terminal, configured to receive a programmable control signal; and A third switch, comprising: A first terminal is coupled to the second terminal of the first switch; A second terminal is coupled to the input terminal of the latch; and A control terminal is configured to receive a read control signal.

13. The semiconductor element of claim 8, wherein the latch comprises: A first inverter, comprising: One input terminal, coupled to the input terminal of the latch; and One output terminal, coupled to the output terminal of the latch; and A second inverter, comprising: An input terminal is coupled to the output terminal of the latch; and One output terminal is coupled to the input terminal of the latch.

14. The semiconductor element of claim 8, wherein a resistor selection pad of one of the plurality of second voltage bonding pads is configured to receive a read voltage during the read operation, wherein the read voltage is less than the programming voltage.

15. A method for fabricating a semiconductor device, comprising: A chip is provided that includes an electronic fuse control circuit, wherein the electronic fuse control circuit includes a programming voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option units, the programming voltage pad being coupled to a first terminal of the fuse element, and each of the plurality of bonding option units including a resistor and a selection switch connected in series between the input of the latch and a corresponding resistor selection pad of the plurality of resistor selection pads; A substrate is provided, comprising a first voltage bonding pad and a plurality of second voltage bonding pads; The chip is mounted on this substrate; The first voltage bonding pad is bonded to the programming voltage pad; as well as At least one of the plurality of second voltage bonding pads is bonded to at least one of the plurality of resistor selection pads.

16. The preparation method according to claim 15, further comprising: A test operation is performed based on the state of the fuse element to determine whether at least one of the plurality of resistor selection pads is bonded to at least one of the plurality of second voltage bonding pads.

17. The fabrication method of claim 16, wherein performing the test operation based on the state of the fuse element to determine whether at least one of the plurality of resistor selection pads is bonded to at least one of the plurality of second voltage bonding pads, comprises: The fuse element is read using a first bonding option unit among the plurality of bonding option units to produce a first read result; as well as When the first read result is determined to be negative, a read operation is performed on the fuse element using a second bonding option unit among the plurality of bonding option units to generate a second read result.

18. The fabrication method of claim 17, wherein the test operation is performed based on the state of the fuse element to determine whether the at least one of the plurality of resistor selection pads is bonded to the at least one of the plurality of second voltage bonding pads, further comprising: When the second read result is determined to be positive, it is decided to couple a resistor selection pad coupled to the second bonding option unit to at least one of the plurality of second voltage bonding pads.

19. The preparation method of claim 17, wherein reading the fuse element using the first bonding option unit of the plurality of bonding option units to generate the first reading result includes: A read voltage is applied to a resistor selection pad coupled to the first engagement option unit; Turn on a selection switch of the first engagement option unit; A ground voltage is applied to the first terminal of the fuse element; and A second end of the fuse element is coupled to the input end of the latch.

20. The preparation method of claim 19, wherein performing the test operation further comprises: Before performing the read operation on the fuse element, a programming operation is performed on the fuse element by applying a programming voltage to the programming voltage pad and a grounding voltage to the second terminal of the fuse element.

Images