A time synchronization method, apparatus, device, and storage medium

Abstract

The application discloses a time synchronization method and device, equipment and storage medium, relates to the communication technical field, and is used for realizing the improvement of the time service precision of B code, satisfying the requirement of the time synchronization precision of the lower clock equipment, and comprising the following steps: receiving a synchronization pulse signal and a first B code signal carrying first time information which are sent by a higher clock equipment; determining the first time information in the first B code signal; adjusting the first time information in the first B code signal based on the received synchronization pulse signal and a preset high-frequency clock to obtain second time information; and sending a second B code signal carrying the second time information to the lower clock equipment after a time interval corresponding to the synchronization pulse signal.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a time synchronization method, apparatus, device and storage medium. Background Technology

[0002] Precise timing systems are indispensable in scenarios such as communications, power, and the Industrial Internet. With the finalization of the 3GPP-Release 16 specification, further optimizations and regulations have been made for 5G local area networks (LANs), high-precision positioning, and support for latency-sensitive networks, providing strong support for numerous scenarios including power differential control, industrial collaborative control, digital factories, and smart cities. Specifically, 5G modules can send inter-range instrumentation group-B (IRIG-B) signals carrying time information to lower-level clock devices. Correspondingly, after receiving the B-code signal, the lower-level clock device can complete time synchronization based on the time information contained in the B-code signal.

[0003] However, in the scenario where the lower-level clock device only receives the B code signal and performs time synchronization based on the received B code signal, the B code signal emitted by the 5G module has a jitter of 100 microseconds (μs). This will cause the lower-level clock device to still have an error at the μs level after completing time synchronization, which is not suitable for timing systems with timing accuracy requirements at the nanosecond (ns) level. Summary of the Invention

[0004] This invention provides a time synchronization method, apparatus, device, and storage medium for improving the timing accuracy of B-code and meeting the time synchronization accuracy requirements of downstream clock devices.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] In a first aspect, a time synchronization method is provided, the method comprising: receiving a synchronization pulse signal sent by an upper-level clock device and a first B code signal carrying first time information; determining the first time information in the first B code signal; adjusting the first time information in the first B code signal based on the received synchronization pulse signal and a preset high-frequency clock to obtain second time information; and sending a second B code signal carrying the second time information to a lower-level clock device after the time interval corresponding to the synchronization pulse signal.

[0007] After receiving the synchronization pulse signal and the first B-code signal carrying the first time information from the upstream clock device, the first time information in the first B-code signal is determined. Based on the received synchronization pulse signal and a preset high-frequency clock, the first time information in the first B-code signal is adjusted to obtain the second time information. After the time interval corresponding to the synchronization pulse signal, the second B-code signal carrying the second time information is sent to the downstream clock device. In the above method, since the timing accuracy of the synchronization pulse signal is within 200ns, adjusting the timing accuracy of the first time information in the first B-code signal with 100μs jitter based on the synchronization pulse signal ensures that the timing accuracy of the adjusted second B-code signal is consistent with that of the synchronization pulse signal, thus meeting the timing accuracy requirements of the downstream clock device.

[0008] In one possible design, the above-mentioned adjustment of the first time information in the first B code signal based on the received synchronization pulse signal and a preset high-frequency clock includes: obtaining the time synchronization point of the synchronization pulse signal based on the preset high-frequency clock; and adjusting the first time information to second time information based on the preset high-frequency clock and the time synchronization point.

[0009] In one possible design, the above-mentioned adjustment of the first time information to the second time information based on a preset high-frequency clock and time synchronization point includes: aligning the reference symbols in the first time information with the time synchronization point based on the preset high-frequency clock to obtain the second time information.

[0010] In one possible design, the aforementioned time synchronization point is the rising edge.

[0011] Secondly, a time synchronization device is provided, comprising a receiving unit, a determining unit, a processing unit, and a transmitting unit. The receiving unit receives a synchronization pulse signal sent by an upstream clock device and a first B-code signal carrying first time information; the determining unit determines the first time information in the first B-code; the processing unit, based on the received synchronization pulse signal and a preset high-frequency clock, adjusts the first time information in the first B-code signal to obtain second time information; and the transmitting unit sends a second B-code signal carrying the second time information to a downstream clock device after the time interval corresponding to the synchronization pulse signal.

[0012] In one possible design, the time synchronization device further includes an acquisition unit; the acquisition unit, based on a preset high-frequency clock, is used to acquire the time synchronization point of the synchronization pulse signal; and the processing unit, based on the preset high-frequency clock and the time synchronization point, is specifically used to adjust the first time information into second time information.

[0013] In one possible design, the processing unit is specifically used to: align the reference symbols in the first time information with the time synchronization point based on a preset high-frequency clock to obtain the second time information.

[0014] Thirdly, an electronic device is provided, comprising a memory and a processor; the memory and the processor are coupled, the memory being used to store computer program code including computer instructions, wherein when the processor executes the computer instructions, the electronic device performs a time synchronization method as provided in the first aspect or any possible implementation thereof.

[0015] Fourthly, a computer-readable storage medium is provided, in which instructions are stored, which, when executed on an electronic device, cause the electronic device to perform a time synchronization method as provided in the first aspect or any possible implementation thereof. Attached Figure Description

[0016] Figure 1 A schematic diagram of a time synchronization system structure is provided for an embodiment of the present invention;

[0017] Figure 2 A flowchart illustrating a time synchronization method provided for embodiments of the present invention. Figure 1 ;

[0018] Figure 3 A flowchart illustrating a time synchronization method provided for embodiments of the present invention. Figure 2 ;

[0019] Figure 4 A schematic diagram of a time synchronization device provided for an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of an electronic device structure provided for an embodiment of the present invention. Figure 1 ;

[0021] Figure 6 A schematic diagram of an electronic device structure provided for an embodiment of the present invention. Figure 2 . Detailed Implementation

[0022] In embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0023] In the description of this invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" and "more than one" refer to two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0024] The time synchronization method provided in this embodiment of the invention can be applied to a time synchronization system, which is suitable for scenarios where an upper-level clock device sends a time synchronization signal to a lower-level clock device. Figure 1 A schematic diagram of one structure of the time synchronization system is shown, such as... Figure 1 As shown, the time synchronization system 10 includes a higher-level clock device 101, an electronic device 102, and a lower-level clock device (…). Figure 1 The example shown is a lower-level clock device 103; in practical applications, there may be more lower-level clock devices.

[0025] The electronic device 102 is connected to both the upper-level clock device 101 and the lower-level clock device 103. The connection between these devices can be wired or wireless, and this embodiment of the invention does not limit the connection method.

[0026] In the above application scenario, the upper-level clock device 101 can be a 5G module, which obtains time information by receiving 5G signals, generates a precise pulse signal and a B code signal with jitter, and sends the pulse signal and B code to the electronic device 102.

[0027] Electronic device 102 is used to receive pulse signals and B-code signals sent by upper-level clock device 101, and recalibrate the B-code signals according to the accurate pulse signals to improve the timing accuracy of the B-codes, and send them to lower-level clock device 103 to meet the timing accuracy requirements of lower-level clock device 103.

[0028] Optionally, the electronic device 102 can be a field programmable gate array (FPGA), including a clock module 1021, an acquisition module 1022, a decoding module 1023, a time recalculation module 1024, a pulse signal calculation module 1025, and a transmission module 1026.

[0029] A basic clock provided by a crystal oscillator is provided outside the electronic device 102. The clock module 1021 generates a high-frequency clock based on the basic clock for accuracy calibration and time calculation.

[0030] The acquisition module 1022 is used to acquire the pulse signal and B code signal sent by the upper-level clock device 101.

[0031] The decoding module 1023 is used to decode the B code signal acquired by the acquisition module 1022 to determine the time information it contains, which includes day, hour, minute and second.

[0032] The time recalculation module 1024 is used to calculate the time information of the next second based on the time information determined by the decoding module, and use it as the time content of the B code output by the time synchronization device in the next second.

[0033] After acquiring the pulse signal, the pulse signal calculation module 1025 starts a time counter. When the count reaches 1 second, it outputs a transmission signal to the transmission module.

[0034] After receiving the transmission signal output by the pulse signal calculation module, the transmission module 1026 transmits the B code of the modified time content determined in the recalculation module.

[0035] The lower-level clock device 103 is used to receive the adjusted B code signal sent by the electronic device 102 and to perform clock synchronization based on the adjusted B code signal.

[0036] Figure 2 This is a flowchart illustrating a time synchronization method according to some exemplary embodiments. In some embodiments, the above-described time synchronization method can be applied to, for example... Figure 1 The electronic device shown can also be applied to a time synchronization device in an electronic device. Hereinafter, embodiments of the present invention will describe the time synchronization method by taking its application in a time synchronization device as an example.

[0037] like Figure 2 As shown, the time synchronization method provided in this embodiment of the invention includes the following steps S201-S204.

[0038] S201, The time synchronization device receives the synchronization pulse signal sent by the upper-level clock device, as well as the first B code signal carrying the first time information.

[0039] Among them, the upper-level clock device can be a 5G module or a device in the upper-level clock synchronization system; the first B code signal is used for the upper-level clock device to synchronize with the lower-level clock device; the synchronization pulse signal can be a pulse second (PPS) signal, with a period of 1 second and the rising edge being the time synchronization point.

[0040] It should be noted that the first B code signal and the synchronization pulse signal have the following characteristics: the first B code signal has a jitter of less than 100μs, and the timing accuracy of the synchronization pulse signal is within 200ns.

[0041] S202, The time synchronization device determines the first time information in the first B code signal.

[0042] As one possible implementation, the time synchronization device parses the received first B code signal to obtain the first time information carried by the first B code signal, which includes day, hour, minute and second.

[0043] It should be noted that in the sequence structure of the B-code signal, two consecutive "P" codes indicate the start of a whole second, and the leading edge of the second "P" code pulse is the "time" reference point, defined as "Pr". There is one position code every 10 code elements, totaling 10, defined as P1, P2, ..., P9, P0. The time format of the B-code signal is second-minute-hour-day, occupying 7 bits for seconds, 7 bits for minutes, 6 bits for hours, and 10 bits for days, positioned between P0 and P5. If we start numbering the code elements from "Pr" and define them as code elements 0, 1, 2, ..., 99, then the "second" information is located in code elements 1, 2, 3, 4, 6, 7, 8; the "minute" information is located in code elements 10, 11, 12, 13, 15, 16, 17; the "hour" information is located in code elements 20, 21, 22, 23, 25, 26; and the "day" information is located in code elements 30, 31, 32, 33, 35, 36, 37, 38, 40, 41.

[0044] S203. Based on the received synchronization pulse signal and the preset high-frequency clock, the time synchronization device adjusts the first time information in the first B code signal to obtain the second time information.

[0045] As one possible implementation, the time synchronization device obtains the time information from the synchronization pulse signal based on a high-frequency clock, and adjusts the first time information according to the obtained time information to obtain the second time information.

[0046] It should be noted that the aforementioned preset high-frequency clock can be a high-frequency clock generated by the clock module in the time synchronization device based on an external crystal oscillator.

[0047] The specific implementation of this step can be found in the subsequent description of the embodiments of the present invention, and will not be repeated here.

[0048] S204. After the time interval corresponding to the synchronization pulse signal, the time synchronization device sends a second B code signal carrying second time information to the lower-level clock device.

[0049] The time interval corresponding to the aforementioned synchronization pulse signal is the period of the synchronization pulse signal, and the lower-level clock device is the downstream device that needs to complete time synchronization through the B code signal.

[0050] As one possible implementation, after determining the second time information, the time synchronization device generates a second B-code signal based on the second time information. Furthermore, after receiving a synchronization pulse signal, the time synchronization device sends the generated second B-code signal to the lower-level clock device one cycle after the synchronization pulse signal.

[0051] For example, taking the second pulse signal as an example, after the time synchronization device receives the second pulse signal sent by the upper-level clock device and counts to 1 second, it sends the generated second B code signal to the lower-level clock device, so that the lower-level clock device can complete the time synchronization with the second B code signal with high time synchronization accuracy.

[0052] In one design, in order to obtain second-time information, such as Figure 3 As shown, S203 provided in this embodiment of the invention may specifically include the following S2031-S2032:

[0053] S2031, The time synchronization device is based on a high-frequency clock and obtains the time synchronization point of the synchronization pulse signal.

[0054] As one possible implementation, the time synchronization device can decode the synchronization pulse signal based on a high-frequency clock to obtain the code elements of the synchronization pulse signal, thereby determining the time synchronization point of the synchronization pulse signal.

[0055] For example, taking a second pulse signal as the synchronization pulse signal, the time synchronization point of the synchronization pulse signal is the rising edge of the synchronization pulse signal.

[0056] The specific implementation method of the time synchronization device in this step, which obtains the time synchronization point of the synchronization pulse signal based on the high-frequency clock, can be referred to the existing technology and will not be elaborated here.

[0057] S2032, The time synchronization device is based on a high-frequency clock and a time synchronization point, and the time synchronization device adjusts the first time information to the second time information.

[0058] As one possible implementation, the time synchronization device decodes the first B code signal based on a high-frequency clock to obtain the code elements of the first B code signal, thereby obtaining the position of the "Pr" code element in the first B code signal, shifting the position of the "Pr" code element to the position corresponding to the time synchronization point of the synchronization pulse signal, aligning it with the time synchronization point, and obtaining the second time information.

[0059] Understandably, since the aforementioned "Pr" symbol is the reference symbol for the first B code signal, aligning it with the rising edge of the synchronization pulse signal can achieve the same timing accuracy for the first time information as for the synchronization pulse signal.

[0060] This invention provides a time synchronization method, apparatus, device, and storage medium. After receiving a synchronization pulse signal from an upstream clock device and a first B-code signal carrying first time information, the first time information in the first B-code signal is determined. Based on the received synchronization pulse signal and a preset high-frequency clock, the first time information in the first B-code signal is adjusted to obtain second time information. After the time interval corresponding to the synchronization pulse signal, a second B-code signal carrying the second time information is sent to the downstream clock device. In this method, since the timing accuracy of the synchronization pulse signal is within 200 ns, adjusting the timing accuracy of the first time information in the first B-code signal with 100 μs jitter based on the synchronization pulse signal ensures that the timing accuracy of the adjusted second B-code signal is consistent with that of the synchronization pulse signal, thereby meeting the timing accuracy requirements of the downstream clock device.

[0061] The foregoing mainly describes the solutions provided by the embodiments of the present invention from a methodological perspective. To achieve the above functions, it includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0062] In this embodiment of the invention, the user equipment can be divided into functional modules according to the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. Optionally, the module division in this embodiment of the invention is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0063] Figure 4 This is a schematic diagram of a time synchronization device provided in an embodiment of the present invention. Figure 4 As shown, the time synchronization device 30 can be deployed in the aforementioned electronic device to perform the aforementioned time synchronization method. Figure 4As shown, the time synchronization device 30 includes a receiving unit 301, a determining unit 302, a processing unit 303, and a sending unit 304.

[0064] The receiving unit 301 is used to receive the synchronization pulse signal sent by the upper-level clock device, and the first B code signal carrying the first time information. For example, as... Figure 2 As shown, the receiving unit 301 can be used to execute S201.

[0065] The determining unit 302 is used to determine the first time information in the first B code. For example, as... Figure 2 As shown, the determining unit 302 can be used to execute S202.

[0066] Processing unit 303 is used to adjust the first time information in the first B-code signal based on the received synchronization pulse signal and a preset high-frequency clock to obtain second time information. For example, as Figure 2 As shown, the processing unit 303 can be used to execute S203.

[0067] The transmitting unit 304 is used to send a second B-code signal carrying second time information to the lower-level clock device after the time interval corresponding to the synchronization pulse signal. For example, Figure 2 As shown, the processing unit 303 can be used to execute S204.

[0068] Optional, such as Figure 4 As shown, in the time synchronization device 30 provided in this embodiment of the invention, the processing unit 303 is specifically used for:

[0069] Based on a high-frequency clock, the time synchronization point of the synchronization pulse signal is obtained. The time synchronization point is the rising edge. For example, as shown... Figure 3 As shown, the processing unit 303 can be used to execute S2031.

[0070] Based on a high-frequency clock and a time synchronization point, the first time information is adjusted to the second time information. For example, such as... Figure 3 As shown, the processing unit 303 can be used to execute S2032.

[0071] Optional, such as Figure 4 As shown, in the time synchronization device 30 provided in this embodiment of the invention, the processing unit 303 is specifically used to align the reference code in the first time information with the time synchronization point based on a high-frequency clock to obtain the second time information.

[0072] When the functions of the integrated modules described above are implemented in hardware, this embodiment of the invention provides a possible structural diagram of an electronic device. This electronic device is used to execute the time synchronization method described above. For example... Figure 5As shown, the electronic device 40 includes a processor 401, a memory 402, and a bus 403. The processor 401 and the memory 402 can be connected via the bus 403.

[0073] Processor 401 is the control center of the communication device. It can be a single processor or a collective term for multiple processing elements. For example, processor 401 can be a general-purpose central processing unit (CPU) or other general-purpose processors. Among them, the general-purpose processor can be a microprocessor or any conventional processor.

[0074] As one embodiment, processor 401 may include one or more CPUs, for example Figure 5 CPU 0 and CPU 1 are shown in the diagram.

[0075] The memory 402 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0076] As one possible implementation, the memory 402 can exist independently of the processor 401. The memory 402 can be connected to the processor 401 via a bus 403 and is used to store instructions or program code. When the processor 401 calls and executes the instructions or program code stored in the memory 402, it can implement the time synchronization method provided in this embodiment of the invention.

[0077] In another possible implementation, the memory 402 can also be integrated with the processor 401.

[0078] Bus 403 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0079] It should be pointed out that, Figure 5 The structure shown does not constitute a limitation on the electronic device 40. Except... Figure 5 In addition to the components shown, the electronic device 40 may include more or fewer components than illustrated, or combine certain components, or have different component arrangements.

[0080] As an example, combined Figure 4 The functions implemented by the receiving unit 301, determining unit 302, processing unit 303, and sending unit 304 in the time synchronization device 30 are the same as those of the receiving unit 301, determining unit 302, processing unit 303, and sending unit 304. Figure 5 The processor 401 in it has the same function.

[0081] Optional, such as Figure 5 As shown, the electronic device provided in this embodiment of the invention may further include a communication interface 404.

[0082] Communication interface 404 is used to connect with other devices via a communication network. This communication network can be Ethernet, a wireless access network, a wireless local area network (WLAN), etc. Communication interface 404 may include a receiving unit for receiving data and a transmitting unit for transmitting data.

[0083] In one design, the communication interface in the electronic device provided by the embodiments of the present invention can also be integrated into the processor.

[0084] Figure 6 Another hardware structure of the electronic device in an embodiment of the present invention is shown. For example... Figure 6 As shown, the electronic device 50 may include a processor 501 and a communication interface 502. The processor 501 is coupled to the communication interface 502.

[0085] The functions of processor 501 can be referred to in the description of processor 401 above. In addition, processor 501 also has storage functions, which can be referred to in the description of memory 402 above.

[0086] The communication interface 502 is used to provide data to the processor 501. The communication interface 502 can be an internal interface of the communication device or an external interface of the communication device (equivalent to the communication interface 404).

[0087] It should be pointed out that, Figure 6 The structures shown do not constitute a limitation on electronic devices, except... Figure 6 In addition to the components shown, the electronic device 50 may include more or fewer components than illustrated, or combine certain components, or have different component arrangements.

[0088] Through the above description of the embodiments, those skilled in the art will clearly understand that, for the sake of convenience and brevity, only the division of the above functional units is used as an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the device can be divided into different functional units to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0089] This invention also provides a computer-readable storage medium storing instructions, which, when executed by a computer, perform each step of the method flow shown in the above-described method embodiments.

[0090] Embodiments of the present invention provide a computer program product containing instructions that, when executed on a computer, cause the computer to perform the time synchronization method described in the above method embodiments.

[0091] The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), registers, hard disks, optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing, or any other form of computer-readable storage medium in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). In embodiments of the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0092] Since the apparatus, device, computer-readable storage medium, and computer program product in the embodiments of the present invention can be applied to the above methods, the technical effects obtained can also be referred to the above method embodiments. The embodiments of the present invention will not be repeated here.

[0093] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A time synchronization method, characterized in that, include: It receives the synchronization pulse signal sent by the upper-level clock device, as well as the first B code signal carrying the first time information and jitter within 100μs; Determine the first time information in the first B code signal; Based on a preset high-frequency clock, the time synchronization point of the synchronization pulse signal is obtained; Based on the preset high-frequency clock and the time synchronization point, the position of the reference symbol in the first time information is shifted to align with the time synchronization point to obtain the second time information; After receiving the synchronization pulse signal, after a time interval of one cycle of the synchronization pulse signal, a second B code signal carrying the second time information is sent to the lower-level clock device.

2. The time synchronization method according to claim 1, characterized in that, The time synchronization point is the rising edge.

3. A time synchronization device, characterized in that, It includes a receiving unit, a determining unit, a processing unit, and a transmitting unit; The receiving unit is used to receive the synchronization pulse signal sent by the upper-level clock device, and the first B code signal carrying first time information and jitter within 100μs. The determining unit is used to determine the first time information in the first B code; The processing unit is used to obtain the time synchronization point of the synchronization pulse signal based on a preset high-frequency clock. The processing unit is further configured to offset the position of the reference symbol in the first time information to be aligned with the time synchronization point based on the preset high-frequency clock and the time synchronization point, so as to obtain the second time information; The transmitting unit is configured to, after receiving the synchronization pulse signal, send a second B code signal carrying the second time information to the lower-level clock device after a time interval of one cycle of the synchronization pulse signal.

4. The time synchronization device according to claim 3, characterized in that, The time synchronization point is the rising edge.

5. An electronic device, characterized in that, The electronic device includes a memory and a processor; The memory and the processor are coupled; The memory is used to store computer program code, which includes computer instructions; When the processor executes the computer instructions, the electronic device performs the time synchronization method as described in any one of claims 1-2.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the time synchronization method as described in any one of claims 1-2.

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