Non-volatile reconfigurable compact all-optical logic gates based on the phase change material Sb2Se3

Abstract

The application discloses a nonvolatile reconfigurable compact all-optical logic gate based on a phase change material Sb2Se3 and belongs to the technical field of photonic information devices; the all-optical logic gate structure is designed on an insulating substrate silicon wafer and comprises a first input waveguide A, an intermediate control waveguide C, a second input waveguide B, an intermediate design region and an output waveguide Y. The all-optical logic gate device has an ultra-small footprint of 2.4mu m x 2.4mu m, realizes the reconfigurable characteristic through the nonvolatility of the fused phase change material, realizes four all-optical logic gates of NOT, OR, AND and XOR on the insulating substrate silicon wafer through a direct binary search algorithm (DBS), and simulation results show that the designed device has good logic contrast; the reconfigurable ultra-compact logic gate will become a potential advantage of nanophotonic integrated circuit application.

Description

Technical Field

[0001] This invention relates to an all-optical logic gate, specifically to a non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb2Se3, belonging to the field of photonic information device technology. Background Technology

[0002] In future all-optical networks, optical computing, optical switching, and optical transmission are the core units for realizing all-optical signal processing, and they all rely on all-optical logic gates for operation. Therefore, all-optical logic gates have enormous application potential in future all-optical high-speed communication networks and next-generation optical computers. Many schemes have been proposed to implement all-optical logic gates, such as photonic crystals and semiconductor amplifiers. However, although these schemes offer higher contrast, they still face difficulties in achieving ultra-small size and high integration, and their functions are fixed and lack reconfigurability.

[0003] To overcome the aforementioned drawbacks, optical phase change materials (O-PCMs) are promising candidates for constructing dynamically tunable devices. Their high modulation intensity, large refractive index difference between amorphous and crystalline states, and low optical power consumption have attracted significant research interest. O-PCMs are widely used in various optical devices, such as switches, photonic memories, mode converters, programmable elements, and power dividers. Several O-PCMs are widely used in various optical devices, including vanadium dioxide (VO2), Ge2Sb2Te5 (GST), and Ge2S2Se4Te1 (GSST). Even though VO2 undergoes a significant refractive index change during phase transition, it requires specific power to maintain this state and suffers from high losses. While GST offers better optical performance than VO2, its absorption loss in the crystalline phase (K = 1.49) is significantly higher than that in the amorphous phase (K = 0.12) at telecommunication wavelengths. GSST replaces the Te portion of GST with Se. For example, the patent document CN113191115B, entitled "A Programmable Arbitrary Power Divider Based on DBS Algorithm," uses GSST as a filling material and achieves arbitrary power splitting ratios by changing the state of GSST through external power application. Despite these improvements, its absorption loss remains significant.

[0004] In recent research, antimony selenide (Sb₂Se₃) has become an ideal O-PCM for programmable optics in the telecommunications band due to its advantages such as extremely low loss at 1550 nm (k≈0), high refractive index contrast (Δn≈0.77), and refractive indices of crystalline and amorphous states closer to Si, which is beneficial for device integration. However, there is currently no method to apply Sb₂Se₃ to construct all-optical logic gates to realize four all-optical logic gates: NOT, OR, AND, and XOR.

[0005] Therefore, it is necessary to construct an all-optical logic gate based on the phase change material Sb2Se3, which can achieve reconfigurability by utilizing non-volatile phase change materials and also achieve high integration to achieve an ultra-compact logic gate. Summary of the Invention

[0006] The purpose of this invention is to overcome the problems of difficult integration and limited functionality in existing all-optical logic gates, and to provide a non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb2Se3. It adopts a silicon and Sb2Se3 hybrid structure, embedding Sb2Se3 into the silicon wafer, and uses a direct binary search algorithm to implement four all-optical logic gates (NOT, OR, AND, and XOR) on an insulating substrate silicon wafer. This all-optical logic gate has good logic contrast, reconfigurability, and ultra-compact characteristics.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a non-volatile reconfigurable compact all-optical logic gate based on the phase change material Sb2Se3, wherein the all-optical logic gate structure is designed on an insulating substrate silicon wafer and includes a first input waveguide A, an intermediate control waveguide C, a second input waveguide B, an intermediate design region, and an output waveguide Y;

[0008] The intermediate design region is composed of a silicon wafer with an etched nano-prism array structure filled with the phase change material Sb2Se3. The intermediate design region is divided into several square pixels, and the filling material in each pixel is either Si or Sb2Se3. The states of Sb2Se3 include a-Sb2Se3 amorphous state and c-Sb2Se3 crystalline state.

[0009] The intermediate control waveguide C continuously inputs the light source into the intermediate design area. Using a randomized initial structure, Sb2Se3 square pillars are randomly filled into the silicon wafer, and the first pixel is selected as the starting point. The quality factor FOM_old of the logic gate under this structure is calculated by the DBS algorithm. The filling material of this pixel is switched and the quality factor FOM_new of the logic gate is calculated again. If FOM_new > FOM_old, the material of this pixel is retained; otherwise, the original material of this pixel is returned, and the process continues to read the next pixel. The calculation is iteratively performed on all pixels, and finally two structures are constructed: one structure implements OR and NOT gates, and the other structure implements AND and XOR gates.

[0010] When calculating the quality factor (FOM) of logic gates using the DBS algorithm, the quality factor FOM is divided into two types based on the two constructed structures: FOM1, which implements OR and NOT gate structures, and FOM2, which implements AND and XOR gate structures.

[0011] FOM1 = FOM_c + FOM_a, where,

[0012] OR Gate:

[0013] FOM_a=-FOM_00a-abs(FOM_11a-1)-abs(FOM_10a-1)-abs(FOM_01a-1),

[0014] NOT gate: FOM_c = 2 * FOM_0c - 1.5 * FOM_1c;

[0015] FOM2 = FOM_a + 3 * FOM_c, where,

[0016] AND Gate:

[0017] FOM_a=1.5*FOM_11a-3*FOM_01a-5*FOM_10a-FOM_00a-abs(FOM_10a-FOM_01a),

[0018] XOR Gate:

[0019] FOM_c=3*FOM_10c+5*FOM_01c-5*FOM_11c-1.5*FOM_00c-2*abs(FOM_10c-FOM_01c);

[0020] In the formula, FOM_c is the quality factor value of c-Sb2Se3 in the crystalline state, FOM_a is the quality factor value of a-Sb2Se3 in the amorphous state, a indicates that Sb2Se3 is amorphous, c indicates that Sb2Se3 is crystalline, and abs indicates that the absolute value is taken.

[0021] In both constructed structures, different logic gates are implemented by adjusting the state of Sb2Se3 through external electric heating. The NOT and XOR gates are implemented in the c-Sb2Se3 crystalline state, and the OR and AND gates are implemented in the a-Sb2Se3 amorphous state.

[0022] The insulating silicon substrate consists of three layers: a 3μm thick silicon dioxide layer in the middle, a 220nm thick silicon layer on top, and a 2μm thick silicon layer on top of the bottom. The four waveguides—the first input waveguide A, the intermediate control waveguide C, the second input waveguide B, and the output waveguide Y—are all 400nm wide, with a 400nm spacing between the input waveguides and a thickness of 220nm.

[0023] The size of the intermediate design region is 2.4 × 2.4 μm. 2 The size of each pixel is 100×100nm, depending on the manufacturing process. 2 It is divided into 24×24 pixels.

[0024] The beneficial effects of this invention are:

[0025] 1) This invention is based on a non-volatile, reconfigurable, compact all-optical logic gate made of phase change material Sb2Se3. It adopts a silicon and Sb2Se3 hybrid structure, embedding Sb2Se3 into a silicon wafer, and uses a direct binary search algorithm to implement four all-optical logic gates (NOT, OR, AND, and XOR) on an insulating substrate silicon wafer. The all-optical logic gate has good logic contrast, reconfigurability, and ultra-compact characteristics. It overcomes the problems of difficult integration and single function in existing all-optical logic gates, and provides a new option for developing optoelectronic integration schemes of the same scale.

[0026] 2) The simulation results of the all-optical logic gates designed in this invention show that the logic contrast of the AND gate, OR gate, NOT gate and XOR gate are 3.3dB, 7.64dB, 6.1dB and 18.92dB respectively at a telecommunication wavelength of 1550nm. The device has good logic contrast, which will become a potential advantage for the application of nanophotonic integrated circuits. Attached Figure Description

[0027] Figure 1 This is a graphical representation and structural parameter diagram of the all-optical logic gate designed for this invention;

[0028] Figure 2 The refractive index curve and extinction coefficient curve of Sb2Se3 in the C-band were measured according to the present invention.

[0029] Figure 3 This is an optimization flowchart of the DBS algorithm used in this invention;

[0030] Figure 4The graphic symbol, light field intensity distribution, and output light power diagram of the all-optical OR logic gate designed for this invention;

[0031] Figure 5 The graphic symbol, light field intensity distribution, and output light power diagram of the all-optical NOT logic gate designed for this invention;

[0032] Figure 6 The graphic symbol, light field intensity distribution, and output light power diagram of the all-optical AND logic gate designed for this invention;

[0033] Figure 7 The graphic symbol, light field intensity distribution, and output light power diagram of the all-optical XOR logic gate designed for this invention. Detailed Implementation

[0034] The present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments.

[0035] 1. Example: This invention provides a non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb₂Se₃. The all-optical logic gate structure is designed on an insulating silicon substrate and includes a first input waveguide A, an intermediate control waveguide C, a second input waveguide B, an intermediate design region, and an output waveguide Y. A 2μm thick silicon layer, a 3μm thick silicon dioxide layer, and a 220nm thick silicon layer are used as standard silicon-on-insulator (SOI) layers. The 220nm silicon layer is located on the top layer, the silicon dioxide layer in the middle layer, and the 2μm silicon layer on the bottom layer. The width of each of the four waveguides—first input waveguide A, intermediate control waveguide C, second input waveguide B, and output waveguide Y—is 400nm, with a spacing of 400nm between the input waveguides and a thickness of 220nm. Figure 1 As shown, the C-band transverse electrical (TE mode) is input from the left end waveguide, passes through the coupling region, and outputs from the right end waveguide.

[0036] The size of the intermediate design area is 2.4 × 2.4 μm. 2 The size of each pixel is 100×100nm, depending on the manufacturing process. 2 The area is divided into 24×24 pixels; the central design region consists of a silicon wafer with an etched nano-prismatic array structure filled with the phase-change material Sb₂Se₃. The filling material within each pixel is either Si or Sb₂Se₃, where the Sb₂Se₃ states include a-Sb₂Se₃ amorphous and c-Sb₂Se₃ crystalline states, such as... Figure 2As shown, the refractive index and extinction coefficient curves of Sb2Se3 in the C-band are displayed. It can be clearly seen that its extinction coefficient is low. Two structures were designed and constructed using its crystalline and amorphous states, realizing four logic gates: NOT, OR, AND, and XOR. In both structures, the state of Sb2Se3 is controlled by external electric heating to realize different logic gates. The NOT and XOR gates are realized in the c-Sb2Se3 crystalline state, and the OR and AND gates are realized in the a-Sb2Se3 amorphous state.

[0037] The 3D-FDTD method was used for simulation. To address the issue of light output in the output waveguide even when there is no light source input in the two input waveguides, a control waveguide was set up during the simulation, and the intermediate control waveguide C was required to have a light source input continuously. The intermediate control waveguide C continuously inputs the light source into the intermediate design area.

[0038] The all-optical logic gates employ a DBS iterative optimization design. The optimization process of the DBS algorithm is as follows: Figure 3 As shown, the materials in the initial structure include Si and Sb2Se3. The algorithm flow includes: Random Initialization; Initialization; Select the first pixel; Calculate and save the FOM value; Keep this pixel state and select the next pixel if the FOM value is not met; Change the state of the pixel and calculate and save the FOM value; FOM value increase; Meet the requirements of FOM? If yes, check if the FOM requirements are met; Return to the original state if no; The algorithm ends and the final structure is saved if the FOM value is met.

[0039] Before optimization, a randomized initial structure is used to randomly fill Sb2Se3 square pillars in the silicon wafer, and the first pixel is selected as the starting point. The quality factor FOM_old of the logic gate under this structure is calculated by the DBS algorithm. The filling material of this pixel is switched and the quality factor FOM_new of the logic gate is calculated again. If FOM_new>FOM_old, the material of this pixel is retained; otherwise, the original material of the pixel is returned. The process continues to read the next pixel and iterates through all pixels. Finally, two structures are constructed: one structure implements OR and NOT gates, and the other structure implements AND and XOR gates.

[0040] When calculating the quality factor (FOM) of logic gates using the DBS algorithm, the quality factor FOM is divided into two types based on the two constructed structures: FOM1, which implements OR and NOT gate structures, and FOM2, which implements AND and XOR gate structures.

[0041] FOM1 = FOM_c + FOM_a, where,

[0042] OR Gate:

[0043] FOM_a=-FOM_00a-abs(FOM_11a-1)-abs(FOM_10a-1)-abs(FOM_01a-1),

[0044] NOT gate: FOM_c = 2 * FOM_0c - 1.5 * FOM_1c;

[0045] FOM2 = FOM_a + 3 * FOM_c, where,

[0046] AND Gate:

[0047] FOM_a=1.5*FOM_11a-3*FOM_01a-5*FOM_10a-FOM_00a-abs(FOM_10a-FOM_01a),

[0048] XOR Gate:

[0049] FOM_c=3*FOM_10c+5*FOM_01c-5*FOM_11c-1.5*FOM_00c-2*abs(FOM_10c-FOM_01c);

[0050] In the formula, FOM_c is the quality factor value of c-Sb2Se3 in the crystalline state, FOM_a is the quality factor value of a-Sb2Se3 in the amorphous state, a indicates that Sb2Se3 is amorphous, c indicates that Sb2Se3 is crystalline, and abs indicates that the absolute value is taken.

[0051] For example, design the first structure to implement the NOT and OR functions. The size of the intermediate design area is 2.4×2.4μm 2 , the material is SI or Sb2Se3. Sb2Se3 has crystalline and amorphous states, and the refractive indices of the crystalline and amorphous states are different. The crystalline state is used for the NOT gate, and the amorphous state is used for the OR gate. First, select a pixel point and calculate the figure of merit FOM_old in this state. Then switch the material (if it is SI, it becomes the phase change material Sb2Se3; if it is the phase change material Sb2Se3, it becomes SI). Then change the phase change material to the crystalline state and calculate the value of FOM_c. Then change the phase change material to the amorphous state and calculate the value of FOM_a. Finally, add these two values to get FOM_new. If FOM_new > FOM_old, keep this material (if SI is changed to the phase change material Sb2Se3, it is the phase change material Sb2Se3). If FOM_new < FOM_old (switch back to SI). Iteratively traverse all pixel points until the required functional requirements are met.

[0052] 2. Simulation experiment:

[0053] The three-dimensional finite-difference time-domain method 3D-FDTD is used to simulate and numerically analyze the four logic gates designed in this invention.

[0054] 2.1 All-optical "OR" logic gate: An all-optical "OR" logic gate is designed using the amorphous state of Sb2Se3.

[0055] Figure 4 (a) is the graphical symbol representation of the "OR" gate. Figure 4 (b) is the structural distribution of the designed "OR" gate. The design of the "OR" gate mainly has two input waveguides, one output waveguide, and an intermediate control waveguide C. The intermediate control waveguide C continuously inputs optical signals to play a control role.

[0056] Figure 4 (c), (e) are the optical field intensity distributions of the "OR" logic gate at the working wavelength of 1550nm. Figure 4 (d) is the output power of the "OR" logic gate at the working wavelength of 1550nm. It can be seen that although the logic gate is designed at the working wavelength, the output power has good stability in the entire C band.

[0057] Table 1 shows the output optical power and binary output truth table data of the designed all-optical "OR" logic gate.

[0058]

[0059] Set the thresholds of logic "0" and logic "1" in the above table to 0.5P in , when the output optical power is lower than 0.5Pin When the output optical power is higher than 0.5P, it equals logic "0". in When the time is equal to logic "1", setting the input signals of both input waveguides A and B to "0" will yield 0.13P. in The output optical power is represented as logic "0".

[0060] When the input signal to waveguide A is "0" and the input signal to waveguide B is "1", 0.78P can be obtained. in The output optical power is represented as logic "1".

[0061] When the input signal to waveguide A is "1" and the input signal to waveguide B is "0", 0.82P can be obtained. in The output optical power is represented as logic "1".

[0062] Set the input signals of input waveguides A and B to "1", and the output optical power to 2.05P. in This is considered a logic "1". Finally, by comparing the lowest logic "1" with the highest logic "0", the contrast of the "OR" logic gate is found to be 6.1dB.

[0063] 2.2 All-optical NOT logic gate: An all-optical NOT logic gate was designed using the crystalline state of Sb2Se3.

[0064] Figure 5 (a) is the graphical symbol representation of the NOT logic gate. Figure 5 (b) The designed NOT gate logic structure mainly uses waveguide B as the input light source waveguide, waveguide C as the control waveguide, and waveguide Y as the output waveguide. Similarly, waveguide C always has a light source input, which ensures that when there is no light source input in waveguide B, the output of waveguide Y can be logic "1" under the action of the NOT logic gate.

[0065] Figure 5 (c), (d), (e), and (f) are the light field intensity distribution diagrams of the NOT gate. When there is no light source input in the input waveguide B, the light source controlling the waveguide is transmitted to the output waveguide Y through the middle design area, which is logic "1". Conversely, when there is a light source input in the input waveguide B, the output waveguide Y exhibits logic "0".

[0066] Figure 5 (g) shows the output optical power diagram of the NOT gate throughout the C-band. The NOT gate has good stability throughout the C-band.

[0067] Table 2 shows the output optical power and truth table data of the designed all-optical NOT logic gate.

[0068]

[0069] As shown in Table 2, the output power should be set to be greater than 0.5P. in Represented as logic "1", the output power is less than 0.5P. in Set to logic "0", logic contrast is 6.1dB.

[0070] 2.3 All-optical AND logic gates:

[0071] Figure 6 (a) is the graphical representation of an AND logic gate. Figure 6 (b) Considering the designed AND logic gate structure with four ports, light is applied to the central design area to perform all logical AND operations. The light field intensity distribution for all logical AND operations is as follows: Figure 6 As shown in (c), (d), (e), and (f). Figure 6 (g) shows the output optical power of all logic operations of the C-band all-optical AND logic gate.

[0072] Table 3 shows the output optical power and logic threshold of the logical AND operation at a working wavelength of 1550nm.

[0073]

[0074] The threshold value for the NOT logic gate is designed to be 0.6P. in Set the output power to be higher than 0.6P. in A logic "1" indicates an output power of less than 0.6P. in The value is logic "0". When there is no light source input in waveguides A and B, the output power of waveguide Y is 0.16P. in This is considered logic "0". When both A and B input waveguides have light source outputs, the output optical power of the Y waveguide is 1.03P. in This is considered a logic "1". When there is a light source input in waveguide A and no light source input in waveguide B, 0.48P is generated. in The output power is considered as logic "0". Conversely, when waveguide B has a light source input while waveguide A does not, 0.41P is generated. in The output power is considered as logic "0".

[0075] Calculations show that the NOT gate has a logic contrast of 3.31 dB, and this structure offers the advantages of being more compact and reconfigurable.

[0076] 2.4 All-optical XOR logic gate:

[0077] Figure 7 (a) is the graphical symbol representation of the "XOR" logic gate. Figure 7(b) is the layout of the "XOR" logic gates after DBS optimization. Figure 7 (c), (d), (e), and (f) represent the light field distributions of the logical XOR operation. Figure 7 (g) is a numerical analysis of each logical operation of the proposed "XOR" logic gate.

[0078] Table 4 shows the output power and threshold of all logical XOR operations at a 1550nm telecommunication wavelength.

[0079]

[0080] As shown in Table 4, the output power should be set below 0.3P. in The value is logic "0", which is higher than 0.3P. in The value is logic "1". Similar to the above, consider three ports: when waveguide A and waveguide B receive the light source, 0.004P is generated. in The output power is 0.005P when there is no light source input to the input waveguide. in When waveguide A has a light source input and waveguide B has no light source input, the output optical power of waveguide Y is 0.39P. in When waveguide A has no light source input and waveguide B has a light source input, the output optical power is 0.4P. in .

[0081] Calculations show that the logic contrast is 18.92dB, and the structure offers the advantages of being ultra-compact, non-volatile, and having high CR.

[0082] This invention employs a reverse optimization method to realize an ultra-compact, reconfigurable all-optical logic gate with a footprint of 2.4 μm × 2.4 μm using two states of phase change materials. This includes four all-optical logic gates: AND, OR, NOT, and XOR. Simulations and numerical analyses using 3D-FDTD were conducted, and the logic contrast ratios of the all-optical logic gates at a 1550 nm telecommunication wavelength were 3.3 dB, 7.64 dB, 6.1 dB, and 18.92 dB, respectively. This structure enables functional diversity of the logic gates, and its ultra-compact nature is beneficial for nanophotonic integration.

[0083] The above description is only used to illustrate the technical solution of the present invention and is not intended to limit it. Any other modifications or equivalent substitutions made by those skilled in the art to the technical solution of the present invention, as long as they do not depart from the spirit and scope of the technical solution of the present invention, should be covered within the scope of the claims of the present invention.

Claims

1. A non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb₂Se₃, characterized in that: The all-optical logic gate structure is designed on an insulating substrate silicon wafer and includes a first input waveguide A, an intermediate control waveguide C, a second input waveguide B, an intermediate design region, and an output waveguide Y. The intermediate design region is composed of a silicon wafer with an etched nano-prism array structure filled with the phase change material Sb2Se3. The intermediate design region is divided into several square pixels, and the filling material in each pixel is Si or Sb2Se3, wherein the state of Sb2Se3 includes a-Sb2Se3 amorphous state and c-Sb2Se3 crystalline state. The intermediate control waveguide C continuously inputs the light source into the intermediate design area, adopts a randomized initial structure, and selects the first pixel as the starting point. The quality factor FOM_old of the logic gate under this structure is calculated by the DBS algorithm. The filling material of this pixel is switched and the quality factor FOM_new of the logic gate is calculated again. If FOM_new > FOM_old, the material of the pixel at this time is retained; otherwise, the original material of the pixel is returned, and the process continues to read the next pixel. The calculation is iteratively performed on all pixels, and finally two structures are constructed: one structure implements OR and NOT gates, and the other structure implements AND and XOR gates.

2. The non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb₂Se₃ according to claim 1, characterized in that: When calculating the quality factor (FOM) of logic gates using the DBS optimization design algorithm, the quality factor FOM is divided into two types based on the two constructed structures: FOM1, which implements OR and NOT gate structures, and FOM2, which implements AND and XOR gate structures. FOM1 = FOM_c + FOM_a, where, OR Gate: FOM_a=-FOM_00a-abs(FOM_11a-1)-abs(FOM_10a-1)-abs(FOM_01a-1), NOT gate: FOM_c = 2 * FOM_0c - 1.5 * FOM_1c; FOM2 = FOM_a + 3 * FOM_c, where, AND Gate: FOM_a=1.5*FOM_11a-3*FOM_01a-5*FOM_10a-FOM_00a-abs(FOM_10a-FOM_01a), XOR Gate: FOM_c=3*FOM_10c+5*FOM_01c-5*FOM_11c-1.5*FOM_00c-2*abs(FOM_10c-FOM_01c); In the formula, FOM_c is the quality factor value of c-Sb2Se3 in the crystalline state, FOM_a is the quality factor value of a-Sb2Se3 in the amorphous state, a indicates that Sb2Se3 is amorphous, c indicates that Sb2Se3 is crystalline, and abs indicates that the absolute value is taken.

3. The non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb₂Se₃ according to claim 1 or 2, characterized in that: In both constructed structures, different logic gates are implemented by adjusting the state of Sb2Se3 through external electric heating. The NOT and XOR gates are implemented in the c-Sb2Se3 crystalline state, and the OR and AND gates are implemented in the a-Sb2Se3 amorphous state.

4. The non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb₂Se₃ according to claim 1, characterized in that: The insulating substrate silicon wafer consists of three layers: a 3μm thick silicon dioxide layer in the middle, a 220nm thick silicon layer on top, and a 2μm thick silicon layer on the bottom.

5. The non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb₂Se₃ according to claim 1, characterized in that: The width of the four waveguides—the first input waveguide A, the intermediate control waveguide C, the second input waveguide B, and the output waveguide Y—is 400 nm, with a spacing of 400 nm between the input waveguides and a thickness of 220 nm.

6. The non-volatile, reconfigurable, compact all-optical logic gate based on the phase change material Sb₂Se₃ according to claim 1, characterized in that: The size of the intermediate design region is 2.4 × 2.4 μm. 2 The size of each pixel is 100×100nm, depending on the manufacturing process. 2 It is divided into 24×24 pixels.

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