Data processing device, communication system, chip, board card, electronic equipment

Abstract

A data processing apparatus includes a first signal generation unit, a delay unit, and a second signal generation unit. The first signal generation unit generates a first handshake signal based on a first signal sent by a first device and a handshake protocol used between the first device and a second device. The first handshake signal is then delayed by the delay unit and sent to the second signal generation unit, so that the second signal generation unit generates the first signal based on the delayed first handshake signal and the handshake protocol, and then sends it to the second device. The second signal generation unit generates a second handshake signal based on a second signal sent by the second device and the handshake protocol. The second handshake signal is then delayed by the delay unit and sent to the first signal generation unit, so that the first signal generation unit generates the second signal based on the delayed second handshake signal and the handshake protocol, and then sends it to the first device.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to data processing devices, communication systems, chips, circuit boards, and electronic devices. Background Technology

[0002] Chip architectures require various bus protocols to achieve data transmission and communication between the master and slave ends. These protocols primarily use a handshake mechanism (ready / valid) to synchronize data. When the transmission rates at the master and slave ends are mismatched, certain methods are needed to mitigate this difference and improve data transmission efficiency. However, the methods used to mitigate this rate difference in related technologies have limited universality. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a data processing apparatus, comprising: a first signal generation unit, a delay unit, and a second signal generation unit; the first signal generation unit is configured to generate a first handshake signal based on a first signal sent by a first device and a handshake protocol used between the first device and a second device, and to delay the first handshake signal through the delay unit before sending it to the second signal generation unit, so that the second signal generation unit generates the first signal based on the delayed first handshake signal and the handshake protocol and then sends it to the second device; the second signal generation unit is configured to generate a second handshake signal based on a second signal sent by the second device and the handshake protocol, and to delay the second handshake signal through the delay unit before sending it to the first signal generation unit, so that the first signal generation unit generates the second signal based on the delayed second handshake signal and the handshake protocol and sends it to the first device; the first signal and the second signal are handshake signals used in the handshake protocol.

[0004] Secondly, embodiments of this disclosure provide a communication system, the communication system comprising: a first device, a second device, and a data processing apparatus as described in any embodiment of this disclosure.

[0005] Thirdly, embodiments of this disclosure provide a chip, the chip including the data processing device described in any embodiment of this disclosure, or the communication system described in any embodiment of this disclosure.

[0006] Fourthly, embodiments of this disclosure provide a board, the board including a package structure encapsulating at least one chip as described in any embodiment of this disclosure.

[0007] Fifthly, embodiments of this disclosure provide an electronic device, including a data processing device as described in any embodiment of this disclosure, a chip as described in any embodiment of this disclosure, or a board as described in any embodiment of this disclosure.

[0008] This embodiment employs a first signal generation unit and a second signal generation unit to uniformly convert the handshake signals used in various handshake protocols into explicit first handshake signals and explicit second handshake signals. A delay unit then delays the explicit first and second handshake signals. The delayed first and second handshake signals are then converted back to the corresponding handshake signals according to the adopted handshake protocol, enabling the first and second devices to recognize them. This decouples protocol conversion from signal delay, making the delay unit applicable to application scenarios using various types of handshake protocols, thereby improving the versatility of the delay unit.

[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0011] Figure 1 This is a schematic diagram illustrating the principle of the handshake mechanism in related technologies.

[0012] Figure 2 This is a schematic diagram of a data processing apparatus according to an embodiment of the present disclosure.

[0013] Figure 3A This is a schematic diagram illustrating the working principle of the delay unit in a single-channel configuration.

[0014] Figure 3B This is a schematic diagram illustrating the working principle of the delay unit in a multi-channel configuration.

[0015] Figure 3C This is a schematic diagram illustrating the working principle of a delay unit in the case of multiple channels and multiple delay sub-units.

[0016] Figure 4A and Figure 4B These are schematic diagrams illustrating the principle of data transmission between the first and second devices.

[0017] Figure 5 This is a schematic diagram of a data processing apparatus according to another embodiment of the present disclosure.

[0018] Figure 6 This is a schematic diagram of a data processing device used in the AXI protocol.

[0019] Figure 7 This is a schematic diagram of a data processing device used in the APB protocol.

[0020] Figure 8 This is a schematic diagram of a board card according to an embodiment of this disclosure. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0022] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Additionally, the term “at least one” herein means any combination of at least two of any one or more of a plurality.

[0023] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0024] To enable those skilled in the art to better understand the technical solutions in the embodiments of this disclosure, and to make the above-mentioned objectives, features and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0025] With the continuous development of chips, especially system-on-a-chip (SoC) and application-specific integrated circuit (ASIC) chips, various bus protocols are often used in chip architectures to implement data transmission and communication between master and slave ends. These protocols (such as the Advanced Microcontroller Bus Architecture (AMBA) protocol) generally employ a handshake mechanism to synchronize data. The handshake mechanism uses two handshake signals, referred to as the first handshake signal and the second handshake signal. In some embodiments, the first handshake signal is a valid signal, and the second handshake signal is a ready signal. For ease of description, the following explanation will use the first handshake signal as valid and the second handshake signal as ready as an example. See also... Figure 1 The general principle of a handshake protocol is as follows:

[0026] (1) The master end 101 writes data to the slave end 102 (write operation). At this time, the first handshake signal can be called the write valid signal, and the second handshake signal can be called the write ready signal.

[0027] When slave 102 is ready to receive data, it will send a write ready signal to master 101 to inform master 101 that slave 102 is ready to receive and write data.

[0028] After receiving the write ready signal, the master end 101 sends the data to be written to the slave end 102 and sends a write valid signal to mark the valid data range. Therefore, data can only be effectively transmitted when both the write ready signal and the write valid signal are valid.

[0029] (2) Read data from terminal 102 and send it to terminal 101 (read operation). At this time, the first handshake signal can be called the read valid signal and the second handshake signal can be called the read ready signal.

[0030] When the master terminal 101 is ready to receive data, it will send a read ready signal to the slave terminal 102 to inform the slave terminal 102 that the master terminal 101 is ready to receive the data to be read.

[0031] After receiving the read ready signal from slave terminal 102, it sends the data to be read to master terminal 101 and simultaneously sends a read valid signal to indicate the valid range of the data. Therefore, data can only be effectively transmitted when both the read ready signal and the read valid signal are valid.

[0032] In summary, whether the master 101 sends data to the slave 102 or the slave 102 sends data to the master 101, the handshake mechanism (i.e., both ready and valid must be valid) must be satisfied in order to complete valid data transmission.

[0033] However, when the transmission bandwidth or processing latency of the master and slave ends are mismatched, the transmission rates of the two ends will be mismatched, resulting in inefficient data transmission. Taking the example of master 101 writing data to slave 102, if the transmission rate of master 101 exceeds that of slave 102, slave 102 may not be able to receive the data sent by master 101 in time. In cases of mismatched transmission rates between master and slave, a backpressure waiting mechanism is typically used (i.e., one end pulls the ready signal low to inform the other end that data transmission is currently impossible, waiting for the ready signal to go high before transmission can proceed). However, the backpressure waiting mechanism can reduce transmission efficiency and may even exacerbate backpressure or cause deadlock.

[0034] To improve data transmission rates, related technologies propose inserting a delay timing module (also called a pipeline) between the master and slave ends to alleviate the transmission rate difference between the two ends. However, the delay unit 202 generally has poor versatility, and different handshake protocols require different delay units 202.

[0035] Based on this, embodiments of this disclosure provide a data processing apparatus, see [link to relevant documentation]. Figure 2 The data processing device includes:

[0036] A first signal generation unit 201, a delay unit 202, and a second signal generation unit 203;

[0037] The first signal generation unit 201 is used to generate a first handshake signal based on a first signal sent by the first device and the handshake protocol used between the first device and the second device, and to send the first handshake signal to the second signal generation unit 203 after delay processing by the delay unit 202, so that the second signal generation unit 203 generates the first signal based on the delayed first handshake signal and the handshake protocol and sends it to the second device.

[0038] The second signal generation unit 203 is used to generate a second handshake signal based on the second signal sent by the second device and the handshake protocol, and send the second handshake signal to the first signal generation unit 201 after delay processing by the delay unit 202, so that the first signal generation unit 201 generates the second signal based on the delayed second handshake signal and the handshake protocol and sends it to the first device.

[0039] The first signal and the second signal are the handshake signals used in the handshake protocol.

[0040] In this embodiment of the present disclosure, one of the first device and the second device may be the master device 101, such as a main processor; the other of the first device and the second device may be the slave device 102, such as a storage unit. In addition to the main processor and the storage unit, the master device 101 and the slave device 102 may also be other types of devices or components, which will not be listed here.

[0041] Different handshake protocols can be used between different first devices and different second devices, such as the Advanced Extensible Interface (AXI) protocol, the Advanced Peripheral Bus (APB) protocol, the Advanced High-performance Bus (AHB) protocol, the Advanced System Bus (ASB) protocol, the Generic Interface (GIF) protocol, the Advanced Trace Bus (ATB) protocol, and the AXI Coherency Extensions (ACE) protocol. The first and / or second signals used in different handshake protocols may be different. For example, the AXI protocol directly uses the ready and valid signals as handshake signals; that is, the first and second signals are the valid and ready signals themselves, respectively. In this case, the first and second signals can also be called the explicit valid and explicit ready signals, respectively. As another example, the APB protocol does not have an explicit valid signal. Instead, it performs a bitwise AND operation on the s_apb_psel and s_apb_penable signals, using the result as the valid signal and the s_apb_pready signal as the ready signal. In handshake protocols, one or more other signals that produce a valid or ready signal through certain operations (e.g., AND, OR, NOT, XOR, etc.) are called implicit valid or implicit ready signals. In the above examples, the s_apb_psel and s_apb_penable signals are both the first signal, and the first signal is the implicit valid signal, while the s_apb_pready signal is the second signal, and the second signal is the explicit ready signal.

[0042] Those skilled in the art will understand that the above embodiments are merely illustrative. In other handshake protocols, there may be one or more types of implicit valid signals. Although the first signal in the APB protocol in the above example is an implicit valid signal and the second signal is an explicit ready signal, in other handshake protocols, the first signal may be an implicit valid signal and the second signal may be an implicit ready signal, or the first signal may be an explicit valid signal and the second signal may be an implicit ready signal. Furthermore, the types of the first and second signals may both be greater than or equal to one. For ease of description, the first and second signals will be collectively referred to as handshake signals below.

[0043] The conversion process between implicit and explicit ready signals, and between implicit and explicit valid signals, can be implemented by the first signal generation unit 201 and the second signal generation unit 203. For example, after the first device outputs an implicit valid signal, the first signal generation unit 201 can convert the implicit valid signal into an explicit valid signal; similarly, after the second device outputs an implicit ready signal, the second signal generation unit 203 can convert the implicit ready signal into an explicit valid signal. Of course, if the first device outputs an explicit valid signal, the first signal generation unit 201 can directly output the explicit valid signal to the delay unit 202; similarly, if the second device outputs an explicit ready signal, the second signal generation unit 203 can directly output the explicit ready signal to the delay unit 202.

[0044] In related technologies, since different handshake protocols often use different handshake signals, different delay units 202 are needed depending on the type of handshake signal used in the handshake protocol to delay different handshake signals, resulting in poor versatility of the delay unit 202. To solve this problem, this embodiment uses a first signal generation unit 201 and a second signal generation unit 203 to uniformly convert the handshake signals used in various handshake protocols into explicit valid and explicit ready signals. Then, the delay unit 202 delays the explicit valid and explicit ready signals. The delayed valid and ready signals are then converted back to the corresponding handshake signals according to the handshake protocol used, so that the first and second devices can recognize them. In this way, the protocol conversion and signal delay are decoupled, making the delay unit 202 applicable to application scenarios using various types of handshake protocols, thereby improving the versatility of the delay unit 202.

[0045] In different application scenarios, the delay unit 202 can delay the received ready and valid signals by different amounts, which can be greater than or equal to one clock cycle. Optionally, the delay amount can be positively correlated with the difference in data transmission rates between the master and slave ends; that is, the greater the difference in data transmission rates between the master and slave ends, the greater the delay amount; the smaller the difference in data transmission rates between the master and slave ends, the smaller the delay amount. For example, assuming the data transmission rate of the master end 101 writing data is 64 GBps, the data transmission rate of the slave end 102 receiving data is 32 GBps, and the clock frequency is 1 GHz, the delay amount can be set to 20 clock cycles. As another example, assuming the data transmission rate of the master end 101 writing data is 64 GBps, the data transmission rate of the slave end 102 receiving data is 16 GBps, and the clock frequency is 1 GHz, the delay amount can be set to 40 clock cycles. Alternatively, the delay amount can be positively correlated with the degree of timing violation between the master and slave ends; that is, the greater the degree of timing violation, the greater the delay amount; conversely, the smaller the degree of timing violation, the smaller the delay amount. The timing violation level is used to characterize the difference between the current timing of the signal and the set timing.

[0046] The operating principle of the delay unit 202 in some embodiments is as follows: Figure 3A As shown, the valid signal output by the first signal generation unit 201, after being processed by the delay unit 202, can be delayed by n clock cycles (i.e., n beats) before being sent to the second signal generation unit 203; the ready signal output by the second signal generation unit 203 can be delayed by n clock cycles (i.e., n beats) before being sent to the first signal generation unit 201. Furthermore, data transmitted between the first device and the second device (taking the first device sending data to the second device as an example) can also be delayed by n clock cycles (i.e., n beats) from one end to the other end before being output.

[0047] In some embodiments, the delay unit 202 includes a plurality of cascaded delay sub-units 2021, each delay sub-unit 2021 being used to delay the valid signal and the ready signal by one clock cycle (i.e., one clock cycle) before outputting them. Since the delay amounts of the ready signal and the valid signal may differ in different application scenarios, the number of delay sub-units 2021 included in the delay unit 202 may also differ in different application scenarios. By employing n (n is a positive integer) cascaded delay sub-units 2021, the delay unit 202 can delay the received valid signal and the ready signal by n clock cycles (i.e., n clock cycles) respectively.

[0048] In some embodiments, the data processing apparatus further includes a configuration unit for configuring the operating state of each of the plurality of delay subunits 2021, including an enabled state and an disabled state. For example, the configuration unit may be a configuration register, which may store multiple configuration data bits, each corresponding to one delay subunit 2021. By setting each configuration data bit, the operating state of each delay subunit 2021 can be configured. Alternatively, the configuration register may be used to store information about the number of delay subunits 2021 that are enabled or disabled. Based on this information, taking the number of enabled delay subunits 2021 stored in the configuration register as an example, the operating state of a corresponding number of delay subunits 2021 can be set to enabled. The delay subunits 2021 set to enabled can be any of the plurality of delay subunits 2021, as long as their number matches the quantity information.

[0049] When a delay subunit 2021 is enabled, it can delay the received ready and valid signals before outputting them. When a delay subunit 2021 is disabled, it can directly output the received ready and valid signals. In this way, the delay amount of the delay unit 202 on the valid and ready signals can be dynamically configured for different application scenarios, making one delay subunit 2021 suitable for various applications. For example, assuming the total number of delay subunits 2021 is N, in the first application scenario, m (m≤N) delay subunits 2021 can be enabled by the configuration unit, thus delaying the ready and valid signals by m clock cycles. In the second application scenario, k (k≤N, and k≠m) delay subunits 2021 can be enabled by the configuration unit, thus delaying the ready and valid signals by k clock cycles.

[0050] In practical applications, the required delay amount for various application scenarios can also be determined in advance through simulation, and a corresponding number of delay sub-units 2021 can be set directly in the corresponding application scenario, so that each delay unit 202 is dedicated to the corresponding application scenario.

[0051] In some embodiments, the first device and the second device include one or more data transmission channels (hereinafter referred to as channels). For example, the first device and the second device may include one or more read channels, or one or more write channels, or one or more read channels and one or more write channels.

[0052] Based on the inclusion of multiple data transmission channels between the first device and the second device, the number of delay units 202 can be greater than one, with one delay unit 202 corresponding to each data transmission channel; the delay unit 202 corresponding to each data transmission channel can delay the valid signal and the ready signal on the data transmission channel by one clock cycle before outputting. For example, see... Figure 3B Assuming there are two channels, denoted as Channel 1 and Channel 2, the number of delay units 202 is also two, denoted as Channel 1 delay unit 202 and Channel 2 delay unit 202. The number of delay sub-units 2021 included in each of these two delay units 202 can be greater than or equal to one, and the number of delay sub-units 2021 included in the two delay units 202 can be the same or different. Each channel of the first device can transmit a first signal; the first signal transmitted by Channel 1 and the first signal transmitted by Channel 2 are denoted as Channel 1 first signal and Channel 2 first signal, respectively. Each channel of the second device can transmit a second signal; the second signal transmitted by Channel 1 and the second signal transmitted by Channel 2 are denoted as Channel 1 second signal and Channel 2 second signal, respectively.

[0053] Based on this, the first signal generation unit 201 can generate a channel 1 valid signal based on the first signal of channel 1 and output it to the channel 1 delay unit 202. The channel 1 delay unit 202 can delay the channel 1 valid signal and output it to the second signal generation unit 203. The second signal generation unit 203 can generate a channel 1 first signal based on the delayed channel 1 valid signal and output it to the second device. Similarly, the second signal generation unit 203 can generate a channel 1 ready signal based on the second signal of channel 1 and output it to the channel 1 delay unit 202. The channel 1 delay unit 202 can delay the channel 1 ready signal and output it to the first signal generation unit 201. The first signal generation unit 201 can generate a channel 1 second signal based on the delayed channel 1 ready signal and output it to the second device. The processing method on channel 2 is similar to that on channel 1, and will not be described again here.

[0054] The above embodiments illustrate a scenario where the number of channels between the first device and the second device is two. Those skilled in the art will understand that the above is merely an illustrative example, and in practical applications, the number of channels can also be greater than two.

[0055] Optionally, the first signal generation unit 201 and the second signal generation unit 203 may also include multiple channels. Each channel of the first signal generation unit 201 corresponds to a channel between the first device and the second device, and each channel of the second signal generation unit 203 corresponds to a channel between the first device and the second device. In this way, each channel of the first signal generation unit 201 can acquire the first signal sent by the corresponding channel of the first device and send the received second signal to the corresponding channel of the first device; each channel of the second signal generation unit 203 can acquire the second signal sent by the corresponding channel of the second device and send the received first signal to the corresponding channel of the second device.

[0056] Alternatively, the first signal generation unit 201 and the second signal generation unit 203 may each include only one channel, and the channels between the first device and the second device may transmit signals to the first signal generation unit 201 and the second signal generation unit 203 through time division multiplexing or other means.

[0057] In some embodiments, in addition to delaying the valid and ready signals, the delay unit 202 can also delay the data to be processed (hereinafter referred to as data) transmitted between the first device and the second device. Each channel between the first device and the second device can transmit data, and the data transmitted on the two channels are respectively denoted as channel 1 data and channel 2 data. Data to be transmitted on a channel can be sent when both the first signal and the second signal of that channel are valid. Taking the first signal and the second signal as the valid signal and the ready signal themselves, respectively, both the valid signal and the ready signal can be active high. Therefore, when both the first signal and the second signal of channel 1 are high, the first device can send channel 1 data to the channel 1 delay unit 202. After delaying the channel 1 data, the channel 1 delay unit 202 sends the delayed channel 1 data to the second device. The transmission method of channel 2 data is similar and will not be described in detail here.

[0058] Figure 3CThe diagram illustrates a scenario where both the number of channels and the number of delay subunits 2021 are greater than one. The example uses the first device as the master (101) and the second device as the slave (102). For simplicity, the first signal generation unit 201 and the second signal generation unit 203 are not shown. The first delay subunit 2021 of each channel is denoted as pipe 1, the second delay subunit 2021 of each channel is denoted as pipe 2, and so on, with the number of channels denoted as M (M is a positive integer). Although the number of delay subunits 2021 is the same for each channel in the diagram, in practical applications, the number of delay subunits 2021 for at least two channels can be configured to be different. All delay subunits 2021 within the same channel belong to the same delay unit 202.

[0059] Each delay subunit 2021 can implement a data delay of 1 cycle for multiple channels. By inserting multiple levels of delay subunits 2021, a data processing device with a data delay cycle greater than 1 can be achieved. Therefore, it can be easily expanded to obtain a data processing device that implements an n-cycle delay for M channels.

[0060] By configuring the delay amount, the rate mismatch between the master and slave ends can be flexibly addressed. Furthermore, when timing violations occur on the critical paths of both ends, the timing can be optimized by adjusting the delay amount. When the timing violation is severe, the delay amount can be increased; conversely, if the timing violation is minor, the delay amount can be decreased. The severity of the timing violation can be determined based on factors such as the total number of logical processing operations (e.g., AND, OR, NOT, XOR, etc.) and / or clock frequency of the signals at both ends.

[0061] In some embodiments, the delay unit 202 can write received data into the data register 204 and read the data from the data register 204 after a preset delay time. When the delay unit 202 includes N delay sub-units 2021, each delay sub-unit 2021 can delay the data by one clock cycle. See also Figure 4AMultiple delay subunits 2021 can share the data register 204. During the process of the first device writing data to the second device, after receiving the data sent by the first device, the first delay subunit 2021 can write the data into the data register 204, and enable the second delay subunit 2021 after a delay of one clock cycle. The second delay subunit 2021 can enable the third delay subunit 2021 after a delay of one clock cycle, and so on. The Nth delay subunit 2021 can read the data from the data register 204 after a delay of one clock cycle and send it to the second device. During the process of the first device reading data from the second device, after receiving the data sent by the second device, the Nth delay sub-unit 2021 can write the data into the data register 204 and enable the (N-1)th delay sub-unit 2021 after a delay of one clock cycle. The (N-1)th delay sub-unit 2021 can enable the (N-2)th delay sub-unit 2021 after a delay of one clock cycle, and so on. The first delay sub-unit 2021 can read the data from the data register 204 after a delay of one clock cycle and send it to the first device.

[0062] See Figure 4B Alternatively, each delay subunit 2021 can correspond to one or more data registers 204. Each delay subunit 2021 can output received data to the corresponding data register 204 for storage, and read the data stored in the corresponding data register 204 after a preset delay time. The total number of data registers 204 matches the number of delay subunits 2021. For example, the number of data registers 204 corresponding to each delay subunit 2021 can be the same. Assuming that the number of data registers 204 corresponding to each delay subunit 2021 is r, then the total number of data registers 204 corresponding to N delay subunits 2021 is N*r. After receiving data, each delay subunit 2021 can send the received data to the corresponding data register 204 for storage. After a delay of one clock cycle, it can send the data read from the corresponding data register 204 to the next delay subunit 2021 and enable the next delay subunit 2021. The data read from the corresponding data register 204 by the first delay subunit 2021 can be sent to the first device, and the data read from the corresponding data register 204 by the Nth delay subunit 2021 can be sent to the second device.

[0063] In related technologies, a buffer (usually a FIFO) is inserted between the master and slave ends to balance the data transfer rates. However, the buffer consumes chip memory resources, and the read / write operations and empty / full state control of the buffer are relatively complex, resulting in poor applicability and ease of use. This embodiment of the present disclosure uses a data register 204 to store data, thereby reducing the consumption of chip memory resources. Furthermore, the data read / write process of the register is relatively simple, requiring no complex control logic, thus improving the applicability and ease of use of the data processing device.

[0064] In some embodiments, the first signal generation unit 201 selects from a plurality of candidate first signal generation units based on the target handshake protocol used between the first device and the second device, each candidate first signal generation unit corresponding to a handshake protocol; the second signal generation unit 203 selects from a plurality of candidate second signal generation units based on the target handshake protocol used between the first device and the second device, each candidate second signal generation unit corresponding to a handshake protocol.

[0065] Optionally, the application scenario of the data processing device can be predetermined. Based on the target handshake protocol used in that application scenario, a first signal generation unit 201 is selected from multiple candidate first signal generation units, and a second signal generation unit 203 is selected from multiple candidate second signal generation units. Then, the first signal generation unit 201 and the second signal generation unit 203 are applied to the data processing device. This allows for the selection of dedicated data processing devices for different application scenarios, saving costs. Different first signal generation units 201 and second signal generation units 203 can be used in different application scenarios to adapt to the specific application.

[0066] Alternatively, multiple candidate first signal generation units, multiple candidate second signal generation units, a first selection unit 205, and a second selection unit 206 can be simultaneously configured in the data processing device. The first selection unit 205 is used to select the first signal generation unit 201 from the multiple candidate first signal generation units based on the target handshake protocol; the second selection unit 206 is used to select the second signal generation unit 203 from the multiple candidate second signal generation units based on the target handshake protocol. This allows the same data processing device to be applied to multiple different application scenarios simultaneously, improving the versatility of the data processing device. For example... Figure 5As shown, the data processing device includes a candidate first signal generation unit using the APB protocol, a candidate first signal generation unit using the AXI protocol, and a candidate first signal generation unit using the ASB protocol. Therefore, this data processing device can be applied to three different application scenarios using the APB protocol, the AXI protocol, and the ASB protocol. Assuming the handshake protocol sampled in the current application scenario is the APB protocol, the first selection unit 205 can select the candidate first signal generation unit using the APB protocol as the first signal generation unit 201, and the second selection unit 206 can select the candidate second signal generation unit using the APB protocol as the second signal generation unit 203.

[0067] Figure 6 and Figure 7 Schematic diagrams of data processing devices for application scenarios using the AXI protocol and the APB protocol are shown respectively. The diagrams use the first device as the master (101) and the second device as the slave (102) as an example for illustration. For simplicity, the first signal generation unit 201 and the second signal generation unit 203 are not shown.

[0068] like Figure 6 As shown, the AXI protocol has five independent data exchange channels: AW, W, B, AR, and R. Each channel has a valid signal, a ready signal, and data to be transmitted. `id` and `data` represent the data transmitted on each channel. The prefixes "AW", "W", "B", "AR", and "R" of `id` and `data` indicate the channel where the data resides, respectively. The suffix "_m" indicates data sent or received by the master end 101, and the suffix "_s" indicates data sent or received by the slave end 102. `Valid` and `ready` represent the valid and ready signals, respectively. The AXI protocol uses explicit valid and explicit ready signals. The meanings of the prefixes and suffixes for the valid and ready signals are the same as those for the prefixes and suffixes of `id` and `data`. Data or signals enclosed in square brackets "[v]" (0 ≤ v ≤ i) represent data or signals output after processing by the v-th delay subunit 2021 of the corresponding channel.

[0069] like Figure 7As shown, pwdata_m and pwdata_s represent the data output by the master terminal 101 and the data received by the slave terminal 102, respectively. pvalid_m and pvalid_s represent the valid signal input to the data processing device and the valid signal output by the data processing device, respectively. predy_m and predy_s represent the ready signal input to the data processing device and the ready signal output by the data processing device, respectively. Data or signals enclosed in square brackets "[v]" (0≤v≤i) represent data or signals output after being processed by the v-th delay subunit 2021 of the corresponding channel. The APB protocol does not include an explicit valid signal; the pvalid_m signal can be obtained by performing logical operations on the implicit valid signal through the first signal generation unit 201.

[0070] The data processing apparatus disclosed herein can effectively solve the problem of rate mismatch between the master and slave ends in various handshake protocols, and is particularly suitable for high-speed parallel computing scenarios such as artificial intelligence (AI) and graphics processing units (GPUs). The embodiments of this disclosure have the following advantages:

[0071] (1) The number of channels and the number of delay cycles can be flexibly set. When the data transmission rate difference between the master and slave ends is small or the timing violation is small, a smaller number of delay cycles can be set for the delay unit 202; while when the data transmission rate difference between the master and slave ends is large or the timing violation is large, a larger number of delay cycles can be set.

[0072] (2) It has good versatility, compatibility and scalability, and can be applied to various handshake protocols. When it is necessary to support new handshake protocols, it can also be easily extended.

[0073] (3) The embodiments disclosed herein can flexibly optimize timing violations on critical paths and can also flexibly reuse modules without additional customization, making them more user-friendly for chip implementation.

[0074] (4) In this embodiment, registers are used to implement data delay, which saves the chip's memory resources, and the control method of registers is simple and flexible.

[0075] This disclosure also provides a communication system, which includes: a first device, a second device, and a data processing apparatus as described in any embodiment of this disclosure.

[0076] This disclosure also provides a chip, which includes the data processing device or the communication system described in any embodiment of this disclosure. Optionally, the chip is an artificial intelligence (AI) chip.

[0077] This disclosure also provides a circuit board that includes a package structure encapsulating at least one of the above-described chips. See also... Figure 8 The present invention provides an exemplary board, which includes the chip 801 and may also include other components, including but not limited to: memory 802, interface device 803 and processor 804.

[0078] The memory 802 is connected to the chip 801 within the chip package structure via a bus and is used to store data. The memory 802 may include multiple sets of memory cells 802a, such as DDR SDRAM (Double Data Rate SDRAM). Each set of memory cells 802a is connected to the chip 801 via a bus.

[0079] The interface device 803 is electrically connected to the chip 801 within the chip package structure. The interface device 803 is used to enable data transmission between the chip 801 and an external device D (e.g., a terminal, server, camera, etc.). In one embodiment, the interface device 803 may be a PCIe interface, a network interface, or other interfaces; this disclosure does not impose any limitations.

[0080] This disclosure also provides an electronic device, including a data processing device as described in any embodiment of this disclosure, a chip as described in any embodiment of this disclosure, or a board as described in any embodiment of this disclosure.

[0081] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of this specification can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions of the embodiments of this specification, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this specification.

[0082] The systems, devices, modules, or units described in the above embodiments can be implemented by computer devices or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0083] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. When implementing the embodiments of this specification, the functions of each module can be implemented in one or more software and / or hardware. Alternatively, some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0084] The above description is merely a specific implementation of the embodiments of this specification. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principles of the embodiments of this specification, and these improvements and modifications should also be considered within the protection scope of the embodiments of this specification.

Claims

1. A data processing apparatus, characterized by, The data processing device is located between the first device and the second device. The handshake protocol used by the first device and the second device is one of several protocols, including protocols that use explicit valid and explicit ready signals as handshake signals, protocols that use implicit valid and explicit ready signals as handshake signals, protocols that use implicit valid and explicit ready signals as handshake signals, and protocols that use implicit valid and implicit ready signals as handshake signals. The data processing device includes: A first signal generation unit, a delay unit, and a second signal generation unit; The first signal generation unit is configured to generate a first handshake signal based on a first signal sent by the first device and the handshake protocol used between the first device and the second device, and then send the first handshake signal to the second signal generation unit after delaying it through the delay unit, so that the second signal generation unit generates the first signal based on the delayed first handshake signal and the handshake protocol and sends it to the second device; the first signal is one of an explicit valid signal and an implicit valid signal, and the first handshake signal is an explicit valid signal; The second signal generation unit is configured to generate a second handshake signal based on the second signal sent by the second device and the handshake protocol, and send the second handshake signal to the first signal generation unit after delaying it through the delay unit, so that the first signal generation unit generates the second signal based on the delayed second handshake signal and the handshake protocol and sends it to the first device; the second signal is one of an explicit ready signal and an implicit ready signal, and the second handshake signal is an explicit ready signal.

2. The data processing apparatus according to claim 1, characterized by The delay unit is further used for: The system acquires data to be processed sent by one of the first device and the second device, performs delay processing on the data to be processed, and then sends it to the other of the first device and the second device.

3. The data processing apparatus according to claim 1, characterized in that, The delay unit includes multiple cascaded delay sub-units, each of which is used to delay the first handshake signal and the second handshake signal by one clock cycle before outputting them.

4. The data processing apparatus according to claim 1, characterized in that, The first device and the second device include multiple data transmission channels, and the number of delay units is greater than 1, with each data transmission channel corresponding to one delay unit; The delay unit corresponding to each data transmission channel is used to delay the first handshake signal and the second handshake signal on the data transmission channel by one clock cycle before outputting them.

5. The data processing apparatus according to claim 1, characterized in that, The delay unit is used for: The received data is output to a data register for storage, and after a preset delay time, the data stored in the data register is read out.

6. The data processing apparatus according to claim 5, characterized in that, In the case where the delay unit comprises multiple delay sub-units, each delay sub-unit corresponds to one or more data registers; each delay sub-unit is used for: The received data is output to the corresponding data register for storage, and after a preset delay time, the data stored in the corresponding data register is read out.

7. The data processing apparatus according to claim 1, characterized in that, The first signal generation unit selects from a plurality of candidate first signal generation units based on the target handshake protocol used between the first device and the second device, and each candidate first signal generation unit corresponds to a handshake protocol; The second signal generation unit selects from a plurality of candidate second signal generation units based on the target handshake protocol used between the first device and the second device, with each candidate second signal generation unit corresponding to a handshake protocol.

8. The data processing apparatus according to claim 7, characterized in that, The data processing device includes: The plurality of candidate first signal generation units, the plurality of candidate second signal generation units, the first selection unit, and the second selection unit; The first selection unit is configured to select the first signal generation unit from the plurality of candidate first signal generation units based on the target handshake protocol; The second selection unit is used to select the second signal generation unit from the plurality of candidate second signal generation units based on the target handshake protocol.

9. The data processing apparatus according to any one of claims 1 to 8, characterized in that, The delay unit includes multiple delay sub-units; the data processing device further includes: A configuration unit is used to configure the operating state of each of the plurality of delay subunits, the operating state including an enabled state and an disabled state; When a delay subunit is enabled, the delay subunit outputs the received second handshake signal and first handshake signal after delay processing; When a delay subunit is in an inactive state, the delay subunit will directly output the received second handshake signal and the first handshake signal.

10. A communication system, characterized in that, The communication system includes: First equipment, The second device, and The data processing apparatus according to any one of claims 1 to 8.

11. A chip, characterized in that, The chip includes the data processing device according to any one of claims 1 to 9, or the communication system according to claim 10.

12. A circuit board, characterized in that, The board includes a package structure that encapsulates at least one chip as described in claim 11.

13. An electronic device, characterized in that, It includes the data processing apparatus according to any one of claims 1 to 9, the communication system according to claim 10, the chip according to claim 11, or the board according to claim 12.

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