A method, system, medium, and device for three-party isomorphic secure computation acceleration

Abstract

The present disclosure provides a three-party heterogeneous secure computing acceleration method, system, medium and device, relates to the technical field of multi-party secure computing, and comprises the following steps: acquiring the requirement of user input data, constructing a heterogeneous secure computing architecture based on CPU and FPGA; generating an obfuscated circuit corresponding to a secure computing task according to the acquired user requirement, and then accelerating the calculation of the obfuscated circuit according to the heterogeneous secure computing architecture based on CPU and FPGA; specifically, an agent computing party is added to calculate the generated obfuscated circuit, and a lightweight FPGA heterogeneous computing architecture is deployed in the agent computing party to accelerate the calculation of the obfuscated circuit. Thus, the generation stage and the calculation stage of the obfuscated circuit are accelerated by using the heterogeneous secure computing architecture based on CPU and FPGA, so that the calculation efficiency is greatly improved.

Description

Technical Field

[0001] This disclosure relates to the field of multi-party secure computing technology, specifically to a method, system, medium, and device for accelerating three-party heterogeneous secure computing. Background Technology

[0002] The statements in this section are merely background information relating to this disclosure and do not necessarily constitute prior art.

[0003] With the advent of the cloud computing and big data era, the internet is constantly releasing massive amounts of data, generating, storing, and analyzing ever-increasing volumes. How to collect and mine valuable information from this massive amount of data while ensuring data privacy has become a challenge. Therefore, research on Secure Function Evaluation (SFE) is particularly important. SFE allows one party to compute any ideal polynomial-time function based on private data, obtaining only the function's output and not any other information about the data. SFE provides strong privacy guarantees; the party performing secure data mining algorithms on user data only learns the final result of the computation, and the data is never revealed to the other party. Therefore, SFE enables data analysts, medical professionals, or statisticians to conduct research on sensitive data without accessing the private data of other participants. Garbled circuits (GC) can meet the requirements of SFE because they compute various important data mining algorithms in parallel, transforming the function to be computed into a "garbled" Boolean logic circuit, ensuring that the party computing the circuit can only obtain the circuit's output and cannot access the input data of other participants.

[0004] Existing research indicates that using GC to implement SFE execution incurs significant additional computational costs and is not computationally efficient compared to plaintext computation. Summary of the Invention

[0005] To address the aforementioned issues, this disclosure proposes a three-party heterogeneous secure computing acceleration method, system, medium, and device. It constructs a lightweight secure computing architecture based on CPU and FPGA heterogeneous computing. The architecture is used by both the obfuscated circuit builder and the proxy computing party. The obfuscated circuit builder uses the architecture to accelerate obfuscated circuit generation, and the proxy computing party uses the framework to accelerate obfuscated circuit computation.

[0006] According to some embodiments, the present disclosure adopts the following technical solutions:

[0007] A method for accelerating secure tri-party heterogeneous computing includes:

[0008] To meet the need for acquiring user input data, a heterogeneous secure computing architecture based on CPU and FPGA is constructed.

[0009] Based on the obtained user requirements, a scrambled circuit is generated for the corresponding secure computing task. Then, the computation of the scrambled circuit is accelerated based on the heterogeneous secure computing architecture based on CPU and FPGA.

[0010] Specifically: Add a proxy computing party to perform calculations on the generated obfuscated circuits, and deploy a lightweight FPGA heterogeneous computing architecture on the proxy computing party to accelerate the calculation of obfuscated circuits.

[0011] According to some embodiments, the present disclosure adopts the following technical solutions:

[0012] A three-party heterogeneous secure computing acceleration system includes three parties: a scrambled circuit builder, a proxy computing party, and a user.

[0013] The obfuscation circuit constructor is used to generate obfuscation circuits corresponding to secure computing tasks according to user needs, and the proxy computing party is responsible for the computing tasks of the obfuscation circuits.

[0014] According to some embodiments, the present disclosure adopts the following technical solutions:

[0015] A computer-readable storage medium storing a plurality of instructions adapted for loading and execution by a processor of a terminal device of the aforementioned third-party heterogeneous secure computing acceleration method.

[0016] According to some embodiments, the present disclosure adopts the following technical solutions:

[0017] A terminal device includes a processor and a computer-readable storage medium, the processor being configured to implement various instructions; the computer-readable storage medium being configured to store multiple instructions adapted to be loaded and executed by the processor as described in the third-party heterogeneous secure computing acceleration method.

[0018] Compared with the prior art, the beneficial effects of this disclosure are as follows:

[0019] The lightweight heterogeneous secure computing acceleration framework proposed in this disclosure involves three parties: a scrambled circuit builder, a user, and a proxy computing provider. The scrambled circuit builder generates scrambled circuits corresponding to the secure computing task based on the user's requirements, while the proxy computing provider is responsible for scrambling the scrambled circuits.

[0020] The proposed solution adds a proxy computing party to reduce the computational burden on users. By deploying an FPGA on the proxy computing party, the computation of obfuscated circuits is accelerated, thus solving the problem of low decryption efficiency of obfuscated circuit gates caused by limited user computing and bandwidth resources.

[0021] This disclosure improves and optimizes the unintentional transmission protocol for three-party scenarios, proposing a highly efficient and lightweight three-party unintentional transmission protocol. In this protocol, the user constructs random unintentional transmission instances locally. Then, based on these instances, the obfuscation circuit builder and the proxy computer only need to perform symmetric operations to obtain all the necessary keys for the obfuscation circuit. Finally, the proxy computer calculates the obfuscation circuit output, solving the problem of low efficiency in modular exponentiation operations in unintentional transmission.

[0022] This disclosure implements a heterogeneous secure computing architecture based on CPU and FPGA. The architecture includes FPGA's DDR, BRAM, workload distributor, and gate overlay units. This architecture is used by both the obfuscated circuit builder and the proxy computer. The obfuscated circuit builder utilizes this architecture to accelerate obfuscated circuit generation, while the proxy computer uses the framework to accelerate obfuscated circuit computation. This disclosure combines the characteristics of CPU and FPGA, rationally allocates computational tasks, and leverages the advantages of FPGA in handling linear tasks. Therefore, by utilizing the heterogeneous secure computing architecture of CPU and FPGA, it accelerates the obfuscated circuit generation and computation stages, resulting in a significant improvement in computational efficiency. Attached Figure Description

[0023] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure.

[0024] Figure 1 This is a diagram of the architecture of a three-party heterogeneous secure computing system in an embodiment of this disclosure;

[0025] Figure 2 This is a schematic diagram of the secure heterogeneous computing process in an embodiment of this disclosure;

[0026] Figure 3 This is a diagram showing the internal module coverage architecture of the FPGA hardware in an embodiment of this disclosure;

[0027] Figure 4 This is a flowchart illustrating the operation of the proxy OT protocol in this embodiment of the disclosure. Detailed Implementation

[0028] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0029] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0030] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0031] Terminology Explanation:

[0032] FPGA (Field-Programmable Gate Array) is a type of semi-custom circuit developed based on programmable logic devices such as PAL, GAL, and CPLD. As a type of application-specific integrated circuit, it compensates for the shortcomings of fully custom circuits and overcomes the limitation of the limited number of logic gates in traditional programmable logic controllers. Logic circuits described in hardware description languages ​​(Verilog or VHDL) can be quickly programmed onto the FPGA for testing using logic synthesis, placement, and routing tools. This process is the mainstream technology for modern integrated circuit design verification. These programmable logic components can be used to implement basic digital logic gates or more complex combinational logic functions, such as decoders. In most FPGAs, these programmable components also contain memory components, such as flip-flops or other more complete memory blocks, thus forming sequential logic circuits. Hardware developers connect the logic blocks inside the FPGA through programmable connections as needed. The logic blocks and connections of a finished FPGA can be changed according to the developer's needs, so the FPGA can perform the required logic functions. Most FPGAs contain high-level built-in modules (such as adders and multipliers) and built-in memory. Many new FPGAs support full or partial in-system reconfiguration, allowing the FPGA design to change with system upgrades or dynamic reconfigurations. Some FPGAs allow a portion of the device to be reprogrammed while other parts continue to function normally.

[0033] Garbled Circuit, also known as Yao's GC, is a solution to the Millionaire's Problem proposed by Professor Yao Qizhi in 1986. Its core technology involves compiling the secure computation function involving both parties into a Boolean logic circuit and encrypting and scrambling the truth table, thus achieving normal circuit output without revealing the private information of the participating parties. Simply put, the entire computation process can be divided into two stages: the first stage, converting the secure computation function into a circuit, is called the circuit generation stage; the second stage, executing the circuit using cryptographic primitives such as OT and encryption, is called the execution stage. Each stage is the responsibility of one of the participating parties until the circuit completes execution and outputs the result. From the perspective of the participants, the two parties involved in the secure computation can be further divided into the circuit generator and the circuit evaluator. The two parties involved in the computation first program the required secure computation using a proprietary programming language (DSL) or related programming language extensions. Then, the program that implements the computation is compiled to generate a Boolean logic circuit file. Next, random mapping labels are generated for the input values ​​of both parties and the intermediate output results. These labels are then used as encryption keys to encrypt the truth table of each corresponding circuit output using a block cipher, and the truth table values ​​are scrambled.

[0034] Oblivious Transfer: Oblivious transfer is a class of protocols in cryptography that allows a sender to transmit one of many potential pieces of information to a receiver without knowing whether the receiver received it. The first form of oblivious transfer was proposed by Rabin in 1981. In this form, the sender has a 1 / 2 probability of sending the message to the receiver, but the sender does not know whether the receiver received it. This oblivious transfer scheme is based on the RSA encryption algorithm. Two-to-one oblivious transfer is a more commonly used oblivious transfer scheme, which was developed by Oded, Shimon, and others into a secure multi-party computation protocol. "n-to-1 oblivious transfer" means that the user can only obtain one element from the database, and the server does not know which element the user queried. Oblivious transfer is an enhanced version of private information retrieval. Claude points out that Rabin's oblivious transfer is equivalent to two-to-one oblivious transfer. Further work shows that oblivious transfer is a fundamental and important problem in cryptography, considered one of the key problems in the field, and is a complete implementation for secure multi-party computation.

[0035] Example 1

[0036] One embodiment of this disclosure provides a method for accelerating three-party heterogeneous secure computing, including:

[0037] To meet the need for acquiring user input data, a heterogeneous secure computing architecture based on CPU and FPGA is constructed.

[0038] Based on the obtained user requirements, a scrambled circuit is generated for the corresponding secure computing task. Then, the computation of the scrambled circuit is accelerated based on the heterogeneous secure computing architecture based on CPU and FPGA.

[0039] Specifically: Add a proxy computing party to perform calculations on the generated obfuscated circuits, and deploy a lightweight FPGA heterogeneous computing architecture on the proxy computing party to accelerate the calculation of obfuscated circuits.

[0040] Furthermore, the proposed construction of a heterogeneous secure computing architecture based on CPU and FPGA includes the FPGA's DDR, BRAM, workload distributor, and gate overlay unit. This disclosure utilizes this architecture in both the obfuscated circuit builder and the proxy computing provider. The obfuscated circuit builder leverages this architecture to accelerate obfuscated circuit generation, while the proxy computing provider uses this framework to accelerate obfuscated circuit computation.

[0041] This disclosed solution involves three parties: the obfuscated circuit builder, the proxy computer, and the user. The specific steps are as follows:

[0042] 1. Implement a heterogeneous secure computing architecture based on CPU and FPGA in the obfuscated circuit construction and proxy computing sides.

[0043] 2. When the obfuscated circuit constructor generates the obfuscation table, it encrypts the gate circuits. During the computation process, the proxy computer decrypts the gate circuits based on the obfuscation table.

[0044] 3. During the confusion circuit generation stage, the CPU of the constructor converts the function problem into a Boolean logic circuit and extracts the information from the Boolean logic circuit.

[0045] 4. Before processing the circuit information in batches, assign a priority to each gate, which is equal to the weight of each gate.

[0046] 5. The repetitive task of generating 160-bit random values ​​for each line can be performed in parallel on the FPGA.

[0047] 6. The workload distributor in the FPGA first distributes the gate scrambling operations to the gate overlay cells.

[0048] 7. When the workload reads data from DDR, the obfuscation operation for that gate begins immediately after the value of the input line required for each gate is read.

[0049] 8. To address the issue of low efficiency in modular exponentiation operations for users in OT, this invention proposes a proxy OT method, which incorporates a proxy calculation method into traditional OT.

[0050] 9. The CPU of the proxy computing party sends the gate information to the DDR of the FPGA according to the breadth priority of the gates in the obfuscated circuit. The FPGA's workload distributor is responsible for reading the information and assigning the gate decryption operation to the gate overlay unit.

[0051] 10. Adopts a hybrid DDR+BRAM memory mechanism.

[0052] 11. Four SHA1 kernels were implemented in the gate overlay unit on the FPGA to perform parallel computation of AND gate encryption and decryption operations.

[0053] As one embodiment, in step 1, to address the slow speed of obfuscated circuit generation and computation, a heterogeneous secure computing architecture based on CPU and FPGA is implemented in both the obfuscated circuit builder and the proxy computing provider. The obfuscated circuit builder utilizes this architecture to accelerate obfuscated circuit generation, while the proxy computing provider uses this framework to accelerate obfuscated circuit computation. This architecture includes DDR, BRAM, workload distributor, and gate overlay units for both the CPU and FPGA.

[0054] Specifically, 1. Each architecture has one CPU and one FPGA by default;

[0055] 2. Both parties use this overlay architecture; both the generator and the computer of the obfuscated circuit adopt this architecture. This overlay architecture is a general-purpose architecture that can be used to solve the problem of slow speed in obfuscated circuit generation and computation.

[0056] In step 2, during the obfuscation circuit generation stage, the obfuscation circuit constructor first generates an obfuscation table. During the generation or calculation of the obfuscation table, encryption and decryption operations are performed on the AND gates. For XOR gates, Free-XOR technology can be used without encryption or decryption. Therefore, by instantiating as many AND gate overlay units as possible in the FPGA to process the AND gates in parallel, faster acceleration is achieved. This architecture allows for handling different problems by only reconnecting the internal component modules of the FPGA, without requiring a complete reprogramming of the FPGA.

[0057] In step 3, during the obfuscation circuit generation stage, the obfuscation circuit builder first generates an obfuscation table and encrypts the gate circuits. During obfuscation circuit generation, the CPU of the obfuscation circuit builder converts the function problem into a Boolean logic circuit and extracts information from the Boolean logic circuit. The CPU of the builder uses the ObliVM framework to convert the function problem into a Boolean logic circuit and extracts information from the Boolean logic circuit. Based on a breadth-first order, it sends the gate information in the circuit (e.g., how many gates are in each layer, the identifier of each gate, and the type of each gate) and which gate each overlay unit in the FPGA is responsible for obfuscating to the FPGA's DDR. Because resources on the FPGA are limited, it is impossible to process all gates in the Boolean logic circuit simultaneously; therefore, the gate information is transmitted in batches, with each batch representing the number of gates for which obfuscation operations are performed in parallel on the FPGA.

[0058] In step 4, a priority is set for each gate, and the extracted circuit information is processed in batches. The repetitive work of generating 160-bit random values ​​for each line is executed in parallel on the FPGA. The workload distributor in the FPGA first distributes the gate obfuscation operation to the gate overlay unit. When the workload reads the data in DDR, the obfuscation operation of the gate is started directly after the value of the input line required by each gate is read.

[0059] Specifically, assuming that the obfuscation operation of each non-XOR gate in the circuit requires 10 cycles, and the obfuscation operation of each XOR gate requires 1 cycle, and gate g is processed starting in the nth cycle, then the gates performing obfuscation operations in cycles n to n+9 should not depend on gate g, because gates dependent on gate g have not yet received their outputs and cannot be obfuscated. Improper scheduling during this process may result in a large number of idle cycles, thus reducing the speedup effect of the FPGA. Therefore, before batch processing, a priority is assigned to each gate, which is equal to the weight of each gate. For example, if the priority of a non-XOR gate dependent on a gate is 'a', then... If the XOR gate that depends on this gate has a priority of x, then And so on.

[0060] In step 5, the computational task of generating a 160-bit random value for each line in the circuit is a repetitive task that can be performed in parallel. Therefore, this task is also executed on the FPGA. Before encrypting the output lines of the AND gate, the pseudo-random number generator in the FPGA generates random numbers for each line.

[0061] In step 6, the workload distributor reads the information from the DDR and correctly assigns the gate obfuscation operation to the gate overlay unit according to the information sent by the CPU. Each AND gate overlay unit performs an encryption operation on the AND gate to obtain the key for the AND gate output line. The workload distributor stores this key in the BRAM. After this key is used for encryption of adjacent layer circuits, the workload distributor deletes it from the BRAM. If the BRAM is full, the DDR stores the remaining keys. In addition, after the obfuscation operation of each gate is completed, the DDR stores the generated obfuscation table. Finally, the FPGA sends the obfuscation circuit to the CPU via the PCIe bus, and the CPU then sends this circuit to the host of the proxy computing party.

[0062] In step 7, when the workload distributor reads data from the DDR, it does not need to wait until all data has been read before starting the gate operation. Instead, the obfuscation operation for each gate begins immediately after the values ​​of the required input lines are read. Finally, the FPGA sends the obfuscation circuit back to the CPU via the PCIe bus, and the constructing CPU shares the obfuscation circuit and the correspondence between its final output line random values ​​and real values ​​with the proxy computing CPU.

[0063] As an example, to address the low efficiency of modular exponentiation operations in operational testing (OT), a proxy OT method is proposed. This method adds a proxy computer to the traditional OT, and the random value corresponding to the user input can be obtained through symmetric operations between the constructor and the proxy computer, reducing the computational load on the user in OT. Proxy OT method: For the input line of the first layer of the circuit and its 160-bit random value... The user generates two 160-bit random numbers. , and a 1-digit random number b And based on their own input ,calculate Then through a secure channel a , , Send to the obfuscated circuit builder, b and Send to the proxy calculator; the obfuscated circuit builder calculates. , And Send to the proxy computing party; the proxy computing party obtains Afterwards, according to b Value calculation Get user input x Corresponding tags

[0064] During the obfuscated circuit computation phase, the proxy accelerates the computation process as follows: the proxy's CPU sends gate information to the FPGA's DDR according to the breadth-first order of gates in the obfuscated circuit. The FPGA's workload allocator reads this information and assigns the gate decryption operation to the gate overlay unit. The mechanism of the mixed BRAM and DDR memory in the proxy's FPGA is similar to that of the obfuscated circuit constructor, but the DDR stores the random value obtained after gate decryption. The FPGA obtains the final real value based on the mapping relationship between the random value and the real value and sends it to the CPU via the PCIe bus. The CPU then sends the final result to the user, who obtains the final output.

[0065] During decryption, this disclosure employs a hybrid DDR+BRAM memory mechanism, which not only handles large-scale problems (such as matrix multiplication in neural networks) but also reduces time consumption compared to reading data directly from DDR.

[0066] In step 11, this disclosure implements four SHA1 cores in the gate overlay unit on the FPGA to perform parallel computation of the AND gate's encryption and decryption operations. Although SHA1 execution speed is slower than AES execution speed, when an AND gate uses AES to encrypt the random value on the output line, it generally performs double encryption and decryption on the random value on the input line and the random value on the output line. Two AES encryption and decryption operations are definitely slower than SHA1 operations. Therefore, when generating the obfuscated circuit, for each AND gate, the two random values ​​on the input line and the gate identifier can be used... g The input lines are cascaded and hashed using SHA1. The hash result is then XORed with the random value on the output line to obtain the key for the output line. Correspondingly, in the obfuscation circuit calculation stage, the random value of the output line is obtained by XORing the hash value of the random value on each AND gate's two input lines with the key on the output line.

[0067] Example 2

[0068] One embodiment of this disclosure provides a three-party heterogeneous secure computing acceleration system, including three participants: a scrambled circuit builder, a proxy computing provider, and a user.

[0069] The obfuscation circuit constructor is used to generate obfuscation circuits corresponding to secure computing tasks according to user needs, and the proxy computing party is responsible for the computing tasks of the obfuscation circuits.

[0070] Example 3

[0071] One embodiment of this disclosure provides a computer-readable storage medium storing a plurality of instructions adapted for loading and execution by a processor of a terminal device of steps in a third-party heterogeneous secure computing acceleration method.

[0072] Example 4

[0073] One embodiment of this disclosure provides a terminal device, including a processor and a computer-readable storage medium. The processor is used to implement various instructions; the computer-readable storage medium is used to store multiple instructions, which are adapted to be loaded by the processor and executed as steps of a three-party heterogeneous secure computing acceleration method.

[0074] The steps of the method described in Example 1 are specifically executed in Examples 2, 3, and 4 above.

[0075] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0076] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0077] While the specific embodiments of this disclosure have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of this disclosure. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this disclosure are still within the scope of protection of this disclosure.

Claims

1. A method for accelerating secure tri-party heterogeneous computing, characterized in that, include: To meet the need for acquiring user input data, a heterogeneous secure computing architecture based on CPU and FPGA is constructed. Based on the obtained user requirements, a scrambled circuit is generated for the corresponding secure computing task. Then, the computation of the scrambled circuit is accelerated based on the heterogeneous secure computing architecture based on CPU and FPGA. Specifically: Add a proxy computing party to perform calculations on the generated obfuscated circuits, and deploy a lightweight FPGA heterogeneous computing architecture on the proxy computing party to accelerate the calculation of obfuscated circuits; During the obfuscated circuit generation stage, the obfuscated circuit builder first generates an obfuscation table and encrypts the gate circuits. When the obfuscated circuit is generated, the CPU of the obfuscated circuit builder converts the function problem into a Boolean logic circuit and extracts the information from the Boolean logic circuit. Each gate is assigned a priority, and the extracted circuit information is processed in batches. The repetitive work of generating 160-bit random values ​​for each line is executed in parallel on the FPGA. The workload distributor in the FPGA first distributes the gate obfuscation operation to the gate overlay unit. When the workload reads data from DDR, the obfuscation operation of the gate is started directly after the value of the input line required by each gate is read.

2. The method for accelerating three-party heterogeneous secure computing as described in claim 1, characterized in that, The heterogeneous secure computing architecture based on CPU and FPGA includes FPGA DDR, BRAM, workload distributor and gate overlay unit.

3. The method for accelerating three-party heterogeneous secure computing as described in claim 1, characterized in that, Accelerating the computation of obfuscated circuits based on a heterogeneous secure computing architecture using CPU and FPGA involves the following steps: the CPU of the proxy computing party sends gate information to the DDR of the FPGA according to the breadth-first order of the gates in the obfuscated circuit; the FPGA's workload distributor is responsible for reading the information and assigning the decryption operation of the gate to the gate overlay unit.

4. The method for accelerating three-party heterogeneous secure computing as described in claim 1, characterized in that, During decryption, a hybrid DDR+BRAM memory mechanism is used.

5. The method for accelerating three-party heterogeneous secure computing as described in claim 1, characterized in that, The FPGA obtains the final true value based on the mapping relationship between the random value and the true value, and sends it to the CPU via the PCIe bus. The CPU then sends the final result to the user, who then obtains the final output.

6. A three-party heterogeneous secure computing acceleration system, employing a three-party heterogeneous secure computing acceleration method as described in any one of claims 1-5, characterized in that, It includes three parties: the obfuscated circuit builder, the proxy computing party, and the user. The obfuscation circuit constructor is used to generate obfuscation circuits corresponding to secure computing tasks according to user needs, and the proxy computing party is responsible for the computing tasks of the obfuscation circuits.

7. A computer-readable storage medium, characterized in that, It stores multiple instructions, which are adapted to be loaded and executed by the processor of a terminal device, according to any one of claims 1-5, a third-party heterogeneous secure computing acceleration method.

8. A terminal device, characterized in that, The method includes a processor and a computer-readable storage medium, wherein the processor implements various instructions; and the computer-readable storage medium stores multiple instructions adapted to be loaded by the processor and executed as described in any one of claims 1-5, a method for accelerating tri-party heterogeneous secure computing.

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