Display panel, driving method thereof, and display device

Abstract

This invention provides a display panel and its driving method and display device, relating to the field of display technology, for improving the impact of noise signals on the display. The display panel includes: a pixel group, including multiple sub-pixels; driving signal lines, one driving signal line corresponding to at least one pixel group, multiple driving signal lines sequentially outputting charging enable levels to drive the corresponding pixel group; the sub-pixels include a first color sub-pixel, including a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are located in different pixel groups and correspond to different driving signal lines, the first sub-pixel and the second sub-pixel are arranged along the arrangement direction of the pixel group, and the second sub-pixel is spaced from the first sub-pixel by no more than a preset number of other first color sub-pixels; in a first mode, the display panel receives a noise signal, and the phase difference between the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the second sub-pixel is a non-integer multiple of the noise period.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. [Background Technology]

[0002] With the development of intelligent display panels, various types of sensors can be integrated into display panels. In some application scenarios, display panels need to receive electromagnetic signals to achieve specific functions.

[0003] To shield the display from the impact of such signals, a shielding layer is typically attached to one side of the display panel. However, attaching a shielding layer not only increases the thickness of the screen and the costs of materials, equipment, and time, but also limits the design freedom of the under-display sensors. For example, in a display panel with an opening area, the sensors are concentrated in the opening area. The shielding layer needs to be cut out at the opening area to allow the shielding layer and the sensors to avoid each other. However, this setup fails to protect the opening area, leading to display differences between the opening and non-opening areas. [Summary of the Invention]

[0004] In view of this, embodiments of the present invention provide a display panel and its driving method and display device, so as to effectively improve the impact of noise signals on the display.

[0005] On one hand, embodiments of the present invention provide a display panel, including:

[0006] Subpixel;

[0007] Multiple pixel groups, each pixel group comprising multiple sub-pixels, wherein the arrangement direction of the pixel groups intersects with the arrangement direction of the sub-pixels within the pixel groups;

[0008] Multiple driving signal lines, one driving signal line corresponding to at least one sub-pixel in the pixel group, and multiple driving signal lines sequentially output charging enable levels in a first order to drive the corresponding pixel group;

[0009] The sub-pixel includes a first color sub-pixel, the first color sub-pixel includes a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are located in different pixel groups and correspond to different driving signal lines respectively, and the first sub-pixel and the second sub-pixel are arranged along the arrangement direction of the pixel group, and the second sub-pixel is spaced from the first sub-pixel by no more than a preset number of other first color sub-pixels;

[0010] The display panel has a first mode in which the display panel receives a noise signal having a noise period, and the phase difference between the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the second sub-pixel is a non-integer multiple of the noise period.

[0011] On the other hand, embodiments of the present invention provide a driving method for a display panel, the display panel comprising:

[0012] Subpixel;

[0013] Multiple pixel groups, each pixel group comprising multiple sub-pixels, wherein the arrangement direction of the pixel groups intersects with the arrangement direction of the sub-pixels within the pixel groups;

[0014] Multiple driving signal lines, one driving signal line corresponding to at least one sub-pixel in the pixel group, wherein the multiple driving signal lines sequentially output charging enable levels in a first order to drive the corresponding pixel group;

[0015] Wherein, the sub-pixel includes a first color sub-pixel, the first color sub-pixel includes a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are located in different pixel groups and correspond to different driving signal lines respectively, and the first sub-pixel and the second sub-pixel are arranged along the arrangement direction of the pixel group, and the second sub-pixel is spaced from the first sub-pixel by a number of other first color sub-pixels less than a preset number;

[0016] The display panel has a first mode;

[0017] The driving method includes: in the first mode, the display panel receives a noise signal having a noise period, and the phase difference between the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the second sub-pixel is a non-integer multiple of the noise period.

[0018] In another aspect, embodiments of the present invention provide a display device including the aforementioned display panel.

[0019] One of the above technical solutions has the following beneficial effects:

[0020] In this embodiment of the invention, by adjusting the phase difference between the charging enable levels provided by the driving signal lines corresponding to closely spaced sub-pixels of the same color, the impact of the emission brightness shift of sub-pixels caused by noise signals on the image seen by the human eye can be effectively improved.

[0021] Specifically, in this embodiment of the invention, the first sub-pixel and the second sub-pixel are both first color sub-pixels, and the interval between them is no greater than a preset number of other first color sub-pixels. In other words, the first sub-pixel and the second sub-pixel are adjacent sub-pixels of the same color.

[0022] In the first mode, when the phase difference between the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the driving signal line corresponding to the second sub-pixel is a non-integer multiple of the noise period, the position points of the noise signals corresponding to the end times of the two charging enable levels are different. This can avoid the end times of the two charging enable levels from simultaneously corresponding to the peak (or trough) of the noise signal, thereby avoiding the maximum positive fluctuation (or maximum negative fluctuation) of the data voltages corresponding to the two adjacent sub-pixels of the same color, and thus avoiding the maximum brightness (or maximum darkness) of the light emission brightness of the two adjacent sub-pixels of the same color.

[0023] For example, in one scenario, at the end of the charging enable level provided by the driving signal line corresponding to the first sub-pixel and at the end of the charging enable level provided by the driving signal line corresponding to the second sub-pixel, the noise signal shows an upward trend. However, the positions corresponding to the two charging end times in the upward trend of the noise signal are different: the position of the noise signal corresponding to the end of the charging enable level of the driving signal line corresponding to the first sub-pixel is closer to the bottom of the noise signal, while the position of the noise signal corresponding to the end of the charging enable level of the driving signal line corresponding to the second sub-pixel is closer to the top of the noise signal. This results in the noise signal having a greater positive impact on the data voltage corresponding to the second sub-pixel before the end of the charging enable level of the driving signal line, causing a greater positive shift in the brightness of the second sub-pixel.

[0024] Alternatively, in another scenario, the noise signal tends to rise at the end of the charging enable level provided by the driving signal line corresponding to the first sub-pixel, and tends to fall at the end of the charging enable level provided by the driving signal line corresponding to the second sub-pixel. Therefore, before the charging of the data line connected to the first sub-pixel ends, the noise signal has a positive impact on the data voltage on that data line, while before the charging of the data line connected to the second sub-pixel ends, the noise signal has a negative impact on the data voltage on that data line, resulting in the first sub-pixel appearing brighter and the second sub-pixel appearing darker.

[0025] This invention, by controlling the phase difference of the charging enable level provided by the driving signal line corresponding to adjacent first color sub-pixels to be a non-integer multiple of the noise period, can achieve controllable distribution of the luminous intensity of adjacent first color sub-pixels, avoiding consecutive maximum brightness or maximum darkness in adjacent first color sub-pixels. Thus, when the display panel displays a pure or polychromatic image of the first color, the brightness shift of adjacent first color sub-pixels will not be perceived as obvious stripes by the human eye, effectively improving the impact of luminous intensity shift of the first color sub-pixels caused by noise signals on the image perceived by the human eye. Furthermore, the above structure, while effectively improving the impact of noise signals on the display, eliminates the need for a shielding layer, thereby overcoming the adverse problems caused by shielding layers as described in the background art. [Attached Image Description]

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0028] Figure 2 for Figure 1 A timing diagram of the signals provided by the corresponding multiple drive signal lines in the first mode;

[0029] Figure 3 for Figure 1 A timing diagram of the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the driving signal line corresponding to the second sub-pixel;

[0030] Figure 4 for Figure 3 A schematic diagram of the luminance of a corresponding sub-pixel;

[0031] Figure 5 for Figure 1 Another timing diagram of the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the driving signal line corresponding to the second sub-pixel.

[0032] Figure 6 for Figure 5 A schematic diagram of the luminance of a corresponding sub-pixel;

[0033] Figure 7 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0034] Figure 8 for Figure 7 A timing diagram of the driving signals provided by the corresponding multiple driving signals in the first mode;

[0035] Figure 9 for Figure 8 A schematic diagram of the luminance of a corresponding sub-pixel;

[0036] Figure 10 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0037] Figure 11 for Figure 10 A timing diagram of the drive signals provided by the corresponding multiple drive signal lines in the first mode;

[0038] Figure 12 for Figure 11 A schematic diagram of the luminance of a corresponding sub-pixel;

[0039] Figure 13 for Figure 1 Another timing diagram of the drive signals provided by the corresponding multiple drive signal lines in the first mode;

[0040] Figure 14 for Figure 1 Another timing diagram of the drive signals provided by the corresponding multiple drive signal lines in the first mode;

[0041] Figure 15 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0042] Figure 16 for Figure 15 A timing diagram of the clock signals provided by the corresponding multiple clock signal lines in the first mode;

[0043] Figure 17 for Figure 16 A schematic diagram of the luminance of a corresponding sub-pixel;

[0044] Figure 18 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0045] Figure 19 for Figure 18 A timing diagram of the clock signals provided by the corresponding multiple clock signal lines in the first mode;

[0046] Figure 20 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0047] Figure 21 for Figure 20 A timing diagram of the clock signals provided by the corresponding multiple clock signal lines in the first mode;

[0048] Figure 22 for Figure 15 Another timing diagram of the clock signals provided by the corresponding multiple clock signal lines in the first mode;

[0049] Figure 23 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0050] Figure 24 for Figure 23 A timing diagram of the clock signals provided by the corresponding multiple clock signal lines in the first mode;

[0051] Figure 25 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0052] Figure 26 for Figure 25 A timing diagram of the clock signals provided by the corresponding multiple clock signal lines in the first mode;

[0053] Figure 27 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0054] Figure 28 for Figure 27 A timing diagram of the clock signals provided by the corresponding multiple clock signal lines in the first mode;

[0055] Figure 29 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0056] Figure 30 for Figure 29 A timing diagram of the scanning signals provided by the corresponding multiple scanning signal lines in the first mode;

[0057] Figure 31 for Figure 30 A schematic diagram of the luminance of a corresponding sub-pixel;

[0058] Figure 32 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0059] Figure 33 for Figure 32 A timing diagram of the scanning signals provided by the corresponding multiple scanning signal lines in the first mode;

[0060] Figure 34 for Figure 33A schematic diagram of the luminance of a corresponding sub-pixel;

[0061] Figure 35 This is another schematic diagram of the luminous brightness of a sub-pixel provided in an embodiment of the present invention;

[0062] Figure 36 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0063] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0064] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0065] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0066] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0067] This invention provides a display panel, such as... Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 The diagram shows a timing sequence of signals provided by the multiple driving signal lines (signal) in the first mode. The display panel includes sub-pixels 1, multiple pixel groups 2, and multiple driving signal lines (signal). For ease of understanding, the multiple driving signal lines are represented by the reference numerals signal_1 and signal_n in the accompanying drawings of this embodiment. However, the value of n varies depending on the structure of the display panel shown in the drawings.

[0068] Pixel group 2 includes multiple sub-pixels 1, and the arrangement direction of pixel group 2 intersects with the arrangement direction of sub-pixels 1 in pixel group 2.

[0069] One drive signal line corresponds to at least one sub-pixel 1 in pixel group 2. Multiple drive signal lines sequentially output charging enable levels in a first order to drive the corresponding pixel group 2. The accompanying drawings of this embodiment illustrate the invention with the charging enable level being low. In other optional embodiments, the charging enable level can also be high.

[0070] It should be noted that the display panel also includes a data line Data electrically connected to sub-pixel 1. When the drive signal line signal provides a charging enable level, the driver chip provides a data voltage to the data line Data to charge it. Alternatively, when the drive signal line signal provides a charging enable level, the data voltage transmitted on the data line Data is written into sub-pixel 1 to charge it. However, it is understandable that when the drive signal line signal provides a charging enable level, whether charging the data line Data or charging sub-pixel 1, fluctuations in the data voltage will ultimately affect the actual luminous brightness of sub-pixel 1.

[0071] Sub-pixel 1 includes a first color sub-pixel 4, which emits first color light. The first color sub-pixel 4 includes a first sub-pixel 5 and a second sub-pixel 6. The first sub-pixel 5 and the second sub-pixel 6 are located in different pixel groups 2 and correspond to different driving signal lines (signal). Furthermore, the first sub-pixel 5 and the second sub-pixel 6 are arranged along the arrangement direction of pixel group 2, and the interval between the second sub-pixel 6 and the first sub-pixel 5 is no greater than a preset number of other first color sub-pixels 4. Figure 1 In the illustration, the first sub-pixel 5 corresponds to the driving signal line signal_1, and the second sub-pixel 6 corresponds to the driving signal line signal_4. However, in different accompanying drawings, the reference numerals for the driving signal lines signal_1 corresponding to the first sub-pixel 5 and the second sub-pixel 6 may differ.

[0072] The display panel has a first mode in which it receives a noise signal with a noise period P. The phase difference ΔT between the charging enable levels provided by the drive signal line signal_1 corresponding to the first sub-pixel 5 and the drive signal line signal_4 corresponding to the second sub-pixel 6 is a non-integer multiple of the noise period P.

[0073] It should be noted that the aforementioned noise signal can be a high-frequency signal such as electromagnetic or radio frequency. In the first mode, the display panel needs to receive periodic noise signals to achieve specific functions. For example, when a mobile phone uses Near Field Communication (NFC) technology to swipe a card at a card reader, the phone receives the radio frequency signal sent by the card reader to achieve the card swiping function; or, when a mobile phone uses wireless charging technology to charge, the phone receives the electromagnetic signal sent by the charging device to achieve the charging function.

[0074] During the research process, the inventors discovered that if noise signals are received during the display panel's display process, the noise signals will affect the stability of the data voltage, thereby affecting the normal charging of the data line or sub-pixel 1.

[0075] Taking the charging enable level provided by the drive signal line signal as an example, the driver chip charges the data line Data:

[0076] When the drive signal line (signal) provides the charging enable level, the driver chip continuously transmits data voltage to the data line (Data) to charge it. During this charging process, if the display panel receives a noise signal, the noise signal will interfere with the charging of the data line (Data). Since the driving force of the driver chip is insufficient to completely counteract this interference, the data voltage will fluctuate under the interference of the noise signal.

[0077] Because the noise signal is periodic, during the entire charging process of the Data line, the data voltage will fluctuate back and forth around the standard voltage value, changing between positive and negative directions, under the influence of the noise signal. However, it is understandable that the data voltage will return to the standard voltage value multiple times during these fluctuations. When the data voltage returns to the standard voltage value, it can be considered that the cumulative effect of the noise signal on the data voltage in the earlier stages has canceled each other out. Therefore, the influence of the noise signal on the data voltage in the short period near the end of charging (which can also be understood as the short period between the last time the data voltage returns to the standard voltage value during the fluctuation process and the end of charging) determines whether the data voltage remaining on the Data line after charging is complete has experienced positive or negative fluctuations.

[0078] For example, if the noise signal (tr) shows an upward trend at the end of charging, then in the short period before the end of charging, the noise signal likely has a positive impact on the data voltage. Therefore, the data voltage remaining on the data line (Data) after charging will fluctuate positively compared to the standard voltage value. Conversely, if the noise signal (td) shows a downward trend at the end of charging, then in the short period before the end of charging, the noise signal likely has a negative impact on the data voltage. Therefore, the data voltage remaining on the data line (Data) after charging will fluctuate negatively compared to the standard voltage value.

[0079] Because the offset data voltage will remain on the data line Data after charging is finished until it is written into sub-pixel 1, the offset data voltage will eventually affect the charging status of sub-pixel 1, causing the luminous brightness of sub-pixel 1 to deviate from its standard luminous brightness.

[0080] It should be noted that, assuming the standard voltage value is V1, the data voltage retained on the data line Data after charging is complete is V1′. During the period between the end of charging and the beginning of charging sub-pixel 1, the data voltage V1′ retained on the data line Data will continue to be affected by noise. However, the fluctuation of the data voltage during this period is based on the data voltage V1′. If the data voltages V1′ corresponding to the two sub-pixels 1 have a significant difference, then when the two data voltages V1′ are written to sub-pixel 1 after subsequent fluctuations, the difference in the written voltage value will also be relatively large. Therefore, at the end of charging the data line Data, the degree of deviation of the data voltage V1′ from the standard voltage value V1 largely determines the degree of deviation in the brightness of sub-pixel 1.

[0081] In summary, if a noise signal is received during the display process, the charging voltage on the data line Data will fluctuate, which will cause the actual luminous brightness of sub-pixel 1 to shift.

[0082] Based on the existence of the above problems, the inventors further studied and found that for adjacent sub-pixels of the same color, if the light emission brightness of these sub-pixels 1 all undergoes the maximum positive shift or the maximum negative shift, the brightness shift of these adjacent sub-pixels of the same color will be more likely to reach the scale that the human eye can perceive, thus causing the human eye to be able to recognize it as obvious ripples.

[0083] In this embodiment of the invention, by adjusting the phase difference between the charging enable levels provided by the driving signal lines signal corresponding to closely spaced sub-pixels of the same color, the impact of the brightness shift of sub-pixels 1 caused by noise on the image seen by the human eye can be effectively reduced.

[0084] Specifically, in this embodiment of the invention, the first sub-pixel 5 and the second sub-pixel 6 are both first color sub-pixels 4, and the interval between them is no greater than a preset number of other first color sub-pixels 4. That is to say, the first sub-pixel 5 and the second sub-pixel 6 are adjacent sub-pixels of the same color.

[0085] In the first mode, when the phase difference ΔT between the charging enable levels provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 and the driving signal line signal_4 corresponding to the second sub-pixel 6 is a non-integer multiple of the noise period P, the position points of the noise signal corresponding to the end time of these two charging enable levels are different. This can prevent the end time of the two charging enable levels from simultaneously corresponding to the peak (or trough) of the noise signal, thereby preventing the data voltages corresponding to these two adjacent sub-pixels of the same color from experiencing maximum positive fluctuations (or maximum negative fluctuations), and thus preventing the light emission brightness of these two adjacent sub-pixels of the same color from exhibiting maximum brightness (or maximum darkness).

[0086] For example, in one case, such as Figure 3 and Figure 4 As shown, Figure 3 for Figure 1 A timing diagram showing the charging enable level provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 and the driving signal line signal_4 corresponding to the second sub-pixel 6. Figure 4 for Figure 3A schematic diagram of the luminance of the corresponding sub-pixel 1 shows that at the end of the charging enable level provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 and at the end of the charging enable level provided by the driving signal line signal_4 corresponding to the second sub-pixel 6, the noise signal shows an upward trend tr. However, the positions corresponding to the two charging end times in the upward trend tr of the noise signal are different: the position of the noise signal corresponding to the end of the charging enable level of the driving signal line signal_1 is closer to the bottom point of the noise signal, while the position of the noise signal corresponding to the end of the charging enable level of the driving signal line signal_4 is closer to the top point of the noise signal. This makes the noise signal have a greater positive impact on the data voltage corresponding to the second sub-pixel 6 before the end of the charging enable level of the driving signal line signal_4, resulting in a greater positive shift in the brightness of the second sub-pixel 6.

[0087] Or, in another case, such as Figure 5 and Figure 6 As shown, Figure 5 for Figure 1 Another timing diagram showing the charging enable level provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 and the driving signal line signal_4 corresponding to the second sub-pixel 6. Figure 6 for Figure 5 The diagram illustrates the luminance of sub-pixel 1. At the end of the charging enable level provided by the driving signal line signal_1 corresponding to the first sub-pixel 5, the noise signal shows an upward trend (tr). At the end of the charging enable level provided by the driving signal line signal_4 corresponding to the second sub-pixel 6, the noise signal shows a downward trend (td). Therefore, before the charging of the data line Data connected to the first sub-pixel 5 ends, the noise signal has a positive impact on the data voltage on that data line Data. Conversely, before the charging of the data line Data connected to the second sub-pixel 6 ends, the noise signal has a negative impact on the data voltage on that data line Data. This results in the first sub-pixel 5 appearing brighter, while the second sub-pixel 6 appears darker.

[0088] It should be noted that, for clarity, in the accompanying drawings of the embodiments of the present invention, sub-pixel 1 is represented by a square. When illustrating the luminance of sub-pixel 1, a dashed border of the square indicates that the luminance of sub-pixel 1 is relatively high, and a thick solid border of the square indicates that the luminance of sub-pixel 1 is relatively low.

[0089] This invention, by controlling the phase difference of the charging enable level provided by the driving signal line signal corresponding to the adjacent first color sub-pixel 4 to be a non-integer multiple of the noise period P, can achieve controllable distribution of the luminous intensity of the adjacent first color sub-pixel 4, avoiding the adjacent first color sub-pixel 4 from continuously displaying maximum brightness or maximum darkness. Thus, when the display panel displays a pure or polychromatic image of the first color, the brightness shift of the adjacent first color sub-pixel 4 will not be perceived as obvious stripes by the human eye, effectively improving the impact of the luminous intensity shift of the first color sub-pixel 4 caused by noise on the image perceived by the human eye. Furthermore, the above structure, while effectively improving the impact of noise on the display, eliminates the need for a shielding layer, thus overcoming the adverse problems caused by shielding layers as described in the background art.

[0090] Furthermore, it should be noted that in the embodiments of the present invention, the timing of the drive signal line signal in the display panel can be adjusted to make the phase difference of the charging enable level and the noise period P satisfy the above relationship. Alternatively, the timing of the noise signal noise provided by the interference source can be adjusted to match the timing of the drive signal line signal in the display panel so that the phase difference of the charging enable level and the noise period P satisfy the above relationship.

[0091] In one feasible implementation, combined with Figure 1 and Figure 2 ΔT = (N + x) × P, where ΔT is the phase difference between the charging enable levels provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 and the driving signal line signal_4 corresponding to the second sub-pixel 6 in the first mode, P is the noise period, N is an integer greater than or equal to 0, and 0.4 ≤ x ≤ 0.6.

[0092] In the first mode, when ΔT and P satisfy the above relationship, the phase difference between the two charging enable levels, after deducting an integer number of noise cycles P, will still differ by about half a noise cycle P. This results in a significant difference in the position of the noise signal at the end of the two charging enable levels. For example, if the end of one charging enable level corresponds to the rising trend tr of the noise signal, then the end of the other charging enable level will correspond to the falling trend td of the noise signal. In this case, the noise signal has opposite effects on the brightness of the first sub-pixel 5 and the second sub-pixel 6, making one of the two first color sub-pixels 4 brighter and the other darker. In this way, the brightness distribution of the first sub-pixel 5 and the second sub-pixel 6 can be controlled, and the brightness difference between these two sub-pixels will visually compensate for each other, making their equivalent brightness approach the target brightness. Therefore, it can be avoided to a greater extent from being perceived as ripples by the human eye.

[0093] Further, see Figure 2 It can also make x = 0.5.

[0094] At this point, after removing the integer number of noise cycles P, the phase difference between the two charge enable levels will still differ by half a noise cycle P. Therefore, while the end times of the two charge enable levels correspond to the rising trend tr and falling trend td of the noise signal, respectively, there will also be cases where the end time of one charge enable level corresponds to the peak of the noise signal, and the end time of the other charge enable level corresponds to the trough of the noise signal. For example, see... Figure 2 The end of the charging enable level provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 corresponds to the bottom point of the noise signal. At this time, the negative impact of the noise signal on the actual light emission brightness of the first sub-pixel 5 reaches its maximum, making the first sub-pixel 5 as dark as possible. Conversely, the end of the charging enable level provided by the driving signal line signal_4 corresponding to the second sub-pixel 6 corresponds to the top point of the noise signal. At this time, the positive impact of the noise signal on the actual light emission brightness of the second sub-pixel 6 reaches its maximum, making the second sub-pixel 6 as bright as possible. In this case, the visual brightness difference between the first sub-pixel 5 and the second sub-pixel 6 is greater, and this brightness difference is more easily compensated for and less likely to be perceived by the human eye.

[0095] In one feasible implementation, the preset quantity is 1, and the second sub-pixel 6 is separated from the first sub-pixel 5 by at most one other first color sub-pixel 4.

[0096] In one setup method, see Figure 1 There are no other first color sub-pixels 4 between the first sub-pixel 5 and the second sub-pixel 6. At this time, the first sub-pixel 5 and the second sub-pixel 6 are adjacent first color sub-pixels 4. Adjusting the timing of the corresponding driving signal lines signal can more effectively avoid the human eye recognizing continuous ripples.

[0097] Alternatively, in another setup, such as Figures 7-9 As shown, Figure 7 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 8 for Figure 7 A timing diagram of the drive signals provided by the corresponding multiple drive signals in the first mode. Figure 9 for Figure 8A schematic diagram of the luminance of the corresponding sub-pixel 1 is shown. The second sub-pixel 6 and the first sub-pixel 5 can also be separated by another first-color sub-pixel 4. In this structure, the first sub-pixel 5 and the second sub-pixel 6 are still relatively close and can still be considered adjacent sub-pixels of the same color. Taking the first-color sub-pixel 4 and the first sub-pixel 5 as examples, even if the phase difference ΔT′ between the charging enable levels provided by the driving signal line signal_4 corresponding to the first-color sub-pixel 4 and the driving signal line signal_1 corresponding to the first sub-pixel 5 is an integer multiple of the noise period P, making their luminance the same and both slightly dark, the brightness difference between the overall dark pattern presented by these two first-color sub-pixels 4 and the bright pattern presented by the second sub-pixel 6 is far from reaching the length that the human eye can distinguish. Therefore, it is still possible to avoid the human eye perceiving the brightness difference of this part of the first-color sub-pixel 4 as a stripe phenomenon.

[0098] In one feasible implementation, such as Figures 10-12 As shown, Figure 10 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 11 for Figure 10 A timing diagram of the drive signals provided by the corresponding multiple drive signal lines in the first mode. Figure 12 for Figure 11 A schematic diagram of the luminance of the corresponding sub-pixel 1 is shown. Sub-pixel 1 also includes a second color sub-pixel 7 and a third color sub-pixel 8. The second color sub-pixel 7 is used to emit second color light, and the third color sub-pixel 8 is used to emit third color light.

[0099] The display panel also includes multiple pixels 13, each including a first color sub-pixel 4, a second color sub-pixel 7, and a third color sub-pixel 8. Among these, the multiple pixels 13 include a first pixel 14, in which the first color sub-pixel 4, the second color sub-pixel 7, and the third color sub-pixel 8 are located in different pixel groups 2 and each corresponds to a different driving signal line (signal).

[0100] In the first mode, the phase difference ΔT1′ between the charging enable levels provided by the drive signal lines corresponding to the first color sub-pixel 4 and the second color sub-pixel 7 in the first pixel 14 is [M-0.1, M+0.1] times the noise period P, where M is a positive integer. And / or, the phase difference ΔT2′ between the charging enable levels provided by the drive signal lines corresponding to the first color sub-pixel 4 and the third color sub-pixel 8 in the first pixel 14 is [R-0.1, R+0.1] times the noise period P, where R is a positive integer. Figure 11 This illustrates that △T1′ and △T2′ are integer multiples of the noise period P, respectively.

[0101] Based on the above settings, for a first pixel 14, the phase difference ΔT1′ between the charging enable level provided by the driving signal line signal (e.g., signal_1) corresponding to the first color sub-pixel 4 and the driving signal line signal (e.g., signal_2) corresponding to the second color sub-pixel 7 in the first pixel 14 and the noise period P tend to be an integer multiple. In this case, the influence of the noise signal on the brightness of the first color sub-pixel 4 and the second color sub-pixel 7 is similar; for example, it can make both different color sub-pixels 1 appear darker. And / or, the phase difference ΔT2′ between the charging enable level provided by the driving signal line signal (e.g., signal_1) corresponding to the first color sub-pixel 4 and the driving signal line signal (e.g., signal_3) corresponding to the third color sub-pixel 8 in the first pixel 14 and the noise period P tends to be an integer multiple. In this case, the influence of the noise signal on the brightness of the first color sub-pixel 4 and the third color sub-pixel 8 is also similar; for example, it can make both different color sub-pixels 1 appear darker.

[0102] With this setting, the noise signal has a unidirectional effect on the luminance of at least two different colored sub-pixels 1 in the first pixel 14, which can effectively improve the color cast of the first pixel 14 itself. The improvement effect is even more significant when all three colors of sub-pixels 1 in the first pixel 14 are simultaneously darkened or simultaneously brightened.

[0103] In one feasible implementation, see again Figure 1 and Figure 2 Subpixel 1 also includes a second color subpixel 7 and a third color subpixel 8.

[0104] The second color sub-pixel 7 includes a third sub-pixel 9 and a fourth sub-pixel 10. The third sub-pixel 9 and the fourth sub-pixel 10 are located in different pixel groups 2 and correspond to different driving signal lines (signal). Furthermore, the third sub-pixel 9 and the fourth sub-pixel 10 are arranged along the arrangement direction of pixel group 2, and the interval between the third sub-pixel 9 and the fourth sub-pixel 10 is less than a preset number of other second color sub-pixels 7. Figure 1 In the diagram, the third sub-pixel 9 corresponds to the driving signal line signal_2, and the fourth sub-pixel 10 corresponds to the driving signal line signal_5.

[0105] It should be noted that, in this embodiment of the invention, the preset quantity can be 1. Wherein, Figure 1The illustration is based on the example that there are no other second color sub-pixels 7 between the third sub-pixel 9 and the fourth sub-pixel 10 (the preset number is 0). In other optional embodiments of the present invention, there may also be one other second color sub-pixel 7 between the third sub-pixel 9 and the fourth sub-pixel 10.

[0106] In the first mode, the phase difference between the charging enable levels provided by the driving signal line signal_2 corresponding to the third sub-pixel 9 and the driving signal line signal_5 corresponding to the fourth sub-pixel 10 is a non-integer multiple of the noise period P.

[0107] Similar to the first color sub-pixel 4, in the first mode, this embodiment of the invention controls the phase difference of the charging enable level provided by the driving signal lines (signal) of two adjacent second color sub-pixels 7 to be a non-integer multiple of the noise period P. This allows for a controllable distribution of the luminous intensity of adjacent second color sub-pixels 7, preventing them from continuously exhibiting maximum brightness or maximum darkness. Thus, when the display panel displays a pure or complex second color image, the brightness shift of adjacent second color sub-pixels 7 will not be perceived as obvious stripes by the human eye, effectively mitigating the impact of the luminous intensity shift of the second color sub-pixels 7 caused by noise on the image perceived by the human eye.

[0108] The third color sub-pixel 8 includes a fifth sub-pixel 11 and a sixth sub-pixel 12. The fifth sub-pixel 11 and the sixth sub-pixel 12 are located in different pixel groups 2 and correspond to different driving signal lines, respectively. Furthermore, the fifth sub-pixel 11 and the sixth sub-pixel 12 are arranged along the arrangement direction of pixel group 2, and the interval between the fifth sub-pixel 11 and the sixth sub-pixel 12 is less than a preset number of other third color sub-pixels 8. Figure 1 In the diagram, the third sub-pixel 9 corresponds to the driving signal line signal_3, and the fourth sub-pixel 10 corresponds to the driving signal line signal_6.

[0109] It should be noted that, in this embodiment of the invention, the preset quantity can be 1. Wherein, Figure 1 The illustration is based on the example that there are no other third color sub-pixels 8 (the preset number is 0) between the fifth sub-pixel 11 and the sixth sub-pixel 12. In other optional embodiments of the present invention, there may also be one other third color sub-pixel 8 between the fifth sub-pixel 11 and the sixth sub-pixel 12.

[0110] In the first mode, the phase difference between the charging enable levels provided by the driving signal line signal_3 corresponding to the fifth sub-pixel 11 and the driving signal line signal_6 corresponding to the sixth sub-pixel 12 is a non-integer multiple of the noise period P.

[0111] Similar to the first color sub-pixel 4, in the first mode, this embodiment of the invention controls the phase difference of the charging enable level provided by the driving signal line signal corresponding to the adjacent third color sub-pixel 8 to be a non-integer multiple of the noise period P. This allows for controllable distribution of the luminous intensity of the adjacent third color sub-pixel 8, preventing them from continuously exhibiting maximum brightness or maximum darkness. Thus, when the display panel displays a pure or complex third color image, the brightness shift of the adjacent third color sub-pixel 8 will not be perceived as obvious stripes by the human eye, effectively mitigating the impact of the luminous intensity shift of the third color sub-pixel 8 caused by noise on the image perceived by the human eye.

[0112] In one feasible implementation, combined with Figure 1 and Figure 13 , Figure 13 for Figure 1 Another timing diagram of the drive signals provided by the corresponding multiple drive signal lines in the first mode, in the first mode:

[0113] The phase difference between the charging enable levels provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 and the driving signal line signal_4 corresponding to the second sub-pixel 6 is ΔT11, where ΔT11 = (N11 + x11) × P, P is the noise period, N11 is an integer greater than or equal to 0, and 0 < x11 < 1.

[0114] The phase difference between the charging enable levels provided by the driving signal line signal_2 corresponding to the third sub-pixel 9 and the driving signal line signal_5 corresponding to the fourth sub-pixel 10 is ΔT12, where ΔT12 = (N12 + x12) × P, N12 is an integer greater than or equal to 0, and 0 < x12 < 1.

[0115] The phase difference between the charging enable levels provided by the driving signal line signal_3 corresponding to the fifth sub-pixel 11 and the driving signal line signal_6 corresponding to the sixth sub-pixel 12 is ΔT13, where ΔT13 = (N13 + x13) × P, N13 is an integer greater than or equal to 0, and 0 < x13 < 1.

[0116] Where x11 = x12 = x13.

[0117] This configuration allows the brightness differences between adjacent sub-pixels of the same color within each color's sub-pixel 1 to become more consistent, thus enabling uniform control of brightness differences between sub-pixels of the same color 1 across different colors. Furthermore, this method simplifies the timing design of the charging enable level; for example, see [link to relevant documentation]. Figure 13When N11=N12=N13, the time interval between the charging enable levels provided by the driving signal line signal_1 corresponding to the first sub-pixel 5 and the driving signal line signal_4 corresponding to the second sub-pixel 6, the time interval between the charging enable levels provided by the driving signal line signal_2 corresponding to the third sub-pixel 9 and the driving signal line signal_5 corresponding to the fourth sub-pixel 10, and the time interval between the charging enable levels provided by the driving signal line signal_3 corresponding to the fifth sub-pixel 11 and the driving signal line signal_6 corresponding to the sixth sub-pixel 12 are all consistent.

[0118] In one feasible implementation, combined with Figure 1 and Figure 14 , Figure 14 for Figure 1 Another timing diagram of the drive signals provided by the corresponding multiple drive signal lines in the first mode, in the first mode:

[0119] The phase difference between the charging enable level provided by the drive signal line signal corresponding to the first sub-pixel 5 and the second sub-pixel 6 is ΔT11, ΔT11=(N11+x11)×P, where P is the noise period, N11 is an integer greater than or equal to 0, and 0<x11<1.

[0120] The phase difference between the charging enable levels provided by the drive signal lines signal corresponding to the third sub-pixel 9 and the fourth sub-pixel 10 is ΔT12, where ΔT12 = (N12 + x12) × P, N12 is an integer greater than or equal to 0, and 0 < x12 < 1.

[0121] The phase difference between the charging enable levels provided by the drive signal lines signal corresponding to the fifth sub-pixel 11 and the sixth sub-pixel 12 is ΔT13, where ΔT13 = (N13 + x13) × P, N13 is an integer greater than or equal to 0, and 0 < x13 < 1.

[0122] Among them, at least two of x11, x12 and x13 are not equal.

[0123] This configuration allows for inconsistent brightness differences between adjacent sub-pixels of at least two colors. This enables the adaptive adjustment of the x-values ​​corresponding to adjacent sub-pixels of different colors based on the human eye's ability to distinguish different colors. For example, for colors more easily perceived by the human eye, the x-values ​​corresponding to adjacent sub-pixels of that color can be made closer to 0.5, increasing the brightness difference between adjacent sub-pixels and making them more visually compensating for each other, thus significantly reducing the risk of them being visible to the human eye.

[0124] Furthermore, see again Figure 14 When the first color sub-pixel 4 is a red sub-pixel, the second color sub-pixel 7 is a green sub-pixel, and the third color sub-pixel 8 is a blue sub-pixel, x11, x12, and x13 can satisfy: |x12-0.5| < |x11-0.5|, |x12-0.5| < |x13-0.5|.

[0125] Compared to red and blue, green is easier for the human eye to recognize. Therefore, by setting x12 closer to 0.5, the brightness difference between adjacent green sub-pixels can be increased to a greater extent, thereby further preventing the human eye from recognizing green stripes.

[0126] In one feasible implementation, combined with Figure 1 ,like Figures 15-17 As shown, Figure 15 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 16 for Figure 15 A timing diagram of the clock signals provided by the multiple clock signal lines ck in the first mode. Figure 17 for Figure 16 A schematic diagram of the luminance of a corresponding sub-pixel 1 is shown. The display panel also includes a plurality of pixel columns 15 arranged along the first direction x, a plurality of repeating units 16 arranged along the first direction x, and a plurality of gating circuits 17 corresponding to the plurality of repeating units 16.

[0127] The pixel column 15 includes multiple sub-pixels 1 arranged along the second direction y, where the first direction x intersects the second direction y. The repeating unit 16 includes multiple pixel columns 15. The gating circuit 17 includes multiple control switches 18. The control terminals of the multiple control switches 18 are electrically connected to multiple clock signal lines ck, respectively. The input terminals of the multiple control switches 18 are electrically connected to the source signal line S, and the output terminals of the multiple control switches 18 are electrically connected to the corresponding pixel columns 15 in the repeating unit 16 via the data line Data. For ease of understanding, the multiple clock signal lines are represented by reference numerals ck_1 to ck_n in the accompanying drawings of this embodiment. However, the value of n varies depending on the structure of the display panel shown in the drawings.

[0128] Multiple clock signal lines ck sequentially provide clock enable levels according to the first order of the first type. When a clock signal line ck provides a clock enable level, the control switch 18 connected to it is turned on, and the data voltage on the source signal line S is transmitted to the data line Data connected to the control switch 18, thereby charging the data line Data. The first sub-pixel 5 and the second sub-pixel 6 are located in different pixel columns 15 and correspond to different clock signal lines ck. Figure 15In the illustration, the clock signal line corresponding to the first sub-pixel 5 is clock signal line ck_1, and the clock signal line corresponding to the second sub-pixel 6 is clock signal line ck_4. However, in different attached drawings, the reference numerals for the clock signal lines ck corresponding to the first sub-pixel 5 and the second sub-pixel 6 may differ.

[0129] In the first mode, the phase difference between the clock enable level provided by the clock signal line ck_ corresponding to the first sub-pixel 5 and the clock signal line ck_4 corresponding to the second sub-pixel 6 is a non-integer multiple of the noise period P.

[0130] Pixel group 2 includes pixel column 15, drive signal line signal includes clock signal line ck, charging enable level includes clock enable level, and first sequence includes first type first sequence.

[0131] In the above structure, the clock signal line ck is used to control the charging of the data line Data. In the first mode, by making the phase difference between the clock enable levels provided by the clock signal line ck_1 corresponding to the first sub-pixel 5 and the clock signal line ck_2 corresponding to the second sub-pixel 6 a non-integer multiple of the noise period P, the position points of the noise signal at the end of the two clock enable levels are different. Consequently, at the end of the charging of the two data lines Data connected to the first sub-pixel 5 and the second sub-pixel 6, the degree of influence of the noise signal on the data voltage ultimately transmitted on the two data lines Data is different. Thus, when the data voltage on the two data lines Data is written to the first sub-pixel 5 and the second sub-pixel 6 to charge them, a brightness difference will exist between the first sub-pixel 5 and the second sub-pixel 6. Combining the above analysis, the brightness difference between adjacent sub-pixels of the same color will visually compensate for each other and will not be visible to the naked eye, and therefore will not be perceived as stripes by the human eye.

[0132] In one feasible implementation, see Figures 15-17 Subpixel 1 also includes a second color subpixel 7 and a third color subpixel 8.

[0133] The plurality of pixel columns 15 include a first pixel column 19, a second pixel column 21, and a third pixel column 20. The first pixel column 19 includes at least a first color sub-pixel 4, and the first color sub-pixels 4 in the first pixel column 19 are aligned. The second pixel column 21 includes at least a third color sub-pixel 8, and the third color sub-pixels 8 in the second pixel column 21 are aligned. The third pixel column 20 includes at least a second color sub-pixel 7, and the second color sub-pixels 7 in the third pixel column 20 are aligned.

[0134] The repeating unit 16 includes at least two first pixel columns 19, at least two second pixel columns 21, and at least two third pixel columns 20. The phase difference between the clock enable levels provided by the clock signal lines ck corresponding to two adjacent first pixel columns 19 in the repeating unit 16 is a non-integer multiple of the noise period P, and / or the phase difference between the clock enable levels provided by the clock signal lines ck corresponding to two adjacent second pixel columns 21 in the repeating unit 16 is a non-integer multiple of the noise period P, and / or the phase difference between the clock enable levels provided by the clock signal lines ck corresponding to two adjacent third pixel columns 20 in the repeating unit 16 is a non-integer multiple of the noise period P.

[0135] Based on the arrangement of sub-pixels 1 in the first pixel column 19, the second pixel column 21, and the third pixel column 20, taking the first pixel column 19 as an example, when the phase difference between the clock enable levels provided by the clock signal lines ck (e.g., ck_1 and ck4) corresponding to two adjacent first pixel columns 19 in the repeating unit 16 is not an integer multiple of the noise period P, any two first color sub-pixels 4 adjacent in the first direction x in two adjacent first pixel columns 19 can be regarded as first sub-pixels 5 and second sub-pixels 6. These first color sub-pixels 4 all have brightness differences, so visually, more brightness differences of the first color sub-pixels 4 will be mutually compensated, making it less likely for the human eye to see the first color stripes. The second pixel column 21 and the third pixel column 20 are similar and will not be elaborated here.

[0136] Furthermore, it should be noted that, generally, multiple pixel columns 15 within the same repeating unit 16 correspond to multiple different clock signal lines ck, but the multiple clock signal lines ck corresponding to different repeating units 16 are the same. For example, see... Figure 15 , Figure 15 Both of the repeating units 16 shown correspond to the same six clock signal lines ck_1 to ck_6. When one of the clock signal lines ck provides a clock enable level, the data line Data connected to a certain pixel column 15 in the multiple repeating units 16 is charged simultaneously.

[0137] If the repeating unit 16 includes only one first pixel column 19, one second pixel column 21, and one third pixel column 20, taking the first pixel column 19 as an example, if we want to control the clock enable levels provided by the clock signal lines ck corresponding to the two first pixel columns 19 to have a phase difference, then at least two repeating units 16 need to correspond to two different sets of clock signal lines ck, so that the first pixel columns 19 in these two repeating units 16 are connected to different clock signal lines ck, so that the clock enable levels provided by the clock signal lines ck corresponding to the two first pixel columns 19 are staggered. With this setting, all repeating units 16 still need to correspond to at least six clock signal lines ck, but since the number of repeating units 16 divided in the display panel is large in this way, the number of source signal lines S is also large.

[0138] Compared with the above method, the division method of the repeating unit 16 in this embodiment of the invention not only does not increase the number of clock signal lines ck, but also reduces the number of source signal lines S, and correspondingly reduces the number of pins that need to be set.

[0139] In this embodiment of the invention, when the sub-pixel column 15 includes a first pixel column 19, a second pixel column 21, and a third pixel column 20, the following embodiments of the invention will be described using two structures as examples:

[0140] First structure:

[0141] In one feasible implementation, see again Figure 15 The first pixel column 19 includes only a plurality of first-color sub-pixels 4 arranged along the second direction y, the second pixel column 21 includes only a plurality of third-color sub-pixels 8 arranged along the second direction y, and the third pixel column 20 includes only a plurality of second-color sub-pixels 7 arranged along the second direction y. Furthermore, the first pixel column 19, the third pixel column 20, and the second pixel column 21 are arranged alternately.

[0142] Among them, three adjacent first pixel columns 19, third pixel columns 20 and second pixel columns 21 constitute a sub-unit 22, and the repeating unit 16 includes at least two sub-units 22.

[0143] In the above structure, each pixel column 15 includes only one color sub-pixel 1. If it is desired to control the difference in luminance between adjacent sub-pixels of the same color 1 in the first direction x, it is only necessary to control the timing of the clock signal line ck corresponding to a certain pixel column 15. Moreover, in the above configuration, at least six pixel columns 15 share a single source signal line S, resulting in a smaller number of pins required in the display panel.

[0144] Furthermore, the repeating unit 16 includes an odd number of sub-units 22. For example, as... Figure 18 and Figure 19As shown, Figure 18 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 19 for Figure 18 The corresponding multiple clock signal lines ck provide a timing diagram of the clock signal provided in the first mode. The repeating unit 16 includes 3 sub-units 22. At this time, the 9 pixel columns 15 share a source signal line S, and the number of pins required to be set in the display panel is greatly reduced.

[0145] Of course, in other optional embodiments of the present invention, the repeating unit 16 may also include an even number of subunits 22. For example, as Figure 20 and Figure 21 As shown, Figure 20 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 21 for Figure 20 The corresponding multiple clock signal lines ck provide a timing diagram of the clock signals in the first mode. The repeating unit 16 includes 4 sub-units 22.

[0146] In one feasible implementation, see again Figure 15 and Figure 16 In the first mode:

[0147] The phase difference between the clock enable levels provided by the clock signal lines ck corresponding to the two closest first color sub-pixels 4 in the first direction x in the repeating unit 16 is ΔT21. That is, the phase difference between the clock enable levels provided by the clock signal lines ck (e.g. ck_1 and ck_4) corresponding to the two adjacent first pixel columns 19 in the repeating unit 16 is ΔT21. ΔT21=(N21+x21)×P, where P is the noise period, N21 is an integer greater than or equal to 0, and 0<x21<1.

[0148] The phase difference between the clock enable levels provided by the clock signal lines ck corresponding to the two closest second color sub-pixels 7 in the first direction x in the repeating unit 16 is ΔT22. That is, the phase difference between the clock enable levels provided by the clock signal lines ck (e.g., ck_3 and ck_6) corresponding to the two adjacent third pixel columns 20 in the repeating unit 16 is ΔT22. ΔT22=(N22+x22)×P, where N22 is an integer greater than or equal to 0, and 0<x22<1.

[0149] The phase difference between the clock enable levels provided by the clock signal lines ck corresponding to the two closest third color sub-pixels 8 in the first direction x in the repeating unit 16 is ΔT23. That is, the phase difference between the clock enable levels provided by the clock signal lines ck (e.g. ck_2 and ck_5) corresponding to the two adjacent second pixel columns 21 in the repeating unit 16 is ΔT21. ΔT23=(N23+x23)×P, where N23 is an integer greater than or equal to 0, and 0<x23<1.

[0150] Where N21 = N22 = N23.

[0151] This setting of N21=N22=N23 can make the sequential restriction of the clock enable levels provided by the multiple clock signal lines ck corresponding to the repeating unit 16 more regular. For example, under the condition that N21=N22=N23 is satisfied, in one setting, see again Figure 16 When the clock signal line ck provides clock enable levels sequentially according to the first order of the first type, the clock signal lines ck corresponding to each pixel column 15 sequentially provide clock enable levels along the arrangement direction of the multiple pixel columns 15 in the repeating unit 16. That is, clock signal lines ck_1, ck_2, ck_3, ck_4, ck_5, and ck_6 sequentially output clock enable levels. Alternatively, in another setting, such as Figure 22 As shown, Figure 22 for Figure 15 Another timing diagram of the clock signals provided by the corresponding multiple clock signal lines ck in the first mode: when the clock signal lines ck sequentially provide clock enable levels according to the first order of the first type, at least two clock signal lines ck corresponding to the first pixel column 19 in the repeating unit 16 sequentially provide clock enable levels, at least two clock signal lines ck corresponding to the third pixel column 20 in the repeating unit 16 sequentially provide clock enable levels, and at least two clock signal lines ck corresponding to the second pixel column 21 in the repeating unit 16 sequentially provide clock enable levels. That is, clock signal lines ck_1, ck_4, ck_2, ck_5, ck_3, and ck_6 sequentially output clock enable levels.

[0152] In the above configuration, in the repeating unit, adjacent first pixel column 19, adjacent second pixel column 21, and adjacent third pixel column 20 will all exhibit a uniform distribution of brightness and darkness, and the brightness difference between adjacent pixel columns 15 of the same color is more easily compensated for. Moreover, the above configuration also simplifies the timing settings of multiple clock signal lines ck, and the order of the clock enable levels output by multiple clock signal lines ck has a certain regularity.

[0153] In one feasible implementation, such as Figure 23 and Figure 24 As shown, Figure 23 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 24 for Figure 23 The corresponding multiple clock signal lines ck provide a timing diagram of the clock signals in the first mode. The data lines Data include a first data line Data1 electrically connected to the first pixel column 19, a second data line Data3 electrically connected to the third pixel column 20, and a third data line Data3 electrically connected to the second pixel column 21.

[0154] The control switch 18 includes a first control switch 23 electrically connected to the first data line Data1, a second control switch 24 electrically connected to the second data line Data2, and a third control switch 25 electrically connected to the third data line Data3. The clock signal line ck includes a first clock signal line CK1 electrically connected to the first control switch 23, a second clock signal line CK2 electrically connected to the second control switch 24, and a third clock signal line CK3 electrically connected to the third control switch 25.

[0155] The first data line Data1, the second data line Data2, and the third data line Data3 each include a first sub-data line data1′ electrically connected to the odd-numbered row sub-pixels 1 and a second sub-data line data2′ electrically connected to the even-numbered row sub-pixels 1, respectively. The first control switch 23, the second control switch 24, and the third control switch 25 each include a first sub-switch 181 electrically connected to the first sub-data line and a second sub-switch 182 electrically connected to the second sub-data line Data2′, respectively. The first clock signal line ck1, the second clock signal line ck2, and the third clock signal line ck3 each include a first sub-clock line ck1′ electrically connected to the first sub-switch 181 and a second sub-clock line ck2′ electrically connected to the second sub-switch 182, wherein the first sub-clock line ck1′ and the second sub-clock line ck2′ provide clock enable levels at different times within the same clock signal line ck.

[0156] In addition, the source signal line S includes multiple sub-source signal lines S1. In one configuration, the first sub-switch 181 and the second sub-switch 182 corresponding to two pixel columns are connected to the same sub-source signal line S1.

[0157] In addition, the display panel also includes a scan signal line, for ease of understanding. Figure 23The scan signal line electrically connected to sub-pixel 1 in the i-th row is denoted by the reference numeral Scan_i. In one configuration, scan signal line scan_2m-1 is electrically connected to the data writing module of the pixel circuit in sub-pixel 1 in row 2m-1 and the reset module of the pixel circuit in sub-pixel 1 in row 2m+1, respectively. When scan signal line scan_2m-1 provides a low level, sub-pixel 1 in row 2m-1 performs a charging operation, and sub-pixel 1 in row 2m+1 performs a reset operation. Scan signal line scan_2m is electrically connected to the data writing module of the pixel circuit in sub-pixel 1 in row 2m and the reset module of the pixel circuit in sub-pixel 1 in row 2m+2, respectively. When scan signal line scan_2m provides a low level, sub-pixel 1 in row 2m performs a charging operation, and sub-pixel 1 in row 2m+2 performs a reset operation.

[0158] Taking sub-pixel 1 in row 2m+1 as an example, when scan signal line scan_2m-1 is turned on, sub-pixel 1 in row 2m-1 performs a charging operation, while sub-pixel 1 in row 2m+1 performs a reset operation. Then, scan signal line scan_2m is turned on, sub-pixel 1 in row 2m performs a charging operation, while sub-pixel 1 in row 2m+2 performs a reset operation. After scan signal line scan_2m is turned on, starting from time t0, the first sub-clock line ck1′ of clock signal lines ck_1 to ck_6 sequentially provides clock enable levels, and multiple first sub-data lines data1′ sequentially begin charging. When the clock enable level provided by the first sub-clock line ck1′ in clock signal line ck_6 is reached, scan signal line scan_2m+1 is turned on, and sub-pixel 1 in row 2m+1 uses the data voltage charged on the first sub-data line data1′ to perform a charging operation, while sub-pixel 1 in row 2m+3 performs a reset operation.

[0159] By adopting the above-mentioned dual data line (Data) setting method, under the premise of ensuring that the display panel can work normally, the duration of the low level provided by the scan signal line (scan) can be increased to more than 1H, thereby increasing the charging time of each row of sub-pixels 1, which is especially beneficial to meet the charging requirements of sub-pixels 1 under high-frequency driving.

[0160] The second structure:

[0161] In one feasible implementation, such as Figure 25 and Figure 26 As shown, Figure 25 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 26 for Figure 25A timing diagram corresponding to multiple clock signal lines ck is provided. The first pixel column 19 also includes a third color sub-pixel 8. The first color sub-pixel 4 and the third color sub-pixel 8 in the first pixel column 19 are arranged alternately in the second direction y. The second pixel column 21 also includes a first color sub-pixel 4. The third color sub-pixel 8 and the first color sub-pixel 4 in the second pixel column 21 are arranged alternately in the second direction y. The third pixel column 20 only includes multiple second color sub-pixels 7 arranged along the second direction y. Furthermore, the first color sub-pixels 4 in the first pixel column 19 and the third color sub-pixels 8 in the second pixel column 21 are aligned.

[0162] The third pixel column 20 includes a first type of third pixel column 30 and a second type of third pixel column 31, with the first pixel column 19, the first type of third pixel column 30, the second pixel column 21 and the second type of third pixel column 31 arranged alternately in sequence.

[0163] Among them, four adjacent first pixel columns 19, first type third pixel columns 30, second pixel columns 21 and second type third pixel columns 31 constitute a sub-unit 22, and the repeating unit 16 includes at least two sub-units 22.

[0164] Based on the above structure, the number of sub-pixels 1 between two adjacent first-color sub-pixels 4, two second-color sub-pixels 7, and two third-color sub-pixels 8 in the first direction x is different. Specifically, there are three sub-pixels 1 (two second-color sub-pixels 7 and one third-color sub-pixel 8) between two adjacent first-color sub-pixels 4 in the first direction x, one sub-pixel 1 (one first-color sub-pixel 4 or one third-color sub-pixel 8) between two adjacent second-color sub-pixels 7 in the first direction x, and three sub-pixels 1 (two second-color sub-pixels 7 and one first-color sub-pixel 4) between two adjacent third-color sub-pixels 8 in the first direction x.

[0165] In one setup method, see Figure 26 When multiple clock signal lines ck output clock enable levels sequentially in the order of clock signal lines ck_1 to ck_8, the number of integer noise cycles P contained in the phase difference between the clock enable levels output by two adjacent first color sub-pixels 4 (e.g., ck_1 and ck_5) is equal to the number of integer noise cycles P contained in the phase difference between the clock enable levels output by two adjacent third color sub-pixels 8 (e.g., ck_3 and ck_7), and greater than the number of integer noise cycles P contained in the phase difference between the clock enable levels output by two adjacent second color sub-pixels 7 (e.g., ck_2 and ck_4, ck_4 and ck_6, ck_6 and ck_8).

[0166] Furthermore, the repeating unit 16 includes an even number of sub-units 22. See, for example, [link to example]. Figure 25 The repeating unit 16 includes two sub-units 22.

[0167] When the repeating unit 16 includes an even number of sub-units 22, taking the first color sub-pixel 4 in the first pixel column 19 as an example, since the repeating unit 16 includes an even number of first pixel columns 19, there is a brightness difference between the first color sub-pixels 4 in every two adjacent first pixel columns 19 within the repeating unit 16, and there is also a brightness difference between the first color sub-pixels 4 in the two closest first pixel columns 19 in the two adjacent repeating units 16. At this time, the brightness difference of the first color sub-pixels 4 is evenly distributed in the display panel, and this brightness difference is less likely to be visible to the human eye.

[0168] In one feasible implementation, see again Figure 25 and Figure 26 In the first mode:

[0169] In the repeating unit 16, the phase difference between the clock enable levels provided by the clock signal lines ck corresponding to the two first color sub-pixels 4 that are closest to each other in the first direction x is ΔT21, ΔT21=(N21+x21)×P, where P is the noise period, N21 is an integer greater than or equal to 0, and 0<x21<1.

[0170] In the repeating unit 16, the phase difference between the clock enable levels provided by the clock signal lines ck corresponding to the two second color sub-pixels 7 that are closest to each other in the first direction x is ΔT22, ΔT22=(N22+x22)×P, where N22 is an integer greater than or equal to 0, and 0<x22<1.

[0171] In the repeating unit 16, the phase difference between the clock enable levels provided by the clock signal lines ck corresponding to the two closest third color sub-pixels 8 in the first direction x is ΔT23, ΔT23=(N23+x23)×P, where N23 is an integer greater than or equal to 0, and 0<x23<1.

[0172] Where N22≠N21, N22≠N23. It should be noted that, based on the arrangement of the first color sub-pixel 4 and the second color sub-pixel 7 in the first pixel column 19 and the second pixel column 21, the above-mentioned ΔT21 and ΔT23 can be equal.

[0173] Based on the above settings, in one configuration method, please refer again. Figure 26When the clock signal lines ck provide clock enable levels sequentially according to the first order of the first type, the clock signal lines ck corresponding to each pixel column 15 in the repeating unit 16 provide clock enable levels sequentially along the arrangement direction of the multiple pixel columns 15. That is, clock signal lines ck_1, ck_2, ck_3, ck_4, ck_5, ck_6, ck_7, and ck_8 output clock enable levels sequentially.

[0174] At this point, the clock enable levels provided by the clock signal lines ck (ck_2 and ck_4, ck_4 and ck_6, ck_6 and ck_8) corresponding to the two adjacent third pixel columns 20 are only separated by a clock enable level provided by another clock signal line ck, making the phase difference ΔT23 corresponding to the adjacent second color sub-pixel 7 relatively small. However, the clock enable levels provided by the clock signal lines ck (ck_1 and ck_5) corresponding to the two adjacent first pixel columns 19, and the clock enable levels provided by the clock signal lines ck (ck_3 and ck_7) corresponding to the two adjacent second pixel columns 21, are separated by three clock enable levels provided by other clock signal lines ck, making the phase difference ΔT21 corresponding to the adjacent first color sub-pixel 4 and the phase difference ΔT23 corresponding to the adjacent third color sub-pixel 8 relatively large. Therefore, N22 is less than N21 and N23.

[0175] Moreover, under the above timing setting method, the timing of multiple clock signal lines ck is more regular, and the timing setting is also simpler.

[0176] In one feasible implementation, such as Figure 27 and Figure 28 As shown, Figure 27 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 28 for Figure 27 The corresponding multiple clock signal lines ck provide a timing diagram of the clock signals in the first mode. The data lines Data include a first data line Data1 electrically connected to the first pixel column 19, a second data line Data2 electrically connected to the first type third pixel column 30, a third data line Data3 electrically connected to the second pixel column 21, and a fourth data line Data4 electrically connected to the second type third pixel column 31.

[0177] The control switch 18 includes a first control switch 23 electrically connected to the first data line Data1, a second control switch 24 electrically connected to the second data line Data2, a third control switch 25 electrically connected to the third data line Data3, and a fourth control switch 32 electrically connected to the fourth data line Data4. The clock signal line ck includes a first clock signal line ck1 electrically connected to the first control switch 23, a second clock signal line ck2 electrically connected to the second control switch 24, a third clock signal line ck3 electrically connected to the third control switch 25, and a fourth clock signal line ck4 electrically connected to the fourth control switch 32.

[0178] The data lines Data1, Data2, Data3, and Data4 each include a first sub-data line electrically connected to the odd-numbered row sub-pixels 1 and a second sub-data line Data2' electrically connected to the even-numbered row sub-pixels 1. The control switches 23, 24, 25, and 32 each include a first sub-switch 181 electrically connected to the first sub-data line and a second sub-switch 182 electrically connected to the second sub-data line Data2'. The clock signal lines ck1, ck2, ck3, and ck4 each include a first sub-clock line ck1' electrically connected to the first sub-switch 181 and a second sub-clock line ck2' electrically connected to the second sub-switch 182. The clock enable levels provided by the first sub-clock line ck1' and the second sub-clock line ck2' within the same clock signal line ck are different at different times.

[0179] In addition, the source signal line S includes multiple sub-source signal lines S1. In one configuration, the first sub-switch 181 and the second sub-switch 182 corresponding to two pixel columns are connected to the same sub-source signal line S1.

[0180] In addition, the display panel also includes a scan signal line (scan). The connection method and working principle of the scan signal line (scan) can be the same as the connection method mentioned in the first structure, and will not be repeated here. By adopting the above-mentioned dual data line (Data) setting method, the charging time of each row of sub-pixels 1 can be increased while ensuring the normal operation of the display panel, thereby improving the charging effect.

[0181] In one feasible implementation, such as Figures 29-31 As shown, Figure 29 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 30 for Figure 29 A timing diagram of the scan signals provided by the corresponding multiple scan signal lines in the first mode. Figure 31 for Figure 30A schematic diagram of the luminance of a corresponding sub-pixel. The display panel includes multiple pixel rows 34 arranged along the second direction y. The pixel rows 34 include multiple sub-pixels 1 arranged along the first direction x. The first direction x intersects with the second direction y.

[0182] The display panel also includes multiple scan signal lines (scan), each scan signal line being electrically connected to a sub-pixel 1 in at least one pixel row 34. For ease of understanding, Figure 29 The multiple scan signal lines are represented by the reference numerals scan_1 to scan_k in the attached diagram.

[0183] In this configuration, multiple scan signal lines (scan) sequentially provide scan enable levels according to a second type of first order, where the second type of first order can be the arrangement order of multiple pixel rows 34. When a scan signal line (scan) provides a scan enable level, the data voltage on the data line (Data) is transmitted to and written to sub-pixel 1 in the pixel row 34 connected to it, thereby charging sub-pixel 1. The first sub-pixel 5 and the second sub-pixel 6 are located in different pixel rows 34 and correspond to different scan signal lines (scan). In the first mode, the phase difference between the scan enable levels provided by the scan signal lines (scan) corresponding to the first sub-pixel 5 and the second sub-pixel 6 is a non-integer multiple of the noise period P.

[0184] Pixel group 2 includes pixel row 34, drive signal line signal includes scan signal line scan, charging enable level includes scan enable level, and first sequence includes second type first sequence.

[0185] When the scan signal line (scan) provides the scan enable level, the data voltage transmitted on the data line (Data) charges sub-pixel 1, which is enabled by the scan signal line (scan). During this charging process, if the display panel receives a noise signal, the noise signal will affect the data voltage written to sub-pixel 1, causing it to fluctuate and affecting the charging degree of sub-pixel 1, thereby affecting the actual light emission brightness of sub-pixel 1.

[0186] In this embodiment of the invention, in the first mode, when the phase difference between the clock enable levels provided by the scan signal lines corresponding to the first sub-pixel 5 and the second sub-pixel 6 is not an integer multiple of the noise period P, the noise signal positions corresponding to the end times of these two scan enable levels are different. This avoids the end times of the two scan enable levels simultaneously corresponding to the peak (or trough) of the noise signal, thereby preventing the data voltages corresponding to these two adjacent sub-pixels of the same color from experiencing maximum positive fluctuations (or maximum negative fluctuations), and further preventing the luminance of these two adjacent sub-pixels of the same color from exhibiting maximum brightness (or maximum darkness). Thus, when the display panel displays a pure or polychromatic image of the first color, the brightness shift of the adjacent first color sub-pixel 4 will not be perceived as obvious stripes by the human eye, effectively improving the impact of the luminance shift of the first color sub-pixel 4 caused by noise on the image seen by the human eye.

[0187] In one feasible implementation, see again Figure 29 and Figure 30 Subpixel 1 also includes a second color subpixel 7 and a third color subpixel 8. Pixel row 34 includes a first color subpixel 4, a second color subpixel 7, and a third color subpixel 8 arranged alternately in sequence, wherein the first color subpixel 4, the second color subpixel 7, and the third color subpixel 8 in the plurality of pixel rows 34 are aligned.

[0188] In the first mode:

[0189] The phase difference between the scan enable levels provided by the scan signal lines corresponding to two adjacent first color sub-pixels 4 in the second direction y is ΔT31, where ΔT31 = (N31 + x31) × P, P is the noise period, N31 is an integer greater than or equal to 0, and 0 < x31 < 1.

[0190] The phase difference between the scan enable levels provided by the scan signal lines corresponding to two adjacent second color sub-pixels 7 in the second direction y is ΔT32, where ΔT32 = (N32 + x32) × P, N32 is an integer greater than or equal to 0, and 0 < x32 < 1.

[0191] The phase difference between the scan enable levels provided by the scan signal lines corresponding to two adjacent third color sub-pixels 8 in the second direction y is ΔT33, where ΔT33 = (N33 + x33) × P, N33 is an integer greater than or equal to 0, and 0 < x33 < 1.

[0192] Where N31 = N32 = N33.

[0193] Based on the arrangement of sub-pixels 1 in each pixel row 34, the two first-color sub-pixels 4, the two second-color sub-pixels 7, and the two third-color sub-pixels 8 that are closest to each other in the second direction y are all located in two adjacent pixel rows 34. When the scan signal line scan sequentially provides scan enable levels to drive multiple pixel rows 34, the interval between the scan enable levels provided by the scan signal line scan corresponding to any two adjacent pixel rows 34 can be the same, so N31, N32, and N33 are equal.

[0194] In one feasible implementation, such as Figures 32-34 As shown, Figure 32 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 33 for Figure 32 A timing diagram of the scan signals provided by the corresponding multiple scan signal lines in the first mode. Figure 34 for Figure 33 A schematic diagram of the luminance of a corresponding sub-pixel. Sub-pixel 1 also includes a second color sub-pixel 7 and a third color sub-pixel 8.

[0195] Pixel row 34 includes alternating first-color sub-pixels 4, second-color sub-pixels 7, and third-color sub-pixels 8. Multiple pixel rows 34 include alternating first pixel rows 35 and second pixel rows 36, where the first-color sub-pixels 4 in the first pixel row 35 are aligned with the third-color sub-pixels 8 in the second pixel row 36, the second-color sub-pixels 7 in the first pixel row 35 are aligned with the second-color sub-pixels 7 in the second pixel row 36, and the third-color sub-pixels 8 in the first pixel row 35 are aligned with the first-color sub-pixels 4 in the second pixel row 36.

[0196] In the first mode:

[0197] The phase difference between the scan enable levels provided by the scan signal lines corresponding to the two closest first color sub-pixels 4 in the second direction y is ΔT31, where ΔT31 = (N31 + x31) × P, P is the noise period, N31 is an integer greater than or equal to 0, and 0 < x31 < 1.

[0198] The phase difference between the scan enable levels provided by the scan signal lines corresponding to the two closest second color sub-pixels 7 in the second direction y is ΔT32, where ΔT32 = (N32 + x32) × P, N32 is an integer greater than or equal to 0, and 0 < x32 < 1.

[0199] The phase difference between the scan enable levels provided by the scan signal lines corresponding to the two closest third color sub-pixels 8 in the second direction y is ΔT33, where ΔT33 = (N33 + x33) × P, N33 is an integer greater than or equal to 0, and 0 < x32 < 1.

[0200] Where N32 ≠ N31, N32 ≠ N33. It should be noted that the N32 corresponding to two different adjacent second color sub-pixels 7 in the second direction y can be the same or different.

[0201] Based on the arrangement of sub-pixels 1 in each pixel row 34, two adjacent first-color sub-pixels 4 in the second direction y are respectively located in two adjacent first pixel rows 35 or two adjacent second pixel rows 36. Similarly, two adjacent third-color sub-pixels 8 in the second direction y are also respectively located in two adjacent first pixel rows 35 or two adjacent second pixel rows 36. Two adjacent second-color sub-pixels 7 in the second direction y are respectively located in adjacent first pixel rows 35 and second pixel rows 36.

[0202] When the scan signal line scan sequentially provides scan enable levels to drive multiple pixel rows 34, there is a gap between the scan enable levels provided by any two adjacent first pixel rows 35 and the scan enable level provided by the scan signal line scan corresponding to the second pixel row 36. There is no gap between the scan enable levels provided by the scan signal line scan corresponding to any two adjacent first pixel rows 35 and the second pixel row 36. Therefore, N31, N32 and N33 are different, and N32 will be smaller than N31 and N33.

[0203] It should be noted that, in this embodiment of the invention, the driving signal line signalal may include one of a clock signal line ck and a scan signal line scan, or may include both clock signal line ck and scan signal line scan simultaneously. When the driving signal line signalal includes both clock signal line ck and scan signal line scan, the charging of the data line Data and sub-pixel 1 by the noise signal can be simultaneously controlled. This allows the degree of charging of the data line Data and the degree of charging of the sub-pixel 1 to jointly influence the light emission brightness of the sub-pixel 1. In this case, the light emission brightness of multiple sub-pixels in the display panel can be as follows: Figure 35 As shown.

[0204] Based on the same inventive concept, embodiments of the present invention also provide a method for driving a display panel, combined with Figure 1 and Figure 2 The display panel includes sub-pixels 1, multiple pixel groups 2, and multiple drive signal lines (signals). Each pixel group 2 includes multiple sub-pixels 1, and the arrangement direction of pixel group 2 intersects with the arrangement direction of the sub-pixels 1 within pixel group 2. Each drive signal line (signal) corresponds to at least one sub-pixel 1 within pixel group 2. The multiple drive signal lines (signals) sequentially output charging enable levels in a first order to drive the corresponding pixel group 2.

[0205] Wherein, sub-pixel 1 includes a first color sub-pixel 4, the first color sub-pixel 4 includes a first sub-pixel 5 and a second sub-pixel 6, the first sub-pixel 5 and the second sub-pixel 6 are located in different pixel groups 2 and correspond to different driving signal lines signal respectively, and the first sub-pixel 5 and the second sub-pixel 6 are arranged along the arrangement direction of pixel group 2, and the second sub-pixel 6 and the first sub-pixel 5 are spaced apart by a number of other first color sub-pixels 4 less than a preset number.

[0206] The display panel has a first mode. The driving method includes: in the first mode, the display panel receives a noise signal, the noise signal having a noise period P, and the phase difference between the charging enable level provided by the driving signal line signal corresponding to the first sub-pixel 5 and the second sub-pixel 6 is a non-integer multiple of the noise period P.

[0207] Based on the foregoing analysis, by controlling the phase difference of the charging enable level provided by the driving signal line signal corresponding to the adjacent first color sub-pixel 4 to be a non-integer multiple of the noise period P, the luminance distribution of the adjacent first color sub-pixel 4 can be controlled, preventing the adjacent first color sub-pixel 4 from continuously exhibiting maximum brightness or maximum darkness. Thus, when the display panel displays a pure or complex first color image, the brightness shift of the adjacent first color sub-pixel 4 will not be perceived as obvious stripes by the human eye, effectively mitigating the impact of the luminance shift of the first color sub-pixel 4 caused by noise on the image perceived by the human eye.

[0208] In one feasible implementation, combined with Figure 1 and Figure 2 ΔT = (N + x) × P, where ΔT is the phase difference between the charging enable level provided by the drive signal line signal corresponding to the first sub-pixel 5 and the second sub-pixel 6 in the first mode, P is the noise period, N is an integer greater than or equal to 0, and 0.4 ≤ x ≤ 0.6.

[0209] In the first mode, when ΔT and P satisfy the above relationship, the phase difference between the two charging enable levels, after deducting an integer number of noise cycles P, will still differ by about half a noise cycle P. This results in a significant difference in the position of the noise signal at the end of the two charging enable levels. For example, if the end of one charging enable level corresponds to the rising trend tr of the noise signal, then the end of the other charging enable level will correspond to the falling trend td of the noise signal. In this case, the noise signal has opposite effects on the brightness of the first sub-pixel 5 and the second sub-pixel 6, making one of the two first color sub-pixels 4 brighter and the other darker. In this way, the brightness distribution of the first sub-pixel 5 and the second sub-pixel 6 can be controlled, and the brightness difference between these two sub-pixels will visually compensate for each other, making their equivalent brightness approach the target brightness. Therefore, it can be avoided to a greater extent from being perceived as ripples by the human eye.

[0210] Furthermore, we can also make x = 0.5.

[0211] At this point, after removing the integer number of noise cycles P, the phase difference between the two charging enable levels will still differ by half a noise cycle P. Therefore, while the end times of the two charging enable levels correspond to the rising trend tr and falling trend td of the noise signal, respectively, there will also be a situation where the end time of one charging enable level corresponds to the peak of the noise signal, and the end time of the other charging enable level corresponds to the trough of the noise signal. In this case, the visual brightness difference between the first sub-pixel 5 and the second sub-pixel 6 is greater, and this brightness difference is more easily compensated for, making it less likely to be perceived by the human eye.

[0212] In one feasible implementation, combined with Figures 10-12 Subpixel 1 further includes a second color subpixel 7 and a third color subpixel 8. The display panel includes multiple pixels 13, each including a first color subpixel 4, a second color subpixel 7, and a third color subpixel 8. The multiple pixels include a first pixel 14, where the first color subpixel 4, the second color subpixel 7, and the third color subpixel 8 each correspond to a different driving signal line (signal).

[0213] Based on this, the driving method further includes: in the first mode, the phase difference between the charging enable level provided by the driving signal line signal corresponding to the first color sub-pixel 4 and the second color sub-pixel 7 in the first pixel 14 is [M-0.1, M+0.1] times the noise period P, where M is a positive integer; and / or, the phase difference between the charging enable level provided by the driving signal line signal corresponding to the first color sub-pixel 4 and the third color sub-pixel 8 in the first pixel 14 is [R-0.1, R+0.1] times the noise period P, where R is a positive integer.

[0214] Based on the foregoing analysis, by adopting the above method, the noise signal affects the luminance of at least two different colored sub-pixels 1 in the first pixel 14 in the same direction, which can effectively improve the color cast of the first pixel 14 itself. The improvement effect is even more significant when all three colors of sub-pixels 1 in the first pixel 14 are simultaneously darkened or simultaneously brightened.

[0215] Based on the same inventive concept, embodiments of the present invention provide a display device, such as... Figure 36 As shown, Figure 36 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the aforementioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Figure 36 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0216] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0217] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, include: Subpixel; Multiple pixel groups, each pixel group comprising multiple sub-pixels, wherein the arrangement direction of the pixel groups intersects with the arrangement direction of the sub-pixels within the pixel groups; Multiple driving signal lines, one driving signal line corresponding to at least one sub-pixel in the pixel group, and multiple driving signal lines sequentially output charging enable levels in a first order to drive the corresponding pixel group; The sub-pixel includes a first color sub-pixel, the first color sub-pixel includes a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are located in different pixel groups and correspond to different driving signal lines respectively, and the first sub-pixel and the second sub-pixel are arranged along the arrangement direction of the pixel group, and the second sub-pixel is spaced from the first sub-pixel by no more than a preset number of other first color sub-pixels; The display panel has a first mode in which the display panel receives a noise signal having a noise period, and the phase difference between the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the second sub-pixel is a non-integer multiple of the noise period. in, Wherein, ΔT is the phase difference between the charging enable levels provided by the driving signal lines corresponding to the first sub-pixel and the second sub-pixel in the first mode, P is the noise period, N is an integer greater than or equal to 0, and 0.4≤x≤0.

6.

2. The display panel according to claim 1, characterized in that, x=0.5。 3. The display panel according to claim 1, characterized in that, The preset quantity is 1, and the second sub-pixel is separated from the first sub-pixel by at most one other first color sub-pixel.

4. The display panel according to claim 1, characterized in that, The sub-pixel also includes a second color sub-pixel and a third color sub-pixel; The display panel further includes a plurality of pixels, the pixels including a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; Among them, the plurality of pixels include a first pixel, wherein the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the first pixel are located in different pixel groups and respectively correspond to different driving signal lines; In the first mode, the phase difference between the charging enable level provided by the driving signal line corresponding to the first color sub-pixel and the second color sub-pixel in the first pixel is [M-0.1, M+0.1] times the noise period, where M is a positive integer; and / or, the phase difference between the charging enable level provided by the driving signal line corresponding to the first color sub-pixel and the third color sub-pixel in the first pixel is [R-0.1, R+0.1] times the noise period, where R is a positive integer.

5. The display panel according to claim 1, characterized in that, The sub-pixel also includes a second color sub-pixel and a third color sub-pixel; The second color sub-pixel includes a third sub-pixel and a fourth sub-pixel. The third sub-pixel and the fourth sub-pixel are located in different pixel groups and correspond to different driving signal lines. Furthermore, the third sub-pixel and the fourth sub-pixel are arranged along the arrangement direction of the pixel groups, and the interval between the third sub-pixel and the fourth sub-pixel is less than the preset number of other second color sub-pixels. In the first mode, the phase difference between the charging enable levels provided by the driving signal lines corresponding to the third sub-pixel and the fourth sub-pixel is a non-integer multiple of the noise period. The third color sub-pixel includes a fifth sub-pixel and a sixth sub-pixel. The fifth sub-pixel and the sixth sub-pixel are located in different pixel groups and correspond to different driving signal lines. Furthermore, the fifth sub-pixel and the sixth sub-pixel are arranged along the arrangement direction of the pixel groups, and the interval between the fifth sub-pixel and the sixth sub-pixel is less than the preset number of other third color sub-pixels. In the first mode, the phase difference between the charging enable levels provided by the driving signal lines corresponding to the fifth sub-pixel and the sixth sub-pixel is a non-integer multiple of the noise period.

6. The display panel according to claim 5, characterized in that, In the first mode: The phase difference between the charging enable levels provided by the driving signal lines corresponding to the first sub-pixel and the second sub-pixel is ΔT11. P is the noise period, N11 is an integer greater than or equal to 0, and 0 < x11 < 1; The phase difference between the charging enable levels provided by the driving signal lines corresponding to the third and fourth sub-pixels is ΔT12. N12 is an integer greater than or equal to 0, where 0 < x12 < 1; The phase difference between the charging enable levels provided by the driving signal lines corresponding to the fifth and sixth sub-pixels is ΔT13. N13 is an integer greater than or equal to 0, where 0 < x13 < 1; Where x11=x12=x13.

7. The display panel according to claim 5, characterized in that, In the first mode: The phase difference between the charging enable levels provided by the driving signal lines corresponding to the first sub-pixel and the second sub-pixel is ΔT11. P is the noise period, N11 is an integer greater than or equal to 0, and 0 < x11 < 1; The phase difference between the charging enable levels provided by the driving signal lines corresponding to the third and fourth sub-pixels is ΔT12. N12 is an integer greater than or equal to 0, where 0 < x12 < 1; The phase difference between the charging enable levels provided by the driving signal lines corresponding to the fifth and sixth sub-pixels is ΔT13. N13 is an integer greater than or equal to 0, where 0 < x13 < 1; Among them, at least two of x11, x12 and x13 are not equal.

8. The display panel according to claim 7, characterized in that, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel; |x12-0.5|<|x11-0.5|, |x12-0.5|<|x13-0.5|.

9. The display panel according to claim 1, characterized in that, The display panel also includes: A plurality of pixel columns arranged along a first direction, the pixel columns including a plurality of sub-pixels arranged along a second direction, the first direction intersecting the second direction; A plurality of repeating units arranged along the first direction, the repeating unit comprising a plurality of the pixel columns; Multiple gating circuits corresponding to the multiple repeating units, each gating circuit including multiple control switches, the control terminals of the multiple control switches being electrically connected to multiple clock signal lines respectively, the input terminals of the multiple control switches being electrically connected to source signal lines, and the output terminals of the multiple control switches being electrically connected to multiple pixel columns in the corresponding repeating units via data lines; In this context, multiple clock signal lines provide clock enable levels sequentially according to a first type of first order. The first sub-pixel and the second sub-pixel are located in different pixel columns and correspond to different clock signal lines respectively. In the first mode, the phase difference between the clock enable levels provided by the clock signal lines corresponding to the first sub-pixel and the second sub-pixel is a non-integer multiple of the noise period. Wherein, the pixel group includes the pixel column, the driving signal line includes the clock signal line, the charging enable level includes the clock enable level, and the first sequence includes the first type of first sequence.

10. The display panel according to claim 9, characterized in that, The sub-pixel also includes a second color sub-pixel and a third color sub-pixel; The plurality of pixel columns include a first pixel column, a second pixel column, and a third pixel column, wherein the first pixel column includes at least the first color sub-pixel, and the first color sub-pixels in the first pixel column are aligned; the second pixel column includes at least the third color sub-pixel, and the third color sub-pixels in the second pixel column are aligned; the third pixel column includes at least the second color sub-pixel, and the second color sub-pixels in the third pixel column are aligned. The repeating unit includes at least two first pixel columns, at least two second pixel columns, and at least two third pixel columns; Wherein, the phase difference between the clock enable level provided by the clock signal line corresponding to two adjacent first pixel columns in the repeating unit is a non-integer multiple of the noise period, and / or, the phase difference between the clock enable level provided by the clock signal line corresponding to two adjacent second pixel columns in the repeating unit is a non-integer multiple of the noise period, and / or, the phase difference between the clock enable level provided by the clock signal line corresponding to two adjacent third pixel columns in the repeating unit is a non-integer multiple of the noise period.

11. The display panel according to claim 10, characterized in that, The first pixel column includes only a plurality of first color sub-pixels arranged along the second direction, the second pixel column includes only a plurality of third color sub-pixels arranged along the second direction, and the third pixel column includes only a plurality of second color sub-pixels arranged along the second direction; The first pixel column, the third pixel column, and the second pixel column are arranged alternately in sequence; Wherein, three adjacent first pixel columns, third pixel columns and second pixel columns constitute a sub-unit, and the repeating unit includes at least two of the sub-units.

12. The display panel according to claim 11, characterized in that, The repeating unit comprises an odd number of the sub-units.

13. The display panel according to claim 11, characterized in that, In the first mode: The phase difference between the clock enable levels provided by the clock signal lines corresponding to the two first color sub-pixels that are closest to each other in the first direction in the repeating unit is ΔT21. P is the noise period, N21 is an integer greater than or equal to 0, and 0 < x21 < 1; The phase difference between the clock enable levels provided by the clock signal lines corresponding to the two second color sub-pixels that are closest to each other in the first direction in the repeating unit is ΔT22. N22 is an integer greater than or equal to 0, where 0 < x22 < 1; The phase difference between the clock enable levels provided by the clock signal lines corresponding to the two third color sub-pixels that are closest to each other in the first direction in the repeating unit is ΔT23. N23 is an integer greater than or equal to 0, where 0 < x23 < 1; Where N21=N22=N23.

14. The display panel according to claim 10, characterized in that, The first pixel column further includes the third color sub-pixel, and the first color sub-pixel and the third color sub-pixel in the first pixel column are arranged alternately in the second direction. The second pixel column also includes the first color sub-pixel, and the third color sub-pixel and the first color sub-pixel in the second pixel column are arranged alternately in the second direction. The third pixel column includes only a plurality of second color sub-pixels arranged along the second direction, and the first color sub-pixel in the first pixel column and the third color sub-pixel in the second pixel column are aligned. The third pixel column includes a first type of third pixel column and a second type of third pixel column, and the first pixel column, the first type of third pixel column, the second pixel column and the second type of third pixel column are arranged alternately in sequence; Wherein, four adjacent first pixel columns, first type third pixel columns, second pixel columns and second type third pixel columns constitute a sub-unit, and the repeating unit includes at least two of the sub-units.

15. The display panel according to claim 14, characterized in that, The repeating unit comprises an even number of the sub-units.

16. The display panel according to claim 14, characterized in that, In the first mode: The phase difference between the clock enable levels provided by the clock signal lines corresponding to the two first color sub-pixels that are closest to each other in the first direction in the repeating unit is ΔT21. P is the noise period, N21 is an integer greater than or equal to 0, and 0 < x21 < 1; The phase difference between the clock enable levels provided by the clock signal lines corresponding to the two second color sub-pixels that are closest to each other in the first direction in the repeating unit is ΔT22. N22 is an integer greater than or equal to 0, where 0 < x22 < 1; The phase difference between the clock enable levels provided by the clock signal lines corresponding to the two third color sub-pixels that are closest to each other in the first direction in the repeating unit is ΔT23. N23 is an integer greater than or equal to 0, where 0 < x23 < 1; Among them, N22≠N21, N22≠N23.

17. The display panel according to claim 11, characterized in that, The data line includes a first data line electrically connected to the first pixel column, a second data line electrically connected to the third pixel column, and a third data line electrically connected to the second pixel column; The control switch includes a first control switch electrically connected to the first data line, a second control switch electrically connected to the second data line, and a third control switch electrically connected to the third data line. The clock signal line includes a first clock signal line electrically connected to the first control switch, a second clock signal line electrically connected to the second control switch, and a third clock signal line electrically connected to the third control switch. Wherein, the first data line, the second data line and the third data line respectively include a first sub-data line electrically connected to the sub-pixels in the odd-numbered rows and a second data line electrically connected to the sub-pixels in the even-numbered rows; The first control switch, the second control switch, and the third control switch each include a first sub-switch electrically connected to the first sub-data line and a second switch electrically connected to the second sub-data line; The first clock signal line, the second clock signal line, and the third clock signal line each include a first sub-clock line electrically connected to the first sub-switch and a second sub-clock line electrically connected to the second sub-switch, wherein the first sub-clock line and the second sub-clock line in the same clock signal line provide the clock enable level at different times.

18. The display panel according to claim 14, characterized in that, The data line includes a first data line electrically connected to the first pixel column, a second data line electrically connected to the first type of third pixel column, a third data line electrically connected to the second pixel column, and a fourth data line electrically connected to the second type of third pixel column. The control switch includes a first control switch electrically connected to the first data line, a second control switch electrically connected to the second data line, a third control switch electrically connected to the third data line, and a fourth control switch electrically connected to the fourth data line. The clock signal line includes a first clock signal line electrically connected to the first control switch, a second clock signal line electrically connected to the second control switch, a third clock signal line electrically connected to the third control switch, and a fourth clock signal line electrically connected to the fourth control switch. The first data line, the second data line, the third data line, and the fourth data line each include a first sub-data line electrically connected to the sub-pixels in the odd-numbered rows and a second data line electrically connected to the sub-pixels in the even-numbered rows. The first control switch, the second control switch, the third control switch, and the fourth control switch each include a first sub-switch electrically connected to the first sub-data line and a second switch electrically connected to the second sub-data line; The first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line each include a first sub-clock line electrically connected to the first sub-switch and a second sub-clock line electrically connected to the second sub-switch, wherein the first sub-clock line and the second sub-clock line in the same clock signal line provide the clock enable level at different times.

19. The display panel according to claim 1, characterized in that, The display panel includes a plurality of pixel rows arranged along a second direction, and the pixel rows include a plurality of sub-pixels arranged along a first direction, the first direction intersecting the second direction; The display panel also includes multiple scan signal lines, which are electrically connected to at least one sub-pixel in the pixel row; In this context, multiple scan signal lines provide scan enable levels sequentially according to a second type of first order. The first sub-pixel and the second sub-pixel are located in different pixel rows and correspond to different scan signal lines. In the first mode, the phase difference between the scan enable levels provided by the scan signal lines corresponding to the first sub-pixel and the second sub-pixel is a non-integer multiple of the noise period. Wherein, the pixel group includes the pixel row, the driving signal line includes the scan signal line, the charging enable level includes the scan enable level, and the first sequence includes the second type of first sequence.

20. The display panel according to claim 19, characterized in that, The sub-pixel also includes a second color sub-pixel and a third color sub-pixel; The pixel row includes first color sub-pixels, second color sub-pixels and third color sub-pixels arranged alternately in sequence, wherein the first color sub-pixels, second color sub-pixels and third color sub-pixels in the plurality of pixel rows are aligned; In the first mode: The phase difference between the scan enable levels provided by the scan signal lines corresponding to two adjacent first color sub-pixels in the second direction is ΔT31. P is the noise period, N31 is an integer greater than or equal to 0, and 0 < x31 < 1; The phase difference between the scan enable levels provided by the scan signal lines corresponding to two adjacent second color sub-pixels in the second direction is ΔT32. N32 is an integer greater than or equal to 0, where 0 < x32 < 1; The phase difference between the scan enable levels provided by the scan signal lines corresponding to two adjacent third color sub-pixels in the second direction is ΔT33. N33 is an integer greater than or equal to 0, where 0 < x33 < 1; Where N31=N32=N33.

21. The display panel according to claim 19, characterized in that, The sub-pixel also includes a second color sub-pixel and a third color sub-pixel; The pixel row includes alternating first color sub-pixels, second color sub-pixels, and third color sub-pixels, wherein the plurality of pixel rows include alternating first pixel rows and second pixel rows, the first color sub-pixels in the first pixel row are aligned with the third color sub-pixels in the second pixel row, the second color sub-pixels in the first pixel row are aligned with the second color sub-pixels in the second pixel row, and the third color sub-pixels in the first pixel row are aligned with the first color sub-pixels in the second pixel row; In the first mode: The phase difference between the scan enable levels provided by the scan signal lines corresponding to the two closest first color sub-pixels in the second direction is ΔT31. P is the noise period, N31 is an integer greater than or equal to 0, and 0 < x31 < 1; The phase difference between the scan enable levels provided by the scan signal lines corresponding to the two closest second color sub-pixels in the second direction is ΔT32. N32 is an integer greater than or equal to 0, where 0 < x32 < 1; The phase difference between the scan enable levels provided by the scan signal lines corresponding to the two closest third color sub-pixels in the second direction is ΔT33. N33 is an integer greater than or equal to 0, and 0 < x32 < 1; Among them, N32≠N31, N32≠N33.

22. A driving method for a display panel, characterized in that, The display panel includes: Subpixel; Multiple pixel groups, each pixel group comprising multiple sub-pixels, wherein the arrangement direction of the pixel groups intersects with the arrangement direction of the sub-pixels within the pixel groups; Multiple driving signal lines, one driving signal line corresponding to at least one sub-pixel in the pixel group, wherein the multiple driving signal lines sequentially output charging enable levels in a first order to drive the corresponding pixel group; Wherein, the sub-pixel includes a first color sub-pixel, the first color sub-pixel includes a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are located in different pixel groups and correspond to different driving signal lines respectively, and the first sub-pixel and the second sub-pixel are arranged along the arrangement direction of the pixel group, and the second sub-pixel is spaced from the first sub-pixel by a number of other first color sub-pixels less than a preset number; The display panel has a first mode; The driving method includes: in the first mode, the display panel receives a noise signal having a noise period, and the phase difference between the charging enable level provided by the driving signal line corresponding to the first sub-pixel and the second sub-pixel is a non-integer multiple of the noise period; in, Wherein, ΔT is the phase difference between the charging enable levels provided by the driving signal lines corresponding to the first sub-pixel and the second sub-pixel in the first mode, P is the noise period, N is an integer greater than or equal to 0, and 0.4≤x≤0.

6.

23. The driving method according to claim 22, characterized in that, x=0.5。 24. The driving method according to claim 22, characterized in that, The sub-pixel also includes a second color sub-pixel and a third color sub-pixel; The display panel includes a plurality of pixels, the pixels including a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; The plurality of pixels include a first pixel, wherein the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the first pixel correspond to different driving signal lines; The driving method further includes: In the first mode, the phase difference between the charging enable level provided by the driving signal line corresponding to the first color sub-pixel and the second color sub-pixel in the first pixel is [M-0.1, M+0.1] times the noise period, where M is a positive integer; and / or, the phase difference between the charging enable level provided by the driving signal line corresponding to the first color sub-pixel and the third color sub-pixel in the first pixel is [R-0.1, R+0.1] times the noise period, where R is a positive integer.

25. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 21.

Images