Physical unclonable function generation circuit

Abstract

The present invention provides a circuit for generating a physically unclonable function, which includes two NOR gates or two NAND gates; wherein, the output terminal of any one NOR gate / NAND gate is connected to one of the input terminals of the other NOR gate / NAND gate; and, the other input terminals of the two NOR gates / NAND gates are respectively set as an asynchronous reset 0 terminal and an asynchronous set 1 terminal. Using the above invention, a stable and high-quality physically unclonable function can be generated.

Description

Technical Field

[0001] The present invention relates to the field of circuit technologies, and more specifically, to a circuit for generating a physical unclonable function. Background Art

[0002] At present, as a relatively new electronic technology, a physical unclonable function (PUF) is mainly used to generate a unique identification code bound to a circuit, and thereby establish a security trust root for a circuit system.

[0003] Existing PUFs are function modules that utilize uncontrollable tiny process errors during the manufacturing process of a circuit to generate uniqueness. For example, the thickness of metal wires, the difference in ion doping concentration, etc. Since the errors are very small and within the process tolerance range, these errors do not affect the functions of the device itself, but constitute uniqueness that is unpredictable and cannot be replicated. This makes the same PUF design completely different in different devices, on different chips, or even on different dies, similar to human fingerprints, and thus can be used as the unique identifier of a chip.

[0004] However, existing PUFs are usually volatile, that is, after the chip is powered on, the circuit structure for generating the PUF generates an electrical signal, which will disappear after the chip is powered off; in addition, certain thermal noise, electromagnetic noise, etc. often accompany each generation process of the PUF, which will also lead to a certain error rate in the finally obtained PUF value. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a circuit for generating a physical unclonable function to solve the problems of easy loss and high error rate existing in existing circuits.

[0006] The circuit for generating a physical unclonable function provided by the present invention includes two NOR gates or two NAND gates; wherein, the output terminal of any one NOR gate / NAND gate is connected to one of the input terminals of the other NOR gate / NAND gate; and, the other input terminals of the two NOR gates / NAND gates are respectively set as an asynchronous reset terminal and an asynchronous set terminal.

[0007] In addition, an optional technical solution is that when including two NOR gates, the two NOR gates include a first NOR gate and a second NOR gate; wherein, the output terminal of the first NOR gate is connected to the first input terminal of the second NOR gate; the output terminal of the second NOR gate is connected to the second input terminal of the first NOR gate; the first input terminal of the first NOR gate is connected to the second input terminal of the second NOR gate.

[0008] In addition, an alternative technical solution is that it further includes a first ReRAM unit and a second ReRAM unit; wherein, the first ReRAM unit and the second ReRAM unit are symmetrically distributed in the physical unclonable function generation circuit.

[0009] In addition, an alternative technical solution is that the first ReRAM unit and the second ReRAM unit each include two resistance states, namely a low resistance state and a high resistance state.

[0010] In addition, an alternative technical solution is that the resistance states of the first ReRAM unit and the second ReRAM unit are the same.

[0011] In addition, an alternative technical solution is that a physical unclonable function is obtained based on the output terminals of the first NOR gate and the second NOR gate.

[0012] In addition, an alternative technical solution is that when two NOR gates are included, the two NAND gates include a first NAND gate and a second NAND gate; wherein, the output terminal of the first NAND gate is connected to the first input terminal of the second NAND gate; the output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate; the first input terminal of the first NAND gate is connected to the second input terminal of the second NAND gate.

[0013] In addition, an alternative technical solution is that two NOR gates or two NAND gates form an RS latch.

[0014] By using the above physical unclonable function generation circuit, by setting two NOR gates or two NAND gates, and making the output terminal of any one NOR gate / NAND gate connected to one of the input terminals of the other NOR gate / NAND gate, and in addition, the other input terminals of the two NOR gates / NAND gates are respectively set as an asynchronous reset terminal and an asynchronous set terminal, the asymmetry of this circuit structure is higher, and the stability of the output physical unclonable function is higher.

[0015] To achieve the above and related purposes, one or more aspects of the present invention include features that will be described in detail later. The following description and the accompanying drawings illustrate certain exemplary aspects of the present invention in detail. However, these aspects only indicate some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easier to understand. In the drawings:

[0017] Figure 1 is the structure of the physical unclonable function generation circuit according to an embodiment of the present invention Figure 1 ;

[0018] Figure 2 The structure of a physical unclonable function generation circuit according to an embodiment of the present invention Figure 2 ;

[0019] Figure 3 The structure of a physical unclonable function generation circuit according to an embodiment of the present invention Figure 3 。

[0020] The reference numerals therein include: a first NOR gate 1, a first input terminal 11, a second input terminal 12, an output terminal 13, a first ReRAM cell 14, a second NOR gate 2, a first input terminal 21, a second input terminal 22, an output terminal 23, and a second ReRAM cell 24.

[0021] In all the drawings, the same reference numerals indicate similar or corresponding features or functions. Detailed implementation manners

[0022] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is obvious that these embodiments can also be implemented without these specific details. In other examples, well-known structures and devices are shown in block diagram form for the convenience of describing one or more embodiments.

[0023] To solve the problems existing in the generation of the existing physical unclonable function, such as easy loss, high error rate, and instability, the present invention provides a physical unclonable function generation circuit, including two NOR gates or two NAND gates; wherein, the output terminal of any one NOR gate / NAND gate is connected to one of the input terminals of the other NOR gate / NAND gate; and, the other input terminals of the two NOR gates / NAND gates are respectively set as an asynchronous reset terminal and an asynchronous set terminal, which can increase the asymmetry of the circuit, make the extracted PUF value more stable, and reduce the space required for the error correction code.

[0024] To elaborate in detail on the structure of the physical unclonable function generation circuit, the specific embodiments of the present invention will be described in detail below with reference to the drawings.

[0025] Figure 1 The schematic structure of a physical unclonable function generation circuit according to the first embodiment of the present invention is shown.

[0026] As Figure 1As shown in the figure, the generating circuit of the physical unclonable function according to the first embodiment of the present invention includes two NOR gates, and the two NOR gates include a first NOR gate 1 and a second NOR gate; wherein, the output terminal 13 of the first NOR gate 1 is connected to the first input terminal 21 of the second NOR gate; the output terminal 23 of the second NOR gate is connected to the second input terminal 12 of the first NOR gate 1; the first input terminal 11 of the first NOR gate 1 and the second input terminal 22 of the second NOR gate are independent of each other. The first input terminal 11 of the first NOR gate 1, i.e., the R terminal, can be set as an asynchronous set-1 terminal, and the second input terminal 22 of the second NOR gate, i.e., the S terminal, can be set as an asynchronous set-0 terminal.

[0027] Among them, for different assignments of R and S, the corresponding list of the output Q is as follows:

[0028] R S Q 0 0 Q 0 1 0 1 0 1 1 1 0

[0029] It can be seen that the first NOR gate 1 and the second NOR gate 2 together form an RS latch. Assuming that all components in the RS latch are ideal components, when both the R terminal and the S terminal input are 0 and just powered on, the state of the output terminal 13, i.e., the Q terminal, cannot be determined. During the application process, due to certain errors between the first NOR gate 1, the second NOR gate 2 and the wires, the overall structure is not strictly symmetric. Therefore, when both the R terminal and the S terminal input are 0 and just powered on, the output will be more biased towards 0 or 1. And this kind of error has actually little influence on the circuit, and under the influence of noise, this gap will be covered by the noise. Therefore, the output of the Q terminal sometimes appears 0 and sometimes appears 1 after each power-on.

[0030] In a specific embodiment of the present invention, in order to improve the stability of the output result, the first ReRAM unit and the second ReRAM unit are symmetrically distributed in the generating circuit of the physical unclonable function. For example, a first ReRAM unit can be connected between the output terminal 13 of the first NOR gate 1 and the first input terminal 21 of the second NOR gate; at the same time, a second ReRAM unit is connected between the output terminal 23 of the second NOR gate and the second input terminal 12 of the first NOR gate 1.

[0031] Specifically, Figure 2 The schematic structure of the generating circuit of the physical unclonable function according to the second embodiment of the present invention is shown.

[0032] As Figure 2As shown, in this embodiment, a ReRAM cell can be connected between the second input terminal 12 of the first NOR gate 1 and the first input terminal 21 of the second NOR gate in the RS latch. The first input terminal 11 of the first NOR gate 1 and the second input terminal 22 of the second NOR gate are connected to each other, that is, the same input signal is connected. The storage function can be realized through the ReRAM cell, and the auxiliary data required for the error correction code can be stored, reducing the storage space required for the error correction code.

[0033] Specifically, the first ReRAM cell 14 and the second ReRAM cell 24 can each include two resistance states, a low resistance state and a high resistance state. In this embodiment, the resistance states of the first ReRAM cell and the second ReRAM cell are the same. If both the first ReRAM cell 14 and the second ReRAM cell 24 are in the low resistance state, when a high level is input at the input terminal input, the entire circuit conducts. In addition, when the first ReRAM cell 14 and the second ReRAM cell 24 are in the low resistance state, the resistance values of the first ReRAM cell 14 and the second ReRAM cell 24 range from 1.5 KΩ to 5 KΩ. The introduction of this resistance value can increase the asymmetry of the circuit structure, so the influence of circuit noise on the output is greatly weakened, making the output physical unclonable function more stable.

[0034] Figure 3 The schematic structure of a physical unclonable function generation circuit according to another embodiment of the present invention is shown.

[0035] As Figure 3 shown, in this embodiment, each time a clock is input at the input terminal for one cycle, a random number can be generated at the corresponding output terminal.

[0036] It should be noted that when the physical unclonable function generation circuit includes two NOR gates, the two NAND gates include a first NAND gate and a second NAND gate; among them, the output terminal of the first NAND gate is connected to the first input terminal of the second NAND gate; the output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate; the first input terminal of the first NAND gate is connected to the second input terminal of the second NAND gate.

[0037] It can be seen that the circuit and principle using NOR gates are similar to those using NAND gates, and will not be elaborated here one by one.

[0038] In addition, during the generation process of the physically unclonable function, the PUF is first "enrolled". The original response r of the PUF is processed through an error correction code (ECC) to obtain the PUF value k and helper data. Furthermore, during subsequent normal use, since there will be a certain error between the original response r' and r of the PUF, helper data is required to assist in the restoration to obtain the same PUF value k. It can be seen that since helper data is required each time, it can be stored in the ReRAM cell.

[0039] According to the generation circuit of the physically unclonable function of the present invention described above, the asymmetry of the RS latch can be increased, making the extracted PUF value more stable and reducing the space required for the error correction code. In addition, the ReRAM cell itself can be used as a non-volatile memory and can be used to store the helper data required for the error correction code. Integrating the ReRAM PUF and the ReRAM memory together can provide a complete PUF generation circuit that does not require additional storage cells on the basis of increasing a small amount of circuit cost.

[0040] The generation circuit of the physically unclonable function according to the present invention has been described by way of example with reference to the accompanying drawings above. However, those skilled in the art should understand that various improvements can be made to the generation circuit of the physically unclonable function proposed above without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the appended claims.

Claims

1. A generating circuit for a physically unclonable function, characterized in that, it includes: Two NOR gates or two NAND gates; wherein, The output terminal of any one NOR gate / NAND gate is connected to one input terminal of the other NOR gate / NAND gate; and, The other input terminals of the two NOR gates / NAND gates are respectively set as an asynchronous reset 0 terminal and an asynchronous set 1 terminal; It further includes a first ReRAM cell and a second ReRAM cell, and the first ReRAM cell is connected between the output terminal of one NOR gate / NAND gate and the first input terminal of the other NOR gate / NAND gate; The second ReRAM cell is connected between the output terminal of the other NOR gate / NAND gate and the second input terminal of one NOR gate / NAND gate.

2. The generating circuit for a physically unclonable function according to claim 1, characterized in that, When including two NOR gates, the two NOR gates include a first NOR gate and a second NOR gate; wherein, The output terminal of the first NOR gate is connected to the first input terminal of the second NOR gate; The output terminal of the second NOR gate is connected to the second input terminal of the first NOR gate; The first input terminal of the first NOR gate is connected to the second input terminal of the second NOR gate.

3. The generating circuit for a physically unclonable function according to claim 2, characterized in that, The first ReRAM cell and the second ReRAM cell are symmetrically distributed in the generating circuit for a physically unclonable function.

4. The generating circuit for a physically unclonable function according to claim 3, characterized in that, The first ReRAM cell and the second ReRAM cell respectively include two resistance states: a low resistance state and a high resistance state.

5. The generating circuit for a physically unclonable function according to claim 3, characterized in that, The resistance states of the first ReRAM cell and the second ReRAM cell are the same.

6. The generating circuit for a physically unclonable function according to claim 2, characterized in that, The physically unclonable function is obtained based on the output terminal of the first NOR gate and the output terminal of the second NOR gate.

7. The generating circuit for a physically unclonable function according to claim 1, characterized in that, When including two NAND gates, the two NAND gates include a first NAND gate and a second NAND gate; wherein, The output terminal of the first NAND gate is connected to the first input terminal of the second NAND gate; The output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate; The first input terminal of the first NAND gate is connected to the second input terminal of the second NAND gate.

8. The generating circuit for a physically unclonable function according to claim 1, characterized in that, The two NOR gates or the two NAND gates form an RS latch.

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