Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, and relates to the field of semiconductors, and solves the problem of serious leakage. The semiconductor structure comprises a substrate, a plurality of word line trenches, and source / drain regions adjacent to the word line trenches; a gate word line in the word line trench; the gate word line comprises a first conductive layer, a single conduction layer, and a second conductive layer which are sequentially stacked, the first conductive layer is located at the bottom of the word line trench, the projection of the gate word line on the sidewall of the word line trench and the projection of the source / drain region on the sidewall of the word line trench have a preset height of overlapping area, and when the voltage applied to the gate word line is less than a preset voltage, the resistance of the single conduction layer is greater than a preset resistance, so that the first conductive layer and the second conductive layer are not conductive. The semiconductor structure provided by the application is used for increasing the driving current and improving the leakage phenomenon.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] A dynamic random access memory (DRAM) is composed of a plurality of repeated memory cells, each of which usually includes a capacitor structure and a transistor, a gate of the transistor is formed by a word line, a drain is connected with a bit line, and a source is connected with the capacitor structure; a voltage signal on the word line can control the opening or closing of the transistor, and then data information stored in the capacitor structure is read through the bit line, or the data information is written into the capacitor structure through the bit line for storage.

[0003] In the related art, the gate of the transistor is formed by the word line and is buried in a word line trench in a substrate, the substrate includes a P-type substrate and an N-type doped region located at a surface layer of the P-type substrate, a portion of the P-type substrate close to the word line trench serves as a channel region of the transistor, and the N-type doped regions on both sides of the word line trench serve as a source region and a drain region of the transistor; a projection part of the gate word line and the source / drain region on a sidewall of the word line trench will form an overlapping region, when the gate word line of the transistor is in a conductive state, electrons will be attracted in the overlapping region, the larger the overlapping region is, the smaller the on-resistance of the source / drain region and the channel region is, and the larger the driving current of the transistor is.

[0004] However, when the gate word line of the transistor is in a closed state, a strong electric field will be formed in the overlapping region to attract a tunneling current, the larger the overlapping region is, the more serious the gate-induced drain leakage (GIDL) phenomenon is. SUMMARY

[0005] In view of the above problems, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which can increase the driving current of the transistor while improving the GIDL leakage phenomenon, thereby improving the reliability of the semiconductor structure.

[0006] To achieve the above object, the embodiments of the present application provide the following technical solutions:

[0007] The first aspect of the embodiment of the present application provides a semiconductor structure, comprising: a substrate having a plurality of word line trenches and source / drain regions adjacent to each word line trench; a gate word line in the word line trench; the gate word line comprises a first conductive layer, a single conduction layer and a second conductive layer which are sequentially stacked, the first conductive layer is located at the bottom of the word line trench, the projection of the gate word line on the sidewall of the word line trench and the projection of the source / drain region on the sidewall of the word line trench have a preset height of overlapping area, when the voltage applied to the gate word line is less than a preset voltage, the resistance of the single conduction layer is greater than a preset resistance, so that the first conductive layer and the second conductive layer are not conductive.

[0008] The semiconductor structure as described above, at least part of the projection of the second conductive layer on the sidewall of the word line trench is located in the projection of the source / drain region on the sidewall of the word line trench.

[0009] The semiconductor structure as described above, the top of the first conductive layer is lower than the bottom of the source / drain region.

[0010] The semiconductor structure as described above, the top of the second conductive layer is flush with the top of the source / drain region.

[0011] The semiconductor structure as described above, the projection of the source / drain region on the sidewall of the word line trench covers the projection of the second conductive layer on the sidewall of the word line trench.

[0012] The semiconductor structure as described above, the preset resistance is a critical resistance for the first conductive layer and the second conductive layer to be conductive.

[0013] The semiconductor structure as described above, the single conduction layer comprises a first resistance and a second resistance, the first resistance is greater than the second resistance, when the single conduction layer is in a conductive state, the resistance of the single conduction layer is the second resistance; when the single conduction layer is in an off state, the resistance of the single conduction layer is the first resistance.

[0014] The semiconductor structure as described above, the conduction current of the single conduction layer is greater than or equal to A, the conduction voltage is greater than or equal to 1.2V.

[0015] The semiconductor structure as described above, the single conduction layer is an OTS gating material layer.

[0016] The semiconductor structure as described above, the single conduction layer is a silicon telluride (SiTe) layer.

[0017] The semiconductor structure as described above, the thickness of the single conduction layer is 5nm-25nm.

[0018] The semiconductor structure as described above, wherein the single-conduction layer has a thickness of 15 nm.

[0019] The semiconductor structure as described above, wherein the first conductive layer and / or the second conductive layer is a conductive metal layer.

[0020] The semiconductor structure as described above, wherein the first conductive layer and / or the second conductive layer is a tungsten (W) layer.

[0021] The semiconductor structure provided by the embodiment of the present application has at least the following advantages:

[0022] The semiconductor structure provided by the embodiment of the present application, the gate word line comprises a first conductive layer, a single-conduction layer and a second conductive layer which are sequentially stacked, wherein the first conductive layer is located at the bottom of the word line trench, when the single-conduction layer is in a conduction state, the first conductive layer and the second conductive layer are conducted through the single-conduction layer, the overlapping area of the source / drain region and the gate word line can attract the electrons of the doped region in the substrate, thereby reducing the resistance of the overlapping area of the source / drain region and the gate word line, and increasing the drive current of the transistor; when the single-conduction layer is in a cut-off state, the first conductive layer and the second conductive layer are not conducted, so that the voltage of the second conductive layer is 0v, and the second conductive layer can significantly reduce the electric field intensity of the overlapping area, thereby improving the phenomenon of electron tunneling between the gate word line and the source / drain region to form a current, and improving the GIDL leakage phenomenon.

[0023] The second aspect of the embodiment of the present application further provides a manufacturing method of a semiconductor structure, comprising: providing a substrate, forming a plurality of word line trenches and source / drain regions adjacent to each word line trench on the substrate; forming a first conductive layer in the word line trench; forming a single-conduction layer on the first conductive layer; forming a second conductive layer on the single-conduction layer, the first conductive layer, the single-conduction layer and the second conductive layer form a gate word line, and the projection of the gate word line on the sidewall of the word line trench and the projection of the source / drain region on the sidewall of the word line trench have a preset height of overlapping area.

[0024] In addition to the technical problems solved by the above-described embodiments of the present application, the technical features constituting the technical solutions and the beneficial effects brought by these technical features, the other technical problems solved by the semiconductor structure and the manufacturing method thereof provided by the embodiments of the present application, the other technical features contained in the technical solutions and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0026] Figure 1 A structural schematic diagram of a semiconductor structure in the related art;

[0027] Figure 2 A schematic diagram of the relationship between the driving current and the GIDL leakage after increasing the height of the overlapping area of the gate word line and the source / drain region in the semiconductor structure;

[0028] Figure 3 A structural schematic diagram of a semiconductor structure provided by the embodiment of the present application;

[0029] Figure 4 A schematic diagram of a use state of the semiconductor structure provided by the embodiment of the present application;

[0030] Figure 5 A schematic diagram of a use state of the gate word line in the embodiment of the present application; Figure 3 A schematic diagram of another use state of the gate word line in the embodiment of the present application;

[0031] Figure 6 A schematic diagram of another use state of the gate word line in the embodiment of the present application; Figure 3 A schematic diagram of another use state of the gate word line in the embodiment of the present application;

[0032] Figure 7 A schematic diagram of the relationship between the voltage value and the resistance value of the single-conduction layer in the on and off states provided by the embodiment of the present application;

[0033] Figure 8 A flow schematic diagram of the manufacturing method of the semiconductor structure provided by the embodiment of the present application.

[0034] Reference signs:

[0035] 100 - substrate;

[0036] 101 - word line trench;

[0037] 102 - source / drain region;

[0038] 200 - gate word line;

[0039] 201 - first conductive layer;

[0040] 202 - single-conduction layer;

[0041] 203 - second conductive layer. DETAILED DESCRIPTION

[0042] As described in the background, the prior art dynamic random memory has a serious problem of GIDL leakage. The inventors have found that the cause of this problem is that, as shown in Figure 1 Figure 1, reducing the distance (denoted by H in the embodiments of the present application) from the top of the gate word line 200 to the upper surface of the substrate 100, and increasing the overlapping area (denoted by A in the embodiments of the present application) of the projections of the gate word line 200 and the source / drain region 102 on the sidewalls of the word line trench 101, when the gate word line 200 is turned on, the overlapping area A will attract the electrons of the doped region of the substrate 100 to reduce the resistance of the overlapping area A of the source / drain region 102 and the gate word line 200, thereby increasing the drive current of the transistor.

[0043] However, when the gate word line is in the off state, the working voltage is applied on the source / drain, and the electrons near the overlapping area A will form a current due to the electron tunneling between the gate and the source / drain because of the strong electric field, i.e. GIDL leakage, and the larger the size of the overlapping area A, the more serious the GIDL leakage phenomenon, thereby causing the problem of low reliability of the semiconductor structure. As shown in Figure 2 Figure 2, as the size of the overlapping area A increases, the drive current increases, and the GIDL leakage phenomenon becomes more and more serious.

[0044] To solve the above problems, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, the gate word line comprises a first conductive layer, a single-conduction layer and a second conductive layer which are sequentially stacked, wherein the first conductive layer is located at the bottom of the word line trench, when the single-conduction layer is in the on state, the first conductive layer and the second conductive layer are conducted through the single-conduction layer, the overlapping area A of the source / drain region and the gate word line will attract the electrons of the doped region of the substrate to reduce the resistance of the overlapping area A of the source / drain region and the gate word line, thereby increasing the drive current of the transistor; and when the single-conduction layer is in the off state, the first conductive layer and the second conductive layer are not conducted, so that the voltage of the second conductive layer is 0v, and the second conductive layer can significantly reduce the electric field intensity of the overlapping area A, thereby improving the phenomenon of electron tunneling between the gate word line and the source / drain to form a current, and improving the GIDL leakage phenomenon.

[0045] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more apparent and understandable, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0046] Figure 3This is a schematic diagram of the semiconductor structure provided in an embodiment of the present invention; Figure 4 A schematic diagram of a semiconductor structure in use provided in an embodiment of the present invention; Figure 5 for Figure 3 A schematic diagram of one usage state of the middle gate word line; Figure 6 for Figure 3 A schematic diagram of another usage state of the middle gate word line.

[0047] like Figures 3 to 6 As shown, the semiconductor structure provided in this embodiment of the invention includes: a substrate 100 and a gate word line 200.

[0048] The substrate 100 has a plurality of word line trenches 101 and source / drain regions 102 adjacent to each word line trench 101.

[0049] The substrate 100 can be a crystalline semiconductor material, such as a silicon (Si) substrate 100. The substrate 100 can also be a germanium (Ge) substrate 100, silicon on insulator (SOI), silicon germanide (SiGe) substrate 100, silicon carbide (SiC) or gallium nitride (GaN) substrate 100, etc. The embodiments of the present invention do not impose specific limitations on this.

[0050] The substrate 100 includes a core region and a peripheral region located around the core region. The core region includes multiple active regions and a shallow trench isolation region that isolates the multiple active regions. The multiple active regions can be arranged in an array.

[0051] A capacitor is subsequently formed above the core region of the substrate 100, and a peripheral circuit, such as a transistor, is subsequently formed above the peripheral region of the substrate 100.

[0052] Each active region has a word line trench 101 formed therein, and a semiconductor layer may be disposed in the substrate 100. For example, the substrate 100 includes a P-type substrate 100 and an N-type doped region located on the surface of the P-type substrate 100. The portion of the P-type substrate 100 near the word line trench serves as the channel region of the transistor, and the N-type doped regions on both sides of the word line trench serve as the source region and drain region of the transistor.

[0053] The gate word line 200 is located in the word line trench 101. The gate word line 200 includes a first conductive layer 201, a single conductive layer 202, and a second conductive layer 203 stacked sequentially. The first conductive layer 201 is located at the bottom of the word line trench 101. The projection of the gate word line 200 on the sidewall of the word line trench 101 and the projection of the source / drain region 102 on the sidewall of the word line trench 101 have a preset height of overlap region A. When the voltage applied to the gate word line 200 is less than the preset voltage, the resistance of the single conductive layer is greater than the preset resistance, so that the first conductive layer 201 and the second conductive layer 203 are not conductive.

[0054] It can be understood that, as Figure 3 and Figure 5 shown, when the gate word line 200 applies a voltage greater than the preset voltage, the resistance of the single conduction layer 202 is less than the preset resistance, the first conductive layer 201 and the second conductive layer 203 are turned on through the single conduction layer 202, at this time, Figure 5 the gate word line 200 in the a figure in the Figure 5 is equivalent to the b figure in the, the height of the projection overlap area A of the gate word line 200 and the source / drain region 102 on the word line trench sidewall is increased, thereby increasing the driving current; when the gate word line 200 applies a voltage less than the preset voltage, the resistance of the single conduction layer 202 is greater than the preset resistance, as Figure 4 and Figure 6 shown, the single conduction layer 202 is in the off state, the single conduction layer 202 is used to block the first conductive layer 201 and the second conductive layer 203, so that the first conductive layer 201 and the second conductive layer 203 are not turned on, at this time, Figure 6 the gate word line 200 in the c figure in the Figure 6 is equivalent to the d figure in the, in this way, the second conductive layer 203 can shield the electric field of the first conductive layer 201, thereby reducing the electric field intensity of the projection overlap area A of the gate word line 200 and the source / drain region 102 on the word line trench sidewall, and further improving the GIDL leakage phenomenon.

[0055] In the present application, when the single conduction layer 202 is in the on state, the first conductive layer 201 and the second conductive layer 203 are turned on through the single conduction layer 202, the overlap area A of the source / drain region 102 and the gate word line 200 can attract the electrons of the base 100 doped region, reduce the resistance of the overlap area A of the source / drain region 102 and the gate word line 200, and thereby increase the driving current of the transistor; when the single conduction layer 202 is in the off state, the first conductive layer 201 and the second conductive layer 203 are not turned on, in this way, the voltage of the second conductive layer 203 is 0v, and the second conductive layer 203 can significantly reduce the electric field intensity of the overlap area A, improve the phenomenon that the electron tunneling occurs between the gate word line 200 and the source / drain to form current, and thereby improve the GIDL leakage phenomenon.

[0056] It should be noted that the height of the projection overlap area A of the gate word line 200 and the source / drain region 102 on the word line trench sidewall is set for the purpose of increasing the driving current of the transistor in the semiconductor structure, and the specific size is not specifically limited in the present embodiment.

[0057] The preset voltage can be 1.2V, when the voltage applied by the gate word line 200 is less than 1.2V, the resistance of the single conduction layer 202 is greater than the preset resistance, so that the first conductive layer 201 and the second conductive layer 203 are not turned on.

[0058] In some optional embodiments, a projection of the at least partial second conductive layer 203 on the sidewall of the word line trench 101 is located within a projection of the source / drain region 102 on the sidewall of the word line trench 101.

[0059] It can be understood that the at least partial second conductive layer 203 refers to the partial second conductive layer 203 or the entire conductive layer, and the overlapping region A of the gate word line 200 and the source / drain region 102 includes the at least partial second conductive layer 203, so that when the single-conduction layer 202 is in the off state, the first conductive layer 201 and the second conductive layer 203 are not conductive, the voltage of the second conductive layer 203 is 0v, the second conductive layer 203 can shield the electric field near the first conductive layer 201, and the phenomenon of forming current due to electron tunneling between the gate word line 200 and the drain is improved, thereby improving the GIDL leakage phenomenon.

[0060] Further, the top of the first conductive layer 201 is lower than the bottom of the source / drain region 102.

[0061] It can be understood that by setting the top of the first conductive layer 201 to be lower than the bottom of the source / drain region 102, the overlapping region A of the gate word line 200 and the source / drain region 102 is the second conductive layer 203 or the second conductive layer 203 and the single-conduction layer 202, when the single-conduction layer 202 is in the off state, the distance of the electrons near the first conductive layer 201 to the source / drain region 102 is far, and the second conductive layer 203 can shield the electric field near the first conductive layer 201, reduce the electric field intensity of the overlapping region A of the gate word line 200 and the source / drain region 102, and avoid electron tunneling between the source / drain region 102 to form current, so as to increase the drive current of the transistor while improving the GIDL leakage phenomenon.

[0062] Further, the top of the second conductive layer 203 is flush with the top of the source / drain region 102.

[0063] By setting the top of the second conductive layer 203 to be flush with the top of the source / drain region 102, the height of the overlapping region A of the gate word line 200 and the source / drain region 102 can be increased, so as to increase the drive current of the transistor, and the overlapping region A mainly includes the second conductive layer 203, so that when the single-conduction layer 202 is in the off state, the distance of the electrons near the first conductive layer 201 to the source / drain region 102 is far, and the second conductive layer 203 can shield the electric field near the first conductive layer 201, reduce the electric field intensity of the overlapping region A of the gate word line 200 and the source / drain region 102, and avoid electron tunneling between the source / drain region 102 to form current, so as to increase the drive current of the transistor while improving the GIDL leakage phenomenon.

[0064] In some alternative embodiments, the projection of the source / drain region 102 on the sidewall of the word line trench 101 covers the projection of the second conductive layer 203 on the sidewall of the word line trench 101, so that the GIDL leakage phenomenon can be improved while increasing the drive current of the transistor.

[0065] On the basis of the above-mentioned embodiments, when the voltage applied to the gate word line 200 is less than a preset voltage, the resistance of the single-conduction layer 202 is greater than a preset resistance, so that the first conductive layer 201 and the second conductive layer 203 are not conductive, wherein the preset resistance is a critical resistance at which the first conductive layer 201 and the second conductive layer 203 are conductive.

[0066] In the embodiments of the present application, the single-conduction layer 202 includes a first resistance and a second resistance, and the resistance value of the single-conduction layer 202 can change between the first resistance and the second resistance at different voltages, wherein the first resistance is greater than the second resistance, the resistance of the single-conduction layer 202 is the second resistance when the single-conduction layer 202 is in a conductive state, and the resistance of the single-conduction layer 202 is the first resistance when the single-conduction layer 202 is in a cut-off state.

[0067] It can be understood that, when the voltage applied to the gate word line 200 is less than a preset voltage, the first resistance is a high-resistance state resistance, and the resistance value is greater than the conductive resistance of the first conductive layer 201 and the second conductive layer 203, so that the first conductive layer 201 and the second conductive layer 203 are blocked by the single-conduction layer 202, at this time, the voltage of the second conductive layer 203 is 0v, so that the second conductive layer 203 can be used to shield the electric field of the gate word line 200, thereby reducing the electric field between the gate word line 200 and the source / drain region 102, and further improving the GIDL leakage; and when the voltage applied to the gate word line 200 is greater than the preset voltage, the second resistance is a low-resistance state resistance, and the resistance value is less than the conductive resistance of the first conductive layer 201 and the second conductive layer 203, so that the first conductive layer 201 and the second conductive layer 203 are conductive through the single-conduction layer 202, so as to increase the height of the overlapping region A between the gate word line 200 and the source / drain region 102, thereby increasing the drive current of the transistor.

[0068] For example, when the voltage applied to the first conductive layer 201 is 3V, the single conductive layer 202 is in a low-resistance state and is turned on. At this time, the gate word line 200 includes the first conductive layer 201, the single conductive layer 202, and the second conductive layer 203. The first conductive layer 201 and the second conductive layer 203 are connected through the single conductive layer 202 to increase the height of the overlap region A between the gate word line 200 and the source / drain region 102, thereby increasing the driving current. When the voltage applied to the first conductive layer 201 is -0.2V, the single conductive layer 202 is in a high-resistance state and is blocked. At this time, the gate word line 200 includes the first conductive layer 201, which reduces the height of the overlap region A between the gate word line 200 and the source / drain region 102. The second conductive layer 203 can also be used to shield the electric field of the gate word line 200, thereby reducing the electric field strength of the overlap region A between the gate word line 200 and the source / drain region 102, and thus improving the GIDL leakage phenomenon.

[0069] Figure 7 This is a schematic diagram showing the relationship between the voltage and resistance values ​​of a single conductive layer in the on and off states, as provided in an embodiment of the present invention.

[0070] Furthermore, by Figure 7 It can be seen that the conduction current of the single conductive layer 202 is greater than or equal to A. The conduction voltage is greater than or equal to 1.2V, so that the first conductive layer 201 and the second conductive layer 203 can be conducted through the single conductive layer 202; and when the voltage of the single conductive layer 202 is greater than the preset voltage, the current increases significantly. Therefore, in order to meet the working reliability of the single conductive layer 202, the single conductive layer 202 can be made of a material whose resistance exhibits two states, high and low, as the voltage changes.

[0071] Among them, the single conductive layer 202 is a bidirectional threshold switching (OTS) gating material layer.

[0072] For example, the single conductive layer 202 can be a silicon telluride (SiTe) layer, and the first conductive layer 201 and the second conductive layer 203 can be conductive metal layers, for example, the first conductive layer 201 and the second conductive layer 203 can be tungsten (W) metal layers.

[0073] Furthermore, the thickness of the single conductive layer 202 can be from 5nm to 25nm, and the resistance value is different depending on the thickness of the single conductive layer 202.

[0074] For example, when the single conductive layer 202 is a 15nm SiTe layer, and the first conductive layer 201 and the second conductive layer 203 are tungsten metal layers, the resistance value of the single conductive layer 202 in the off state can be 6 times the resistance value in the on state. Figure 7 As shown, the current value is from A is changed to A.

[0075] The semiconductor structure provided by the embodiment of the present application, the gate word line comprises a first conductive layer, a single conduction layer and a second conductive layer which are sequentially stacked, wherein the first conductive layer is located at the bottom of the word line trench, when the single conduction layer is in the conduction state, the first conductive layer and the second conductive layer are conducted through the single conduction layer, the overlapping area A of the source / drain region and the gate word line can attract the electrons of the base doped region, thereby reducing the resistance of the overlapping area A of the source / drain region and the gate word line, so as to increase the drive current of the transistor; when the single conduction layer is in the cut-off state, the first conductive layer and the second conductive layer are not conducted, so that the voltage of the second conductive layer is 0v, and the second conductive layer can reduce the electric field intensity of the overlapping area A, thereby improving the phenomenon that the current is formed by the electron tunneling between the gate word line and the source / drain region, so as to improve the GIDL leakage phenomenon.

[0076] Figure 8 The flowchart of the manufacturing method of the semiconductor structure provided by the embodiment of the present application is shown.

[0077] As Figure 8 shown, the embodiment of the present application further provides a manufacturing method of a semiconductor structure, and the steps of the method comprise:

[0078] Step S101: providing a substrate, and forming a plurality of word line trenches and source / drain regions adjacent to the word line trenches on the substrate.

[0079] Step S102: forming a first conductive layer in the word line trench.

[0080] Step S103: forming a single conduction layer on the first conductive layer.

[0081] Step S104: forming a second conductive layer on the single conduction layer, wherein the first conductive layer, the single conduction layer and the second conductive layer form a gate word line, and the projection of the gate word line on the sidewall of the word line trench and the projection of the source / drain region on the sidewall of the word line trench have a preset height of overlapping area.

[0082] When the voltage applied by the gate word line is less than a preset voltage, the resistance of the single conduction layer is greater than a preset resistance, the single conduction layer is in the cut-off state, and the single conduction layer is used to block the first conductive layer and the second conductive layer, so that the first conductive layer and the second conductive layer are not conducted; when the voltage applied by the single conduction layer is greater than the preset voltage, the resistance of the single conduction layer is less than the preset resistance, the single conduction layer is in the conduction state, and the single conduction layer is used to conduct the first conductive layer and the second conductive layer.

[0083] The method for manufacturing the semiconductor structure comprises the following steps: providing a substrate, forming a plurality of word line grooves and source / drain regions adjacent to each word line groove on the substrate, forming a first conductive layer in the word line groove, forming a single conduction layer on the first conductive layer, and forming a second conductive layer on the single conduction layer, wherein the first conductive layer is located at the bottom of the word line groove, the first conductive layer and the second conductive layer are conducted through the single conduction layer when the single conduction layer is in a conduction state, the overlapping area of the source / drain region and the gate word line can attract the electrons of the substrate doped region, thereby reducing the resistance of the overlapping area of the source / drain region and the gate word line, and increasing the drive current of the transistor; and when the single conduction layer is in a cut-off state, the first conductive layer and the second conductive layer are not conducted, so that the voltage of the second conductive layer is 0v, the second conductive layer reduces the electric field intensity of the overlapping area, and improves the phenomenon that the current is formed by the electron tunneling between the gate word line and the source / drain region, thereby improving the GIDL leakage phenomenon.

[0084] In the description of the present specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be referred to each other.

[0085] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0086] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor memory device, comprising: a substrate having a plurality of word line trenches and source / drain regions adjacent to each of the word line trenches; a gate word line in the word line trench; the gate word line comprises a first conductive layer, a single conduction layer and a second conductive layer which are sequentially stacked, the first conductive layer is located at the bottom of the word line trench, and the projection of the gate word line on the sidewall of the word line trench and the projection of the source / drain region on the sidewall of the word line trench have an overlapping area in the direction parallel to the substrate; the single conduction layer is an OTS gating material layer; the first conductive layer and / or the second conductive layer is a conductive metal layer.

2. The semiconductor structure of claim 1, wherein, At least part of the projection of the second conductive layer on the sidewall of the word line trench is located in the projection of the source / drain region on the sidewall of the word line trench.

3. The semiconductor structure of claim 2, wherein, The top of the first conductive layer is lower than the bottom of the source / drain region.

4. The semiconductor structure according to claim 2 or 3, characterized in that The top of the second conductive layer is flush with the top of the source / drain region.

5. The semiconductor structure of claim 2, wherein, The projection of the source / drain region on the sidewall of the word line trench covers the projection of the second conductive layer on the sidewall of the word line trench.

6. The semiconductor structure of any one of claims 1-3, wherein, The single conduction layer comprises a first resistance and a second resistance, the first resistance is greater than the second resistance, when the single conduction layer is in a conduction state, the resistance of the single conduction layer is the second resistance; when the single conduction layer is in an off state, the resistance of the single conduction layer is the first resistance.

7. The semiconductor structure of claim 1, wherein, The single conduction layer is a silicon telluride (SiTe) layer.

8. The semiconductor structure of claim 6, wherein, The thickness of the single conduction layer is 5nm-25nm.

9. The semiconductor structure of claim 8, wherein, The thickness of the single conduction layer is 15nm.

10. The semiconductor structure of claim 1, wherein, The first conductive layer and / or the second conductive layer is a tungsten (W) layer.

11. A method of fabricating a semiconductor structure, comprising: The application relates to a semiconductor memory device, comprising: a substrate having a plurality of word line trenches and source / drain regions adjacent to each of the word line trenches; a first conductive layer is formed in the word line trench; a single conduction layer is formed on the first conductive layer; a second conductive layer is formed on the single conduction layer; wherein the first conductive layer, the single conduction layer and the second conductive layer form a gate word line, the projection of the gate word line on the sidewall of the word line trench and the projection of the source / drain region on the sidewall of the word line trench have an overlapping area in the direction parallel to the substrate; the single conduction layer is an OTS gating material layer; the first conductive layer and / or the second conductive layer is a conductive metal layer.

Images