Multi-port storage device, read / write method and device

Abstract

This invention discloses a multi-port storage device, a read / write method, and an apparatus. The device includes: CEILING(M / 2)*(N+1)-1 pseudo-dual-port dual-read memories, a write operation control unit, a read operation control unit, and a storage mapping table; where M is the number of read ports; N is the number of write ports; the pseudo-dual-port dual-read memories have a first port and a second port; the first port is a read port; the second port is either a read port or a write port; the pseudo-dual-port dual-read memories are used to perform at least one of read operations, write operations, and read-write operations; CEILING represents rounding up; the storage mapping table is used to indicate the pseudo-dual-port dual-read memories where valid data for each address is stored; the write operation control unit is used to control and manage write operations on the pseudo-dual-port dual-read memories; and the read operation control unit is used to control and manage read operations on the pseudo-dual-port dual-read memories.

Description

Technical Field

[0001] This invention relates to chip design technology, and more particularly to a multi-port storage device, a read / write method, and an apparatus. Background Technology

[0002] In ASIC (Application Specific Integrated Circuit) design, memory is frequently used, such as SRAM (Static Random Access Memory) and eDRAM (Enhanced Dynamic Random Access Memory). For some specialized chips, such as those used in network switching, the total area of ​​the memory can reach or even exceed half the total chip area. This demonstrates the significant impact of memory design quality on the overall chip area. Based on the access ports, memory can be categorized into single-port memory, pseudo-dual-port / dual-port memory, and multi-port memory. For multi-port memory, when its capacity is small, it can be directly implemented using register units. However, when the capacity is large, using registers leads to a series of problems, such as large area and power consumption, a particularly large number of logic units, and severe wiring congestion, ultimately making it difficult to achieve the expected performance or even impossible to implement. For large-capacity multi-port memory, another implementation method is through pseudo-dual-port static memory. Using pseudo-dual-port memory can effectively reduce area, power consumption, and significantly reduce the number of logic units and wiring congestion, thus enabling the multi-port memory design to ultimately meet the expected performance requirements.

[0003] Existing technologies use too many pseudo-dual-port memory cells, resulting in large-area and high-power multi-port memory implementations. Summary of the Invention

[0004] To address the existing technical problems, embodiments of the present invention provide a multi-port storage device, a read / write method, and an apparatus.

[0005] The technical solution of this invention is implemented as follows:

[0006] This invention provides a multi-port storage device, comprising: CEILING(M / 2)*(N+1)-1 pseudo-dual-port dual-read memories, a write operation control unit, a read operation control unit, and a storage mapping table; where M is the number of read ports; N is the number of write ports; and CEILING represents rounding up.

[0007] The pseudo dual-port dual-read memory is used to perform at least one of read operation, write operation, and read-write operation.

[0008] The storage mapping table is used to indicate the pseudo dual-port dual-read memory where the valid data for each address is stored.

[0009] The write operation control unit is used to control and manage the write operations for the pseudo dual-port dual-read memory.

[0010] The read operation control unit is used to control and manage the read operations of the pseudo dual-port dual-read memory.

[0011] In the above scheme, the pseudo dual-port dual-read memory has a first port and a second port; the first port is a read port; the second port is a read port or a write port.

[0012] In the above scheme, the capacity of the storage mapping table is W*(CEILING(LOG2(CEILING(M / 2)*(N+1)-1))) bits;

[0013] Wherein, W is the depth of a single pseudo dual-port dual-read memory.

[0014] This invention provides a read / write method for a multi-port storage device, applicable to any of the multi-port storage devices described above; the method includes:

[0015] Receive target operation;

[0016] The pseudo dual-port dual-read memory for performing the target operation is determined according to the storage mapping table;

[0017] The target operation is performed through the determined pseudo-dual-port dual-read memory, and the memory mapping table is updated.

[0018] In the above scheme, when the target operation is a write operation; determining the pseudo-dual-port dual-read memory to perform the target operation based on the storage mapping table includes:

[0019] Based on the information of the write operation and the storage mapping table, determine the pseudo-dual-port two-read memory that can perform the write operation; based on the pseudo-dual-port two-read memory that can perform the write operation, determine the pseudo-dual-port two-read memory to perform the write operation.

[0020] Updating the storage mapping table includes:

[0021] Write the list of numbers of the pseudo dual-port dual-read memory to be executed the write operation into the memory mapping table.

[0022] In the above scheme, when the target operation is a read operation; determining the pseudo-dual-port dual-read memory to perform the target operation according to the storage mapping table includes:

[0023] The storage mapping table is queried according to the read address corresponding to the read operation to determine the corresponding storage flag information;

[0024] The one or more pseudo-dual-port dual-read memories involved are determined based on the storage flag information.

[0025] In the above scheme, when the target operation is a simultaneous read / write operation; determining the pseudo-dual-port dual-read memory to perform the target operation based on the storage mapping table includes:

[0026] For the read operation of the simultaneous read and write operation, the storage mapping table is queried according to the read address corresponding to the read operation to determine the corresponding storage flag information; the one or more pseudo dual-port dual-read memories involved are determined according to the storage flag information.

[0027] For the write operation of the simultaneous read and write operation, based on the information of the write operation and the storage mapping table, a pseudo dual-port dual-read memory that can perform the write operation is determined; based on the pseudo dual-port dual-read memory that can perform the write operation, a pseudo dual-port dual-read memory for performing the write operation is determined.

[0028] Updating the storage mapping table includes:

[0029] Write the list of numbers of the pseudo dual-port dual-read memory to be executed the write operation into the memory mapping table.

[0030] In the above scheme, the pseudo dual-port dual-read memory that performs the write operation is one or more consecutive pseudo dual-port dual-read memories.

[0031] The step of writing the list of identified pseudo-dual-port dual-read memory numbers for which write operations will be performed into the memory mapping table includes:

[0032] Write the determined starting pseudo-dual-port dual-read memory number of the pseudo-dual-port dual-read memory to be used for the write operation into the memory mapping table.

[0033] The number of the initial pseudo dual-port dual-read memory corresponds to the information of the write operation, which includes at least the number of read ports and the number of write ports.

[0034] In the above scheme, for all read operations, determining the one or more pseudo-dual-port dual-read memories involved based on the storage flag information further includes:

[0035] Identify a pseudo-dual-port dual-read memory that performs two read operations;

[0036] The update of the storage mapping table further includes:

[0037] A pseudo-dual-port dual-read memory that performs two read operations simultaneously is marked as an illegal write operation memory.

[0038] In the above scheme, in response to the situation where there is an illegal write operation on the memory, before determining the pseudo dual-port dual-read memory to perform the target operation according to the memory mapping table, the method further includes:

[0039] Identify existing illegal write-operation memory, and determine a list of writable memory based on the illegal write-operation memory; the list of writable memory includes: other pseudo dual-port dual-read memory other than the illegal write-operation memory.

[0040] Accordingly, determining the pseudo-dual-port dual-read memory for performing the target operation based on the storage mapping table includes:

[0041] For any write operation, allocate several consecutive pseudo-dual-port two-read memories according to the writable memory list.

[0042] This invention also provides a read / write device for a multi-port storage device, wherein the multi-port storage device is any one of the multi-port storage devices described above, and the device includes:

[0043] The receiving module is used to receive the target operation;

[0044] The processing module is used to determine the pseudo dual-port dual-read memory to perform the target operation based on the storage mapping table;

[0045] The target operation is performed through the determined pseudo-dual-port dual-read memory, and the memory mapping table is updated.

[0046] The multi-port storage device, read / write method, and apparatus provided in this invention include: CEILING(M / 2)*(N+1)-1 pseudo-dual-port dual-read memories, a write operation control unit, a read operation control unit, and a storage mapping table; where M is the number of read ports; N is the number of write ports; CEILING represents rounding up; the pseudo-dual-port dual-read memories are used to perform at least one of read operations, write operations, and read-write operations; the storage mapping table indicates the pseudo-dual-port dual-read memories where valid data for each address is stored; the write operation control unit controls and manages write operations on the pseudo-dual-port dual-read memories; and the read operation control unit controls and manages read operations on the pseudo-dual-port dual-read memories. This improves the port utilization of the pseudo-dual-port dual-read memories, thereby further reducing the memory area. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a pseudo-dual-port memory.

[0048] Figure 2 This is a schematic diagram of a pseudo-dual-port memory implementation.

[0049] Figure 3 A schematic diagram of a pseudo dual-port dual-read memory model provided in an embodiment of the present invention;

[0050] Figure 4 This invention provides an architecture diagram of a multi-port memory with an odd number of read ports based on a pseudo-dual-port dual-read memory.

[0051] Figure 5 A flowchart illustrating a read / write method for a multi-port storage device provided in an embodiment of the present invention;

[0052] Figure 6 A flowchart of multi-port storage device read / write operations provided in an embodiment of the present invention;

[0053] Figure 7 A flowchart illustrating read operations only for a multi-port storage device provided in this embodiment of the invention;

[0054] Figure 8 A flowchart illustrating only write operations for a multi-port storage device provided in this embodiment of the invention;

[0055] Figure 9 This is a flowchart of a read operation during simultaneous read / write operations on a multi-port storage device, provided in an embodiment of the present invention.

[0056] Figure 10 This is a flowchart of a write operation during simultaneous read / write operations of a multi-port storage device, provided in an embodiment of the present invention.

[0057] Figure 11 This is a design architecture diagram of a storage device based on a pseudo-dual-port dual-read memory to implement a three-read, three-write storage device, provided in an embodiment of the present invention.

[0058] Figure 12 This is a schematic diagram comparing the area of ​​a pseudo-dual-port dual-read memory and a regular pseudo-dual-port memory that implement a multi-port storage device with an odd number of read ports, as provided in an embodiment of the present invention. Detailed Implementation

[0059] Before providing a more detailed description of the present invention in conjunction with the embodiments below, the relevant technologies will be explained first.

[0060] In related technologies, a pseudo-dual-port memory is provided, such as... Figure 1 As shown, Figure 1 This is a conventional pseudo-dual-port memory model, which supports read and write operations on a maximum of two ports simultaneously, with port 1 fixed as the read port and port 2 fixed as the write port.

[0061] Figure 2The following is a specific implementation method for a conventional pseudo-dual-port memory: For a multi-port memory with M read ports and N write ports and a capacity of W*B, it can be implemented using M*N ordinary pseudo-dual-port memories with a capacity of W*B. An additional memory mapping table with a capacity of W*(CEILING(LOG2N)) is required; CEILING represents rounding up. However, the above scheme uses too many pseudo-dual-port memory cells, resulting in a large area and high power consumption for the implemented multi-port memory.

[0062] ASIC designs require large-capacity multi-read / multi-write memory. However, implementing this using the aforementioned methods still results in significant area and power consumption. Therefore, this invention provides a novel pseudo-dual-port dual-read memory to implement multi-port memory. Compared to existing technologies, this significantly reduces area and power consumption. The novel pseudo-dual-port dual-read memory has the same number of ports, density, and performance as a regular pseudo-dual-port memory, but its port usage is more flexible.

[0063] The present invention will be further described in detail below with reference to the embodiments.

[0064] Figure 3 This is a schematic diagram of a pseudo-dual-port dual-read memory model provided in an embodiment of the present invention, as shown below. Figure 3 As shown, in the pseudo dual-port dual-read memory, port 1 is fixed as a read port, while port 2 can be selected as either a read port or a write port (e.g., ...). Figure 3 (See Figure 2 for read / write enable settings). You can choose one of the two options depending on your needs.

[0065] Multi-port memory implemented based on a novel pseudo-dual-port dual-read memory achieves the same bandwidth using fewer memory units, thus reducing area. When implementing a multi-port memory with an even number of read ports based on a pseudo-dual-port dual-read memory, all read ports are utilized. However, when implementing a multi-port memory with an odd number of read ports based on a pseudo-dual-port dual-read memory, not all read ports are utilized. This invention proposes a method for implementing a multi-port memory with an odd number of read ports that can improve port utilization, thereby further reducing memory area.

[0066] To implement a multi-port memory with a depth of W, a width of B, a number of read ports of M, and a number of write ports of N, where M is an odd number, the total number of pseudo-dual-port two-read memories required is CEILING(M / 2)*(N+1)-1 (CEILING represents rounding up). The depth of a single pseudo-dual-port two-read memory is W, and the width is B. The CEILING(M / 2)*(N+1)-1 pseudo-dual-port two-read memories are numbered sequentially as #0, #1, ... #CEILING(M / 2)*(N+1)-2.

[0067] Additionally, a storage mapping table (SMT) is needed to indicate which memory contains the valid data for each address. The capacity of the storage mapping table is W*(CEILING(LOG2(CEILING(M / 2)*(N+1)-1))) bits (LOG2 represents the logarithm to base 2).

[0068] Figure 4 This invention provides an architecture diagram for a multi-port memory with an odd number of read ports based on a pseudo-dual-port dual-read memory; as shown in the embodiment of the invention. Figure 4 As shown, the multi-port memory includes:

[0069] CEILING(M / 2)*(N+1)-1 pseudo dual-port dual-read memory, write operation control unit, read operation control unit and memory mapping table.

[0070] Where M is the number of read ports; N is the number of write ports; and CEILING indicates rounding up.

[0071] The pseudo dual-port dual-read memory is used to perform at least one of read operation, write operation, and read-write operation.

[0072] The storage mapping table is used to indicate the pseudo dual-port dual-read memory where the valid data for each address is stored.

[0073] The write operation control unit is used to control and manage the write operations for the pseudo dual-port dual-read memory.

[0074] The read operation control unit is used to control and manage the read operations of the pseudo dual-port dual-read memory.

[0075] The pseudo dual-port dual-read memory has a first port and a second port; the first port is a read port; and the second port is either a read port or a write port.

[0076] The capacity of the storage mapping table is W*(CEILING(LOG2(CEILING(M / 2)*(N+1)-1))) bits; where W is the depth of a single pseudo dual-port dual-read memory.

[0077] Here, the storage mapping table also includes an address space, which is related to the address space of the pseudo dual-port dual-read memory. For example, if the address space of the pseudo dual-port dual-read memory is 1000 addresses or 2000 addresses, then the address space of the storage mapping table is 1000 addresses or 2000 addresses accordingly.

[0078] In practical applications, for read and write operations, in addition to allocating the corresponding pseudo dual-port two-read memory, the specific address is also recorded. The recording method can be as follows: after determining the allocated pseudo dual-port two-read memory (denoted as memory A), the address of the dual-port two-read memory (denoted as address B) is determined at the same time. Address B in the corresponding address space of the storage mapping table corresponds to the allocated memory A.

[0079] This invention also provides a read / write method for a multi-port storage device, applicable to the aforementioned multi-port storage device; such as... Figure 5 As shown, the method includes:

[0080] Step 501: Receive the target operation;

[0081] Step 502: Determine the pseudo dual-port dual-read memory to perform the target operation based on the storage mapping table;

[0082] Step 503: Perform the target operation through the determined pseudo dual-port dual-read memory.

[0083] In one embodiment, when the target operation is a write operation; determining the pseudo-dual-port dual-read memory to perform the target operation based on the memory mapping table includes:

[0084] Based on the information of the write operation and the storage mapping table, determine the pseudo-dual-port two-read memory that can perform the write operation; based on the pseudo-dual-port two-read memory that can perform the write operation, determine the pseudo-dual-port two-read memory to perform the write operation.

[0085] Updating the storage mapping table includes:

[0086] Write the list of numbers of the pseudo dual-port dual-read memory that are determined to be capable of performing write operations into the memory mapping table.

[0087] The information for the write operation includes the address corresponding to the write operation.

[0088] In one embodiment, when the target operation is a read operation; determining the pseudo-dual-port dual-read memory to perform the target operation according to the storage mapping table includes:

[0089] The storage mapping table is queried according to the read address corresponding to the read operation to determine the corresponding storage flag information;

[0090] The one or more pseudo-dual-port dual-read memories involved are determined based on the storage flag information.

[0091] In one embodiment, when the target operation is a simultaneous read / write operation; determining the pseudo-dual-port dual-read memory to perform the target operation based on the storage mapping table includes:

[0092] For the read operation of the simultaneous read and write operation, the storage mapping table is queried according to the read address corresponding to the read operation to determine the corresponding storage flag information; the one or more pseudo dual-port dual-read memories involved are determined according to the storage flag information.

[0093] For the write operation of the simultaneous read and write operation, based on the information of the write operation and the storage mapping table, a pseudo dual-port dual-read memory that can perform the write operation is determined; based on the pseudo dual-port dual-read memory that can perform the write operation, a pseudo dual-port dual-read memory for performing the write operation is determined.

[0094] Updating the storage mapping table includes:

[0095] Write the list of numbers of the pseudo dual-port dual-read memory to be executed the write operation into the memory mapping table.

[0096] In one embodiment, the pseudo-dual-port dual-read memory for performing the write operation is one or more consecutive pseudo-dual-port dual-read memories.

[0097] The step of writing the list of identified pseudo-dual-port dual-read memory numbers for which write operations will be performed into the memory mapping table includes:

[0098] Write the determined starting pseudo-dual-port dual-read memory number of the pseudo-dual-port dual-read memory to be used for the write operation into the memory mapping table.

[0099] The number of the initial pseudo dual-port dual-read memory corresponds to the information of the write operation, which includes at least the number of read ports and the number of write ports.

[0100] In other words, assuming that the determined pseudo-dual-port two-read memory numbers (which can also be understood as IDs or other identifiers) for performing write operations include memory 2, memory 3, and memory 4, the list of determined pseudo-dual-port two-read memory numbers for performing write operations is written into the storage mapping table. That is, the number, i.e., memory 2, is written into the storage mapping table. In order to facilitate the determination of the memory to which the operation ends in subsequent operations, the number, i.e., memory 2, is marked with the number of reads and writes, such as three reads and three writes. In this way, the number of the memory to which the operation ends can be determined.

[0101] In one embodiment, considering the existence of a pseudo dual-port dual-read memory where both ports are used for read operations, it is correspondingly unable to perform write operations.

[0102] Based on this, for read operations, determining the one or more pseudo-dual-port dual-read memories involved based on the storage flag information further includes:

[0103] Identify a pseudo-dual-port dual-read memory that performs two read operations;

[0104] The update of the storage mapping table further includes:

[0105] A pseudo-dual-port dual-read memory that performs two read operations simultaneously is marked as an illegal write operation memory.

[0106] Memory marked as having an illegal write operation cannot be written to; the information must be updated after the read operation is completed, and then the memory marked as having an operable write operation can be written to.

[0107] In one embodiment, in response to the presence of an illegal write operation memory, before determining the pseudo dual-port dual-read memory for performing the target operation based on the memory mapping table, the method further includes:

[0108] Identify existing illegal write-operation memory, and determine a list of writable memory based on the illegal write-operation memory; the list of writable memory includes: other pseudo dual-port dual-read memory other than the illegal write-operation memory.

[0109] Accordingly, determining the pseudo-dual-port dual-read memory for performing the target operation based on the storage mapping table includes:

[0110] For any write operation, allocate several consecutive pseudo-dual-port two-read memories according to the writable memory list.

[0111] It remains in use as a pseudo dual-port dual-read memory until the write operation is invalidated and the read operation is completed.

[0112] Here, deleting the illegal memory marker for a write operation in the memory mapping table needs to be done after the read operation is completed.

[0113] The updates to the storage mapping table are performed by the write operation control unit, while the queries and reads of the storage mapping table are performed by the read operation control unit.

[0114] That is, the write operation control unit implements the control and management of write operations for the pseudo dual-port dual-read memory, and specifically executes the write operation-related steps in the above method, which will not be repeated here.

[0115] The read operation control unit controls and manages the read operations of the pseudo dual-port dual-read memory, and executes the write operation-related steps in the above method, which will not be repeated here.

[0116] To further explain the aforementioned multi-port storage devices and corresponding methods, the read and write methods of multi-port storage devices are described below in three scenarios:

[0117] Case 1: Only write operations occur. For example... Figure 7 As shown,

[0118] Suppose that there are n (n <= N) write ports performing write operations simultaneously. Then, the i-th (i = 0, 1, ..., n - 1) write operation is written to the #i * CEILING(M / 2) to #(i + 1) * CEILING(M / 2) - 1 pseudo-dual-port two-read memories (hereinafter referred to as memory cells for short), and the storage mapping table is updated simultaneously by writing the number i * CEILING(M / 2) into the storage mapping table. Here, the i * CEILING(M / 2) actually represents the starting number of the memory cells involved, that is, in the storage mapping table, i * CEILING(M / 2) indicates that the write operation is performed on the #i * CEILING(M / 2) to #(i + 1) * CEILING(M / 2) - 1 memory cells.

[0119] Case 2: Only read operations. As Figure 8 shown,

[0120] Suppose that there are m (m <= M) read ports performing read operations simultaneously. First, find the corresponding storage flag bit information in the storage mapping table according to each read address. From the description of Case 1, it can be seen that the storage flag bit information read from the storage mapping table is only the starting number i * CEILING(M / 2) of the actual memory cells. The CEILING(M / 2) memory cells starting from this number are the actual storage locations corresponding to this address.

[0121] If i * CEILING(M / 2) + j > CEILING(M / 2) * (N + 1) - 2, where j = 0, 1, …, CEILING(M / 2) - 1; then the number i * CEILING(M / 2) + j should be converted to the actual memory number MOD(i * CEILING(M / 2) + j, CEILING(M / 2) * (N + 1) - 1).

[0122] According to the foregoing rules, the memory cells where the valid data corresponding to each read address is located can be obtained, and the number p of different memory cells involved in the m read operations is calculated. The number of read operations to be performed on each memory cell is recorded as X[0], X[1], ..., X[p - 1] respectively, and X[0], X[1], …, X[p - 1] are sorted in ascending order; if the number of read operations of X[i] and X[i + 1] is the same (i + 1 < p - 1), then they are sorted in ascending order according to the memory numbers corresponding to X[i] and X[i + 1]. If the memory number corresponding to X[i] is smaller, then Y[i] = X[i], Y[i + 1] = X[i + 1]; otherwise, Y[i] = X[i + 1], Y[i + 1] = X[i]. Y[0], Y[1], …, Y[p - 1] are obtained according to the above rules. Two cases are divided according to the sizes of m and p:

[0123] Case a): If p >= m (where p represents the number of read operations and m represents the number of read ports), then different read operations can definitely read data from different memory units. Starting from Y[0], determine which memory unit each different read operation reads data from. For a certain memory unit k (k = 0, 1, … p - 1), if Y[k] = 1, then the read operation corresponding to Y[k] reads data from the memory unit corresponding to Y[k], and ignore this read operation included in other memory units; if Y[k] > 1, then select one of the read operations in Y[k] to read data from the memory unit corresponding to Y[k], until all read operations find different memory units to read data.

[0124] Case b): If p < m, then at least one memory unit has two read operations, and m - p represents the number of memory units that need to perform two read operations. Starting from Y[0], determine which memory unit each different read operation reads data from. For any memory unit k (k < p), if Y[k] = 1, then read operation k reads data from the memory unit corresponding to Y[k], and ignore read operation k included in other memory units; if Y[k] > 1, there are two cases:

[0125] Case i: If k < p - (m - p), then select one of the read operations in Y[k] to read data from this memory unit, and ignore this read operation included in other memory units;

[0126] Case ii: If k >= p - (m - p), then select two of the read operations in Y[k] to read data from this memory unit, and mark this memory unit as an illegal memory unit for write operations, and at the same time ignore these two read operations included in other memory units;

[0127] Case 3: When there are both read and write operations simultaneously.

[0128] Suppose there are m (m <= M) read ports performing read operations and n (n <= N) write ports performing write operations simultaneously. Look up the corresponding storage mapping information in the storage mapping table according to each read address, and calculate that the i-th (i <= N + 1) memory unit has X[i] read addresses to read data respectively. The following describes the read operation and the write operation separately:

[0129] a) For the read operation, perform the read operation according to the process of only having read operations, as Figure 9 shown.

[0130] b) For the write operation, as Figure 10 shown, there are two cases:

[0131] i. If there is no illegal memory unit for write operations, it is the same as the method of only having write operations.

[0132] ii. If there are illegal memory cells for write operations, denote the numbers of all memory cells as a sequence O[x] (x = 0, 1, ..., CEILING(M / 2)*(N+1)-2). For a memory with at most M read ports, when M is odd, it is easy to see that the maximum number of memory cells with illegal write operations is INT(M / 2), and CEILING(M / 2)-INT(M / 2) = 1. Therefore, at this time, the minimum number of writable memory cells is CEILING(M / 2)*(N+1)-1-INT(M / 2) = CEILING(M / 2)*N + CEILING(M / 2)-1-INT(M / 2) = CEILING(M / 2)*N, that is, each write operation has at least CEILING(M / 2) memory cells that can be written. Assume that the smallest number of the illegal memory cell for a write operation is Imin and the largest number is Imax. As can be seen from the aforementioned read operation process, the numbers of other illegal memory cells for write operations must be between Imin and Imax. Using MOD(Imax+1, CEILING(M / 2)*(N+1)-1) as the first writable memory cell number, we obtain the numbers P[x] (x=0,1,…) of all writable memory cells after deleting the illegal memory cell for a write operation, where P[0]=MOD(Imax+1, CEILING(M / 2)*(N+1)-1). Then, the i-th (i=0,1,n-1) write operation to memory cells P[i*CEILING(M / 2)]~P[(i+1)*CEILING(M / 2)-1], and simultaneously update the memory mapping table, writing the number P[i*CEILING(M / 2)] to the write address corresponding to the i-th write operation in the memory mapping table.

[0133] To further illustrate the multi-port dual-read memory provided in the embodiments of the present invention, a scheme for implementing a three-read, three-write memory based on a pseudo dual-port dual-read memory is provided.

[0134] Figure 11 This invention provides an architecture diagram for implementing a three-read, three-write memory based on a pseudo-dual-port two-read memory; as shown in the embodiment of the invention. Figure 11 As shown, this paper takes the implementation of a multi-port memory with three reads (M=3), three writes (N=3), 2048 depths (W=2048), and 32-bit widths (B=32) as an example to illustrate how to implement a multi-port memory based on a pseudo-dual-port two-read memory.

[0135] To implement the aforementioned three-read, three-write memory, the required number of pseudo-dual-port two-read memories is CEILING(M / 2)*(N+1)-1=CEILING(3 / 2)*(3+1)-1=7. The depth and width of a single pseudo-dual-port two-read memory are the same as the depth and width of the multi-port memory, i.e., the depth of a single pseudo-dual-port two-read memory is 2048 and the width is 32. The seven pseudo-dual-port two-read memories are numbered #0, #1…#6. The number of bits in the storage mapping table is W*(CEILING(LOG2(CEILING(M / 2)*(N+1)-1)))=2048*CEILING(LOG27)=2048*3=6144. The values ​​of the storage mapping table (SMT) are initialized to all 0s.

[0136] 1. Simultaneously write addresses 0, 1, and 2: At this time, there is no read operation and no illegal memory cell for write operation. Therefore, write the data corresponding to address 0 to memory cells #0 and #1, write the data corresponding to address 1 to memory cells #2 and #3, write the data corresponding to address 2 to memory cells #4 and #5, update the memory mapping table, SMT[0] = 3'h0, SMT[1] = 3'h2, SMT[2] = 3'h4.

[0137] 2. Read addresses 0, 1, 2, and write addresses 3, 4, 5 simultaneously: Read the memory mapping table according to the read addresses to obtain SMT[0] = 3'h0, SMT[1] = 3'h2, SMT[2] = 3'h4. Convert the above memory starting numbers into the actual storage location information of the effective data as SMT_T[0] = 7'b1100000, SMT_T[1] = 7'b0011000, SMT_T[2] = 7'b0000110. Thus, the three read operations (m = 3) involve different memory units #0 to #5, a total of 6 (p = 6). Since p > m, different read operations can read data from different memory units. There are no invalid memory units for write operations. Therefore, write operations are performed in the manner of only write operations, and read operations are performed in the manner of only read operations.

[0138] Specifically, read 0 accesses memory cell #0, read 1 accesses memory cell #2, and read 2 accesses memory cell #4; write data corresponding to address 3 is written to memory cells #0 and #1, write data corresponding to address 4 is written to memory cells #2 and #3, and write data corresponding to address 5 is written to memory cells #4 and #5. SMT[3] = 3'h0, SMT[4] = 3'h2, and SMT[5] = 3'h4.

[0139] 3. Write addresses 6, 7, and 8. The operation process is similar to step 1.

[0140] 4. Read addresses 0, 3, 6 while writing to addresses 1, 4, 7: The read operation process is described first, followed by the write operation process.

[0141] a) Read operation process: According to the storage mapping table, SMT[0] = SMT[3] = SMT[6] = 3’h0, then SMT_T[0] = SMT_T[3] = SMT_T[6] = 7’b1100000, that is, the read operation count m = 3, and the number of different memory units involved in the read operation p = 2 (memory units #0 and #1). Since p < m, there are m - p = 3 - 2 = 1 memory unit with two read operations. The read operation count of memory unit #0 is X[0] = 3, and the read operation count of memory unit #1 is X[1] = 3. Since the read operation counts are the same, after sorting by memory number from smallest to largest, Y[0] corresponds to memory unit #0, Y[1] corresponds to memory unit #1, and Y[0] = 3, Y[1] = 3; for the three read operations corresponding to Y[0], read address 0, read address 3, and read address 6, according to the aforementioned rules, when i = 0 < (m - p) = 1, select one of the read operations, such as read address 0, which accesses memory #0 corresponding to Y[0]; when i = (m - p) = 1, the memory unit corresponding to Y[1] should perform two read operations, and Y[1] originally contains three read operations, read address 0, read address 3, and read address 6. After removing the read address 0 operation that accesses memory #0, the remaining two read operations both access the memory unit #1 corresponding to Y[1], that is, read address 3 and read address 6, read data from the two read ports of memory unit #1 respectively, and mark memory unit #1 as an illegal memory unit for write operations.

[0142] b) Write operation process: The entire memory unit sequence O[x] is #0, #1,... #6, and the illegal memory unit for write operations is #1. Then the starting memory number of the writable memory units is #(1 + 1) = #2, and the writable memory unit number sequence P[x] is #2, #3, #4, #5, #6, #0; then, write the write data corresponding to address 1 into memory units #2 and #3, update SMT[1] = 7’h2, write the data corresponding to address 4 into memory units #4 and #5, update SMT[4] = 7’h4, and write the data corresponding to address 7 into memory units #6 and #0, update SMT[7] = 7’h6.

[0143] 5. Read addresses 0, 3, 7 while writing to addresses 2, 4, 5: The read operation process is described first, followed by the write operation process.

[0144] a) Read operation process: According to the storage mapping table, SMT[0] = SMT[3] = 3'h0, SMT[7] = 3'h6, then SMT_T[0] = SMT_T[3] = 7'b1100000, SMT_T[7] = 7'b1000001, that is, the number of read operations m = 3, the number of different memory units involved in the read operation p = 3, which are memory units #0, #1, and #6 respectively. Since p = m, different read operations operate on different memory units respectively, and there is no illegal memory unit for write operations. The number of read operations X[0] = 3 for memory unit #0, the number of read operations X[1] = 2 for memory unit #1, and the number of read operations X[6] = 1 for memory unit #2; according to the aforementioned sorting rules, Y[0] = X[6] = 1, Y[1] = X[1] = 2, Y[2] = X[0] = 3. Since Y[0]=X[6]=1, the read operation corresponding to X[6] reads address 7 to read memory cell 6. Y[1]=2 contains two read operations, read 0 and 3. Choose one of the read operations, such as read data from memory cell #1 at address 0. Y[2]=3 has three read operations, read 0, 3 and 7. Remove the two read operations, read 0 and 7, which read data from other memory cells. Then only the read address 1 operation remains, that is, read data from memory cell #0 at address 1.

[0145] b) Write operation process: Since there is no illegal memory cell to write, the data is written according to the method of only write operation.

[0146] Other operations for a three-read, three-write memory can be performed in a similar manner as described above.

[0147] Figure 12 This diagram illustrates a comparison of the area of ​​a multi-port storage device with an odd number of read ports, implemented using a pseudo-dual-port dual-read memory and a regular pseudo-dual-port memory, as provided in this embodiment of the invention. The evaluation was conducted based on a memory developed by Synopsys using TSMC's 7nm process. The pseudo-dual-port regular memory is a dual-port high-speed ultra-high-density memory provided by Synopsys, and the pseudo-dual-port dual-read memory is a pseudo-dual-port dual-read memory provided by Synopsys. As shown in the table below, the solution provided in this embodiment of the invention significantly saves area compared to the pseudo-dual-port regular memory solution.

[0148] This invention also provides a schematic diagram of the structure of a data processing device; the device includes:

[0149] The receiving module is used to receive the target operation;

[0150] The processing module is used to determine the pseudo dual-port dual-read memory to perform the target operation based on the storage mapping table;

[0151] The target operation is performed through the determined pseudo-dual-port dual-read memory, and the memory mapping table is updated.

[0152] The device can also achieve Figure 5 The other steps in the method shown will not be elaborated here.

[0153] This invention also provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor; when the processor of the electronic device executes the program, it implements the methods provided by one or more of the above-described technical solutions.

[0154] The methods disclosed in the embodiments of this application can be applied to a processor, or implemented by a processor. A processor may be an integrated circuit chip with signal processing capabilities.

[0155] This application also provides a storage medium, specifically a computer storage medium, and more specifically a computer-readable storage medium. It stores computer instructions, i.e., a computer program; when these computer instructions are executed by a processor, they provide the methods described in one or more of the above-described technical solutions.

[0156] In the several embodiments provided in this application, it should be understood that the disclosed methods and smart devices can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0157] Furthermore, the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0158] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-port storage device, characterized in that, The device comprises: CEILING(M / 2) (N+1)-1 pseudo dual-port two-read memories, a write operation control unit, a read operation control unit and a storage mapping table; M is the number of read ports; N is the number of write ports; CEILING represents rounding up. The pseudo dual-port dual-read memory is used to perform read operations or simultaneous read and write operations; The storage mapping table is used to indicate the pseudo dual-port dual-read memory where the valid data for each address is stored. The write operation control unit is used to control and manage the write operations for the pseudo dual-port dual-read memory. The read operation control unit is used to control and manage the read operations of the pseudo dual-port dual-read memory.

2. The apparatus of claim 1, wherein, The pseudo dual-port dual-read memory has a first port and a second port; the first port is a read port; the second port is either a read port or a write port.

3. The device according to claim 1 or 2, characterized in that, The storage map table has a capacity of W (CEILING(LOG2(CEILING(M / 2) (N+1)-1))) bits; Wherein, W is the depth of a single pseudo dual-port dual-read memory.

4. A method for reading and writing a multi-port storage device, characterized in that, Applied to the multi-port storage device according to any one of claims 1 to 3; the method includes: Receive target operation; The pseudo dual-port dual-read memory for performing the target operation is determined according to the storage mapping table; The target operation is performed through the determined pseudo-dual-port dual-read memory, and the memory mapping table is updated.

5. The method according to claim 4, characterized in that, When the target operation is a write operation; determining the pseudo-dual-port dual-read memory to perform the target operation according to the storage mapping table includes: Based on the information of the write operation and the storage mapping table, determine the pseudo-dual-port two-read memory that can perform the write operation; based on the pseudo-dual-port two-read memory that can perform the write operation, determine the pseudo-dual-port two-read memory to perform the write operation. Updating the storage mapping table includes: Write the list of numbers of the pseudo dual-port dual-read memory to be executed into the memory mapping table.

6. The method according to claim 4, characterized in that, When the target operation is a read operation; determining the pseudo-dual-port dual-read memory to perform the target operation according to the storage mapping table includes: The storage mapping table is queried according to the read address corresponding to the read operation to determine the corresponding storage flag information; The one or more pseudo-dual-port dual-read memories involved are determined based on the storage flag information.

7. The method according to claim 4, characterized in that, When the target operation is a simultaneous read / write operation; determining the pseudo-dual-port dual-read memory to perform the target operation based on the storage mapping table includes: For the read operation of the simultaneous read and write operation, the storage mapping table is queried according to the read address corresponding to the read operation to determine the corresponding storage flag information; the one or more pseudo dual-port dual-read memories involved are determined according to the storage flag information. For the write operation of the simultaneous read and write operation, based on the information of the write operation and the storage mapping table, a pseudo dual-port dual-read memory that can perform the write operation is determined; based on the pseudo dual-port dual-read memory that can perform the write operation, a pseudo dual-port dual-read memory for performing the write operation is determined. Updating the storage mapping table includes: Write the list of numbers of the pseudo dual-port dual-read memory to be executed into the memory mapping table.

8. The method according to claim 5 or 7, characterized in that, The pseudo-dual-port dual-read memory that performs the write operation is one or more consecutive pseudo-dual-port dual-read memories. The step of writing the list of identified pseudo-dual-port dual-read memory numbers for which write operations will be performed into the memory mapping table includes: Write the determined number of the starting pseudo-dual-port dual-read memory for which the write operation is performed into the storage mapping table. The number of the initial pseudo dual-port dual-read memory corresponds to the information of the write operation, which includes at least the number of read ports and the number of write ports.

9. The method according to claim 6 or 7, characterized in that, For read operations, determining the one or more pseudo-dual-port dual-read memories involved based on the storage flag information further includes: Identify a pseudo-dual-port dual-read memory that performs two read operations; The update of the storage mapping table further includes: A pseudo-dual-port dual-read memory that performs two read operations simultaneously is marked as an illegal write operation memory.

10. The method according to claim 6 or 7, characterized in that, In response to the presence of an illegal write operation memory, before determining the pseudo-dual-port dual-read memory for performing the target operation based on the memory mapping table, the method further includes: Identify existing illegal write-operation memories, and determine a list of writable memories based on the illegal write-operation memories; the list of writable memories includes: other pseudo dual-port dual-read memories other than the illegal write-operation memories; Accordingly, determining the pseudo-dual-port dual-read memory for performing the target operation based on the storage mapping table includes: For any write operation, allocate several consecutive pseudo-dual-port two-read memories according to the writable memory list.

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