Charge pump circuit for load switch, chip, and communication terminal

Abstract

This invention discloses a charge pump circuit, chip, and communication terminal for a load switch, including a boost module. The boost module comprises: a first pumping capacitor coupled between a first input terminal and a first boost node; a first transistor coupled between a third input terminal and the first boost node; a first resistor and a third transistor coupled between the first boost node and an output terminal; a second pumping capacitor coupled between a second input terminal and a second boost node; a second transistor coupled between the third input terminal and the second boost node; and a second resistor and a fourth transistor coupled between the second boost node and the output terminal. The charge pump circuit of this invention, through the hysteresis and voltage division effect of the resistor, ensures that the source-drain voltage difference between the third and fourth transistors is not too large when the output voltage of the boost module is low, reducing the conduction degree of the body diode and parasitic transistor in the third and fourth transistors, and improving the driving capability of the charge pump.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a charge pump circuit, chip, and communication terminal for load switching. Background Technology

[0002] Load switches are widely used in various power management systems and are an important component of power supply and system monitoring products, providing protection for both the power supply and the load. Because the electron carrier mobility is greater than the hole carrier mobility (approximately 2.6:1), existing load switches typically use NMOS transistors, which effectively reduces chip area and saves costs. To ensure that the input voltage Vin of the load switch is fully transferred to the output, a charge pump circuit is needed to boost the gate voltage of the load switch above Vin. Normally, during normal operation, the gate-source voltage needs to be controlled at around 5V. This not only effectively improves conduction efficiency but also reduces the on-resistance of the power transistor, while allowing it to operate within a safer operating range.

[0003] However, existing charge pump circuits are susceptible to the effects of parasitic transistors. When the input voltage Vin approaches the gate voltage Vgate, the transistor in the charge pump requires a certain conduction time. Instantly, charge is transferred to the output of the charge pump through the body diode of the transistor, causing the parasitic transistor of the transistor to conduct. This causes the charge on the capacitor to be discharged to ground, resulting in a weakening of the charge pump's driving capability. This poses a risk that the chip may not start normally or may even fail to start at all. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a charge pump circuit, chip and communication terminal for load switching, which solves the problem of weak driving capability of existing charge pump circuits and improves circuit efficiency.

[0005] According to a first aspect of the present invention, a charge pump circuit for a load switch is provided, the charge pump circuit being used to convert an input voltage into a gate drive voltage of the load switch, wherein the charge pump circuit includes: a boost module having a first input terminal for receiving a first voltage, a second input terminal for receiving a second voltage, a third input terminal for receiving the input voltage, and an output terminal for outputting a boosted gate drive voltage; wherein the boost module includes: a first pumping capacitor coupled between the first input terminal and a first boost node; a first transistor coupled between the third input terminal and the first boost node; a first resistor and a third transistor connected in series between the first boost node and the output terminal; a second pumping capacitor coupled between the second input terminal and a second boost node; a second transistor coupled between the third input terminal and the second boost node; and a second resistor and a fourth transistor connected in series between the second boost node and the output terminal.

[0006] Optionally, the first transistor and the third transistor each have a control terminal coupled to the second boost node, and the second transistor and the fourth transistor each have a control terminal coupled to the first boost node.

[0007] Optionally, the potentials of the first voltage and the second voltage are switched between a reference voltage and ground.

[0008] Optionally, the charge pump circuit further includes: a first driving module coupled to the boost module, used to provide the first voltage to the first input terminal according to the first clock signal and the reference voltage; and a second driving module coupled to the boost module, used to provide the second voltage to the second input terminal according to the second clock signal and the reference voltage.

[0009] Optionally, the first driving module includes: first and second inverters, the input terminal of the first inverter is used to receive the first clock signal, the output terminal of the first inverter is coupled to the input terminal of the second inverter, and a fifth and a sixth transistor coupled between the reference voltage and ground, the control terminals of the fifth and sixth transistors are coupled to the output terminal of the second inverter, and the common terminal of the fifth and sixth transistors serves as the output terminal of the first voltage; wherein, the fifth transistor is a P-type field-effect transistor and the sixth transistor is an N-type field-effect transistor.

[0010] Optionally, the second driving module includes: a third and a fourth inverter, the input of the third inverter being used to receive the second clock signal, the output of the third inverter being coupled to the input of the fourth inverter, and a seventh and an eighth transistor coupled between the reference voltage and ground, the control terminals of the seventh and eighth transistors being coupled to the output of the fourth inverter, and the common terminal of the seventh and eighth transistors serving as the output of the second voltage; wherein the seventh transistor is a P-type field-effect transistor and the eighth transistor is an N-type field-effect transistor.

[0011] Optionally, the first clock signal and the second clock signal are differential clock signals.

[0012] Optionally, the first transistor and the second transistor are N-type field-effect transistors, and the third transistor and the fourth transistor are P-type field-effect transistors.

[0013] According to a second aspect of the present invention, a chip is provided, wherein the charge pump circuit described above is included.

[0014] According to a third aspect of the present invention, a communication terminal is provided, wherein the above-described charge pump circuit or chip is included.

[0015] In summary, the charge pump circuit for load switching in this embodiment of the invention includes a resistor disposed between the boost node in the boost module and the P-type field-effect transistor. Through the hysteresis effect of the resistor, the P-type field-effect transistor has sufficient time to fully conduct when the gate drive voltage output by the charge pump is low. Furthermore, the voltage division between the resistor and the on-resistance of the P-type field-effect transistor ensures that the voltage difference between the source and drain of the P-type field-effect transistor is not excessive, ultimately reducing the conduction degree of the body diode and parasitic transistor in the P-type field-effect transistor. This allows the charge at the pump capacitor to be transferred to the output terminal through the P-type field-effect transistor, improving the driving capability of the charge pump. Moreover, since the resistor occupies a relatively small area in the chip layout, the charge pump circuit in this embodiment of the invention does not require additional circuit area, offering advantages such as strong driving capability, small layout area, and low power consumption. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic circuit diagram of a charge pump circuit for a load switch in the prior art is shown.

[0018] Figure 2A schematic circuit diagram of a charge pump circuit for a load switch according to an embodiment of the present invention is shown. Detailed Implementation

[0019] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0020] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled" to another element or "coupled" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0021] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0022] Figure 1 A schematic circuit diagram of a prior art charge pump circuit for a load switch is shown. Figure 1 As shown, the charge pump circuit 100 includes a boost module 110, a first drive module 120, and a second drive module 130. The boost module 110 includes a first input terminal 101 for receiving a first voltage V1, a second input terminal 102 for receiving a second voltage V2, a third input terminal 103 for receiving an input voltage Vin, and an output terminal 104 for outputting the boosted gate drive voltage Vgate. The first drive module 120 is coupled to the boost module 110 and provides the first voltage V1 to the first input terminal 101 according to a first clock signal CLK and the input voltage Vin. The second drive module 130 is coupled to the boost module 110 and provides the second voltage V2 to the second input terminal 102 according to a second clock signal CLKB and the input voltage Vin. The first clock signal CLK and the second clock signal CLKB are differential clock signals, and the reference voltage Vref is a 5V voltage generated internally by the circuit.

[0023] Specifically, the boost module 110 includes pump capacitor C1, pump capacitor C2, and transistors T1-T4. The first end of pump capacitor C1 is coupled to the first input terminal 101 to receive the first voltage V1, and the second end is coupled to the intermediate boost node 1a inside the boost module 110. The first end of pump capacitor C2 is coupled to the second input terminal 102 to receive the second voltage V2, and the second end is coupled to the intermediate boost node 1b inside the boost module 110. Transistors T1-T4 adopt a differential cross-coupled architecture. Transistors T1 and T2 are N-type field-effect transistors, and transistors T3 and T4 are P-type field-effect transistors. The sources of transistors T1 and T2 are coupled to the third input terminal 103 to receive the input voltage Vin. The drains of transistors T1 and T3, and the gates of transistors T2 and T4 are coupled to the intermediate boost node 1a. The drains of transistors T2 and T4, and the gates of transistors T1 and T3 are coupled to the intermediate boost node 1b. The sources of transistors T3 and T4 are coupled to the output terminal 104.

[0024] The first driving module 120 includes inverters INV1 and INV2, and transistors T5 and T6. The input of inverter INV1 receives a first clock signal CLK, and its output is coupled to the input of inverter INV2. The source of transistor T5 is coupled to a reference voltage Vref, its drain is coupled to the drain of transistor T6, the source of transistor T6 is coupled to ground, and the gates of transistors T5 and T6 are coupled to the output of inverter INV2. The common terminal of the drains of transistors T5 and T6 is used to output the first voltage V1.

[0025] Similarly, the second drive module 130 includes inverters INV3 and INV4, and transistors T7 and T8. The input of inverter INV3 receives the second clock signal CLKB, and its output is coupled to the input of inverter INV4. The source of transistor T7 is coupled to the reference voltage Vref, its drain is coupled to the drain of transistor T8, the source of transistor T8 is coupled to ground, and the gates of transistors T7 and T8 are coupled to the output of inverter INV4. The common terminal of the drains of transistors T7 and T8 is used to output the second voltage V2.

[0026] The charge pump circuit 100 utilizes the high-pass characteristics of pumping capacitors C1 and C2 to continuously superimpose the input voltage Vin onto the reference voltage Vref, thereby maintaining the gate drive voltage Vgate at the output terminal at a high voltage.

[0027] In the existing charge pump circuit 100, the first voltage V1 and the second voltage V2 are transmitted to the output terminal of the charge pump through transistors T3 and T4, respectively. However, due to the parasitic transistors of transistors T3 and T4, the charge on the capacitor may be discharged to ground, resulting in a weakening of the driving capability of the charge pump. Taking transistor T3 as an example, when the gate drive voltage Vgate is low, for example, when the gate drive voltage Vgate is equal to the input voltage Vin, the voltage at the boost node 1a is equal to Vin + 5V (taking the reference voltage Vref equal to 5V as an example). That is, the voltage difference between the source and drain terminals of transistor T3 is 5V. Since transistor T3 needs a certain amount of time to turn on, there will be instantaneous charge transferred to the output terminal through the body diode (assuming the body diode's on-state voltage is 0.7V) D0 of transistor T3. This voltage difference will make the body diode D0 conduct fully, causing the parasitic transistor (parasitic PNP) Q0 of transistor T3 to turn on. The parasitic transistor Q0 will discharge the charge on the pump capacitor C1 to ground, resulting in a weakening of the charge pump's driving capability, making the chip unable to start normally.

[0028] Figure 2 A schematic circuit diagram of a charge pump circuit for a load switch according to an embodiment of the present invention is shown. Figure 2 As shown, the charge pump circuit 200 includes a boost module 210, a first drive module 220, and a second drive module 230. The boost module 210 includes a first input terminal 201 for receiving a first voltage V1, a second input terminal 202 for receiving a second voltage V2, a third input terminal 203 for receiving an input voltage Vin, and an output terminal 204 for outputting the boosted gate drive voltage Vgate. The first drive module 220 is coupled to the boost module 210 and provides the first voltage V1 to the first input terminal 201 according to a first clock signal CLK and a reference voltage Vref. The second drive module 230 is coupled to the boost module 210 and provides the second voltage V2 to the second input terminal 202 according to a second clock signal CLKB and a reference voltage Vref. The first clock signal CLK and the second clock signal CLKB are differential clock signals, and the reference voltage Vref is a 5V voltage generated internally by the circuit.

[0029] Specifically, the boost module 210 includes pump capacitor C1, pump capacitor C2, transistors T1-T4, and resistors R1 and R2. The first end of pump capacitor C1 is coupled to the first input terminal 201 to receive the first voltage V1, and the second end is coupled to the intermediate boost node 1a inside the boost module 210. The first end of pump capacitor C2 is coupled to the second input terminal 202 to receive the second voltage V2, and the second end is coupled to the intermediate boost node 1b inside the boost module 210. Transistors T1-T4 adopt a differential cross-coupled architecture. Transistors T1 and T2 are N-type field-effect transistors, and transistors T3 and T4 are P-type field-effect transistors. The sources of transistors T1 and T2 are coupled to the third input terminal 203 to receive the input voltage Vin. The drain of transistor T1, the first end of resistor R1, and the gates of transistors T2 and T4 are coupled to the intermediate boost node 1a. The second end of resistor R1 is coupled to the drain of transistor T3. The drain of transistor T2, the first end of resistor R2, and the gates of transistors T1 and T3 are coupled to the intermediate boost node 1b. The second end of resistor R2 is coupled to the drain of transistor T4. The sources of transistors T3 and T4 are coupled to the output terminal 204.

[0030] The first driving module 220 includes inverters INV1 and INV2, and transistors T5 and T6. The input of inverter INV1 receives the first clock signal CLK, and its output is coupled to the input of inverter INV2. The source of transistor T5 is coupled to a reference voltage Vref, its drain is coupled to the drain of transistor T6, and the source of transistor T6 is coupled to ground. The gates of transistors T5 and T6 are coupled to the output of inverter INV2. Transistor T5 is a P-type field-effect transistor, and transistor T6 is an N-type field-effect transistor. The common terminal of the drains of transistors T5 and T6 is used to output the first voltage V1.

[0031] Similarly, the second drive module 230 includes inverters INV3 and INV4, and transistors T7 and T8. The input of inverter INV3 receives the second clock signal CLKB, and its output is coupled to the input of inverter INV4. The source of transistor T7 is coupled to the reference voltage Vref, its drain is coupled to the drain of transistor T8, the source of transistor T8 is coupled to ground, and the gates of transistors T7 and T8 are coupled to the output of inverter INV4. Transistor T7 is a P-type field-effect transistor, and transistor T8 is an N-type field-effect transistor. The common terminal of the drains of transistors T7 and T8 is used to output the second voltage V2.

[0032] In the charge pump circuit 200 of this embodiment, resistors R1 and R2 can play a certain hysteresis role, so that when the gate drive voltage Vgate equals the input voltage Vin, transistors T3 and T4 have enough time to fully conduct. In addition, due to the voltage division effect of resistors R1 and R2, the voltage difference between the source and drain of transistors T3 and T4 is not too large, avoiding the conduction of the body diodes in transistors T3 and T4, thereby reducing the weakening effect of the parasitic transistors of transistors T3 and T4 on the driving capability of the circuit, and effectively improving the driving capability of the charge pump. Taking transistor T3 as an example, when the gate drive voltage Vgate equals the input voltage Vin, the voltage at boost node 1a is pumped to Vin+Vref, and the voltage at boost node 1b is Vin. Due to the presence of resistor R1, the voltage at node 1c will lag behind the voltage at boost node 1a, so that the voltage at node 1c is gradually pulled up, thereby giving transistor T3 enough time to fully conduct. Furthermore, the on-resistance Ron of transistor T3 is divided by resistor R1, and the maximum voltage at node 1c is equal to Vref*Ron / (R1+Ron). This voltage is less than 5V (taking a reference voltage Vref equal to 5V as an example). This effectively reduces the charge flowing through the body diode in transistor T3, weakens the conduction of the body diode, and effectively avoids the conduction of the parasitic transistor in transistor T3, ensuring that most of the charge on pump capacitor C1 can be transferred to the output of the charge pump through transistor T3. Similarly, when the voltage at boost node 1b is pumped to Vin+Vref, resistor R2 can also reduce the conduction of the body diode and parasitic transistor in transistor T4, ensuring that most of the charge on pump capacitor C2 can be transferred to the output of the charge pump through transistor T4, improving the driving capability of the charge pump.

[0033] Furthermore, since the resistor occupies a relatively small area in the chip layout, the charge pump circuit of this embodiment does not require additional circuit area, and has the advantages of strong driving capability, small layout area and low power consumption.

[0034] In other circuits of the present invention, a chip is also provided, such as a power management chip or an RF chip or other integrated circuit chip. The charge pump circuit provided in the embodiments of the present invention can be integrated into the chip. The specific structure of the charge pump circuit in the integrated circuit chip will not be described in detail here.

[0035] Furthermore, the aforementioned charge pump circuit with enhanced driving capability can also be used in communication terminals as an important component of radio frequency integrated circuits or power management circuits. Here, "communication terminal" refers to a device that can be used in a mobile environment and supports multiple communication standards such as GSM, EDGE, TD-SCDMA, TDD-LTE, and FDD-LTE, including mobile phones, laptops, tablets, and in-vehicle computers. Moreover, the technical solution provided by this invention is also applicable to other applications of radio frequency integrated circuits, such as communication base stations.

[0036] In summary, the charge pump circuit for load switching in this embodiment of the invention includes a resistor disposed between the boost node in the boost module and the P-type field-effect transistor. Through the hysteresis effect of the resistor, the P-type field-effect transistor has sufficient time to fully conduct when the gate drive voltage output by the charge pump is low. Furthermore, the voltage division between the resistor and the on-resistance of the P-type field-effect transistor ensures that the voltage difference between the source and drain of the P-type field-effect transistor is not excessive, ultimately reducing the conduction degree of the body diode and parasitic transistor in the P-type field-effect transistor. This allows the charge at the pump capacitor to be transferred to the output terminal through the P-type field-effect transistor, improving the driving capability of the charge pump. Moreover, since the resistor occupies a relatively small area in the chip layout, the charge pump circuit in this embodiment of the invention does not require additional circuit area, offering advantages such as strong driving capability, small layout area, and low power consumption.

[0037] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0038] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A charge pump circuit for a load switch, the charge pump circuit being used to convert an input voltage into a gate drive voltage for the load switch, wherein, The charge pump circuit includes: The boost module has a first input terminal for receiving a first voltage, a second input terminal for receiving a second voltage, a third input terminal for receiving the input voltage, and an output terminal for outputting the boosted gate drive voltage. The boost module includes: A first pumping capacitor, the first end of which is coupled to the first input terminal, and the second end of which is coupled to the first boost node; A first transistor, wherein a first terminal of the first transistor is coupled to the third input terminal, and a second terminal of the first transistor is coupled to the first boost node; A first resistor and a third transistor, wherein a first end of the first resistor is coupled to the first boost node, a second end of the first resistor is coupled to the first end of the third transistor, and a second end of the third transistor is coupled to the output terminal; The second pumping capacitor has a first end coupled to the second input terminal and a second end coupled to the second boost node. The second transistor has a first terminal coupled to the third input terminal and a second terminal coupled to the second boost node. A second resistor and a fourth transistor, wherein a first end of the second resistor is coupled to the second boost node, a second end of the second resistor is coupled to the first end of the fourth transistor, and a second end of the fourth transistor is coupled to the output terminal.

2. The charge pump circuit according to claim 1, wherein, The first transistor and the third transistor each have a control terminal coupled to the second boost node, and the second transistor and the fourth transistor each have a control terminal coupled to the first boost node.

3. The charge pump circuit according to claim 1, wherein, The potentials of the first voltage and the second voltage switch between a reference voltage and ground.

4. The charge pump circuit according to claim 3 further includes: A first driving module, coupled to the boost module, is used to provide the first voltage to the first input terminal according to the first clock signal and the reference voltage; The second driving module, coupled to the boost module, is used to provide the second voltage to the second input terminal according to the second clock signal and the reference voltage.

5. The charge pump circuit according to claim 4, wherein, The first driving module includes: The first inverter has a first and a second inverter. The input of the first inverter receives the first clock signal. The output of the first inverter is coupled to the input of the second inverter. A fifth and a sixth transistor are coupled between the reference voltage and ground, the control terminals of the fifth and sixth transistors are coupled to the output terminal of the second inverter, and the common terminal of the fifth and sixth transistors serves as the output terminal of the first voltage; The fifth transistor is a P-type field-effect transistor, and the sixth transistor is an N-type field-effect transistor.

6. The charge pump circuit according to claim 4, wherein, The second drive module includes: The third and fourth inverters, the input of the third inverter is used to receive the second clock signal, and the output of the third inverter is coupled to the input of the fourth inverter. A seventh and eighth transistor are coupled between the reference voltage and ground, the control terminals of the seventh and eighth transistors are coupled to the output terminal of the fourth inverter, and the common terminal of the seventh and eighth transistors serves as the output terminal of the second voltage; The seventh transistor is a P-type field-effect transistor, and the eighth transistor is an N-type field-effect transistor.

7. The charge pump circuit according to claim 4, wherein, The first clock signal and the second clock signal are differential clock signals.

8. The charge pump circuit according to any one of claims 1-7, wherein, The first transistor and the second transistor are N-type field-effect transistors, and the third transistor and the fourth transistor are P-type field-effect transistors.

9. A chip, wherein, Includes the charge pump circuit according to any one of claims 1-8.

10. A communication terminal, wherein, Includes the charge pump circuit according to any one of claims 1-8, or the chip according to claim 9.

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