Multi-link receiving method and multi-link receiver

Abstract

The present invention provides a multi-link reception method and a multi-link receiver. The method includes: determining a reference delay range for the jth data segment based on a preset delay time and the reception time of the jth data segment of the i-th data frame; in response to determining that the jth data segment is the first of N data segments of the i-th data frame to be received, using the reference delay range for the j-th data segment as a designated delay range; and in response to determining that the reception time of each data segment of the i-th data frame is within the designated delay range, restoring the i-th data frame based on the N data segments of the i-th data frame. This method can easily achieve the effect of managing differential delays in a multi-link transmission mechanism.

Description

Technical Field

[0001] The present invention relates to a multi-link communication mechanism, and more particularly to a multi-link receiving method and a multi-link receiver. Background Art

[0002] In addition to the advantage of using lower line speeds to transmit larger bandwidths, the multi-link transmission mechanism also offers the advantages of link protection and load balancing, and is therefore widely used in communication systems.

[0003] Please refer to Figures 1A to 1C ,in Figure 1A This is the existing multi-link transmission mechanism diagram, Figure 1B It is a schematic diagram of dividing the data frame into data segments. Figure 1C This is a diagram showing how data segments are transmitted via multiple link channels. Figures 1A to 1C In the embodiment, a multi-link channel 103 may exist between the multi-link transmitter 101 and the multi-link receiver 102. In one embodiment, assuming that the multi-link channel 103 includes a total of N link channels (N is a positive integer), when the multi-link transmitter 101 wishes to send a data frame (denoted by FX) to the multi-link receiver 102, the data frame may be divided into N data segments link_1[X] to link_N[X], and the N data segments may be sent to the multi-link receiver 102 via the N link channels.

[0004] For example, assuming that the multi-link transmitter 101 wants to send a data frame F1 to the multi-link receiver 102, the multi-link transmitter 101 may first divide the data frame F1 into N data segments link_1[1]-link_N[1], and then send the data segments link_1[1]-link_N[1] to the multi-link receiver 102 via the N link channels. Similarly, when the multi-link transmitter 101 wants to send a data frame F2, it may also divide the data frame F2 into data segments link_1[2]-link_N[2], and then send the data segments link_1[2]-link_N[2] to the multi-link receiver 102 via the N link channels. In addition, when the multi-link transmitter 101 wants to send a data frame FM, it may also divide the data frame FM into data segments link_1[M]-link_N[M], and then send the data segments link_1[M]-link_N[M] to the multi-link receiver 102 through the N link channels.

[0005] Please refer to Figure 2 , which is based on Figures 1A to 1C A schematic diagram of the multi-link receiving mechanism is shown. Figure 2In the multi-link receiver 102, a receiving interface 102a, a buffer 102b, a reassembly circuit 102c, and a differential delay control management (DDCM) circuit 102d are included. Generally, data segments link_1[X]-link_N[X] arrive at the receiving interface 102a via different transmission paths. Therefore, there will be a difference in the time it takes for the data segments link_1[X]-link_N[X] to arrive at the receiving interface 102a (commonly known as differential delay). In this case, the buffer 102b can be used to temporarily store the data segments link_1[X]-link_N[X], while the reassembly circuit 102c and the DDCM circuit 102d can work together to combine the data segments link_1[X]-link_N[X] to restore the data frame FX.

[0006] As can be seen from the above, the DDCM mechanism is very important in multi-link transmission systems. However, due to the complexity of the DDCM mechanism, if it is not properly implemented, it may cause additional delays and packet loss. Summary of the Invention

[0007] In view of this, the present invention provides a multi-link receiving method and a multi-link receiver, which can be used to solve the above technical problems.

[0008] The present invention provides a multi-link receiving method, suitable for a multi-link receiver, comprising: in response to determining that a j-th data segment belonging to an i-th data frame is received, determining a reference delay range for the j-th data segment of the i-th data frame based on a predetermined delay time and a reception time point of the j-th data segment of the i-th data frame, wherein the i-th data frame includes N data segments, 1≤j≤N, i is an index value, and N is a positive integer; in response to determining that the j-th data segment of the i-th data frame is the first of the N data segments of the i-th data frame to be received, using the reference delay range for the j-th data segment of the i-th data frame as a designated delay range corresponding to the i-th data frame; and in response to determining that the reception time points of the data segments of the i-th data frame are all within the designated delay range corresponding to the i-th data frame, restoring the i-th data frame based on the N data segments of the i-th data frame.

[0009] The present invention provides a multi-link receiver, comprising a receiving circuit and a processing circuit. The receiving circuit receives a j-th data segment belonging to an i-th data frame. The processing circuit is coupled to the receiving circuit and configured to: determine a reference delay range for the j-th data segment of the i-th data frame based on a predetermined delay time and a reception time point of the j-th data segment of the i-th data frame, wherein the i-th data frame includes N data segments, 1≤j≤N, i is an index value, and N is a positive integer; in response to determining that the j-th data segment of the i-th data frame is the first of the N data segments of the i-th data frame to be received, use the reference delay range for the j-th data segment of the i-th data frame as a designated delay range corresponding to the i-th data frame; and in response to determining that the reception time points of each of the data segments of the i-th data frame are within the designated delay range corresponding to the i-th data frame, restore the i-th data frame based on the N data segments of the i-th data frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0011] Figure 1A This is a diagram of the existing multi-link transmission mechanism.

[0012] Figure 1B It is a schematic diagram of dividing the data frame into data segments.

[0013] Figure 1C It is a schematic diagram of transmitting data segments through multiple link channels.

[0014] Figure 2 is based on Figures 1A to 1C A schematic diagram of the multi-link receiving mechanism is shown.

[0015] Figure 3 FIG. 4 is a schematic diagram of a multi-link transmission system according to an embodiment of the present invention.

[0016] Figure 4 FIG. 4 is a flow chart of a multi-link receiving method according to an embodiment of the present invention.

[0017] Figure 5 It is an application scenario diagram drawn according to an embodiment of the present invention.

[0018] Figure 6 is based on Figure 5 Another application scenario diagram is shown.

[0019] Figure 7 FIG. 4 is a schematic diagram of a multi-link receiver according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0021] Please refer to Figure 3 , which is a schematic diagram of a multi-link transmission system according to an embodiment of the present invention. Figure 3 In the embodiment, the multi-link transmission system 30 includes, for example, a multi-link transmitter 101 and a multi-link receiver 310. The multi-link transmitter 101 can transmit N data segments divided from a data frame to the multi-link receiver 310 via a multi-link channel 103. In this embodiment, the details of the multi-link transmitter 101 and the multi-link channel 103 can be found in the previous description and are not further described here.

[0022] In one embodiment, the multi-link receiver 310 includes a receiving circuit 312 and a processing circuit 314, wherein the processing circuit 314 is coupled to the receiving circuit 312. In an embodiment of the present invention, the receiving circuit 312 and the processing circuit 314 can work together to implement the multi-link receiving method proposed by the present invention, which is described in detail below.

[0023] Please refer to Figure 4 , which is a flow chart of a multi-link receiving method according to an embodiment of the present invention. The method of this embodiment can be Figure 3 The multi-link receiver 310 executes the following: Figure 3 Description of components shown Figure 4 In addition, in order to make the present invention easier to understand, the following will be supplemented with Figure 5 To further explain, Figure 5 It is an application scenario diagram drawn according to an embodiment of the present invention.

[0024] First, in Figure 5 In this scenario, assume that the multi-link transmitter 101 divides the i-th data frame into N data segments and then transmits the N data segments of the i-th data frame to the multi-link receiver 310 via the multi-link channel 103. For ease of explanation, N is assumed to be 3, and the j-th data segment of the i-th data frame can be represented as link_j[i], but the present invention is not limited to this.

[0025] In step S410, the receiving circuit 312 receives the jth data segment of the i-th data frame. Then, in step S420, the processing circuit 314 determines a reference delay range for the jth data segment of the i-th data frame based on the predetermined delay time and the reception time of the jth data segment of the i-th data frame.

[0026] For example, in Figure 5 In the scenario, after the receiving circuit 312 receives the data segment link_2[i] (i.e., the second data segment of the i-th data frame), the processing circuit 314 may determine the reference delay range R2 of the data segment link_2[i] according to the preset delay time R and the receiving time point of the data segment link_2[i]. i .

[0027] In one embodiment, assuming that the preset delay time is R and the receiving time point of the data segment link_2[i] is T2 i , the processing circuit 314 may for example convert T2 i and T2 i +R is the reference delay range R2 of data segment link_2[i] i In different embodiments, the designer can select an appropriate R value according to needs.

[0028] In addition, for other data segments of the i-th data frame, the processing circuit 314 can also determine corresponding reference delay ranges for these data segments individually. For example, after the receiving circuit 312 receives the data segment link_3[i] (i.e., the third data segment of the i-th data frame), the processing circuit 314 can determine the reference delay range R3 of the data segment link_3[i] based on the preset delay time R and the reception time point of the data segment link_3[i]. i Assume that the receiving time of data segment link_3[i] is T3 i , the processing circuit 314 may, for example, i and T3 i +R is the reference delay range R3 of data segment link_3[i] i lower and upper limits.

[0029] Then, in step S430, in response to determining that the j-th data segment of the i-th data frame is the first received data segment among the N data segments of the i-th data frame, the processing circuit 314 uses the reference delay range of the j-th data segment of the i-th data frame as the designated delay range SR corresponding to the i-th data frame. i That is, the processing circuit 314 can find the data segment first received by the multi-link receiver 310 among the N data segments of the i-th data frame, and then use the reference delay range corresponding to this data segment as the specified delay range SR corresponding to the i-th data frame. i .

[0030] exist Figure 5In the scenario, assuming that the data segment link_2[i] is the first of the N data segments of the i-th data frame received by the multi-link receiver 310, the processing circuit 314 may use the reference delay range R2 of the data segment link_2[i]. i As the specified delay range SR corresponding to the i-th data frame i That is, when the data segment link_2[i] precedes other data segments (eg, data segment link_3[i]) of the i-th data frame, the processing circuit 314 may set the reference delay range R2 of the data segment link_2[i] to i Defined as a specified delay range SR i .

[0031] In other embodiments, if the data segment link_3[i] precedes other data segments (eg, data segment link_2[i]) in the i-th data frame, the processing circuit 314 may set the reference delay range R3 of the data segment link_3[i] to i Defined as a specified delay range SR i , but is not limited to this.

[0032] Afterwards, the processing circuit 314 may determine whether the receiving time points of each data segment of the i-th data frame are all within the specified delay range SR corresponding to the i-th data frame. i middle.

[0033] exist Figure 5 In this scenario, assume that the first data segment link_1[i] (not shown) of the i-th data frame cannot be received by the receiving circuit 312 for some reason. In other words, the processing circuit 314 cannot obtain the reception time point of the data segment link_1[i]. In this case, the processing circuit 314 can determine that the reception time points of the data segments of the i-th data frame are not all within the specified delay range SR corresponding to the i-th data frame. i In this case, the processing circuit 314 may ignore each data segment of the i-th data frame and not restore the i-th data frame. In addition, the processing circuit 314 may also generate an alarm corresponding to the i-th data frame to record that the i-th data frame has not been successfully reassembled and restored.

[0034] On the other hand, in response to determining that the receiving time points of each data segment of the i-th data frame are all within the specified delay range SR corresponding to the i-th data frame, i In the embodiment of the present invention, the processing circuit 314 may execute step S440 accordingly.

[0035] In step S440 , in response to determining that the receiving time points of each data segment of the i-th data frame are all within the designated delay range corresponding to the i-th data frame, the processing circuit 314 restores the i-th data frame based on the N data segments of the i-th data frame.

[0036] In one embodiment, it is assumed that the receiving time points of the data segments link_1[i] and link_3[i] are both within the specified delay range SR i In the example, the processor 314 can reassemble the data segments link_1[i]-link_3[i] to restore the i-th data frame.

[0037] For data segments of other data frames from the multi-link sender 101 , the multi-link receiver 310 may also perform corresponding operations based on the above teachings.

[0038] For example, assume that the multi-link transmitter 101 divides the (i+1)th data frame into N data segments and then transmits the N data segments of the (i+1)th data frame to the multi-link receiver 310 via the multi-link channel 103. For ease of explanation, it is assumed below that the j-th data segment of the (i+1)th data frame can be represented as link_j[i+1], but the present invention is not limited thereto.

[0039] Figure 5 In this scenario, the processing circuit 314 may determine corresponding reference delay ranges for the data segments link_1[i+1] to link_3[i+1] received by the receiving circuit 312. For example, after the receiving circuit 312 receives the data segment link_1[i+1] (i.e., the first data segment of the i+1th data frame), the processing circuit 314 may determine the reference delay range R1 for the data segment link_1[i+1] based on the predetermined delay time R and the reception time point of the data segment link_1[i+1]. i+1 Assume that the receiving time of data segment link_1[i+1] is T1 i+1 , the processing circuit 314 may, for example, i+1 and T1 i+1 +R is the reference delay range R1 of data segment link_1[i+1] i+1 Based on the similarity principle, the processing circuit 314 can accordingly determine the reference delay ranges corresponding to the data segments link_2[i+1] and link_3[i+1].

[0040] exist Figure 5In the scenario, since the data segment link_1[i+1] is received earliest by the multi-link receiver 310 among the data segments link_1[i+1] to link_3[i+1], the processing circuit 314 can set the reference delay range R1 of the data segment link_1[i+1] to i+1 Defined as the specified delay range SR corresponding to the i+1th data frame i+1 Afterwards, the processing circuit 314 may determine whether the receiving time points of each data segment link_1[i+1] to link_3[i+1] are all within the specified delay range SR i+1 middle.

[0041] exist Figure 5 Since the receiving time points of each data segment link_1[i+1]~link_3[i+1] are all within the specified delay range SR i+1 Therefore, the processing circuit 314 can accordingly reassemble the data segments link_1[i+1]-link_3[i+1] to restore the i+1th data frame.

[0042] In addition, for the data segments link_1[i+2] to link_3[i+2] corresponding to the i+2th data frame, the processing circuit 314 may set the reference delay range R3 of the data segment link_3[i+2] to i+2 Defined as the specified delay range SR corresponding to the i+2th data frame i+2 Afterwards, the processing circuit 314 may determine whether the receiving time points of each data segment link_1[i+2] to link_3[i+2] are all within the specified delay range SR i+2 Since the receiving time points of each data segment link_1[i+2]~link_3[i+2] are all within the specified delay range SR i+2 Therefore, the processing circuit 314 can accordingly reassemble the data segments link_1[i+2]-link_3[i+2] to restore the i+2th data frame. The relevant details can be referred to the previous embodiment and will not be repeated here.

[0043] In one embodiment, the receiving circuit 312 may further receive the nth data segment belonging to the mth data frame, wherein the mth data frame includes N data segments, 1≤n≤N, m is an index value, and m is greater than i. Thereafter, the processing circuit 314 may determine whether the receiving time point of the nth data segment of the mth data frame is within the specified delay range SR corresponding to the i-th data frame. i middle.

[0044] In one embodiment, in response to determining that the receiving time point of the nth data segment of the mth data frame is within a specified delay range SR corresponding to the i-th data frame, i In order to make the above contents easier to understand, the following is supplemented with Figure 6 Give explanation.

[0045] Please refer to Figure 6 , which is based on Figure 5 Another application scenario diagram is shown. Figure 6 In the example, it is assumed that the value of m is i+1, but the present invention is not limited thereto. In this case, after the receiving circuit 312 receives any of the data segments link_1[i+1] to link_3[i+1], the processing circuit 314 may determine whether the receiving time point of any of the data segments link_1[i+1] to link_3[i+1] is within the specified delay range SR corresponding to the i-th data frame. i middle.

[0046] exist Figure 6 In this scenario, it is assumed that the receiving time point of the data segment link_1[i+1] (ie, T1 i+1 ) is within the specified delay range SR i , the processing circuit 314 may ignore the data segments link_1[i]-link_3[i] of the i-th data frame and may not restore the i-th data frame. In addition, the processing circuit 314 may also generate an alarm corresponding to the i-th data frame to record that the i-th data frame has not been successfully reassembled and restored.

[0047] In short, if the receiving time point of the data segment of the subsequent data frame falls within the designated delay range corresponding to the previous data frame, the processing circuit 314 may ignore the data segments of the previous data frame and generate an alarm, but is not limited thereto.

[0048] In other embodiments, in response to determining that the receiving time point of the nth data segment of the mth data frame is not within the specified delay range SR corresponding to the i-th data frame, i In the example, the processing circuit 314 may determine a reference delay range of the nth data segment of the mth data frame according to a predetermined delay time (ie, R) and a receiving time point of the nth data segment of the mth data frame.

[0049] Then, in response to determining that the nth data segment of the mth data frame is the first of the N data segments of the mth data frame to be received, the processing circuit 314 uses the reference delay range of the nth data segment of the mth data frame as the designated delay range corresponding to the mth data frame. Next, in response to determining that the reception time points of each of the data segments of the mth data frame are all within the designated delay range corresponding to the mth data frame, the processing circuit 314 restores the mth data frame based on the N data segments of the mth data frame.

[0050] Furthermore, in response to determining that the reception time points of the data segments of the m-th data frame are not all within the specified delay range corresponding to the m-th data frame, the processing circuit 314 may ignore the N data segments of the m-th data frame, but the present invention is not limited thereto. For related details, please refer to the description of the previous embodiment and will not be repeated here.

[0051] Please refer to Figure 7 , which is a schematic diagram of a multi-link receiver according to an embodiment of the present invention. Figure 7 In the embodiment, the receiving circuit 312 of the multi-link receiver 310 may include a receiving interface 71 and N indicator generators 721 - 72N, and the processing circuit 314 may include N first range determination circuits 731 - 73N, a determination circuit 76 , a second range determination circuit 74 and a restoration circuit 75 .

[0052] exist Figure 7 In the embodiment, the indicator generators 721-72N correspond to the N data segments link_1[i]-link_N[i] of the i-th data frame Fi, respectively. In one embodiment, the receiving interface 71 is coupled to the indicator generators 721-72N and triggers the j-th indicator generator among the indicator generators 721-72N to generate an indicator after receiving the j-th data segment of the i-th data frame Fi from the multi-link transmitter 101. The time at which the j-th indicator generator generates the indicator corresponds to the reception time of the j-th data segment of the i-th data frame Fi.

[0053] For example, when the receiving interface 71 receives the data segment link_1[i] (i.e., the first data segment of the i-th data frame Fi) from the multi-link transmitter 101, the receiving interface 71 may trigger the indicator generator 721 (i.e., the first indicator generator among the indicator generators 721-72N) to generate the indicator D1i, wherein the generation time of the indicator D1i may correspond to the reception time point of the data segment link_1[i]. In addition, when the receiving interface 71 receives the data segment link_2[i] (i.e., the second data segment of the i-th data frame Fi) from the multi-link transmitter 101, the receiving interface 71 may trigger the indicator generator 722 (i.e., the second indicator generator among the indicator generators 721-72N) to generate the indicator D2i, wherein the generation time of the indicator D2i may correspond to the reception time point of the data segment link_2[i] (e.g., Figure 5 T2 i Furthermore, when the receiving interface 71 receives the data segment link_N[i] (i.e., the second data segment of the i-th data frame Fi) from the multi-link transmitter 101, the receiving interface 71 may trigger the indicator generator 72N (i.e., the N-th indicator generator among the indicator generators 721-72N) to generate the indicator DNi, where the generation time of the indicator DNi may correspond to the reception time point of the data segment link_N[i].

[0054] exist Figure 7 In the embodiment, the first range determination circuits 731-73N are respectively coupled to the indicator generators 721-72N. In one embodiment, the j-th range determination circuit among the first range determination circuits 731-73N determines a reference delay range for the j-th data segment of the i-th data frame Fi according to the predetermined delay time (i.e., R) and the reception time point of the j-th data segment of the i-th data frame Fi in response to the indicator of the j-th indicator generator.

[0055] For example, the first range determination circuit 731 may determine the reference delay range R1 of the data segment link_1[i] according to the predetermined delay time (i.e., R) and the receiving time point of the data segment link_1[i] of the i-th data frame Fi in response to the indicator D1i of the indicator generator 721. i In addition, the first range determination circuit 732 may respond to the indicator D2i of the indicator generator 722 according to the preset delay time (ie, R) and the receiving time point of the data segment link_2[i] of the i-th data frame Fi (eg Figure 5 T2 i ) determines the reference delay range of data segment link_1[i] (e.g. Figure 5 Reference delay range R2 iFurthermore, the first range determination circuit 73N may determine the reference delay range RN of the data segment link_N[i] according to the predetermined delay time (i.e., R) and the receiving time point of the data segment link_N[i] of the i-th data frame Fi in response to the indicator DNi of the indicator generator 72N. i .

[0056] In one embodiment, the determination circuit 76 is coupled to the indicator generators 721-72N and can find the earliest generated indicator (which corresponds to the earliest received data segment) based on the generation time point of the indicators D1i-DNi (i.e., the reception time point of the data segments link_1[i]-link_N[i]).

[0057] In one embodiment, in response to determining that the jth indicator generator generates indicators before other indicator generators, the determination circuit 76 may determine that the jth data segment of the i-th data frame Fi is the first received data segment among the N data segments link_1[i]-link_N[i] of the i-th data frame Fi.

[0058] For example, if the determination circuit 76 determines that the indicator generator 721 generates the indicator D1i before the other indicator generators, the determination circuit 76 may accordingly determine that the data segment link_1[i] is the first one among the data segments link_1[i]-link_N[i] to be received by the multi-link receiver 310 (i.e., the data segment link_1[i] is the earliest one among the data segments link_1[i]-link_N[i] to be received by the multi-link receiver 310). For another example, if the determination circuit 76 determines that the indicator generator 722 generates the indicator D2i before the other indicator generators, the determination circuit 76 may accordingly determine that the data segment link_2[i] is the first one among the data segments link_1[i]-link_N[i] to be received by the multi-link receiver 310 (i.e., the data segment link_2[i] is the earliest one among the data segments link_1[i]-link_N[i] to be received by the multi-link receiver 310). In addition, assuming that the judgment circuit 76 determines that the indicator generator 72N generates the indicator D2N before the other indicator generators, the judgment circuit 76 can accordingly determine that the data segment link_N[i] is the first one among the data segments link_1[i] to link_N[i] to be received by the multi-link receiver 310 (that is, the data segment link_N[i] is the earliest one among the data segments link_1[i] to link_N[i] to be received by the multi-link receiver 310).

[0059] In one embodiment, the second range determination circuit 74 is coupled to the indicator generators 721-72N and may use the reference delay range of the j-th data segment as the designated delay range corresponding to the i-th data frame Fi after the determination circuit 76 determines that the j-th data segment of the i-th data frame Fi is the first received data segment among the N data segments link_1[i]-link_N[i] of the i-th data frame Fi.

[0060] by Figure 5 For example, since the data segment link_2[i] is determined to be the first one among the data segments link_1[i] to link_N[i] to be received by the multi-link receiver 310, the second range determination circuit 74 may use the reference delay range R2 of the data segment link_2[i]. i As the specified delay range SR corresponding to the i-th data frame Fi i .

[0061] Then, the second range determination circuit 74 can determine whether the receiving time points of each data segment link_1[i]-link_N[i] of the i-th data frame Fi are all within the specified delay range SR corresponding to the i-th data frame Fi. i If so, the second range determination circuit 74 may provide the first command C1 to the restoration circuit 75 , otherwise, the second range determination circuit 74 may provide the second command C2 to the restoration circuit 75 .

[0062] In one embodiment, the restoration circuit 75 is coupled to the second range determination circuit 74 and the indicator generators 721-72N, and restores the i-th data frame Fi based on the data segments link_1[i]-link_N[i] of the i-th data frame Fi in response to the first command C1. On the other hand, if the restoration circuit 75 receives the second command C2 from the second range determination circuit 74, the restoration circuit 75 may ignore the data segments link_1[i]-link_N[i] of the i-th data frame Fi in response to the second command C2 and may provide a corresponding alarm ALM, but the present invention is not limited thereto.

[0063] In the embodiment of the present invention, the details of the operations performed by the first range determination circuits 731 - 73N, the determination circuit 76 , the second range determination circuit 74 and the restoration circuit 75 can be referred to the description in the previous embodiment and will not be repeated here.

[0064] In summary, after receiving multiple data segments belonging to the same data frame transmitted via multiple links, embodiments of the present invention can use the earliest received data segment to determine the designated delay range corresponding to the data frame. Subsequently, upon determining that all data segments belonging to the same data frame have been received within the designated delay range, embodiments of the present invention can reassemble these data segments to restore the data frame. On the other hand, if the data segments belonging to the same data frame are not received within the designated delay range, embodiments of the present invention can ignore these data segments and provide a corresponding alert. Thus, embodiments of the present invention provide a simple and easily implemented DDCM mechanism that can easily achieve the effect of managing differential delays in a multi-link transmission mechanism.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-link receiving method, suitable for a multi-link receiver, characterized in that: include: In response to determining that a j-th data segment belonging to an i-th data frame is received, determining a reference delay range for the j-th data segment of the i-th data frame according to a predetermined delay time and a reception time point of the j-th data segment of the i-th data frame, wherein the i-th data frame includes N data segments, 1≤j≤N, i is an index value, and N is a positive integer; In response to determining that the j-th data segment of the i-th data frame is the first of the N data segments of the i-th data frame to be received, using the reference delay range of the j-th data segment of the i-th data frame as a designated delay range corresponding to the i-th data frame; In response to determining that a reception time point of each of the data segments of the i-th data frame is within the designated delay range corresponding to the i-th data frame, restoring the i-th data frame based on the N data segments of the i-th data frame; receiving an nth data segment belonging to an mth data frame, wherein the mth data frame includes N data segments, 1≤n≤N, m is an index value and m is greater than i; In response to determining that a reception time point of the nth data segment of the mth data frame is within the designated delay range corresponding to the ith data frame, the N data segments of the ith data frame are ignored.

2. The method according to claim 1, further comprising: In response to determining that the receiving time points of the N data segments of the i-th data frame are not all located within the designated delay range corresponding to the i-th data frame, the N data segments of the i-th data frame are ignored.

3. The method according to claim 1, further comprising: In response to determining that a reception time point of the nth data segment of the mth data frame is not within the designated delay range corresponding to the i-th data frame, determining a reference delay range for the nth data segment of the mth data frame according to the predetermined delay time and the reception time point of the nth data segment of the mth data frame; In response to determining that the nth data segment of the mth data frame is the first of the N data segments of the mth data frame to be received, using the reference delay range of the nth data segment of the mth data frame as a designated delay range corresponding to the mth data frame; In response to determining that reception time points of the data segments of the mth data frame are all within the designated delay range corresponding to the mth data frame, the mth data frame is restored based on the N data segments of the mth data frame.

4. A multi-link receiver, characterized in that: include: a receiving circuit for receiving a j-th data segment belonging to an i-th data frame; a processing circuit coupled to the receiving circuit and configured to: determining a reference delay range of the j-th data segment of the i-th data frame according to a predetermined delay time and a receiving time point of the j-th data segment of the i-th data frame, wherein the i-th data frame includes N data segments, 1≤j≤N, i is an index value, and N is a positive integer; In response to determining that the j-th data segment of the i-th data frame is the first of the N data segments of the i-th data frame to be received, using the reference delay range of the j-th data segment of the i-th data frame as a designated delay range corresponding to the i-th data frame; In response to determining that a reception time point of each of the data segments of the i-th data frame is within the designated delay range corresponding to the i-th data frame, restoring the i-th data frame based on the N data segments of the i-th data frame; wherein the receiving circuit receives an nth data segment belonging to an mth data frame, wherein the mth data frame includes N data segments, 1≤n≤N, m is an index value and m is greater than i; In response to the processing circuit determining that the reception time point of the nth data segment of the mth data frame is within the designated delay range corresponding to the i-th data frame, the processing circuit ignores the N data segments of the i-th data frame.

5. The multi-link receiver according to claim 4, wherein the receiving circuit comprises: N indicator generators, wherein the N indicator generators correspond to the N data segments of the i-th data frame respectively; a receiving interface coupled to the N indicator generators and triggering a j-th indicator generator among the N indicator generators to generate an indicator after receiving the j-th data segment belonging to the i-th data frame from the multi-link sender, wherein the time at which the j-th indicator generator generates the indicator corresponds to the receiving time point of the j-th data segment of the i-th data frame.

6. The multi-link receiver of claim 5 , wherein the processing circuit comprises: N first range determination circuits are respectively coupled to the N indicator generators, wherein the j-th range determination circuit among the N first range determination circuits determines the reference delay range of the j-th data segment of the i-th data frame according to the preset delay time and the receiving time point of the j-th data segment of the i-th data frame in response to the indicator of the j-th indicator generator.

7. The multi-link receiver of claim 5 , wherein the processing circuit comprises: A determination circuit, coupled to the N indicator generators, is configured to: In response to determining that the j-th indicator generator generates the indicator before the other indicator generators, the j-th data segment of the i-th data frame is determined to be the first received among the N data segments of the i-th data frame.

8. The multi-link receiver of claim 5, wherein the processing circuit comprises: A second range determination circuit is coupled to the N indicator generators and is configured to: using the reference delay range of the j-th data segment of the i-th data frame as the designated delay range corresponding to the i-th data frame; providing a first command in response to determining that the receiving time points of the data segments of the i-th data frame are all within the designated delay range corresponding to the i-th data frame; The restoration circuit is coupled to the second range determination circuit and the N indicator generators, and restores the i-th data frame based on the N data segments of the i-th data frame in response to the first command.

9. The multi-link receiver according to claim 8, wherein: providing a second command to the restoration circuit in response to the second range determination circuit determining that the reception time points of the N data segments of the i-th data frame are not all within the designated delay range corresponding to the i-th data frame; The restoration circuit ignores the N data segments of the i-th data frame in response to the second command.

10. The multi-link receiver of claim 4, wherein the processing circuit is further configured to: In response to determining that a reception time point of the nth data segment of the mth data frame is not within the designated delay range corresponding to the i-th data frame, determining a reference delay range for the nth data segment of the mth data frame according to the predetermined delay time and the reception time point of the nth data segment of the mth data frame; In response to determining that the nth data segment of the mth data frame is the first of the N data segments of the mth data frame to be received, using the reference delay range of the nth data segment of the mth data frame as a designated delay range corresponding to the mth data frame; In response to determining that reception time points of the data segments of the mth data frame are all within the designated delay range corresponding to the mth data frame, the mth data frame is restored based on the N data segments of the mth data frame.

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