Transceiver with multi-channel clear channel assessment

Abstract

A wireless network device configured to monitor multiple channels for clear channel assessment (CCA) is disclosed. The receiver circuit of the network device includes at least one CCA block for indicating whether a particular channel is clear. In some embodiments, the network device sequentially checks each channel and transmits at least one data packet if both channels are clear. The at least one data packet can include a mode switch data packet and a second data packet transmitted using a new PHY mode. The network device can also have multiple CCA blocks. In this case, the channels can be checked simultaneously and the network device transmits at least one data packet if both channels are clear. Alternatively, the network device simultaneously monitors multiple channels and selects one of the channels to transmit a preferred PHY mode on that channel, thereby avoiding the need for a mode switch data packet.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application 17 / 532,343, filed November 22, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure describes systems and methods for transmitting data packets over a shared medium using multiple frequency channels. Background Technology

[0004] Various wireless network protocols support multiple channels, and moreover, they can support more than one PHY mode. For example, when using the same modulation type (such as Frequency Shift Keying (FSK)), the PHY modes may differ, but the data rates or coding schemes may also differ. When using different modulation types (e.g., FSK and Orthogonal Frequency Division Multiplexing (OFDM)), the PHY modes may also differ, where the data rates between the two different PHY modes may be different or the same. With multiple channels and PHY modes used in a single network, Clear Channel Assessment (CCA) becomes more complex. Multiple PHY modes may require different channel center frequencies and different channel bandwidths. For example, some network protocols (such as IEEE 802.15.4-2020 and WiSUN FAN 1.1) specify mode-switching schemes, where the transmitter can transmit a first data packet (called a mode-switching packet) that informs the receiver that a different PHY mode will be used to transmit the next data packet.

[0005] Using traditional CCA (Concurrent Mode Acquisition) can result in the transmission of mode switching packets without the subsequent transmission of new PHY mode packets. This wastes energy on both sides of the link. In addition to energy waste, it also negatively impacts network capacity, latency, and throughput.

[0006] In a conventional CCA scheme, the first CCA needs to succeed before the mode switching packet transmission, and the second CCA needs to succeed before the new PHY mode packet transmission. In WiSUN, the channel for the mode switching packet using the basic PHY can be different from the channel for the new PHY mode packet using the new PHY mode. In other words, they may have different center frequencies and / or different bandwidths. The channels can completely or partially overlap, or they can be completely separate without overlap. A conventional CCA will be performed with the channel filter's center frequency and bandwidth tuned to the channel it wants to transmit on. In the WiSUN mode switching scheme, the channel filter may need to be tuned differently before the CCA of the new PHY mode packet. This may result in interference being filtered out during the first CCA, while the same interference may fall into the passband of the channel filter during the second CCA. This could result in the first CCA succeeding, allowing the mode switching packet transmission, and the second CCA failing, meaning the channel allocated to the new PHY mode is occupied and the new PHY mode packet cannot be transmitted. In this case, because there is no data payload in the mode switching packet, the energy used to transmit the mode switching packet can be considered wasted. Moreover, in this situation, the propagation time of transmission mode switching packets may cause other nodes to delay their transmission, resulting in reduced network traffic capacity, increased latency, and reduced throughput.

[0007] Another problem is that all nodes that receive the mode switch packet may become inaccessible for a period of time because each node may have already switched its receiver to the new PHY mode. Other nodes may not be aware of this and may attempt to transmit using the underlying PHY, which may not be received because the receiving node may have configured its receiver for the new PHY mode. This will further reduce network capacity, increase latency, and decrease throughput.

[0008] Therefore, it would be beneficial if a transceiver existed that could more efficiently handle multiple channels and PHY modes. Furthermore, it would be advantageous if the transceiver could efficiently switch between these different PHY modes.

[0009] Furthermore, avoiding the need for mode-switching packets would be beneficial. The disadvantage of mode-switching packets stems from the lack of encryption and addressing. Because they are not encrypted, they are vulnerable to attacks from malicious sources. For example, by transmitting malicious mode-switching packets, receiving nodes could switch their PHY modes and become unavailable to the network. Moreover, since mode-switching packets lack any addressing, any receiving node can exploit them. Summary of the Invention

[0010] A wireless network device configured to monitor multiple channels for clear channel assessment (CCA) is disclosed. The receiver circuitry of the network device includes at least one CCA block for indicating whether a particular channel is idle. In some embodiments, the network device sequentially checks each channel, and if both channels are idle, it transmits at least one data packet. The at least one data packet may include a mode-switching data packet and a second data packet transmitted using the new PHY mode. The network device may also have multiple CCA blocks. In this case, channels can be checked simultaneously, and if both channels are idle, the network device transmits at least one data packet. Alternatively, the network device may monitor multiple channels simultaneously and select one of the channels to transmit a preferred PHY mode on that channel, thereby avoiding the need for a mode-switching data packet. The selection of the preferred PHY mode may be based on data rate, link budget, range, noise level, channel characteristics, or other metrics.

[0011] According to one embodiment, a network device for transmitting data packets using multiple channels is disclosed. The network device includes a transceiver comprising: receiver circuitry, transmission circuitry, and a channel access controller. The receiver circuitry includes at least one Free Channel Assessment (CCA) block for determining whether a channel is free. The transmission circuitry is adapted to transmit data packets on any of the multiple channels. The channel access controller controls the receiver circuitry to perform free channel tests on at least two of the multiple channels during a first time period, and controls the transmission circuitry to transmit at least one data packet on a free channel during a second time period after the first time period. In some embodiments, the free channel tests are performed sequentially during the first time period, and the network device transmits at least two data packets using two different free channels during the second time period. In some embodiments, the first data packet includes a mode-switching data packet transmitted using a first PHY mode, and the second data packet includes a data packet using a second PHY mode. In some embodiments, the CCA block includes a channel filter having a programmable frequency and bandwidth, and the channel access controller configures the channel filter such that the bandwidth of the channel filter covers a frequency range combining at least two of the multiple channels.

[0012] In some embodiments, the receiver circuitry includes a channel filter with a programmable frequency and bandwidth. A channel access controller configures the channel filter for a first channel, waits for the completion of a first idle channel test, configures a channel filter for a second channel, and waits for the completion of a second idle channel test before transmitting at least one data packet. In some embodiments, each failed idle channel test is followed by an adjustment and retry of a backoff delay, where the backoff delay represents the time between the completion of a failed idle channel test and the initiation of an idle channel test retry. In some embodiments, the receiver circuitry includes a local oscillator and a channel filter with a programmable bandwidth. The channel access controller configures the bandwidth of the local oscillator and the channel filter to tune the receiving frequency to the first channel, waits for the completion of the first idle channel test, configures the bandwidth of the local oscillator and the channel filter to tune the receiving frequency to the second channel, and waits for the completion of a second idle channel test before transmitting at least one data packet on the idle channel. In some embodiments, each of the plurality of channels uses a different PHY mode.

[0013] According to another embodiment, a network device for transmitting data packets using multiple channels is disclosed. The network device includes a transceiver comprising: receiver circuitry, transmission circuitry, and a channel access controller. The receiver circuitry includes multiple free channel assessment (CCA) blocks configured to operate simultaneously. The transmission circuitry is adapted to transmit data packets on any of the multiple different channels. The channel access controller controls the receiver circuitry to perform free channel assessment on at least two of the multiple different channels during a first time period, and controls the transmission circuitry to transmit at least one data packet on a free channel after the first time period and during a second time period. In some embodiments, the network device transmits at least two data packets during the second time period, using two different channels. In some embodiments, the first data packet includes a mode-switching data packet transmitted using a first PHY mode, and the second data packet includes a data packet using a second PHY mode. In some embodiments, each CCA block includes a channel filter having a programmable frequency and bandwidth, and the channel access controller configures the multiple channel filters before performing free channel assessment. In some embodiments, each CCA block includes a channel filter with a programmable frequency and bandwidth. The channel access controller processes the CCA blocks simultaneously, such that the channel access controller configures a first channel filter for a first channel, configures a second channel filter for a second channel, enables receiver circuitry, and waits for idle channel evaluation of both channels to complete before transmitting at least one data packet. In some embodiments, each of the multiple different channels uses a different PHY mode.

[0014] According to another embodiment, a network device for transmitting data packets using two different channels is disclosed. The network device includes a transceiver comprising: receiver circuitry, transmission circuitry, and a channel access controller. The receiver circuitry includes at least one Free Channel Assessment (CCA) block configured to determine whether a channel is free. The transmission circuitry is adapted to transmit data packets on a base channel using a basic PHY or on a preferred channel using a preferred PHY. The channel access controller controls the receiver circuitry to perform a first free channel test on the preferred channel and optionally a second free channel test on the base channel. The channel access controller configures the transmission circuitry to transmit the preferred PHY when the first free channel test is successful, or to transmit the base PHY if the first free channel test fails and the second free channel test succeeds. In some embodiments, the preferred channel is the free channel with the highest data rate. In some embodiments, the free channel tests are performed sequentially, with the second free channel test performed only if the first free channel test fails. In some embodiments, the network device includes a second free channel assessment block, wherein the first and second free channel tests are performed simultaneously. In some embodiments, the two different channels include two different PHY modes. In some embodiments, the preferred channel is the channel with the lowest energy. Attached Figure Description

[0015] For a better understanding of this disclosure, reference is made to the accompanying drawings, in which the same elements are denoted by the same reference numerals, wherein:

[0016] Figure 1 A block diagram of a network device that may include the transceivers described herein;

[0017] Figure 2 yes Figure 1 A block diagram of the radio receiver for a network device;

[0018] Figure 3 A block diagram of a receiver circuit supporting a CCA with multiple channels according to a first embodiment is shown;

[0019] Figure 4 It shows that it can be used with Figure 3 The first sequence used together with the receiver circuit;

[0020] Figure 5A It shows that it can be used with Figure 3 The second sequence used in conjunction with the receiver circuitry;

[0021] Figure 5B It shows in Figure 5A The bandwidth of the channel filter used;

[0022] Figure 6A block diagram of a receiver circuit supporting a CCA with multiple channels according to a second embodiment is shown;

[0023] Figure 7 It shows that it can be used with Figure 6 The first sequence used together with the receiver circuit; and

[0024] Figure 8 It shows that it can be used with Figure 6 The second sequence used in conjunction with the receiver circuit. Detailed Implementation

[0025] Figure 1 A network device that may include the transceiver described herein is illustrated. The network device 10 has a processing unit 20 and an associated memory device 25. The processing unit 20 may be any suitable component, such as a microprocessor, embedded processor, application-specific circuitry, programmable circuitry, microcontroller, or other similar device. The memory device 25 contains instructions that, when executed by the processing unit 20, enable the network device 10 to perform the functions described herein. The memory device 25 may be non-volatile memory, such as FLASH ROM, electrically erasable ROM, or other suitable devices. In other embodiments, the memory device 25 may be volatile memory, such as RAM or DRAM. The instructions contained within the memory device 25 may be referred to as software programs, which are set on a non-transitory storage medium.

[0026] Network device 10 also includes a network interface 30, which may be a wireless network interface including an antenna 37. Network interface 30 may support any wireless network protocol that supports range detection, such as Bluetooth. Network interface 30 is used to allow network device 10 to communicate with other devices configured on network 39.

[0027] Network interface 30 includes transceiver 31. Transceiver 31 processes input signals and converts wireless signals into digital signals. Transceiver 31 also transmits output signals. The components within transceiver 31 are described in more detail below.

[0028] Transceiver 31 includes receiving circuitry 36. Receiving circuitry 36 is used to receive, synchronize, and decode digital signals received from antenna 37. Specifically, receiving circuitry 36 has a preamble detector for identifying the start of an input data packet. Receiving circuitry 36 also has a synchronization detector for identifying a specific bit sequence known as a synchronization character. Additionally, receiving circuitry 36 has a decoder for converting the digital signals into appropriately aligned data bytes.

[0029] The network interface 30 also includes transmission circuitry 38. Transmission circuitry 38 may include a power amplifier for providing the signal to be transmitted to the antenna 37.

[0030] Network device 10 may include a second memory device 40. Data received from or to be transmitted via network interface 30 may also be stored in the second memory device 40. The second memory device 40 is conventionally volatile memory.

[0031] Although memory device 25 is disclosed, these instructions can be stored on any computer-readable medium. For example, read-only memory (ROM), random access memory (RAM), magnetic storage devices such as hard disk drives, or optical storage devices such as CDs or DVDs can be used. Furthermore, these instructions can be downloaded to memory device 25, for example, via a network connection (not shown), via a CD-ROM, or via another mechanism. These instructions can be written in any programming language and are not limited to this disclosure. Therefore, in some embodiments, multiple computer-readable non-transitory media containing the instructions described herein may be present. Figure 1 As shown, the first computer-readable non-transitory medium can communicate with the processing unit 20. The second computer-readable non-transitory medium can be a CD-ROM or a different memory device located remotely from the network device 10. Instructions contained on the second computer-readable non-transitory medium can be downloaded to the memory device 25 to allow the network device 10 to execute the instructions.

[0032] Although the processing unit 20, memory device 25, network interface 30 and second memory device 40 are in Figure 1 These are shown as separate components, but it should be understood that some or all of these components may be integrated into a single electronic component. Conversely, Figure 1 Used to illustrate the functionality of network device 10, rather than its physical configuration.

[0033] Although not shown, network device 10 also has a power source, which may be a battery or a connection to a permanent power source (such as a wall power outlet).

[0034] Figure 2 A block diagram of the receiving circuit 36 ​​is shown. The wireless signal first enters the transceiver 31 through antenna 37. This antenna 37 is in electrical communication with a low-noise amplifier (LNA) 51. The LNA 51 receives a very weak signal from antenna 37 and amplifies it while maintaining the signal-to-noise ratio (SNR) of the input signal. The amplified signal is then passed to mixer 52. Mixer 52 also communicates with a local oscillator 53, which provides two phases to mixer 52. The cosine of the frequency can be referred to as I. o The sine wave of the frequency can be called Q. o Together they are called Complex I o / Q oSignal. Using mixer 52, multiplex I o / Q o The signal is then multiplied by the input signal to produce a complex I. m / Q m Signal. In-phase signal I from mixer 52. m and the quadrature signal Q m It is then fed into a programmable gain amplifier (PGA) 54. The PGA 54 will then... m and Q m Amplified signals are programmable quantities. These amplified signals are called I0. g and Q g Amplified signal I g and Q g The analog signals are then fed from the PGA 54 to the analog-to-digital converter (ADC) 55. The ADC 55 converts these analog signals into digital signals I. d and Q d These digital signals can pass through channel filter 56 and then leave transceiver 31 as I and Q signals. Channel filter 56 is programmable for a specific frequency and bandwidth. For example, channel filter 56 may have inputs that provide channel settings 57 to be used (such as center frequency and bandwidth). In some embodiments, channel filter 56 may include a composite digital mixer, a composite digital oscillator, and two digital low-pass filters. The composite digital mixer passes through a composite I-Q filter. d and Q d The signal is multiplied by a complex signal from a composite digital oscillator to provide complex multiplication. The complex output of the digital mixer is fed to the input of digital low-pass filters, one of which is used for the same-channel and the other for the quadrature channel. The output of the digital filters provides the I and Q outputs of channel filter 56. This allows the center frequency to be configured by setting the frequency of the composite digital oscillator and the bandwidth to be configured by configuring the digital low-pass filters. As those skilled in the art will recognize, decimation filters, DC cancellation circuitry, IQ calibration circuitry, and other circuitry can all be part of channel filter 56. Alternatively, the center frequency can be changed by configuring local oscillator 53 to tune the receiver to the desired channel.

[0035] The I and Q signals then enter a Radio Signal Strength Indicator (RSSI) detector 58, which measures the energy in the received signal. In some embodiments, the RSSI detector 58 includes an amplitude detector that determines the amplitude of the input signal. In some embodiments, the amplitude detector may be incorporated into a CORDIC dedicated to the RSSI detector 58. Alternatively, the CORDIC may be used for other functions, such as determining the phase that can be used by other components in transceiver 31.

[0036] The amplitude can then be the input to a logarithmic converter that transforms the amplitude from the linear domain to the logarithmic domain. The output of the logarithmic converter can then be used as the input to a filter that can be used to average the information. Alternatively, the filter can be placed before the logarithmic converter to filter the amplitude signal in the linear domain. The output from RSSI detector 58 is then provided to threshold comparator 59. If the energy detected by RSSI detector 58 is less than a predetermined threshold, threshold comparator 59 outputs a signal indicating that the channel is idle, referred to as Channel Below Threshold or CBT. If the energy detected by RSSI detector 58 is greater than the predetermined threshold, threshold comparator 59 outputs a signal indicating that the channel is busy, referred to as Channel Above Threshold or CAT. It should be noted that the described RSSI detection is also referred to as energy detection or "energy above threshold".

[0037] The channel filter 56, RSSI detector 58, and threshold comparator 59 can be considered together as a CCA block 60. Based on the input provided to the channel filter 56, the CCA block 60 provides a channel free signal for a specific frequency band. In other words, the term "channel" refers to a specific frequency range. Note that multiple CCA blocks can be combined into the receiver circuit 36, allowing multiple frequency bands to be monitored simultaneously.

[0038] Besides using RSSI for CCA, those skilled in the art will recognize that other features can also be used. For example, carrier sensing can be used, as published in the IEEE 802.15.4-2020 standard. Using carrier sensing, CCA should report a busy medium when a signal with the same modulation and spreading characteristics as the PHY expected for the channel is detected. Alternatively, carrier sensing can be combined with RSSI detection, such as by applying an OR or AND function to the outputs of both the RSSI detector and the carrier sensing detector.

[0039] The architecture of network device 10 has been described; the operation of network device 10 when used in a multi-PHY network will be described. In some network protocols (such as the WiSUN Field Area Network (FAN) protocol), the transmitting node sends a first data packet (called a mode switching data packet) to the receiving node, notifying the receiving node that the next data packet will be sent using a different PHY mode. Then, the transmitting node sends a second data packet (called a new PHY mode data packet).

[0040] PHY mode is a set of parameters that define the characteristics of data packets. These parameters may include modulation type, coding scheme, bit rate, data rate, baud rate, and other parameters.

[0041] The CCA process is complete when it generates an idle channel indication (also known as CCA success) or a busy channel indication (also known as CCA failure). Using a conventional CCA scheme, when using mode switching, such as according to WiSUN FAN 1.1, the following steps are typically performed. First, the network device 10, referred to as the transmission node, must configure the channel settings 57 to correspond to the frequency and bandwidth associated with the first PHY mode intended for transmission on that channel. This could be the PHY mode used for the mode switching packets. Once the channel filter is configured, the receiver is enabled. A backoff time may be included before the CCA begins, but typically it is zero before the first CCA attempt and gradually increases as CCA retries accumulate. Once the CCA begins, the receiver is enabled long enough to stabilize the RSSI value. After a period of time, the CCA is completed by checking the output of the threshold comparator 59 in the CCA block 60. The CCA block 60 can return a channel idle indication (CBT), at which point the transmission node can transmit the mode switching packets.

[0042] Once the mode switch data packet has been transmitted, a CCA procedure similar to that described for the mode switch data packet is performed before transmitting the new PHY mode data packet. The transmitting node must then set channel setting 57 to correspond to the frequency and bandwidth associated with the second PHY mode, which corresponds to the new PHY mode data packet. After CCA is completed, CCA block 60 can return a channel idle indication, at which point the transmitting node can transmit the new PHY mode data packet.

[0043] As described above, various problems exist associated with this method. For example, after sending the mode-switching data packet, the transmitting node may not receive an indication of an idle channel for the second PHY mode for a predetermined period of time. Consequently, the transmitting node will not send new PHY mode data packets and will revert to the first PHY mode. However, the receiving node may still be configured for the second PHY mode, and therefore, it will be unable to receive data packets from the transmitting node until it returns to the mode-switching PHY mode (also known as the basic PHY mode).

[0044] This disclosure describes several embodiments to overcome this drawback.

[0045] Figure 3 A portion of network device 10 is shown, which utilizes Figure 2The receiving circuit 36 ​​is used to enable the transmitting circuit 38. In this embodiment, the receiving circuit 36 ​​includes only one CCA block 60. The network device 10 also includes a channel access controller 100. In some embodiments, the channel access controller 100 may be implemented in hardware. In other embodiments, the channel access controller 100 may be implemented in software executing on the processing unit 20.

[0046] Network device 10 also includes a protocol processor 110. In some embodiments, the protocol processor 110 may be implemented in hardware. In other embodiments, the protocol processor 110 may be implemented in software executing on processing unit 20.

[0047] Protocol processor 110 cooperates with channel access controller 100 to configure receive circuitry 36 and enable transmit circuitry 38. In some embodiments, channel access controller 100 and protocol processor 110 may share hardware or may be combined into a single hardware or software component. In other embodiments, the channel access controller may be implemented as part of a receiver / transmitter controller (also referred to as a radio controller). Radio controllers are commonly used in many wireless SoC products, where they control PHY settings, activate receivers or transmitters, and support radio functions.

[0048] Figure 4 The use according to one embodiment is shown. Figure 3 The operating sequence of the receiving circuit 36 ​​is as follows. First, as shown in block 400, an idle channel test for channel 2 is performed. In these figures, the idle channel test includes the following steps. First, the receiving circuit 36 ​​waits for a predetermined backoff delay time. Note that the backoff time is typically zero before the first CCA attempt and gradually increases as CCA retries accumulate. After this backoff delay time, the receiving circuit 36 ​​is enabled, where the channel settings are configured for the desired PHY mode, and time is allowed for RSSI stabilization. Then, the channel access controller 100 checks the CAT and CBT outputs of the receiving circuit 36. If the energy is higher than a predetermined threshold, as indicated by the CAT, an indication of channel busy is provided. This indication must be called CCAx failure. If the energy is lower than a predetermined threshold, as indicated by the CBT, an indication of channel idle is provided, which is called CCAx success. Figure 4 The sequence shown can be controlled by the channel access controller 100 or the protocol processor 110 or a combination thereof.

[0049] In order to perform an idle channel test for channel 2, the channel access controller 100 can provide channel settings 57 to the receiver circuitry 36 associated with the second PHY mode operating on the second channel.

[0050] The idle channel test for channel 2 returns either CCA2 failure or CCA2 success. If the idle channel test fails, the channel access controller 100 adjusts the backoff delay time, as shown in box 410. If the delay is less than a threshold, the channel access controller 100 performs another idle channel test for channel 2. If the number of retries has been exhausted, the channel access controller 100 indicates that the operation has failed, as shown in box 460.

[0051] If the idle channel test for channel 2 is successful, the channel access controller 100 performs an idle channel test for channel 1, as shown in block 420. To perform the idle channel test for channel 1, the channel access controller 100 may provide channel settings 57 to the receiver circuitry 36 associated with the first PHY mode operating on the first channel.

[0052] The idle channel test for channel 1 returns either CCA1 failure or CCA1 success. If the idle channel test fails, the channel access controller 100 adjusts the backoff delay time, as shown in box 430. If the delay is less than a threshold, the channel access controller 100 performs another idle channel test for channel 1. If the number of retries has been exhausted, the channel access controller 100 indicates that the operation has failed, as shown in box 460.

[0053] If the idle channel test for channel 1 is successful, the protocol processor 110 instructs the transmission circuit 38 to transmit the mode switching data packet, as shown in block 440. The protocol processor 110 may provide the transmission circuit 38 with an enable signal and the PHY mode to be used, which is the first PHY mode.

[0054] Once the mode switching data packet has been transmitted, the protocol processor 110 can provide an enable signal to the transmission circuit 38 along with the PHY mode to be used, which is the second PHY mode. The new PHY mode data packet can now be transmitted, as shown in box 450.

[0055] By performing two CCA tests during the first time period and transmission during the second time period (which begins after the first time period), this embodiment ensures that both channels are idle before any data packet is transmitted. This reduces the likelihood that mode-switching packets are delivered but new PHY mode packets are not, thus saving bandwidth and power.

[0056] Furthermore, in some embodiments, the sequence can be switched so that an idle channel test is performed first on channel 1.

[0057] Figure 5A The use according to the second embodiment is shown. Figure 3The operating sequence of the receiving circuit 36. In this embodiment, the channel filter 56 is designed such that its bandwidth can cover both the first channel and the second channel. Figure 5B A first frequency range 550 used by the first channel and a second frequency range 551 used by the second channel are shown. In this embodiment, the channel setting 57 causes the bandwidth of the channel filter 56 to create a frequency range 552 that covers both the first and second channels. Thus, if the idle channel test fails, it cannot be determined which channel is busy. However, if the idle channel test succeeds, it is assumed that both channels are idle.

[0058] like Figure 5A As shown, in order to perform an idle channel test on the combined channel, the channel access controller 100 can provide a channel setting 57 covering both the first channel and the second channel to the receiving circuit 36.

[0059] As shown in box 500, the idle channel test for the combined channel returns either a COMP CCA failure or a COMP CCA success. If the idle channel test fails, the channel access controller 100 adjusts the backoff delay time, as shown in box 510. If the delay is less than a threshold, the channel access controller 100 performs another idle channel test for the combined channel. If the number of retries has been exhausted, the channel access controller 100 indicates that the operation has failed, as shown in box 540.

[0060] If the idle channel test for the combined channel is successful, the protocol processor 110 instructs the transmission circuit 38 to transmit the mode switching data packet, as shown in block 520. The protocol processor 110 may provide the transmission circuit 38 with an enable signal and the PHY mode to be used, which is the first PHY mode.

[0061] Once the mode switching data packet has been transmitted, the protocol processor 110 can provide an enable signal and the PHY mode to be used to the transmission circuit 38, which is the second PHY mode. The new PHY mode data packet can now be transmitted, as shown in box 530. Figure 5A The sequence shown can be controlled by the channel access controller 100 or the protocol processor 110 or a combination thereof.

[0062] Figure 6 A portion of network device 10 is shown, which utilizes Figure 2 The receiving circuit 36 ​​enables the transmitting circuit 38. In this embodiment, the receiving circuit 36 ​​includes two CCA blocks 60, each of which includes a channel filter 56, an RSSI detector 58, and a threshold comparator 59. Each CCA block 60 can be independently configured using its own set of channel settings 57 and provides its own CAT and CBT outputs.

[0063] Therefore, in one embodiment, Figure 4 The sequence shown can be executed using a receiver circuit 36 ​​with two CCA blocks 60. In other words, as Figure 4 As shown, the channel access controller 100 can optionally check each channel sequentially.

[0064] However, Figure 4 The sequence shown can be optimized by performing two idle channel tests simultaneously. By processing two idle channel tests concurrently, receiver turn-on time can be reduced, thereby reducing power consumption. Another benefit is reduced latency between the idle channel test and subsequent transmissions. This embodiment... Figure 7 As shown in the diagram. First, the channel access controller 100 can configure the first CCA block and the second CCA block respectively using the channel settings 57 for the first channel and the second channel.

[0065] As shown in box 700, an idle channel test for channel 1 can be initiated. This can be performed simultaneously with an idle channel test for channel 2, as shown in box 710. As described above, the idle channel test for channel 1 returns either CCA1 failure or CCA1 success. If the idle channel test for channel 1 fails, the channel access controller 100 adjusts the backoff delay time, as shown in box 720. If the delay is less than a threshold, the channel access controller 100 performs another idle channel test for channel 1. If the number of retries has been exhausted, the channel access controller 100 indicates that the operation has failed, as shown in box 760.

[0066] Simultaneously, the idle channel test for channel 2 returns either CCA2 failure or CCA2 success. If the idle channel test for channel 2 fails, the channel access controller 100 adjusts the backoff delay time, as shown in box 730. If the delay is less than a threshold, the channel access controller 100 performs another idle channel test for channel 2. If the number of retries has been exhausted, the channel access controller 100 indicates that the operation has failed, as shown in box 760.

[0067] If the idle channel test is successful for both Channel 1 and Channel 2, the protocol processor 110 instructs the transmission circuit 38 to transmit the mode switching data packet, as shown in block 740. The protocol processor 110 may provide the transmission circuit 38 with an enable signal and the PHY mode to be used, which is the first PHY mode.

[0068] Once the mode switching data packet has been transmitted, the protocol processor 110 can provide an enable signal to the transmission circuit 38 along with the PHY mode to be used, which is the second PHY mode. The new PHY mode data packet can now be transmitted, as shown in box 750. Figure 7The sequence shown can be controlled by the channel access controller 100 or the protocol processor 110 or a combination thereof.

[0069] therefore, Figure 4 , Figure 5A and Figure 7 Each of the embodiments shown illustrates a sequence in which, during a first time period, the network device ensures that both the first and second channels are idle. During a second time period following the first time period, the network device transmits two data packets using different PHY modes. These two data packets can be a mode-switching packet and a new PHY packet; the mode-switching packet informs the receiving node that a different PHY mode will be used to transmit the next data packet, and the second PHY mode will be used to transmit the new PHY packet.

[0070] Figure 8 It shows that it can be used Figure 6 The network device 10 shown executes different sequences. In this configuration, it is assumed that the receiving node is able to receive data packets transmitted using different channels without prior notice of which channel to use. An example of such a receiver is disclosed in U.S. Patent Application Publication US20210135692A1. This embodiment eliminates the need for mode-switching packets without requiring prior notice of which channel to use. This significantly improves network security because all data packets can be encrypted. Furthermore, all data packets can contain specific destination addresses that support more efficient network traffic.

[0071] First, the channel access controller 100 can configure the first CCA block and the second CCA block respectively using the channel settings 57 for the first channel and the second channel.

[0072] As shown in box 800, an idle channel test for channel 1 can be started. This can be performed simultaneously with an idle channel test for channel 2, as shown in box 810. As described above, the idle channel test for channel 1 returns either CCA1 failure or CCA1 success. Simultaneously, the idle channel test for channel 2 returns either CCA2 failure or CCA2 success.

[0073] One of these two channels can be the preferred channel. For example, channel 2 could use a different PHY mode with a higher bit rate. It should be noted that the preferred PHY mode can be selected based on other criteria, such as transmission range, signal-to-noise ratio (SNR), link budget, or other criteria. In this case, channel 2 is higher rate (HR) and could be preferred. Channel 1 can be considered the basic PHY. In this example, it is assumed that channel 2 is a higher rate channel and therefore the preferred PHY mode.

[0074] Therefore, if the idle channel test for channel 2 is successful, the protocol processor 110 can provide the transmission circuit 38 with an enable signal and the PHY mode to be used, which is a higher rate (HR) PHY mode, as shown in block 820. However, if the idle channel test for channel 2 fails, but the idle channel test for channel 1 succeeds, the protocol processor 110 can provide the transmission circuit 38 with an enable signal and the PHY mode to be used, which is a basic PHY mode, as shown in block 830. In this way, packet transmission is not delayed until subsequent retries.

[0075] If both idle channel tests fail, the operation can be considered a failure. Although not shown, a retry can be introduced. Figure 8 The sequence shown may include, for example, steps such as adjusting the delays of the two channels and retrying the idle channel test until the delay exceeds a threshold if both fail. Figure 8 The sequence shown can be controlled by the channel access controller 100 or the protocol processor 110 or a combination thereof.

[0076] Figure 8 A sequence of concurrent executions using an idle channel test is illustrated. Those skilled in the art will recognize that idle channel tests can also be performed sequentially using a single CCA block. For example, an idle channel test in the preferred PHY mode can be performed first. This is done by configuring the channel filter center frequency and bandwidth to a channel dedicated to the preferred PHY mode, enabling the receiver, and waiting for the result. If the first idle channel test succeeds, the preferred PHY mode can be used to transmit data packets. If the first idle channel test fails, a second idle channel test can be performed by configuring the channel filter center frequency and bandwidth to a channel dedicated to the basic PHY mode, enabling the receiver, and waiting for the idle channel test result. If the second idle channel test succeeds, the basic PHY can be used to transmit data packets. If the second idle channel test also fails, the channel access controller 100 can terminate or retry with or without adjusting the backoff delay. Other variations of this sequence can also be used.

[0077] Note that the above description indicates that different channels are associated with different PHY modes. However, other embodiments are also possible. For example, a wireless network protocol may use a single PHY mode with multiple frequency ranges. For example, a protocol including multiple CCA blocks 60... Figure 6 The receiving circuitry can be used to simultaneously check multiple frequency channels. Then, network device 10 can select the channel that returns a channel idle indication.

[0078] In another embodiment, the channel access controller 100 can access the output of the RSSI detector 58 in each CCA block 60. In this embodiment, the channel access controller 100 can select the channel with the lowest energy and use that channel to transmit output data packets.

[0079] This system and method offer numerous advantages. As described above, in current systems using different PHY modes, conventional network devices check a first channel. When idle, the network device transmits a mode-switching packet. Then, the network device checks a second channel. When the second channel is idle, a second packet using the new PHY mode is transmitted. However, a problem exists: the second channel may remain busy, preventing the network device from sending the second packet. This causes the network device to abort the sequence, but the receiving node may still be waiting for a packet using the second PHY mode. By checking both channels before transmitting the mode-switching packet, the probability of the second packet not being transmitted is significantly reduced. This improves throughput and reduces required power consumption.

[0080] This disclosure is not limited to the specific embodiments described herein. In fact, various other embodiments and modifications of this disclosure will be apparent to those skilled in the art from the foregoing description and drawings, in addition to those embodiments described herein. Therefore, such other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, although this disclosure has been described herein in the context of a specific implementation in a specific environment for a specific purpose, those skilled in the art will recognize that the usefulness of this disclosure is not limited thereto, and that this disclosure can advantageously achieve any number of purposes in any number of environments. Therefore, the following claims should be interpreted in accordance with the full scope and spirit of this disclosure as described herein.

Claims

1. A network device for transmitting data packets using multiple channels, comprising: Transceiver, the transceiver comprising: The receiver circuit includes at least one idle channel assessment (CCA) block for determining whether the channel is idle; A transmission circuit, the transmission circuit being adapted to transmit data packets on any one of the plurality of channels; and A channel access controller, wherein the channel access controller controls the receiver circuitry to perform idle channel tests on at least two of the plurality of channels during a first time period, and controls the transmission circuitry to transmit at least one data packet on an idle channel after the first time period and during a second time period; wherein the receiver circuitry includes a channel filter having a programmable frequency and bandwidth, and wherein the channel access controller configures the channel filter for a first channel, waits for the completion of a first idle channel test, configures the channel filter for a second channel, and waits for the completion of a second idle channel test before transmitting the at least one data packet, wherein the completion of the first idle channel test indicates that the first channel is idle, and the completion of the second idle channel test indicates that the second channel is idle.

2. The network device according to claim 1, wherein, The idle channel test is performed sequentially during the first time period, and the network device transmits at least two data packets using two different idle channels during the second time period.

3. The network device according to claim 2, wherein, The first data packet includes a mode switching data packet sent using the first PHY mode, and the second data packet includes a data packet sent using the second PHY mode.

4. The network device according to claim 1, wherein, Each failed idle channel test is followed by a backoff delay adjustment and retry, where the backoff delay represents the time between completing a failed idle channel test and starting an idle channel test retry.

5. The network device according to claim 1, wherein, The receiver circuit includes a local oscillator, wherein the channel access controller configures the bandwidth of the channel filter and the local oscillator to tune the receiving frequency to a first channel, waits for the completion of a first idle channel test, configures the bandwidth of the channel filter and the local oscillator to tune the receiving frequency to a second channel, and waits for the completion of a second idle channel test before transmitting the at least one data packet on the idle channel.

6. The network device according to claim 1, wherein, Each of the multiple channels uses a different PHY mode.

7. The network device according to claim 1, wherein, The first channel is a preferred channel using a preferred PHY, and the second channel is a basic channel using a basic PHY. If the first idle channel test is successful, the channel access controller configures the transmission circuit to transmit the preferred PHY on the preferred channel. If the first idle channel test fails and the second idle channel test is successful, the channel access controller configures the transmission circuit to transmit the basic PHY on the basic channel.

8. A network device for transmitting data packets using multiple different channels, comprising: Transceiver, the transceiver comprising: A receiver circuit, the receiver circuit including a plurality of free channel evaluation (CCA) blocks configured to operate simultaneously; A transmission circuit, the transmission circuit being adapted to transmit data packets on any one of the plurality of different channels; and A channel access controller, wherein the channel access controller controls the receiver circuitry to perform an idle channel assessment on at least two of a plurality of different channels during a first time period, and controls the transmission circuitry to transmit at least one data packet on an idle channel after the first time period and during a second time period; wherein each CCA block includes a channel filter having a programmable frequency and bandwidth, wherein the channel access controller processes the CCA block simultaneously such that the channel access controller configures a first channel filter for a first channel, configures a second channel filter for a second channel, enables the receiver circuitry, and waits for the idle channel assessment to complete before transmitting the at least one data packet, wherein the completion of the idle channel assessment indicates that both the first channel and the second channel are idle.

9. The network device according to claim 8, wherein, The network device transmits at least two data packets during the second time period, wherein the at least two data packets are transmitted using two different channels.

10. The network device according to claim 9, wherein, The first data packet includes a mode switching data packet sent using the first PHY mode, and the second data packet includes a data packet sent using the second PHY mode.

11. The network device according to claim 8, wherein, The channel access controller configures the plurality of channel filters before performing the idle channel assessment.

12. The network device according to claim 8, wherein, Each of the multiple different channels uses a different PHY mode.

13. The network device according to claim 8, wherein, The first channel is a preferred channel using a preferred PHY, and the second channel is a basic channel using a basic PHY. If the first idle channel test is successful, the channel access controller configures the transmission circuit to transmit the preferred PHY on the preferred channel. If the first idle channel test fails and the second idle channel test is successful, the channel access controller configures the transmission circuit to transmit the basic PHY on the basic channel.

14. A network device for transmitting data packets using multiple channels, comprising: Transceiver, the transceiver comprising: The receiver circuit includes at least one idle channel assessment (CCA) block for determining whether the channel is idle; A transmission circuit, the transmission circuit being adapted to transmit data packets on any one of the plurality of channels; and A channel access controller, wherein the channel access controller controls the receiver circuitry to perform idle channel tests on at least two of the plurality of channels during a first time period, and controls the transmission circuitry to transmit at least one data packet on an idle channel after the first time period and during a second time period; wherein the CCA block includes a channel filter having a programmable frequency and bandwidth, wherein the channel access controller configures the channel filter such that the bandwidth of the channel filter includes a combined frequency range of at least two of the plurality of channels, wherein the idle channel tests on at least two of the plurality of channels indicate that at least two of the plurality of channels are idle.

15. The network device according to claim 14, wherein, The network device transmits at least two data packets during the second time period, wherein the at least two data packets are transmitted using two different channels.

16. The network device according to claim 15, wherein, The first data packet includes a mode switching data packet sent using the first PHY mode, and the second data packet includes a data packet sent using the second PHY mode.

17. The network device according to claim 14, wherein, At least two of the multiple channels each use a different PHY mode.

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