A timing coding method and system
By generating and fusing test waveform signals, the interference problem caused by the frame rate difference between APS and EVS sensors was solved, enabling efficient chip verification testing and simplifying the code development process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN RUISHIZHIXIN TECH CO LTD
- Filing Date
- 2023-02-21
- Publication Date
- 2026-07-10
AI Technical Summary
During chip verification testing, the frame rate difference between the APS sensor and the EVS sensor causes mutual interference, resulting in stripes and flickering. Furthermore, verification personnel need to manually write code according to different test requirements, which is time-consuming, inefficient, and prone to errors.
By generating first and second test waveform signals, fusing them to generate a third test waveform signal, and adjusting each waveform signal according to the chip state, timing encoding and decoding of APS and EVS sensors can be realized, supporting any number of signals and timing sequences, and simplifying code development.
It improves the efficiency and accuracy of chip verification testing, reduces development cycle and error rate, and is suitable for testing needs of various image sensors.
Smart Images
Figure CN116156155B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of sensor fusion technology, and in particular to a timing encoding and decoding method and system. Background Technology
[0002] An image chip integrating APS and EVS sensors will have trigger signals from both sensors. However, the frame rates of the APS and EVS sensors differ significantly, with the APS sensor operating at around 30fps and the EVS sensor at around 2000fps. In the early stages of chip development, interference between the APS and EVS sensors can cause phenomena such as stripes and flickering. Image debugging requires adjusting the trigger timing of the APS and EVS sensors to verify the impact of timing on crosstalk. However, the performance requirements for chip testing and verification are increasing. In practical applications, testing the interaction between the EVS and APS sensors necessitates the creation of multiple custom signal control chips. Since the control signals for the EVS and APS sensors differ, their timing characteristics also differ. Verification personnel must design different verification code according to different test requirements, resulting in long development cycles, low efficiency, and the risk of errors due to switching between different test items. Summary of the Invention
[0003] To address the aforementioned problems, the present invention aims to provide a timing encoding and decoding method and system that solves the problems encountered during chip verification testing, such as the need to generate multiple different custom signals to control the chip, requiring verification personnel to write different codes according to different test requirements, resulting in long development cycles, low efficiency, and errors due to cross-switching between different test items.
[0004] To achieve the above objectives, the present invention adopts the following technical solution: The present invention discloses a timing encoding and decoding method, the method comprising: generating a first test waveform signal and a second test waveform signal;
[0005] The first test waveform signal and the second test waveform signal are fused to generate a third test waveform signal;
[0006] The first and second test waveform signals are adjusted according to the state of the chip under test when the third test waveform signal is running.
[0007] Preferably, generating the first test waveform signal and the second test waveform signal specifically includes:
[0008] The test waveform is encoded into a register list, and the test waveform encoding method supports any number of signals and generates any timing sequence.
[0009] Convert the user-defined first graphical waveform into the first register list, and convert the user-defined second graphical waveform into the second register list;
[0010] The first register list is decoded to generate the first test waveform signal, and the second register list is decoded to generate the second test waveform signal.
[0011] Preferably, the step of fusing the first test waveform signal and the second test waveform signal to generate the third test waveform signal specifically includes:
[0012] The third test waveform signal is set as the result of the first test waveform signal and the second test waveform signal.
[0013] Preferably, setting the third test waveform signal as the result of the AND operation of the first test waveform signal and the second test waveform signal specifically includes:
[0014] When the virtual level of the first test waveform signal and the virtual level of the second test waveform signal are both high, the waveform of the third test waveform signal is generated.
[0015] Preferably, the step of encoding the test waveform into a register list, wherein the test waveform encoding method supports any number of signals and generates any timing sequence, specifically includes:
[0016] The register contains 3 bits (bits 30-bit 28) to represent the high and low levels, with 0x0 representing a low level and 0x1 representing a high level. Bits 27-bit 0 contain 28 bits to represent the duration of the level.
[0017] The highest bit 31 indicates whether there is a dependency relationship; it is set to 1 if there is, and 0 otherwise.
[0018] When register bits 30~bit 28 are 0x2, the loop starts; when 0x3 is 0x3, the loop ends; bits 27~bit 0 are the number of loop iterations.
[0019] A loop count of 0 indicates an infinite loop.
[0020] Preferably, the decoding process specifically includes:
[0021] Start scanning register table table[n], and determine if table[0] is the start flag;
[0022] Check loop body 1. If the current position in the table is recorded in an array (loop1_start = 0, loop1_number = 0), it indicates an infinite loop.
[0023] Determine if loop body 2 is iterated twice, and record in the current table: loop2_start = 1, loop2_number = 2;
[0024] The level is determined because there is a control bit, which generates a high level of 1000clk and a virtual signal.
[0025] Determine the level and generate a low level of 2000clk;
[0026] When loop body 2 ends, record the current position loop2_end = 5, then decrement loop2_number by one, jump to the loop start position Table[1], until the loop ends;
[0027] Continue performing level operations;
[0028] When loop 1 ends, jump to the starting position Table[0] of loop 1.
[0029] Preferably, the method includes:
[0030] The first test waveform signal is a control signal for controlling the EVS sensor;
[0031] The second test waveform signal is the control signal for controlling the APS sensor.
[0032] The second objective of this invention can be achieved by adopting the following technical solution: a system based on a timing encoding / decoding method, the system comprising:
[0033] A waveform generation unit is used to generate a first test waveform signal and a second test waveform signal;
[0034] A fusion unit is used to fuse the first test waveform signal and the second test waveform signal to generate a third test waveform signal;
[0035] The adjustment unit allows the user to adjust the first and second test waveform signals respectively based on the state of the chip under test when the third test waveform signal is running.
[0036] The third objective of this invention can be achieved by adopting the following technical solution:
[0037] A computer device includes a processor and a memory for storing a processor-executable program, wherein when the processor executes the program stored in the memory, it implements the aforementioned timing encoding / decoding method.
[0038] The fourth objective of this invention can be achieved by adopting the following technical solution:
[0039] A storage medium stores a program that, when executed by a processor, implements the aforementioned timing encoding / decoding method.
[0040] This invention generates a first test waveform signal and a second test waveform signal; fuses the first and second test waveform signals to generate a third test waveform signal; adjusts the first and second test waveform signals according to the state of the chip under test under the third test waveform signal; and adjusts the trigger signals of the first and second test waveform signals, the refresh signals of the first and second test waveform signals, and the refresh signals of the second test waveform signals according to the state of the chip under test under the third test waveform signal to refresh the pixel voltage. Based on the test results, the refresh signals of the first and second test waveform signals are obtained. The invention also determines the optimal triggering effect after how many frames, the triggering duration, and the number of triggers, thereby verifying the impact of the timing of the first and second test waveform signals on crosstalk. Attached Figure Description
[0041] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. In the drawings:
[0042] Figure 1 This is a flowchart of a timing encoding / decoding method according to the present invention;
[0043] Figure 2 This is a waveform fusion diagram of a timing encoding / decoding method according to the present invention;
[0044] Figure 3 This is a flowchart illustrating the generation of a first test wave signal and a second test wave signal according to the present invention. Detailed Implementation
[0045] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.
[0046] Example 1:
[0047] This invention discloses a timing encoding and decoding method, with reference to Figure 1-3 The method includes:
[0048] Step 100: Generate the first test waveform signal and the second test waveform signal;
[0049] Specifically, the generation process of the first test waveform signal includes: step 100A, cyclically generating a square wave twice; step 100B, maintaining a low level for a certain period of time; and step 100C, repeating steps 100A and 100B.
[0050] The generation process of the second test waveform signal includes: step 100a, cyclically generating a square wave twice; step 100b, maintaining a low level for a certain period of time; and step 100c, repeating steps 100a and 100b.
[0051] Step 200: Fuse the first test waveform signal and the second test waveform signal to generate a third test waveform signal;
[0052] Specifically, if bit 31 of the level register for the first and second test waveform signals is simultaneously 1, the third test waveform signal is pulled high; otherwise, it is pulled low.
[0053] Step 300: Adjust the first test waveform signal and the second test waveform signal according to the state of the chip under test under the third test waveform signal.
[0054] This invention generates a first test waveform signal and a second test waveform signal; fuses the first and second test waveform signals to generate a third test waveform signal; adjusts the first and second test waveform signals according to the state of the chip under test under the third test waveform signal; and adjusts the trigger signals of the first and second test waveform signals, the refresh signals of the first and second test waveform signals, and the refresh signals of the second test waveform signals according to the state of the chip under test under the third test waveform signal to refresh the pixel voltage. Based on the test results, the refresh signals of the first and second test waveform signals are obtained. The invention also determines the optimal triggering effect after how many frames, the triggering duration, and the number of triggers, thereby verifying the impact of the timing of the first and second test waveform signals on crosstalk.
[0055] Preferably, step 100, generating the first test waveform signal and the second test waveform signal, specifically includes:
[0056] Step 110: Encode the test waveform into a register list. The test waveform encoding method supports any number of signals and generates any timing sequence.
[0057] Specifically, each signal is described by a set of 32-bit registers, the meanings of which are as follows:
[0058] Bit31: Control bit
[0059] Position 1 indicates that this waveform is dependent on other waveforms, and a high-level virtual signal is generated based on the current register, for example... Figure 2 In the process, when the virtual level of the level registers for the first and second test waveform signals are both high, the third test waveform signal is generated. This encoding method can cover most application scenarios, such as generating a 32-bit register table from the first test waveform signal.
[0060] This position 0 indicates normal control logic;
[0061] Bits 30-28: Used to express level and loop body
[0062] Bits 27~0: Express the duration of the level and the number of loops.
[0063]
[0064] Step 120: Convert the user-defined first graphical waveform into a first register list, and convert the user-defined second graphical waveform into a second register list.
[0065] Table 1 Waveform Description of the First Test Signal
[0066]
[0067] Similarly, those skilled in the art can set the waveform description table of the second test signal according to the actual test requirements. The specific waveform description table can be set according to the actual situation, and will not be elaborated here.
[0068] Step 130: Decode the first register list to generate the first test waveform signal, and decode the second register list to generate the second test waveform signal.
[0069] Preferably, the decoding process specifically includes:
[0070] Step 1301: Start scanning register table[n] and determine if table[0] is the start flag;
[0071] Step 1302: Determine the loop body 1. Use an array to record the current position in the table: loop1_start = 0, loop1_number = 0, indicating an infinite loop.
[0072] Step 1303: Determine that loop body 2 is a 2-cycle loop, and record loop2_start = 1 and loop2_number = 2 in the current table;
[0073] Step 1304: Determine the level. Because there is a control bit, generate a high level of 1000clk and a virtual signal.
[0074] Step 1305: Determine the level and generate a low level of 2000clk;
[0075] Step 1306, loop body 2 ends, record the current position loop2_end = 5, then decrement loop2_number by one, jump to the loop start position Table[1], until the loop ends;
[0076] Step 1307, continue with the level operation;
[0077] Step 1308, Loop 1 ends, jump to the starting position Table[0] of Loop 1.
[0078] To design computer programs that are easy and simple for testers to operate without requiring knowledge of encoding / decoding methods, and to reduce development difficulty and time, simple statements are used for description, in the following format:
[0079] 1. Name: Represents the operation name.
[0080] 2. Level:
[0081] Control bit: Whether there is a dependency
[0082] Level state: Indicates whether there is a timing dependency.
[0083] Counter: Represents the duration of the waveform
[0084] 3. Circulatory system
[0085] Control bit: Whether there is a dependency
[0086] Counter: Represents the number of loops.
[0087] For example, the waveform in Table 1, the user input description is as follows:
[0088] start / / Waveform start
[0089] loop_start, 0, 0; / / Loop start, no dependencies, infinite loop.
[0090] loop_start, 0, 2; / / Loop start, no dependencies, 2 iterations
[0091] level, 1, 1, 1000; / / Dependency exists, 1000 is a high level clk.
[0092] level, 0, 0, 2000; / / No dependency, 2000 clk is low level
[0093] loop_end, 0, 2; / / No dependencies, loop ends
[0094] level, 0, 0, 1000; / / No dependency, 1000 clk represents low level.
[0095] loop_end, 0, 2; / / No dependencies, loop ends
[0096] end / / Waveform ends.
[0097] Preferably, step 300, fusing the first test waveform signal and the second test waveform signal to generate a third test waveform signal, specifically includes:
[0098] The third test waveform signal is set as the result of the first test waveform signal and the second test waveform signal.
[0099] Of course, in specific applications, the waveforms of the first and second test waveforms can be fused within a certain time period, while other time periods are left unprocessed. For example, the first and second test waveforms at approximately 15fps can be fused, while others are left unfused. The specific fusion process of the third test waveform signal can be performed according to specific test requirements, thus making the test method of this application applicable to the fusion test between all image sensors, thereby improving test efficiency and test versatility.
[0100] Preferably, setting the third test waveform signal as the result of the AND operation of the first test waveform signal and the second test waveform signal specifically includes:
[0101] When the virtual level of the first test waveform signal and the virtual level of the second test waveform signal are both high, the waveform of the third test waveform signal is generated.
[0102] Preferably, step 110 involves encoding the test waveform into a register list. The test waveform encoding method supports any number of signals and generates any timing sequence, specifically including:
[0103] The register contains 3 bits (bits 30-bit 28) to represent the high and low levels, with 0x0 representing a low level and 0x1 representing a high level. Bits 27-bit 0 contain 28 bits to represent the duration of the level.
[0104] The highest bit 31 indicates whether there is a dependency relationship; it is set to 1 if there is, and 0 otherwise.
[0105] When register bits 30~bit 28 are 0x2, the loop starts; when 0x3 is 0x3, the loop ends; bits 27~bit 0 are the number of loop iterations.
[0106] A loop count of 0 indicates an infinite loop.
[0107] Preferably, the method includes:
[0108] The first test waveform signal is a control signal for controlling the EVS sensor;
[0109] The second test waveform signal is the control signal for controlling the APS sensor.
[0110] In practical applications, technicians can test the fusion results of control signals from other image sensors according to the actual situation, and the specific type of image sensor can be selected based on the actual situation.
[0111] Example 2:
[0112] This embodiment provides a system based on a timing encoding / decoding method, the system comprising:
[0113] A waveform generation unit is used to generate a first test waveform signal and a second test waveform signal;
[0114] A fusion unit is used to fuse the first test waveform signal and the second test waveform signal to generate a third test waveform signal;
[0115] The adjustment unit allows the user to adjust the first and second test waveform signals respectively based on the state of the chip under test when the third test waveform signal is running.
[0116] This invention generates a first test waveform signal and a second test waveform signal; fuses the first and second test waveform signals to generate a third test waveform signal; adjusts the first and second test waveform signals according to the state of the chip under test under the third test waveform signal; and adjusts the trigger signals of the first and second test waveform signals, the refresh signals of the first and second test waveform signals, and the refresh signals of the second test waveform signals according to the state of the chip under test under the third test waveform signal to refresh the pixel voltage. Based on the test results, the refresh signals of the first and second test waveform signals are obtained. The invention also determines the optimal triggering effect after how many frames, the triggering duration, and the number of triggers, thereby verifying the impact of the timing of the first and second test waveform signals on crosstalk.
[0117] The specific implementation of each module in this embodiment can be found in Embodiment 1 above, and will not be repeated here. It should be noted that the device provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure can be divided into different functional modules to complete all or part of the functions described above.
[0118] It is understood that the terms "first," "second," etc., used in the apparatus of the above embodiments can be used to describe various units, but these units are not limited by these terms. These terms are only used to distinguish the first module from another module. For example, without departing from the scope of the invention, the first transmitting module can be referred to as the second transmitting module, and similarly, the second transmitting module can be referred to as the first transmitting module. Both the first transmitting module and the second transmitting module are transmitting modules, but they are not the same transmitting module.
[0119] Example 3:
[0120] This embodiment provides a computer device, including a processor and a memory for storing a processor-executable program. When the processor executes the program stored in the memory, it implements the above-described timing encoding and decoding method. The method includes: step 100, generating a first test waveform signal and a second test waveform signal; step 200, fusing the first test waveform signal and the second test waveform signal to generate a third test waveform signal; and step 300, adjusting the first test waveform signal and the second test waveform signal according to the state of the chip under test under the third test waveform signal.
[0121] Example 4:
[0122] This embodiment provides a storage medium, which is a computer-readable storage medium storing a computer program. When the program is executed by a processor, the processor executes the computer program stored in the memory to implement a timing encoding and decoding method of Embodiment 1 above. The method includes: step 100, generating a first test waveform signal and a second test waveform signal; step 200, fusing the first test waveform signal and the second test waveform signal to generate a third test waveform signal; and step 300, adjusting the first test waveform signal and the second test waveform signal according to the state of the chip under test under the third test waveform signal.
[0123] It should be noted that the computer-readable storage medium in this embodiment can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.
[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A timing encoding / decoding method, characterized in that, The method includes: Generate a first test waveform signal and a second test waveform signal, wherein the first test waveform signal is a control signal for controlling the EVS sensor and the second test waveform signal is a control signal for controlling the APS sensor; The first test waveform signal and the second test waveform signal are fused to generate a third test waveform signal. The fusion includes performing a logical AND operation on the first test waveform signal and the second test waveform signal, and fusing the waveforms of the first test waveform signal and the second test waveform signal for a certain time period, while not fusing the waveforms of other time periods. The first and second test waveform signals are adjusted according to the state of the chip under test under the third test waveform signal. Specifically, the trigger signals of the first and second test waveform signals are adjusted according to the state of the chip under test under the third test waveform signal. The refresh signals of the first and second test waveform signals are also adjusted. The refresh signals of the first and second test waveform signals are used to refresh the pixel voltage. Based on the test results, the number of frames after which the refresh signals of the first and second test waveform signals have a better triggering effect, as well as the duration and number of triggers, are obtained to verify the influence of the timing of the first and second test waveform signals on crosstalk. The chip under test is an image fusion chip of an APS sensor and an EVS sensor; The generation of the first test waveform signal and the second test waveform signal includes: The test waveform is encoded into a register list, and the test waveform encoding method supports any number of signals and generates any timing sequence. Based on the encoding method, the user-defined first graphical waveform is converted into a first register list, and the user-defined second graphical waveform is converted into a second register list. The first register list is decoded to generate the first test waveform signal, and the second register list is decoded to generate the second test waveform signal.
2. The timing encoding / decoding method according to claim 1, characterized in that, The step of performing a logical AND operation on the first test waveform signal and the second test waveform signal specifically includes: When the virtual level of the first test waveform signal and the virtual level of the second test waveform signal are both high, the waveform of the third test waveform signal is generated.
3. A timing encoding / decoding system, characterized in that, The system is used to perform the method as described in any one of claims 1-2, the system comprising: A waveform generation unit is used to generate a first test waveform signal and a second test waveform signal; A fusion unit is used to fuse the first test waveform signal and the second test waveform signal to generate a third test waveform signal; The adjustment unit allows the user to adjust the first and second test waveform signals respectively based on the state of the chip under test when the third test waveform signal is running.
4. A computer device, characterized in that, The computer device includes a processor and a memory for storing a processor-executable program, wherein when the processor executes the program stored in the memory, the computer device performs the method as described in any one of claims 1 to 2.
5. A storage medium, characterized in that, A stored program, which, when executed by a processor, performs the method according to any one of claims 1 to 2.