An avionics ACSC board card intelligent test method and system based on reverse engineering

Abstract

This invention relates to the field of avionics testing technology, and more particularly to an intelligent testing method and system for avionics ACSC boards based on reverse engineering. The method first responds to the access of the target board by performing physical reverse engineering analysis of the target board to construct a software test model including circuit topology and test items. Then, the test firmware program containing the test communication protocol is burned into a programmable logic device to establish a communication link between the test system and the target board. Based on the software test model, corresponding test commands and excitation signals are sent to the target board to drive specific circuit modules. Simultaneously, response signals are acquired in real time. The response signals are compared with the corresponding expected intervals to obtain fault location analysis results. This invention solves the "black box" problem through reverse engineering and employs low-level hardware driving and precise timing control technology to ensure that the test environment is consistent with the onboard operating state, achieving high-fidelity and high-efficiency testing of avionics boards.

Description

Technical Field

[0001] This invention relates to the field of avionics testing technology. More specifically, this invention relates to an intelligent testing method and system for avionics ACSC boards based on reverse engineering. Background Technology

[0002] With the rapid development of aviation technology, the complexity and integration of aircraft systems are constantly increasing, placing more stringent demands on the reliability and fault diagnosis capabilities of key components. The intelligent controller of the aircraft air conditioning system is responsible for temperature regulation of the entire cabin environment and the coordinated control of multiple systems. In scenarios involving rapid temperature changes from low altitudes to high altitudes (tens of thousands of meters), the external temperature can plummet from 20 degrees Celsius to -30 degrees Celsius. Its performance directly affects passenger comfort and safety during flight. The key component of this controller is the electronic circuit board, which provides stable and clean power support and reliable functional drive for the entire control system. Due to its special electrical and functional attributes under high-reliability conditions, any performance degradation or potential failure can trigger system-level risks. Therefore, the testing and maintenance of these electronic circuit boards require extremely high standards.

[0003] However, in the current aviation field, the performance testing of the aforementioned electronic boards mainly relies on manual testing. This method is overly dependent on human experience, which is not only inefficient but also highly susceptible to human subjectivity, making it difficult to accurately locate faults and quickly troubleshoot them, thus seriously affecting maintenance efficiency and equipment availability. Summary of the Invention

[0004] To address the aforementioned technical problems of low efficiency and poor reliability in existing technologies, this invention discloses an intelligent testing method and system for avionics ACSC boards based on reverse engineering.

[0005] In a first aspect, this invention discloses an intelligent testing method for avionics ACSC boards based on reverse engineering, comprising: In response to the access of the target board, a physical reverse engineering analysis of the target board is performed to construct a software test model that includes circuit topology and test items; The test firmware program containing the test communication protocol is burned into the programmable logic device to establish a communication link between the test system and the target board. Based on the software testing model, corresponding test commands and stimulus signals are sent to the target board to drive specific circuit modules to work; during this process, response signals are collected in real time. The response signal is compared with the corresponding expected range to obtain the fault location analysis results.

[0006] Preferably, the target board is subjected to physical reverse engineering to construct a software test model that includes circuit topology and test items, including: Obtain the target board's pin electrical characteristics database; A mathematical graph structure mapping the connection relationships of components is constructed based on the pin electrical characteristics database; A graph-based circuit partitioning algorithm is used to decouple the mathematical graph structure into multiple functionally independent circuit sub-modules; Identify the boundary signal flow and key control timing between multiple circuit sub-modules, and establish a circuit module association diagram that includes timing dependencies; Match corresponding functional attributes to all circuit sub-modules, and logically combine the circuit sub-modules according to the circuit module association diagram to obtain the software test model.

[0007] Preferably, the test communication protocol is configured as follows: During the test firmware program's execution, take over control of the target board's data bus; Parse test commands and / or excitation signals from the test system, and convert the test commands and / or excitation signals into control signals for the corresponding circuit sub-modules; The voltage or logic state of the target circuit node in the sampling circuit submodule is sampled in real time and packaged and sent back to the test system.

[0008] Preferably, the circuit submodule includes a digital logic module and an analog / mixed-signal module.

[0009] Preferably, the programmable logic device includes an ultra-low power CPLD; when rewriting the firmware of the ultra-low power CPLD, the test communication protocol is logically locked through the underlying hardware description language.

[0010] By using the above technical solutions, the automatic optimization of critical path logic by the synthesis tools is avoided, ensuring that the logic function of the CPLD is completely reliable during testing. This operation not only ensures the accuracy of the test benchmark, but also avoids the deviation of logic function caused by toolchain optimization.

[0011] Preferably, for digital logic modules, the method of the present invention further includes: The control signal obtained from the test command is applied to the input terminal of the digital logic module, and the response signal of the corresponding output terminal is collected. The test instructions rely on the pre-configured test vectors generated by the software test model.

[0012] Preferably, the control signal is converted from digital to analog to obtain multiple different analog signals; for analog / mixed signal modules, the method of the present invention further includes: Multiple different analog signals are applied to the input of the analog / mixed signal module, and the response signals at the corresponding output are acquired.

[0013] Preferably, for circuit sub-modules containing analog / mixed-signal modules and high-power switching transistor arrays, to ensure a high degree of consistency between the test state and the on-board operating state, the method also introduces dynamic timing matching and precise drive technology. Specifically, firstly, based on the timing dependencies identified in the circuit module association diagram, drive signals that strictly conform to the power-on, configuration, and operating timing requirements of analog chips (such as power management chips and operational amplifiers) are generated to avoid chip initialization failure or abnormal operation due to timing errors. Secondly, for high-power switching arrays composed of multiple MOSFETs or IGBTs, precise drive timing that conforms to their switching characteristics and load conditions is generated to avoid abnormal switching action; ensuring reliable and clean switching action under high current and high voltage stress, completely replicating its real operating conditions in the aircraft air conditioning system controller.

[0014] Preferably, after constructing the software testing model, the method of the present invention further includes: Read and back up the original firmware of the programmable logic device.

[0015] Preferably, after the test is completed, the method of the present invention further includes: The original firmware program is burned into the programmable logic device.

[0016] Preferably, the target board uses a JTAG interface for programming.

[0017] Secondly, the present invention also discloses an intelligent testing system for avionics ACSC boards based on reverse engineering, which is used for the intelligent testing method for avionics ACSC boards based on reverse engineering described in the first aspect. The system of the present invention includes a test management host computer, a communication and control core unit, a protocol adaptation and signal conditioning unit, and an intelligent diagnostic engine. When the target board is connected, the system first performs physical reverse engineering analysis on the target board to build a software test model that includes circuit topology and test items; The test management host computer is used to provide human interaction services; The protocol adaptation and signal conditioning unit is used for physical transfer to target boards and communication and control core units; The communication and control core unit is used for: The test firmware program containing the test communication protocol is burned into the programmable logic device to establish a communication link between the test system and the target board. Based on the software testing model, corresponding test commands and stimulus signals are sent to the target board to drive specific circuit modules to work; during this process, response signals are collected in real time. The intelligent diagnostic engine is used for: The response signal is compared with the corresponding expected range to obtain the fault location analysis results.

[0018] The beneficial effects of this invention are as follows: (1) The method of this invention constructs a complete software test model by reverse engineering the target board, realizing the reverse engineering analysis of the hardware "black box" and significantly improving the accuracy and efficiency of fault diagnosis. On this basis, this invention also opens up a real-time interaction channel between the test system and the board by modifying the onboard programmable logic device program and predefined communication protocol. Compared with the prior art, the method of this invention constructs an automated closed-loop test mechanism of reverse engineering analysis, temporary replacement of original factory program, driver testing, response acquisition and fault location analysis, which can realize automated and efficient testing of aviation electronic boards and ensure the efficiency and reliability of the testing process.

[0019] (2) The method of the present invention not only realizes program backup and restoration, but also proposes solutions to key technical difficulties such as ultra-low power CPLD, complex timing of analog chips and precise driving of high power switching transistors, ensuring high fidelity of the test process, that is, the test environment can accurately reproduce the real working state of the board on the aircraft, thereby greatly improving the accuracy and reliability of fault diagnosis.

[0020] (3) The system of the present invention has human-computer interaction, communication control, signal adaptation and intelligent diagnosis functions, and can realize automatic diagnosis and accurate location of faults. Attached Figure Description

[0021] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein: Figure 1 This is a flowchart of the intelligent testing method for avionics ACSC boards based on reverse engineering in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the intelligent testing system for avionics ACSC boards based on reverse engineering in Embodiment 2 of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] Example 1 like Figure 1 As shown, this embodiment discloses a reverse engineering-based intelligent testing method for avionics ACSC boards, including: S10: In response to the access of the target board, perform physical reverse engineering analysis on the target board and build a software test model that includes circuit topology and test items.

[0025] It is particularly important to emphasize that in the aerospace field, the circuit design drawings for electronic circuit boards are encrypted. Generally, testing units cannot directly access this information for module partitioning. Traditional methods rely primarily on testers visually observing the pad / pin positions and using touch-based testing to assess the specific performance of these boards. However, in the assembly of aircraft in some multinational projects (such as Boeing series), the commissioned testing unit receives the target circuit board provided by the client. Therefore, the method described in this embodiment is essentially based on testing and fault location under this "black box" condition, which is completely different from traditional electronic circuit board fault location methods in other industries.

[0026] There are several ways to connect the target board. It can be connected manually; it can be connected using a high-precision robotic arm; or multiple target boards can be placed in a trolley with multiple positioning disks / frames and then sent into the testing equipment in batches via the trolley.

[0027] Furthermore, the step of constructing the software test model in step S10 specifically includes: S11: Obtain the target board's pin electrical characteristics database.

[0028] In this embodiment, for obtaining the pin electrical characteristic database, visual recognition technology can be used first to identify the approximate distribution of electronic components on the target board. Then, using flying probe technology, the number and electrical characteristics of each electronic component's pins are detected individually and locally. Based on the flying probe detection results, a pin electrical characteristic database containing the number, location, electrical characteristics, and type of electronic components is obtained. This pin electrical characteristic database can approximate a BOM (Bill of Materials) table; this process is equivalent to preliminary reverse engineering analysis of the finished product. It should be noted that during the physical pin inspection process, tools such as multimeters, oscilloscopes, and logic analyzers are also required. Electrical characteristics include level standards (such as TTL, CMOS, etc.), signal timing, and power supply pin information.

[0029] S12: Construct a mathematical graph structure that maps the connection relationships of components based on the pin electrical characteristics database.

[0030] It should be explained that step S12 involves the mapping and reconstruction from the physical board to the schematic diagram. Given the target board size, electrical characteristics of electronic components, spatial distribution, and quantity, component mapping is performed at the system software level to obtain a mathematical graph structure containing the distribution and connection relationships of all electronic components. In practice, the physical board may also involve some hidden wiring (inner layer routing) or embedded designs. Simply compiling a database of pin electrical characteristics is insufficient as direct evidence for testing and analysis. To simplify this complex problem, a modular division based on the mathematical graph structure is necessary.

[0031] S13: A graph-based circuit partitioning algorithm is used to decouple the mathematical graph structure into multiple functionally independent circuit sub-modules.

[0032] In the circuit partitioning algorithm described above, circuit submodules are mainly classified into three types: power supply circuit submodules, digital logic modules, and analog / mixed-signal modules. These three types of circuit submodules can be further divided based on certain characteristics. Specifically, the division of power supply circuit submodules can be confirmed by identifying typical topologies such as voltage regulator chips, filter capacitor distribution, and inductors; the division of digital logic modules can be confirmed by the pin configuration modes of ultra-low-power CPLDs (Complex Programmable Logic Devices).

[0033] The division of analog / mixed-signal modules can be confirmed by the typical connection methods of devices such as operational amplifiers and sensors. These characteristics all possess unique package diagrams and names; therefore, utilizing this feature to decouple the mathematical graph structure is more beneficial for data analysis and automated execution on the test side.

[0034] It is important to note that when rewriting the firmware of an ultra-low-power CPLD, the test communication protocol is logically locked using the underlying hardware description language to avoid automatic optimization of the critical path logic by the synthesis tools, ensuring the complete reliability of the CPLD's logic function during testing. This operation guarantees the accuracy of the test benchmark while avoiding logic function deviations caused by toolchain optimization.

[0035] More preferably, for circuit sub-modules containing analog / mixed-signal modules and high-power switching transistor arrays, to ensure a high degree of consistency between the test state and the on-board operating state, the method also introduces dynamic timing matching and precise drive technology. Specifically, firstly, based on the timing dependencies identified in the circuit module association diagram, drive signals that strictly conform to the power-on, configuration, and operating timing requirements of analog chips (such as power management chips and operational amplifiers) are generated to avoid chip initialization failure or malfunction due to timing errors. Secondly, for high-power switching arrays composed of multiple MOSFETs or IGBTs, precise drive timing that conforms to their switching characteristics and load conditions is generated to avoid abnormal switching action; ensuring reliable and clean switching action under high current and high voltage stress, completely replicating its real operating conditions in the aircraft air conditioning system controller.

[0036] S14: Identify the boundary signal flow and key control timing between multiple circuit sub-modules, and establish a circuit module association diagram that includes timing dependencies.

[0037] Step S14 mainly relies on the electrical characteristics of the aforementioned electronic components to identify the direction of boundary signal flow. This is a relatively conventional and general technology, and will not be elaborated further here.

[0038] S15: Match the corresponding functional attributes for all circuit sub-modules, and logically combine the circuit sub-modules according to the circuit module association diagram to obtain the software test model.

[0039] In this embodiment, there are multiple sub-modules of each type. Taking a power supply circuit sub-module as an example, it can include a buck converter and a filter unit. Therefore, the aforementioned functional attributes are essentially textual label descriptions of each circuit sub-module, used to specifically distinguish each sub-module. The aforementioned logical combination refers to the summary of logical relationships between modules. For example, the buck converter outputs +5V to the microprocessor; it has directionality and network topology relationships, which can be mathematically represented in the form of adjacency vectors or represented in textual form.

[0040] Through steps S11-S15 above, the method of the present invention constructs a complete software testing model by reverse engineering the target board, achieving a breakthrough from "black box" to "transparent" testing, which can significantly improve the accuracy and efficiency of fault diagnosis.

[0041] After constructing the software testing model, the method in this embodiment further includes: Read and back up the original firmware of the programmable logic device. Back up the original firmware in advance to support factory restoration after testing.

[0042] S20: Burn the test firmware program containing the test communication protocol into the programmable logic device to establish a communication link between the test system and the target board.

[0043] It's important to note that factory-installed programs typically include soft limits, such as voltage range limits, current drive capability limits, or frequency response limits. In general circuit board designs, these soft limits can compensate for hardware design deficiencies, thus reducing costs. However, in the aerospace field, these soft limits primarily serve a dual protection function. In the complex scenarios of spacecraft flight, electromagnetic interference, energy radiation, single-event effects, or signal hijacking can all potentially breach these soft limits, causing failure. Ultimately, the backup protection still relies on hardware-level limitations.

[0044] Therefore, step S20 is needed to replace the original factory program of the target board. This is partly to enable the target board to adapt to extreme tests in the testing scenario, specifically whether hardware protection still works when soft limits fail; and partly to support the testing system in achieving more reliable and efficient testing. This is specifically reflected in the configuration of the test communication protocol. S21: Take over control of the target board's data bus during firmware testing.

[0045] S22: Parse the test commands and / or excitation signals from the test system, and convert the test commands and / or excitation signals into control signals for the corresponding circuit sub-modules.

[0046] S23: Real-time sampling of the voltage or logic state of the target circuit node in the circuit submodule, and packaging and transmitting it back to the test system.

[0047] In this embodiment, the target board uses a JTAG interface for programming to ensure the reliability and efficiency of program programming.

[0048] S30: Based on the software testing model, send corresponding test commands and stimulus signals to the target board to drive specific circuit modules to work; during this process, collect response signals in real time.

[0049] Specifically, based on the module division and inter-module relationship representation in the software testing model, the following operations are performed for different circuit modules: For example, for a digital logic module: S31: Apply the control signal obtained from the test instruction to the input terminal of the digital logic module and collect the response signal of the corresponding output terminal.

[0050] The test instructions rely on pre-configured test vectors generated by the software test model. After obtaining the vector representation of the digital logic module, test vectors of the same number of columns are applied to the input terminals to increase / decrease the amplitude at the input nodes, and the response at the output terminals is recorded to update the vector representation. Then, by analyzing the correspondence between inputs and outputs and basic circuit analysis logic, such as branch current method, mesh current method, loop current method, superposition theorem, Thevenin theorem, and Norton's theorem, the function of the digital logic module is derived, such as the logic gate type (AND, OR, NOT, etc.), combinational logic function, or sequential logic function (such as counters, state machines, etc.).

[0051] In addition, the control signal can also be converted into multiple different analog signals through digital-to-analog conversion. Therefore, for the analog / mixed-signal module, step S30 above also includes: S32: Apply multiple different analog signals to the input of the analog / mixed signal module and acquire the response signals at the corresponding output.

[0052] Unlike functional testing of digital logic modules, response signals acquired based on analog signal acquisition are generated by a continuous analog signal system. Although the same circuit analysis logic is used, the mathematical analysis tools differ. For digital logic modules, analysis using difference equations, Z-transforms, or discrete Fourier transforms is also required.

[0053] As for the power supply circuit submodule, it is essentially a type of analog circuit, so the test method mentioned in step S32 is also applicable.

[0054] S40: Compare the response signal with the corresponding expected range to obtain the fault location analysis results.

[0055] After obtaining the circuit submodules with defined modules and functions, the expected ranges can be obtained from relevant industry standards in the aerospace field. Testers can compile these standards into data tables beforehand and import them into the test system. A circuit submodule can have multiple comparison dimensions, such as current output value, frequency, or voltage amplitude. Therefore, each circuit submodule can have multiple expected ranges configured.

[0056] During step S40, if any response signal from one of the circuit submodules is outside the expected range, the input to that submodule is cut off, the submodule is isolated, and fault information including location is recorded. Then, by iterating through all modules, the fault information is finally summarized to obtain the fault location analysis result.

[0057] Finally, after the test is completed, it is also necessary to ensure that the target board can still be used normally after installation. This requires burning its original firmware program into the programmable logic device.

[0058] Through the implementation of steps S10-S40 above, the method of this embodiment establishes a complete automated testing closed-loop system, covering key aspects such as reverse engineering, program replacement, driver detection, signal collection, and fault analysis, thereby achieving intelligent and efficient testing of avionics boards. Unlike existing technologies, this embodiment not only achieves program backup and restoration but also proposes solutions to key technical challenges such as the complex timing of ultra-low power CPLDs and analog chips, as well as the precise driving of high-power switching transistors. This ensures high fidelity in the testing process, meaning the testing environment can accurately reproduce the actual working state of the board on the aircraft, thus greatly improving the accuracy and reliability of fault diagnosis.

[0059] Example 2 like Figure 2 As shown, this embodiment discloses an intelligent testing system for avionics ACSC boards based on reverse engineering, used for the intelligent testing method for avionics ACSC boards based on reverse engineering described in the first aspect. The system of the present invention includes a test management host computer, a communication and control core unit, a protocol adaptation and signal conditioning unit, and an intelligent diagnostic engine.

[0060] When the system responds to the access of the target board, it first performs physical reverse engineering analysis on the target board to build a software test model that includes circuit topology and test items.

[0061] It should be noted that the aforementioned target board is used to power subsequent boards. When the load circuit fails, it may cause a momentary or continuous high-power overload. Therefore, in order to prevent overcurrent from burning out the target board, this embodiment of the system is equipped with a current monitoring and rapid protection mechanism: once the output current exceeds the preset safety threshold, the system will immediately cut off the output, thereby effectively protecting the target board and subsequent circuits.

[0062] The test management host computer provides a human-computer interaction interface for test process configuration, model management, test command issuance, result visualization, and report generation.

[0063] The protocol adaptation and signal conditioning unit is used for physical connection between the target board and the communication and control core unit. It is also responsible for electrical adaptation and safety isolation of the test system's signals and the board interfaces. Furthermore, the protocol adaptation and signal conditioning unit is a dedicated signal adapter board designed based on reverse engineering results, used to realize the physical connection and signal adaptation between the test system and the target board. Specifically, the signal adapter board includes an interface definition matching submodule and a signal level conditioning submodule. The interface definition matching submodule is used to route all pin signals of the target board to the corresponding interfaces of the test system; the signal level conditioning submodule is used to convert the control signal level output by the test system into a level recognizable by the target board, and to convert the response signal level of the target board into a level that the test system can acquire.

[0064] The communication and control core unit is used to burn the test firmware program containing the test communication protocol into the programmable logic device to establish a communication link between the test system and the target board. It is also used to send corresponding test commands and stimulus signals to the target board according to the software test model to drive specific circuit modules. During this process, response signals are acquired in real time. Specifically, it includes a microprocessor (such as an STM32) and a field-programmable gate array (FPGA). The microprocessor is responsible for interacting with the host computer and controlling the test process, while the FPGA is responsible for implementing high-speed, real-time data communication and signal processing with the board's custom protocol.

[0065] The intelligent diagnostic engine compares the response signal with the corresponding expected range to obtain fault location analysis results. The intelligent diagnostic engine is a software module built into the host computer or control core. Based on the test model, it performs signal comparison and logical judgment, executes closed-loop control strategies, and achieves automatic fault diagnosis and location.

[0066] The system in this embodiment also includes other components well known to those skilled in the art, such as communication interfaces. Their settings and functions are known in the art, and therefore will not be described in detail here.

[0067] In the description of this specification, "multiple" means at least two, such as two, three or more, etc., unless otherwise expressly and specifically defined.

[0068] While this specification has shown and described numerous embodiments of the invention, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and essence of the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in the practice of this invention.

Claims

1. A smart testing method for avionics ACSC boards based on reverse engineering, characterized in that, include: In response to the access of the target board, a physical reverse engineering analysis of the target board is performed to construct a software test model that includes circuit topology and test items; The test firmware program containing the test communication protocol is burned into the programmable logic device to establish a communication link between the test system and the target board. According to the software testing model, corresponding test instructions and stimulus signals are sent to the target board to drive specific circuit modules to work; during this process, response signals are collected in real time. The response signal is compared with the corresponding expected range to obtain the fault location analysis result.

2. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 1, characterized in that, Perform physical reverse engineering analysis on the target board to construct a software test model that includes circuit topology and test items, including: Obtain the target board's pin electrical characteristics database; A mathematical graph structure mapping the connection relationships of components is constructed based on the pin electrical characteristic database; A graph-based circuit partitioning algorithm is used to decouple the mathematical graph structure into multiple functionally independent circuit sub-modules. Identify the boundary signal flow and key control timing between multiple circuit sub-modules, and establish a circuit module association diagram that includes timing dependencies; Match corresponding functional attributes to all circuit sub-modules, and logically combine the circuit sub-modules according to the circuit module association diagram to obtain the software test model.

3. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 2, characterized in that, The test communication protocol is configured as follows: During the execution of the test firmware program, control of the data bus of the target board is taken over. Parse test commands and / or excitation signals from the test system, and convert the test commands and / or excitation signals into control signals for the corresponding circuit sub-modules; The voltage or logic state of the target circuit node in the sampling circuit submodule is sampled in real time and packaged and sent back to the test system.

4. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 3, characterized in that, The circuit submodule includes a digital logic module and an analog / mixed-signal module.

5. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 4, characterized in that, The programmable logic device includes an ultra-low power CPLD; when rewriting the firmware of the ultra-low power CPLD, the test communication protocol is logically locked through the underlying hardware description language.

6. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 4, characterized in that, For the digital logic module and the analog / mixed-signal module, the method further includes: For the digital logic module, a control signal converted from a test instruction is applied to the input terminal of the digital logic module, and the response signal at the corresponding output terminal is acquired; wherein, the test instruction depends on the test vector pre-configured in the software test model for generation; the control signal is converted from digital to analog to obtain multiple different analog signals; For the analog / mixed signal module, multiple different analog signals are applied to the input terminal of the analog / mixed signal module, and the response signals of the corresponding output terminals are collected.

7. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 6, characterized in that, For circuit sub-modules comprising analog / mixed-signal modules and high-power switching transistor arrays, the method further includes: Based on the timing dependencies in the circuit module association diagram, drive signals that meet the power-on timing requirements of the analog chip are generated; and precise drive timings that meet its switching characteristics and load conditions are generated.

8. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 1, characterized in that, After constructing the software testing model, the method further includes: Read and back up the original firmware of the programmable logic device; After the test is completed, the method further includes: The original firmware program is burned into the programmable logic device.

9. The intelligent testing method for avionics ACSC boards based on reverse engineering according to claim 1, characterized in that, The target board uses a JTAG interface for programming.

10. A reverse engineering-based intelligent test system for avionics ACSC boards, characterized in that, The intelligent testing method for avionics ACSC boards based on reverse engineering as described in any one of claims 1-9, the system includes a test management host computer, a communication and control core unit, a protocol adaptation and signal conditioning unit, and an intelligent diagnostic engine; When the target board is connected, the system first performs physical reverse engineering analysis on the target board to construct a software test model that includes circuit topology and test items. The test management host computer is used to provide human interaction services; The protocol adaptation and signal conditioning unit is used to physically connect the target board and the communication and control core unit. The communication and control core unit is used for: The test firmware program containing the test communication protocol is burned into the programmable logic device to establish a communication link between the test system and the target board. According to the software testing model, corresponding test instructions and stimulus signals are sent to the target board to drive specific circuit modules to work; during this process, response signals are collected in real time. The intelligent diagnostic engine is used for: The response signal is compared with the corresponding expected range to obtain the fault location analysis result.

Images